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https://github.com/Telecominfraproject/OpenCellular.git
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fa1cec0b60
UART reference clock is 100KHz for ISH4 and 120MHz for ISH3 BUG=none BRANCH=None TEST=`make buildall -j` Change-Id: Ie33e0bd33e0a0c8e56a58fcf4a48677d38c9d61e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/409594 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
227 lines
7.1 KiB
C
227 lines
7.1 KiB
C
/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* UART module for ISH */
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#ifndef __CROS_EC_UART_DEFS_H_
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#define __CROS_EC_UART_DEFS_H_
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#include <stdint.h>
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#include <stddef.h>
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#define UART_ERROR -1
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#define UART_BUSY -2
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#define HSU_BASE ISH_UART_BASE
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#define UART0_OFFS (0x80)
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#define UART0_BASE (ISH_UART_BASE + UART0_OFFS)
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#define UART0_SIZE (0x80)
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#define UART1_OFFS (0x100)
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#define UART1_BASE (ISH_UART_BASE + UART1_OFFS)
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#define UART1_SIZE (0x80)
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#define UART2_OFFS (0x180)
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#define UART2_BASE (ISH_UART_BASE + UART2_OFFS)
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#define UART2_SIZE (0x80)
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/* Register accesses */
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#define LSR(n) (uart_ctx[n].base + UART_REG_LSR * uart_ctx[n].addr_interval)
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#define THR(n) (uart_ctx[n].base + UART_REG_THR * uart_ctx[n].addr_interval)
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#define FOR(n) (uart_ctx[n].base + UART_REG_FOR * uart_ctx[n].addr_interval)
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#define RBR(n) (uart_ctx[n].base + UART_REG_RBR * uart_ctx[n].addr_interval)
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#define DLL(n) (uart_ctx[n].base + UART_REG_DLL * uart_ctx[n].addr_interval)
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#define DLH(n) (uart_ctx[n].base + UART_REG_DLH * uart_ctx[n].addr_interval)
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#define DLD(n) (uart_ctx[n].base + UART_REG_DLD * uart_ctx[n].addr_interval)
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#define IER(n) (uart_ctx[n].base + UART_REG_IER * uart_ctx[n].addr_interval)
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#define IIR(n) (uart_ctx[n].base + UART_REG_IIR * uart_ctx[n].addr_interval)
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#define FCR(n) (uart_ctx[n].base + UART_REG_FCR * uart_ctx[n].addr_interval)
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#define LCR(n) (uart_ctx[n].base + UART_REG_LCR * uart_ctx[n].addr_interval)
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#define MCR(n) (uart_ctx[n].base + UART_REG_MCR * uart_ctx[n].addr_interval)
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#define MSR(n) (uart_ctx[n].base + UART_REG_MSR * uart_ctx[n].addr_interval)
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#define FCTR(n) (uart_ctx[n].base + UART_REG_FCTR * uart_ctx[n].addr_interval)
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#define EFR(n) (uart_ctx[n].base + UART_REG_EFR * uart_ctx[n].addr_interval)
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#define RXTRG(n) \
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(uart_ctx[n].base + UART_REG_RXTRG * uart_ctx[n].addr_interval)
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#define ABR(n) (uart_ctx[n].base + UART_REG_ABR * uart_ctx[n].addr_interval)
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#define PS(n) (uart_ctx[n].base + UART_REG_PS * uart_ctx[n].addr_interval)
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#define MUL(n) (uart_ctx[n].base + UART_REG_MUL * uart_ctx[n].addr_interval)
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#define DIV(n) (uart_ctx[n].base + UART_REG_DIV * uart_ctx[n].addr_interval)
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/* RBR: Receive Buffer register (BLAB bit = 0) */
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#define UART_REG_RBR (0)
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/* THR: Transmit Holding register (BLAB bit = 0) */
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#define UART_REG_THR (0)
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/* IER: Interrupt Enable register (BLAB bit = 0) */
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#define UART_REG_IER (1)
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#define FCR_FIFO_SIZE_16 (0x00)
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#define FCR_FIFO_SIZE_64 (0x20)
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#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
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/* FCR: FIFO Control register */
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#define UART_REG_FCR (2)
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#define FCR_FIFO_ENABLE (0x01)
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#define FCR_RESET_RX (0x02)
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#define FCR_RESET_TX (0x04)
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/* LCR: Line Control register */
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#define UART_REG_LCR (3)
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#define LCR_DLAB (0x80)
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#define LCR_5BIT_CHR (0x00)
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#define LCR_6BIT_CHR (0x01)
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#define LCR_7BIT_CHR (0x02)
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#define LCR_8BIT_CHR (0x03)
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#define LCR_BIT_CHR_MASK (0x03)
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#define LCR_SB (0x40) /*Set Break */
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/* MCR: Modem Control register */
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#define UART_REG_MCR (4)
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#define MCR_DTR (0x1)
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#define MCR_RTS (0x2)
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#define MCR_LOO (0x10)
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#define MCR_INTR_ENABLE (0x08)
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#define MCR_AUTO_FLOW_EN (0x20)
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/* LSR: Line Status register */
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#define UART_REG_LSR (5)
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#define LSR_DR (0x01) /* Data Ready */
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#define LSR_OE (0x02) /* Overrun error */
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#define LSR_PE (0x04) /* Parity error */
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#define LSR_FE (0x08) /* Framing error */
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#define LSR_BI (0x10) /* Breaking interrupt */
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#define LSR_THR_EMPTY (0x20) /* Non FIFO mode: Transmit holding
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* register empty
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*/
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#define LSR_TDRQ (0x20) /* FIFO mode: Transmit Data request */
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#define LSR_TEMT (0x40) /* Transmitter empty */
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#define FCR_ITL_FIFO_64_BYTES_56 (0xc0)
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#define IER_RECV (0x01)
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#define IER_TDRQ (0x02)
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#define IER_LINE_STAT (0x04)
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#define UART_REG_IIR (2)
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/* MSR: Modem Status register */
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#define UART_REG_MSR (6)
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/* DLL: Divisor Latch Reg. low byte (BLAB bit = 1) */
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#define UART_REG_DLL (0)
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/* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
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#define UART_REG_DLH (1)
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/* DLH: Divisor Latch Fractional. (BLAB bit = 1) */
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#define UART_REG_DLD (2)
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/* FOR: Fifo O Register (ISH only) */
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#define UART_REG_FOR (0x20)
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#define FOR_OCCUPANCY_OFFS 0
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#define FOR_OCCUPANCY_MASK 0x7F
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/* ABR: Auto-Baud Control Register (ISH only) */
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#define UART_REG_ABR (0x24)
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#define ABR_UUE (0x10)
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/* Pre-Scalar Register (ISH only) */
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#define UART_REG_PS (0x30)
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/* DDS registers (ISH only) */
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#define UART_REG_MUL (0x34)
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#define UART_REG_DIV (0x38)
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/* G_IEN: Global Interrupt Enable (ISH only) */
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#define HSU_REG_GIEN (0)
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#define HSU_REG_GIST (4)
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#define GIEN_PWR_MGMT (0x01000000)
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#define GIEN_DMA_EN (0x00000020)
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#define GIEN_UART2_EN (0x00000004)
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#define GIEN_UART1_EN (0x00000002)
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#define GIEN_UART0_EN (0x00000001)
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#define GIST_DMA_EN (0x00000020)
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#define GIST_UART2_EN (0x00000004)
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#define GIST_UART1_EN (0x00000002)
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#define GIST_UART0_EN (0x00000001)
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#define GIST_UARTx_EN (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
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/* UART config flag, send to sc_io_control if the current UART line has HW
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* flow control lines connected.
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*/
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#define UART_CONFIG_HW_FLOW_CONTROL (1<<0)
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/* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is
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* raised only when the rx buffer is completely full. Otherwise, the event
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* is raised after a timeout is received on the UART line,
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* and all data received until now is provided.
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*/
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#define UART_CONFIG_DELIVER_FULL_RX_BUF (1<<1)
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/* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted
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* is raised when all rx buffers that were added are full. Otherwise, no
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* event is raised.
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*/
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#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF (1<<2)
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#define UART_INT_DEVICES 2
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#define UART_EXT_DEVICES 8
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#define UART_DEVICES UART_INT_DEVICES
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#define UART_ISH_ADDR_INTERVAL 1
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#define B9600 0x0000d
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#define B57600 0x00000018
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#define B115200 0x00000011
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#define B921600 0x00000012
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#define B2000000 0x00000013
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#define B3000000 0x00000014
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#define B3250000 0x00000015
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#define B3500000 0x00000016
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#define B4000000 0x00000017
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#define B19200 0x0000e
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#define B38400 0x0000f
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/* KHZ, MHZ */
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#define KHZ(x) ((x) * 1000)
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#define MHZ(x) (KHZ(x) * 1000)
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#if (defined CONFIG_ISH_30 || defined CONFIG_ISH_20)
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#define UART_ISH_INPUT_FREQ MHZ(120)
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#elif defined CONFIG_ISH_40
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#define UART_ISH_INPUT_FREQ MHZ(100)
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#endif
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#define UART_DEFAULT_BAUD_RATE 115200
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#define UART_STATE_CG (1 << UART_OP_CG)
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enum UART_PORT {
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UART_PORT_0,
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UART_PORT_1,
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UART_PORT_MAX
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};
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enum UART_OP {
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UART_OP_READ,
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UART_OP_WRITE,
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UART_OP_CG,
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UART_OP_MAX
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};
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enum {
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BAUD_IDX,
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BAUD_SPEED,
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BAUD_TABLE_MAX
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};
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struct uart_ctx {
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uint32_t id;
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uint32_t base;
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uint32_t addr_interval;
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uint32_t uart_state;
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uint32_t is_open;
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uint32_t baud_rate;
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uint32_t input_freq;
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uint32_t client_flags;
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};
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#endif /* _CROS_EC_UART_DEFS_H_ */
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