mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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d96460541a
We don't need to loop and waiting ADC's data valid flag after the change was made. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. We build a EC binary for PD EVB (declared two ADC channels for VBUS measurement of PD task and priority is highest) 2. Use console command "adc" continually to read ADC channels and check if any error. Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b Reviewed-on: https://chromium-review.googlesource.com/421307 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
177 lines
3.4 KiB
C
177 lines
3.4 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "intc.h"
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#include "it83xx_pd.h"
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#include "kmsc_chip.h"
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#include "registers.h"
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#include "task.h"
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#include "usb_pd.h"
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#ifdef CONFIG_USB_PD_TCPM_ITE83XX
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static void chip_pd_irq(enum usbpd_port port)
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{
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task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
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/* check status */
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if (USBPD_IS_HARD_RESET_DETECT(port)) {
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/* clear interrupt */
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IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_HARD_RESET_DETECT;
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task_set_event(PD_PORT_TO_TASK_ID(port),
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PD_EVENT_TCPC_RESET, 0);
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} else {
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if (USBPD_IS_RX_DONE(port)) {
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/* mask RX done interrupt */
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IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
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/* clear RX done interrupt */
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IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_RX_DONE;
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task_set_event(PD_PORT_TO_TASK_ID(port),
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PD_EVENT_RX, 0);
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}
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if (USBPD_IS_TX_DONE(port)) {
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/* clear TX done interrupt */
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IT83XX_USBPD_ISR(port) = USBPD_REG_MASK_MSG_TX_DONE;
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task_set_event(PD_PORT_TO_TASK_ID(port),
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TASK_EVENT_PHY_TX_DONE, 0);
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}
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}
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}
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#endif
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void intc_cpu_int_group_5(void)
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{
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/* Determine interrupt number. */
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int intc_group_5 = intc_get_ec_int();
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switch (intc_group_5) {
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#ifdef CONFIG_LPC
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case IT83XX_IRQ_KBC_OUT:
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lpc_kbc_obe_interrupt();
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break;
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case IT83XX_IRQ_KBC_IN:
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lpc_kbc_ibf_interrupt();
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break;
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#endif
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default:
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break;
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}
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}
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DECLARE_IRQ(CPU_INT_GROUP_5, intc_cpu_int_group_5, 2);
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void intc_cpu_int_group_4(void)
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{
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/* Determine interrupt number. */
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int intc_group_4 = intc_get_ec_int();
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switch (intc_group_4) {
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#ifdef CONFIG_LPC
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case IT83XX_IRQ_PMC_IN:
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pm1_ibf_interrupt();
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break;
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case IT83XX_IRQ_PMC2_IN:
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pm2_ibf_interrupt();
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break;
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case IT83XX_IRQ_PMC3_IN:
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pm3_ibf_interrupt();
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break;
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case IT83XX_IRQ_PMC4_IN:
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pm4_ibf_interrupt();
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break;
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case IT83XX_IRQ_PMC5_IN:
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pm5_ibf_interrupt();
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break;
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#endif
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default:
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break;
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}
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}
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DECLARE_IRQ(CPU_INT_GROUP_4, intc_cpu_int_group_4, 2);
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void intc_cpu_int_group_12(void)
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{
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/* Determine interrupt number. */
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int intc_group_12 = intc_get_ec_int();
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switch (intc_group_12) {
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#ifdef CONFIG_PECI
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case IT83XX_IRQ_PECI:
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peci_interrupt();
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break;
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#endif
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#ifdef CONFIG_USB_PD_TCPM_ITE83XX
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case IT83XX_IRQ_USBPD0:
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chip_pd_irq(USBPD_PORT_A);
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break;
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case IT83XX_IRQ_USBPD1:
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chip_pd_irq(USBPD_PORT_B);
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break;
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#endif /* CONFIG_USB_PD_TCPM_ITE83XX */
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default:
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break;
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}
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}
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DECLARE_IRQ(CPU_INT_GROUP_12, intc_cpu_int_group_12, 2);
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void intc_cpu_int_group_7(void)
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{
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/* Determine interrupt number. */
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int intc_group_7 = intc_get_ec_int();
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switch (intc_group_7) {
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#ifdef CONFIG_ADC
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case IT83XX_IRQ_ADC:
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adc_interrupt();
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break;
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#endif
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default:
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break;
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}
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}
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DECLARE_IRQ(CPU_INT_GROUP_7, intc_cpu_int_group_7, 2);
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void intc_cpu_int_group_6(void)
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{
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/* Determine interrupt number. */
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int intc_group_6 = intc_get_ec_int();
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switch (intc_group_6) {
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#ifdef CONFIG_I2C
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case IT83XX_IRQ_SMB_A:
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i2c_interrupt(IT83XX_I2C_CH_A);
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break;
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case IT83XX_IRQ_SMB_B:
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i2c_interrupt(IT83XX_I2C_CH_B);
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break;
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case IT83XX_IRQ_SMB_C:
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i2c_interrupt(IT83XX_I2C_CH_C);
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break;
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case IT83XX_IRQ_SMB_D:
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i2c_interrupt(IT83XX_I2C_CH_D);
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break;
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case IT83XX_IRQ_SMB_E:
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i2c_interrupt(IT83XX_I2C_CH_E);
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break;
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case IT83XX_IRQ_SMB_F:
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i2c_interrupt(IT83XX_I2C_CH_F);
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break;
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#endif
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default:
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break;
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}
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}
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DECLARE_IRQ(CPU_INT_GROUP_6, intc_cpu_int_group_6, 2);
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