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95858f385c
Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/cortex-m/config_core.h"
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 93
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 2048
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/* Interval between HOOK_TICK notifications */
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#define HOOK_TICK_INTERVAL_MS 250
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/*
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* Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
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* additional port.
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*/
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#define CONFIG_I2C_MULTI_PORT_CONTROLLER
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#define I2C_CONTROLLER_COUNT 4
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#define I2C_PORT_COUNT 5
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/****************************************************************************/
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/* Memory mapping */
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/*
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* The memory region for RAM is actually 0x00100000-0x00120000.
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* RAM for RO/RW = 20k
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* CODE size of the Loader is 3k
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* As per the above configuartion the upper 20k
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* is used to store data.The rest is for code.
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* the lower 107K is flash[ 3k Loader and 104k RO/RW],
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* and the higher 20K is RAM shared by loader and RO/RW.
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*/
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/****************************************************************************/
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/* Define our RAM layout. */
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#define CONFIG_MEC_SRAM_BASE_START 0x00100000
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#define CONFIG_MEC_SRAM_BASE_END 0x00120000
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#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \
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CONFIG_MEC_SRAM_BASE_START)
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/* 20k RAM for RO / RW / loader */
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#define CONFIG_RAM_SIZE 0x00005000
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#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \
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CONFIG_RAM_SIZE)
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* non-standard task stack sizes */
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#define IDLE_TASK_STACK_SIZE 512
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#define LARGER_TASK_STACK_SIZE 640
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#define CHARGER_TASK_STACK_SIZE 640
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#define HOOKS_TASK_STACK_SIZE 640
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#define CONSOLE_TASK_STACK_SIZE 640
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#define HOST_CMD_TASK_STACK_SIZE 640
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/*
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* TODO: Large stack consumption
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* https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
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*/
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#define PD_TASK_STACK_SIZE 800
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/* Default task stack size */
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#define TASK_STACK_SIZE 512
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/****************************************************************************/
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/* Define our flash layout. */
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/* Protect bank size 4K bytes */
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#define CONFIG_FLASH_BANK_SIZE 0x00001000
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/* Sector erase size 4K bytes */
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#define CONFIG_FLASH_ERASE_SIZE 0x00001000
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/* Minimum write size */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000004
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/* One page size for write */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
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/* Program memory base address */
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#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
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#include "config_flash_layout.h"
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/****************************************************************************/
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/* Customize the build */
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/* Optional features present on this chip */
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#if 0
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#define CONFIG_ADC
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#define CONFIG_PECI
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#define CONFIG_MPU
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#endif
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#define CONFIG_DMA
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#define CONFIG_LPC
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#define CONFIG_SPI
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#define CONFIG_SWITCH
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#define GPIO_PIN(index) (index / 10), (1 << (index % 10))
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#define GPIO_PIN_MASK(pin, mask) (pin), (mask)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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