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7aab81edce
When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Hardware timers driver */
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#include "clock.h"
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#include "common.h"
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#include "hooks.h"
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#include "hwtimer.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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void __hw_clock_event_set(uint32_t deadline)
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{
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MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) -
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(0xffffffff - deadline);
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MEC1322_TMR32_CTL(1) |= (1 << 5);
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}
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uint32_t __hw_clock_event_get(void)
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{
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return MEC1322_TMR32_CNT(1) - MEC1322_TMR32_CNT(0) + 0xffffffff;
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}
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void __hw_clock_event_clear(void)
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{
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MEC1322_TMR32_CTL(1) &= ~(1 << 5);
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}
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uint32_t __hw_clock_source_read(void)
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{
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return 0xffffffff - MEC1322_TMR32_CNT(0);
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}
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void __hw_clock_source_set(uint32_t ts)
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{
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MEC1322_TMR32_CTL(0) &= ~(1 << 5);
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MEC1322_TMR32_CNT(0) = 0xffffffff - ts;
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MEC1322_TMR32_CTL(0) |= (1 << 5);
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}
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static void __hw_clock_source_irq(int timer_id)
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{
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if (timer_id == 1)
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MEC1322_TMR32_STS(1) |= 1;
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/* If IRQ is from timer 0, 32-bit timer overflowed */
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process_timers(timer_id == 0);
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}
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void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
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DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
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void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
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DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
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static void configure_timer(int timer_id)
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{
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uint32_t val;
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/* Ensure timer is not running */
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MEC1322_TMR32_CTL(timer_id) &= ~(1 << 5);
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/* Enable timer */
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MEC1322_TMR32_CTL(timer_id) |= (1 << 0);
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val = MEC1322_TMR32_CTL(timer_id);
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/* Pre-scale = 48 -> 1MHz -> Period = 1us */
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val = (val & 0xffff) | (47 << 16);
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MEC1322_TMR32_CTL(timer_id) = val;
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/* Set preload to use the full 32 bits of the timer */
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MEC1322_TMR32_PRE(timer_id) = 0xffffffff;
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/* Enable interrupt */
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MEC1322_TMR32_IEN(timer_id) |= 1;
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}
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int __hw_clock_source_init(uint32_t start_t)
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{
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/*
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* The timer can only fire interrupt when its value reaches zero.
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* Therefore we need two timers:
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* - Timer 0 as free running timer
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* - Timer 1 as event timer
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*/
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configure_timer(0);
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configure_timer(1);
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/* Override the count */
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MEC1322_TMR32_CNT(0) = 0xffffffff - start_t;
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/* Auto restart */
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MEC1322_TMR32_CTL(0) |= (1 << 3);
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/* Start counting in timer 0 */
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MEC1322_TMR32_CTL(0) |= (1 << 5);
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/* Enable interrupt */
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task_enable_irq(MEC1322_IRQ_TIMER32_0);
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task_enable_irq(MEC1322_IRQ_TIMER32_1);
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MEC1322_INT_ENABLE(23) |= (1 << 4) | (1 << 5);
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MEC1322_INT_BLK_EN |= (1 << 23);
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return MEC1322_IRQ_TIMER32_1;
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}
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