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375b607761
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
62 lines
2.1 KiB
Makefile
62 lines
2.1 KiB
Makefile
# -*- makefile -*-
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# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# NPCX chip specific files build
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#
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# NPCX SoC has a Cortex-M4F ARM core
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CORE:=cortex-m
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# Allow the full Cortex-M4 instruction set
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CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
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# Assign default CHIP_FAMILY as npcx5 for old boards used npcx5 series
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ifeq ($(CHIP_FAMILY),)
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CHIP_FAMILY:=npcx5
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endif
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# Required chip modules
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chip-y=header.o clock.o gpio.o hwtimer.o jtag.o system.o uart.o
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chip-y+=system-$(CHIP_FAMILY).o
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# Optional chip modules
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chip-$(CONFIG_ADC)+=adc.o
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chip-$(CONFIG_FANS)+=fan.o
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chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
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chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
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chip-$(CONFIG_LPC)+=lpc.o
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chip-$(CONFIG_ESPI)+=espi.o
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chip-$(CONFIG_PECI)+=peci.o
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chip-$(CONFIG_HOSTCMD_SPS)+=shi.o
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# pwm functions are implemented with the fan functions
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chip-$(CONFIG_PWM)+=pwm.o
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chip-$(CONFIG_SPI)+=spi.o
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chip-$(CONFIG_WATCHDOG)+=watchdog.o
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chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
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# spi flash program fw for openocd
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npcx-flash-fw=chip/npcx/spiflashfw/ec_npcxflash
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npcx-flash-fw-bin=${out}/$(npcx-flash-fw).bin
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PROJECT_EXTRA+=${npcx-flash-fw-bin}
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# ECST tool is for filling the header used by booter of npcx EC
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show_esct_cmd=$(if $(V),,echo ' ECST ' $(subst $(out)/,,$@) ; )
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# ECST options for header
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bld_ecst=${out}/util/ecst -chip $(CHIP_VARIANT) -usearmrst -mode bt -ph -i $(1) -o $(2) -nohcrc \
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-nofcrc -flashsize 8 -spimaxclk 50 -spireadmode dual 1> /dev/null
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# Replace original one with the flat file including header
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moveflat=mv -f $(1) $(2)
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# Commands for ECST
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cmd_ecst=$(show_esct_cmd)$(call moveflat,$@,$@.tmp);$(call bld_ecst,$@.tmp,$@)
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# Commands to append npcx header in ec.RO.flat
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cmd_org_ec_elf_to_flat = $(OBJCOPY) --set-section-flags .roshared=share \
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-O binary $(patsubst %.flat,%.elf,$@) $@
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cmd_npcx_ro_elf_to_flat=$(cmd_org_ec_elf_to_flat);$(cmd_ecst)
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cmd_ec_elf_to_flat = $(if $(filter $(out)/RO/ec.RO.flat, $@), \
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$(cmd_npcx_ro_elf_to_flat), $(cmd_org_ec_elf_to_flat) )
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