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9cd1dcc3fd
This CL includes:
1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish
which npcx's ec is used on the board.
2. Add config_chip-npcx5/7.h files and move features depend on chip
family into them.
3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and
NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on
npcx7 ec. We'll use them later in gpio/system/flash drivers.
4. Add ram size checking for all npcx ec series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481560
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_CHIP_H
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#define __CROS_EC_CONFIG_CHIP_H
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/* CPU core BFD configuration */
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#include "core/cortex-m/config_core.h"
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/* Features depend on chip family */
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#if defined(CHIP_FAMILY_NPCX5)
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#include "config_chip-npcx5.h"
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#elif defined(CHIP_FAMILY_NPCX7)
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#include "config_chip-npcx7.h"
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#else
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#error "Unsupported chip family"
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#endif
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/* 32k hz internal oscillator frequency (FRCLK) */
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#define INT_32K_CLOCK 32768
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 64
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/* Use a bigger console output buffer */
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#undef CONFIG_UART_TX_BUF_SIZE
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#define CONFIG_UART_TX_BUF_SIZE 1024
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/*
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* Interval between HOOK_TICK notifications
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* Notice instant wake-up from deep-idle cannot exceed 200 ms
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*/
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#define HOOK_TICK_INTERVAL_MS 200
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#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
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/* System stack size */
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#define CONFIG_STACK_SIZE 1024
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/* non-standard task stack sizes */
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#define IDLE_TASK_STACK_SIZE 512
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#define LARGER_TASK_STACK_SIZE 640
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#define VENTI_TASK_STACK_SIZE 768
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#define CHARGER_TASK_STACK_SIZE 640
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#define HOOKS_TASK_STACK_SIZE 640
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#define CONSOLE_TASK_STACK_SIZE 640
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/* Default task stack size */
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#define TASK_STACK_SIZE 512
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/* Address of RAM log used by Booter */
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#define ADDR_BOOT_RAMLOG 0x100C7FC0
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/* SPI Flash Spec of W25Q20CV */
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#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size 4K bytes */
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#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* sector erase size 4K bytes */
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#define CONFIG_FLASH_WRITE_SIZE 0x00000001 /* minimum write size */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
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#include "config_flash_layout.h"
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/* Optional features present on this chip */
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#define CONFIG_ADC
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#define CONFIG_PECI
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#define CONFIG_SWITCH
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#define CONFIG_MPU
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#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
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#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask)
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#endif /* __CROS_EC_CONFIG_CHIP_H */
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