mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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35f4d8acaa
Add support to write and erase all flash with flashrom. Add support to use all the memory. Note that PSTATE must not used its own page, as the STM32F4 use big pages. BUG=b:38018926 BRANCH=none TEST=With flashrom, write all, RO, RW regions. Use flash command on the console, including flashwp Change-Id: I4f0aee1b3a4f342bdf4ca97bf5d8e8bcc153fd9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264032 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
79 lines
2.8 KiB
Makefile
79 lines
2.8 KiB
Makefile
# -*- makefile -*-
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# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# STM32 chip specific files build
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#
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ifeq ($(CHIP_FAMILY),stm32f0)
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# STM32F0xx sub-family has a Cortex-M0 ARM core
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CORE:=cortex-m0
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# Force ARMv6-M ISA used by the Cortex-M0
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CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0
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else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4))
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# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
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CORE:=cortex-m
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# Allow the full Cortex-M4 instruction set
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CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
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else
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# other STM32 SoCs have a Cortex-M3 ARM core
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CORE:=cortex-m
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# Force Cortex-M3 subset of instructions
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CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
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endif
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# Select between 16-bit and 32-bit timer for clock source
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TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,)
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DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4),-stm32f4,)
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chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o
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chip-$(CONFIG_COMMON_RUNTIME)+=system.o
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chip-y+=jtag-$(CHIP_FAMILY).o clock-$(CHIP_FAMILY).o
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ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4))
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chip-y+=clock-f.o
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endif
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chip-$(CONFIG_SPI)+=spi.o
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chip-$(CONFIG_SPI_MASTER)+=spi_master.o
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chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o
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chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o
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chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o
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chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o
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chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o
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chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o
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chip-$(CONFIG_WATCHDOG)+=watchdog.o
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chip-$(HAS_TASK_CONSOLE)+=uart.o
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chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
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chip-$(HAS_TASK_POWERLED)+=power_led.o
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chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o
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ifdef CONFIG_FLASH_PHYSICAL
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chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o
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chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o
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chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o
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endif
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chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
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chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o
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chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o
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chip-$(CONFIG_PWM)+=pwm.o
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chip-$(CONFIG_RNG)+=trng.o
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ifeq ($(CHIP_FAMILY),stm32f4)
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chip-$(CONFIG_USB)+=usb_dwc.o usb_endpoints.o
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chip-$(CONFIG_USB_CONSOLE)+=usb_dwc_console.o
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chip-$(CONFIG_USB_POWER)+=usb_power.o
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chip-$(CONFIG_STREAM_USB)+=usb_dwc_stream.o
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chip-$(CONFIG_USB_I2C)+=usb_dwc_i2c.o
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else
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chip-$(CONFIG_STREAM_USB)+=usb-stream.o
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chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o
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chip-$(CONFIG_USB_CONSOLE)+=usb_console.o
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chip-$(CONFIG_USB_GPIO)+=usb_gpio.o
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chip-$(CONFIG_USB_HID)+=usb_hid.o
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chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o
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chip-$(CONFIG_USB_HID_TOUCHPAD)+=usb_hid_touchpad.o
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chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o
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chip-$(CONFIG_USB_SPI)+=usb_spi.o
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endif
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