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014d180b1d
The USART peripheral in the L and F families is different enough to need different receive drivers. In particular, the L family USART perihperal has no way of disabling the overflow error bit. So for that family we check and clear the bit, and keep a count of overflows. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Iea26c242d5177afd552a3bd4d6ab1a9c7a65f90e Reviewed-on: https://chromium-review.googlesource.com/288978 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* USART driver for Chrome EC */
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#include "atomic.h"
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#include "common.h"
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#include "gpio.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "usart.h"
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#include "util.h"
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void usart_init(struct usart_config const *config)
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{
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intptr_t base = config->hw->base;
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/*
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* Enable clock to USART, this must be done first, before attempting
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* to configure the USART.
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*/
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*(config->hw->clock_register) |= config->hw->clock_enable;
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/*
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* For STM32F3, A delay of 1 APB clock cycles is needed before we
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* can access any USART register. Fortunately, we have
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* gpio_config_module() below and thus don't need to add the delay.
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*/
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/*
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* Switch all GPIOs assigned to the USART module over to their USART
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* alternate functions.
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*/
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gpio_config_module(MODULE_USART, 1);
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/*
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* 8N1, 16 samples per bit. error interrupts, and special modes
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* disabled.
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*/
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STM32_USART_CR1(base) = 0x0000;
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STM32_USART_CR2(base) = 0x0000;
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STM32_USART_CR3(base) = 0x0000;
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/*
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* Enable the RX, TX, and variant specific HW.
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*/
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config->rx->init(config);
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config->tx->init(config);
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config->hw->ops->enable(config);
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/*
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* Clear error counts.
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*/
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config->state->rx_overrun = 0;
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config->state->rx_dropped = 0;
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/*
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* Enable the USART, this must be done last since most of the
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* configuration bits require that the USART be disabled for writes to
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* succeed.
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*/
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STM32_USART_CR1(base) |= STM32_USART_CR1_UE;
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}
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void usart_shutdown(struct usart_config const *config)
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{
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STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE;
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config->hw->ops->disable(config);
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}
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void usart_set_baud_f0_l(struct usart_config const *config, int frequency_hz)
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{
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int div = DIV_ROUND_NEAREST(frequency_hz, config->baud);
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intptr_t base = config->hw->base;
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if (div / 16 > 0) {
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/*
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* CPU clock is high enough to support x16 oversampling.
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* BRR = (div mantissa)<<4 | (4-bit div fraction)
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*/
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STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8;
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STM32_USART_BRR(base) = div;
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} else {
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/*
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* CPU clock is low; use x8 oversampling.
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* BRR = (div mantissa)<<4 | (3-bit div fraction)
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*/
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STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7);
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STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8;
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}
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}
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void usart_set_baud_f(struct usart_config const *config, int frequency_hz)
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{
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int div = DIV_ROUND_NEAREST(frequency_hz, config->baud);
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/* STM32F only supports x16 oversampling */
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STM32_USART_BRR(config->hw->base) = div;
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}
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void usart_interrupt(struct usart_config const *config)
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{
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config->tx->interrupt(config);
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config->rx->interrupt(config);
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}
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