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03a665939f
In order to ensure we are always meeting the deadlines for the IRQ_HPD pulse, increase the priority of the processing by moving the rising edge from the low-priority HOOK task (in a deferred function) to the caller task (which is the high-priority PD task). The downside is we are now sleeping in the PD task blocking the processing of the PD messages during this time. Changed HPD_DSTREAM_DEBOUNCE_IRQ to 500us instead of 750us. According to DP spec, the IRQ_HPD pulse width is between 500us and 1000us. Ensure there is a minimum of 2ms delay in between each IRQ_HPD as specified by the DP spec, by sleeping before sending the next pulse if needed. (in practice, this should not wait if we are not too off processing the messages) BUG=chromium:711334 BRANCH=glados strago reef oak TEST=manual, on SKL platform with kernel 3.18 and MST, verify display is functional on USB-C dock. Change-Id: Ib2e9dd608c5f1c671cc5a0fd979a5742101375ff Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/508629 Reviewed-by: Todd Broch <tbroch@chromium.org>
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Type-C port manager for Parade PS8751 with integrated superspeed muxes */
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#include "common.h"
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#include "ps8751.h"
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#include "tcpm.h"
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#include "timer.h"
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#include "usb_pd.h"
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#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || \
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!defined(CONFIG_USB_PD_TCPM_MUX) || \
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!defined(CONFIG_USBC_SS_MUX)
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#error "PS8751 is using a standard TCPCI interface with integrated mux control"
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#error "Please upgrade your board configuration"
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#endif
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/*
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* timestamp of the next possible toggle to ensure the 2-ms spacing
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* between IRQ_HPD.
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*/
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static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_COUNT];
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static int dp_set_hpd(int port, int enable)
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{
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int reg;
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int rv;
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rv = tcpc_read(port, PS8751_REG_CTRL_1, ®);
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if (rv)
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return rv;
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if (enable)
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reg |= PS8751_REG_CTRL_1_HPD;
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else
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reg &= ~PS8751_REG_CTRL_1_HPD;
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return tcpc_write(port, PS8751_REG_CTRL_1, reg);
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}
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static int dp_set_irq(int port, int enable)
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{
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int reg;
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int rv;
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rv = tcpc_read(port, PS8751_REG_CTRL_1, ®);
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if (rv)
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return rv;
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if (enable)
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reg |= PS8751_REG_CTRL_1_IRQ;
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else
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reg &= ~PS8751_REG_CTRL_1_IRQ;
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return tcpc_write(port, PS8751_REG_CTRL_1, reg);
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}
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void ps8751_tcpc_update_hpd_status(int port, int hpd_lvl, int hpd_irq)
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{
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dp_set_hpd(port, hpd_lvl);
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if (hpd_irq) {
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uint64_t now = get_time().val;
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/* wait for the minimum spacing between IRQ_HPD if needed */
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if (now < hpd_deadline[port])
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usleep(hpd_deadline[port] - now);
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dp_set_irq(port, 0);
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usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
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dp_set_irq(port, hpd_irq);
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}
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/* enforce 2-ms delay between HPD pulses */
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hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
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}
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int ps8751_tcpc_get_fw_version(int port, int *version)
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{
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return tcpc_read(port, PS8751_REG_VERSION, version);
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}
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#ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
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struct i2c_stress_test_dev ps8751_i2c_stress_test_dev = {
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.reg_info = {
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.read_reg = PS8751_REG_VENDOR_ID_L,
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.read_val = PS8751_VENDOR_ID & 0xFF,
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.write_reg = PS8751_REG_CTRL_1,
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},
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.i2c_read = &tcpc_i2c_read,
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.i2c_write = &tcpc_i2c_write,
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};
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#endif /* CONFIG_CMD_I2C_STRESS_TEST_TCPC */
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