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https://github.com/Telecominfraproject/OpenCellular.git
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2bb093151f
Add support for ADC / thermistor reads on the BD99992GW PMIC. BUG=chrome-os-partner:42156 TEST=Manual on Glados with subsequent commit. Boot to S0, run "temps". Verify that temperatures start around 28C and begin to increase after system is powered-on for a long duration. BRANCH=None Change-Id: Ic15f41046130317a0e0c3bce4a923ba624328c0d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289935 Reviewed-by: Alec Berg <alecaberg@chromium.org>
91 lines
3.0 KiB
C
91 lines
3.0 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* G781 temperature sensor module for Chrome EC */
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#ifndef __CROS_EC_TEMP_SENSOR_BD99992GW_H
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#define __CROS_EC_TEMP_SENSOR_BD99992GW_H
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#define BD99992GW_I2C_ADDR 0x60
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/* ADC channels */
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enum bd99992gw_adc_channel {
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BD99992GW_ADC_CHANNEL_NONE = -1,
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BD99992GW_ADC_CHANNEL_BATTERY = 0,
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BD99992GW_ADC_CHANNEL_AC = 1,
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BD99992GW_ADC_CHANNEL_SYSTHERM0 = 2,
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BD99992GW_ADC_CHANNEL_SYSTHERM1 = 3,
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BD99992GW_ADC_CHANNEL_SYSTHERM2 = 4,
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BD99992GW_ADC_CHANNEL_SYSTHERM3 = 5,
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BD99992GW_ADC_CHANNEL_DIE_TEMP = 6,
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BD99992GW_ADC_CHANNEL_VDC = 7,
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BD99992GW_ADC_CHANNEL_COUNT = 8,
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};
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/* Registers */
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#define BD99992GW_REG_IRQLVL1 0x02
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#define BD99992GW_IRQLVL1_ADC (1 << 1) /* ADC IRQ asserted */
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#define BD99992GW_REG_ADC1INT 0x03
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#define BD99992GW_ADC1INT_RND (1 << 0) /* RR cycle completed */
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#define BD99992GW_REG_MADC1INT 0x0a
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#define BD99992GW_MADC1INT_RND (1 << 0) /* RR cycle mask */
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#define BD99992GW_REG_IRQLVL1MSK 0x13
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#define BD99992GW_IRQLVL1MSK_MADC (1 << 1) /* ADC IRQ mask */
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#define BD99992GW_REG_ADC1CNTL1 0x80
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#define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */
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#define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */
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#define BD99992GW_ADC1CNTL1_ADPAUSE (1 << 2) /* ADC pause */
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#define BD99992GW_ADC1CNTL1_ADSTRT (1 << 1) /* ADC start */
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#define BD99992GW_ADC1CNTL1_ADEN (1 << 0) /* ADC enable */
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#define BD99992GW_REG_ADC1CNTL2 0x81
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#define BD99992GW_ADC1CNTL2_ADCTHERM (1 << 0) /* Enable ADC sequencing */
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/* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
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#define BD99992GW_ADC_POINTER_REG_COUNT 8
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#define BD99992GW_REG_ADC1ADDR0 0x82
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#define BD99992GW_REG_ADC1ADDR1 0x83
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#define BD99992GW_REG_ADC1ADDR2 0x84
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#define BD99992GW_REG_ADC1ADDR3 0x85
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#define BD99992GW_REG_ADC1ADDR4 0x86
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#define BD99992GW_REG_ADC1ADDR5 0x87
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#define BD99992GW_REG_ADC1ADDR6 0x88
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#define BD99992GW_REG_ADC1ADDR7 0x89
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#define BD99992GW_ADC1ADDR_STOP (1 << 3) /* Last conversion channel */
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/* Result registers */
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#define BD99992GW_REG_ADC1DATA0L 0x95
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#define BD99992GW_REG_ADC1DATA0H 0x96
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#define BD99992GW_REG_ADC1DATA1L 0x97
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#define BD99992GW_REG_ADC1DATA1H 0x98
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#define BD99992GW_REG_ADC1DATA2L 0x99
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#define BD99992GW_REG_ADC1DATA2H 0x9a
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#define BD99992GW_REG_ADC1DATA3L 0x9b
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#define BD99992GW_REG_ADC1DATA3H 0x9c
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#define BD99992GW_REG_ADC1DATA4L 0x9d
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#define BD99992GW_REG_ADC1DATA4H 0x9e
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#define BD99992GW_REG_ADC1DATA5L 0x9f
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#define BD99992GW_REG_ADC1DATA5H 0xa0
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#define BD99992GW_REG_ADC1DATA6L 0xa1
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#define BD99992GW_REG_ADC1DATA6H 0xa2
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#define BD99992GW_REG_ADC1DATA7L 0xa3
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#define BD99992GW_REG_ADC1DATA7H 0xa4
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/**
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* Get the latest value from the sensor.
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*
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* @param idx ADC channel to read.
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* @param temp_ptr Destination for temperature in K.
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*
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* @return EC_SUCCESS if successful, non-zero if error.
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*/
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int bd99992gw_get_val(int idx, int *temp_ptr);
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#endif /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
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