mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2026-01-03 05:29:29 +00:00
927b2e754f
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Reef can boot to OS. S3, S5, hibernate are working.
Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427018
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
132 lines
2.9 KiB
C
132 lines
2.9 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Apollolake chipset power control module for Chrome EC */
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#include "apollolake.h"
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#include "console.h"
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#include "gpio.h"
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#include "intel_x86.h"
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#include "timer.h"
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/* Console output macros */
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#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
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static int forcing_coldreset; /* Forced coldreset in progress? */
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__attribute__((weak)) void chipset_do_shutdown(void)
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{
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/* Need to implement board specific shutdown */
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}
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void chipset_force_shutdown(void)
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{
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if (!forcing_coldreset)
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CPRINTS("%s()", __func__);
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chipset_do_shutdown();
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}
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enum power_state chipset_force_g3(void)
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{
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chipset_force_shutdown();
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/* Power up the platform again for forced cold reset */
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if (forcing_coldreset) {
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forcing_coldreset = 0;
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return POWER_G3S5;
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}
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return POWER_G3;
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}
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void chipset_reset(int cold_reset)
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{
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CPRINTS("%s(%d)", __func__, cold_reset);
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if (cold_reset) {
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/*
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* Perform chipset_force_shutdown and mark forcing_coldreset.
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* Once in S5G3 state, check forcing_coldreset to power up.
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*/
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forcing_coldreset = 1;
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chipset_force_shutdown();
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} else {
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/*
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* Send a pulse to SOC PMU_RSTBTN_N to trigger a warm reset.
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*/
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gpio_set_level(GPIO_PCH_RCIN_L, 0);
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usleep(32 * MSEC);
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gpio_set_level(GPIO_PCH_RCIN_L, 1);
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}
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}
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static void handle_all_sys_pgood(enum power_state state)
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{
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/*
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* Pass through asynchronously, as SOC may not react
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* immediately to power changes.
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*/
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int in_level = gpio_get_level(GPIO_ALL_SYS_PGOOD);
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int out_level = gpio_get_level(GPIO_PCH_SYS_PWROK);
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/* Nothing to do. */
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if (in_level == out_level)
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return;
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gpio_set_level(GPIO_PCH_SYS_PWROK, in_level);
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CPRINTS("Pass through GPIO_ALL_SYS_PGOOD: %d", in_level);
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}
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enum power_state power_handle_state(enum power_state state)
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{
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enum power_state new_state;
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/* Process ALL_SYS_PGOOD state changes. */
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handle_all_sys_pgood(state);
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if (state == POWER_S5 && !power_has_signals(IN_PGOOD_ALL_CORE)) {
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/* Required rail went away */
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chipset_force_shutdown();
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new_state = POWER_S5G3;
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goto rsmrst_handle;
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} else if (state == POWER_G3S5) {
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/* Platform is powering up, clear forcing_coldreset */
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forcing_coldreset = 0;
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}
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new_state = common_intel_x86_power_handle_state(state);
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rsmrst_handle:
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/*
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* Process RSMRST_L state changes:
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* RSMRST_L de-assertion is passed to SoC only on G3S5 to S5 transition.
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* RSMRST_L is also checked in some states and, if asserted, will
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* force shutdown.
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*/
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common_intel_x86_handle_rsmrst(new_state);
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return new_state;
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}
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/**
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* chipset check if PLTRST# is valid.
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*
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* @return non-zero if PLTRST# is valid, 0 if invalid.
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*/
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int chipset_pltrst_is_valid(void)
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{
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/*
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* Invalid PLTRST# from SOC unless RSMRST#
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* from PMIC through EC to soc is deasserted.
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*/
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return (gpio_get_level(GPIO_RSMRST_L_PGOOD) &&
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gpio_get_level(GPIO_PCH_RSMRST_L));
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}
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