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93cc00fde1
This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
57 lines
1.1 KiB
C
57 lines
1.1 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Atomic operations for Andes */
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#ifndef __CROS_EC_ATOMIC_H
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#define __CROS_EC_ATOMIC_H
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#include "common.h"
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#include "cpu.h"
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static inline void atomic_clear(uint32_t *addr, uint32_t bits)
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{
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uint32_t psw = get_psw();
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asm volatile ("setgie.d");
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*addr &= ~bits;
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set_psw(psw);
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}
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static inline void atomic_or(uint32_t *addr, uint32_t bits)
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{
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uint32_t psw = get_psw();
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asm volatile ("setgie.d");
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*addr |= bits;
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set_psw(psw);
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}
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static inline void atomic_add(uint32_t *addr, uint32_t value)
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{
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uint32_t psw = get_psw();
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asm volatile ("setgie.d");
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*addr += value;
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set_psw(psw);
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}
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static inline void atomic_sub(uint32_t *addr, uint32_t value)
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{
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uint32_t psw = get_psw();
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asm volatile ("setgie.d");
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*addr -= value;
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set_psw(psw);
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}
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static inline uint32_t atomic_read_clear(uint32_t *addr)
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{
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uint32_t val;
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uint32_t psw = get_psw();
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asm volatile ("setgie.d");
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val = *addr;
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*addr = 0;
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set_psw(psw);
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return val;
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}
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#endif /* __CROS_EC_ATOMIC_H */
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