mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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b8154d0246
Kevin is code space constrained, so use RAM normally used for data instead for code. BUG=chrome-os-partner:52876 BRANCH=None TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes to add sensor task). Also, verify kevin continues to boot + power sequence. Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343191 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_CONFIG_FLASH_LAYOUT_H
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#define __CROS_EC_CONFIG_FLASH_LAYOUT_H
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/*
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* npcx flash layout:
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* - Memory-mapped external SPI.
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* - Image header at the beginning of protected region, followed by RO image.
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* - RW image starts at the second half of flash.
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*/
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/* Memmapped, external SPI */
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#define CONFIG_EXTERNAL_STORAGE
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#define CONFIG_MAPPED_STORAGE
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/* Storage is memory-mapped, but program runs from SRAM */
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#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
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#undef CONFIG_FLASH_PSTATE
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#if defined(CHIP_VARIANT_NPCX5M5G)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
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#elif defined(CHIP_VARIANT_NPCX5M6G)
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#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
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#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
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#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
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#else
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#error "Unsupported chip variant"
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#endif
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/* Header support which is used by booter to copy FW from flash to code ram */
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#define NPCX_RO_HEADER
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#define CONFIG_RO_HDR_MEM_OFF 0x0
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#define CONFIG_RO_HDR_SIZE 0x40
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#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
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#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
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/* RO firmware offset in flash */
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#define CONFIG_RO_MEM_OFF 0
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#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE
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/* RW firmware offset in flash */
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#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF
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#define CONFIG_RW_SIZE CONFIG_RO_SIZE
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/* The storage offset of ec.R*.flat which is used for firmware_image.lds */
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#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
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#define CONFIG_RW_STORAGE_OFF 0
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#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
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