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f7aec0ceb5
This is the power sequence for rev-0 board. Confirmed the behavior of reprogramming the PMIC registers to enable the instant reset and shutdown. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control pwr_button:press sleep:0.2 pwr_button:release Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0 * Console command: power off Result: S0 -> S5 -> G3 * Console command: power on Result: G3 -> S0 * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969702
20 lines
771 B
Makefile
20 lines
771 B
Makefile
# -*- makefile -*-
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# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Power management for application processor and peripherals
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#
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power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o
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power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
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power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
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power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
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power-$(CONFIG_CHIPSET_MEDIATEK)+=mediatek.o
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power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
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power-$(CONFIG_CHIPSET_ROCKCHIP)+=rockchip.o
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power-$(CONFIG_CHIPSET_SDM845)+=sdm845.o
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power-$(CONFIG_CHIPSET_SKYLAKE)+=skylake.o intel_x86.o
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power-$(CONFIG_CHIPSET_STONEY)+=stoney.o
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power-$(CONFIG_POWER_COMMON)+=common.o
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