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dcaf8edc47
When the FLPRG# strap pin is set to active low, and npcx7 chip is reset, it will enter uut mode. This CL adds the host tool to communicate with npcx chip in uut mode to flash ec firmware via UART port. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST= ------------------------------------------------------------------------ 1. Connect the servo connector (J24) on npcx7 EVB to servo board v2 via flex cable. 2. Manually turn the switch SW1.6 to "ON" on npcx7 EVB. 3. Reset ec by issuing Power-Up or VCC1_RST reset. 4. Manually turn the switch SW1.6 to "OFF" on npcx7 EVB. 5. Move npcx7_evb from array BOARDS_NPCX_7M7X_JTAG to BOARDS_NPCX_UUT in flash_ec. 6. "./util/flash_ec --board=npcx7_evb." Change-Id: I2c588418e809e59f97ef4c3ad7ad13a3fef42f11 Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/952037 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: Alexandru M Stan <amstan@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Tested-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
70 lines
2.5 KiB
C
70 lines
2.5 KiB
C
/*
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* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __UTIL_UUT_CMD_H
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#define __UTIL_UUT_CMD_H
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#include <stdbool.h>
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/*---------------------------------------------------------------------------
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* Constant definitions
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*---------------------------------------------------------------------------
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*/
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#define MAX_CMD_BUF_SIZE 10
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#define MAX_RESP_BUF_SIZE 512
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enum uart_protocol_cmd {
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UFPP_H2D_SYNC_CMD = 0x55, /* Single-Byte Host to Device */
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/* synchronization command */
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UFPP_D2H_SYNC_CMD = 0x5A, /* Single-Byte Device to Host */
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/* synchronization response */
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UFPP_WRITE_CMD = 0x07, /* Write command and response */
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UFPP_READ_CMD = 0x1C, /* Read command and response */
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UFPP_READ_CRC_CMD = 0x89, /* Read CRC command and response */
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UFPP_FCALL_CMD = 0x70, /* Call function command */
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UFPP_FCALL_RSLT_CMD = 0x73, /* Call function response */
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UFPP_SPI_CMD = 0x92, /* SPI specific command */
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UFPP_ERROR_CMD = 0xFF /* Error response */
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};
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struct command_node {
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uint8_t cmd[512];
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uint32_t cmd_size;
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uint32_t resp_size;
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};
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/*---------------------------------------------------------------------------
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* Functions prototypes
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*---------------------------------------------------------------------------
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*/
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void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len);
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void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
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uint8_t *cmd_info, uint32_t *cmd_len);
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void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
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uint32_t *cmd_len);
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void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len);
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void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num);
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void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
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uint32_t *cmd_num);
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void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
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uint32_t *cmd_num);
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bool cmd_disp_sync(uint8_t *resp_buf);
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bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
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uint32_t total_size);
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bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
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uint32_t total_size);
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void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size);
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void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num);
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void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num);
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void cmd_disp_exec_exit(uint8_t *resp_buf);
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void cmd_disp_exec_ret(uint8_t *resp_buf);
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#endif /* __UTIL_UUT_CMD_H */
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