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10ec0fed8e
statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
120 lines
2.7 KiB
C
120 lines
2.7 KiB
C
#include <lib.h> /* Prototypes */
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#include <arch/io.h>
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#include "pc80/mc146818rtc.h"
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#if CONFIG_USE_OPTION_TABLE
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#include "option_table.h"
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#endif
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/* Base Address */
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#ifndef CONFIG_TTYS0_BASE
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#define CONFIG_TTYS0_BASE 0x3f8
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#endif
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#ifndef CONFIG_TTYS0_BAUD
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#define CONFIG_TTYS0_BAUD 115200
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#endif
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#if ((115200%CONFIG_TTYS0_BAUD) != 0)
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#error Bad ttys0 baud rate
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#endif
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#ifndef CONFIG_TTYS0_DIV
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#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
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#endif
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/* Line Control Settings */
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#ifndef CONFIG_TTYS0_LCS
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/* Set 8bit, 1 stop bit, no parity */
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#define CONFIG_TTYS0_LCS 0x3
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#endif
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#define UART_LCS CONFIG_TTYS0_LCS
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#if CONFIG_CACHE_AS_RAM == 0
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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static int uart_can_tx_byte(void)
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{
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return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
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}
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static void uart_wait_to_tx_byte(void)
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{
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while(!uart_can_tx_byte())
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;
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}
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static void uart_wait_until_sent(void)
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{
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while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
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;
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}
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static void uart_tx_byte(unsigned char data)
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{
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uart_wait_to_tx_byte();
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outb(data, CONFIG_TTYS0_BASE + UART_TBR);
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/* Make certain the data clears the fifos */
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uart_wait_until_sent();
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}
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void uart_init(void)
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{
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/* disable interrupts */
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outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
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/* enable fifo's */
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outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
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#if CONFIG_USE_OPTION_TABLE
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static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
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unsigned ttys0_div, ttys0_index;
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ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
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ttys0_index &= 7;
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ttys0_div = divisor[ttys0_index];
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outb(ttys0_div & 0xff, CONFIG_TTYS0_BASE + UART_DLL);
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outb(0, CONFIG_TTYS0_BASE + UART_DLM);
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#else
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outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
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outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
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#endif
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outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
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}
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#else
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/* CONFIG_CACHE_AS_RAM == 1 */
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extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
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void uart_init(void)
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{
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#if CONFIG_USE_OPTION_TABLE
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static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
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unsigned ttys0_div, ttys0_index;
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ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
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ttys0_index &= 7;
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ttys0_div = divisor[ttys0_index];
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uart8250_init(CONFIG_TTYS0_BASE, ttys0_div, UART_LCS);
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#else
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uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV, UART_LCS);
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#endif
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}
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#endif
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