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Some boards (like nocturne) use PSL mode, but the deassertion of PSL_OUT does not directly cut the EC's VCC1 rail. Therefore, the board needs to implement a board specific implementation of hibernate while also being able to configure PSL mode. This commit exports a function of entering PSL mode which could be used in a board specific hibernate implementation. BUG=b:79713379 BRANCH=poppy TEST=`make -j buildall` Change-Id: I8debcae5e713b85c6d23ee3419416b6ae5d5dbf0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1067891 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
79 lines
2.7 KiB
C
79 lines
2.7 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* NPCX-specific SIB module for Chrome EC */
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#ifndef __CROS_EC_SYSTEM_CHIP_H
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#define __CROS_EC_SYSTEM_CHIP_H
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/* Flags for BBRM_DATA_INDEX_WAKE */
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#define HIBERNATE_WAKE_MTC (1 << 0) /* MTC alarm */
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#define HIBERNATE_WAKE_PIN (1 << 1) /* Wake pin */
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/* Indices for battery-backed ram (BBRAM) data position */
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enum bbram_data_index {
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BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
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BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
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BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */
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BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */
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BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */
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BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */
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BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */
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BBRM_DATA_INDEX_VBNVCNTXT = 16, /* VbNvContext for ARM arch */
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BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */
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BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of
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* panic data starting at index
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* 36.
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*/
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BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/
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};
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/* Issue a watchdog reset*/
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void system_watchdog_reset(void);
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/*
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* Configure the specific memory addresses in the the MPU
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* (Memory Protection Unit) for Nuvoton different chip series.
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*/
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void system_mpu_config(void);
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/* Hibernate function for different Nuvoton chip series. */
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void __hibernate_npcx_series(void);
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/* Check and clear BBRAM status on power-on reset */
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void system_check_bbram_on_reset(void);
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/* The utilities and variables depend on npcx chip family */
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#if defined(CHIP_FAMILY_NPCX5)
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/* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
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void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
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uint32_t size, uint32_t exeAddr);
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/* Begin address for hibernate utility; defined in linker script */
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extern unsigned int __flash_lpfw_start;
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/* End address for hibernate utility; defined in linker script */
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extern unsigned int __flash_lpfw_end;
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/* Begin address for little FW; defined in linker script */
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extern unsigned int __flash_lplfw_start;
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/* End address for little FW; defined in linker script */
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extern unsigned int __flash_lplfw_end;
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#elif defined(CHIP_FAMILY_NPCX7)
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/* Configure PSL mode setting for the wake-up pins. */
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int system_config_psl_mode(enum gpio_signal signal);
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/* Configure PSL pins and enter PSL mode. */
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void system_enter_psl_mode(void);
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/* End address for hibernate utility; defined in linker script */
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extern unsigned int __after_init_end;
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#endif
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#endif /* __CROS_EC_SYSTEM_CHIP_H */
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