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cadc0f2513
The message will indicate the reset is caused by which program address
of jump and link instruction.
BRANCH=None
BUG=b:79706847
TEST=No error message under these tests: cold reset, soft reset,
and sysjump.
On bip, declare ".get_cc = NULL" for it83xx tcpm driver. And get
the following message.
log:
--- UART initialized after reboot ---
[Reset cause: unknown]
...
===Unknown reset! jump from f824 or f826===
[0.004504 low power idle task started]
...
Disassembly:
0000f814 <tcpm_get_cc>:
f814: fc 00 push25 $r6, #0 ! {$r6, $fp, $gp, $lp}
f816: 46 30 00 17 sethi $r3, #0x17
f81a: 58 31 8a cc ori $r3, $r3, #0xacc
f81e: 95 04 slli333 $r4, $r0, #4
f820: 88 64 add45 $r3, $r4
f822: a0 da lwi333 $r3, [$r3 + #8]
f824: a0 da lwi333 $r3, [$r3 + #8]
f826: dd 23 jral5 $r3
f828: fc 80 pop25 $r6, #0 ! {$r6, $fp, $gp, $lp}
Change-Id: I2eaf2ad95eb92c68ce6f8240ea6ec90ac2b4a5c9
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1070387
Reviewed-by: Jett Rink <jettrink@chromium.org>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Registers map and definitions for Andes cores
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*/
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#ifndef __CROS_EC_CPU_H
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#define __CROS_EC_CPU_H
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#include <stdint.h>
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/* Process Status Word bits */
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#define PSW_GIE (1 << 0) /* Global Interrupt Enable */
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#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
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#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
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/* write Process Status Word privileged register */
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static inline void set_psw(uint32_t val)
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{
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asm volatile ("mtsr %0, $PSW" : : "r"(val));
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}
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/* read Process Status Word privileged register */
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static inline uint32_t get_psw(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $PSW" : "=r"(ret));
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return ret;
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}
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/* write Interruption Program Counter privileged register */
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static inline void set_ipc(uint32_t val)
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{
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asm volatile ("mtsr %0, $IPC" : : "r"(val));
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}
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/* read Interruption Program Counter privileged register */
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static inline uint32_t get_ipc(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $IPC" : "=r"(ret));
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return ret;
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}
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/* read Interruption Type privileged register */
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static inline uint32_t get_itype(void)
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{
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uint32_t ret;
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asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
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return ret;
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}
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/* Generic CPU core initialization */
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void cpu_init(void);
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extern uint32_t ilp;
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extern uint32_t ec_reset_lp;
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#endif /* __CROS_EC_CPU_H */
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