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When shutting down the MAX77620 PMIC by asserting its SHDN pin, the EN_PP3300 output of the PMIC (GPIO3) is not driving low keeping the PP3300 rail up. Workaround that issue by removing the pull-up on EN_PP3300 when we assert SHDN. Revert the previous CL 263958 aka "ryu: workaround MAX77620 shutdown issue", in order to use a better workaround which ensures that the power rails sequencing at startup Detect the PP1800 rail going up and down by reading the HPD_IN gpio state (which has a pull-up tied to PP1800), then enable/disable EN_PP3300 in sequence. The code using an interrupt on HPD_IN is enabled only on P5, and as a downside, it is killing the base charging on those boards. Indeed HPD_IN(C1) is hijacking the EXTINT1 which used to be connected to the LID_OPEN (E1) GPIO used for the base detection. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:38689 TEST=on both P4 and P5 boards, do various power cycling sequences of the AP using the "apshutdown" and "powerbtn" commands. Change-Id: Icad6e9ae6a08d76cbfd19f97dd7c129bf43037d8 Reviewed-on: https://chromium-review.googlesource.com/265186 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
678 lines
18 KiB
C
678 lines
18 KiB
C
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* ryu board configuration */
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#include "adc.h"
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#include "adc_chip.h"
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#include "battery.h"
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#include "case_closed_debug.h"
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#include "charge_manager.h"
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#include "charge_ramp.h"
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#include "charge_state.h"
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#include "charger.h"
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#include "common.h"
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#include "console.h"
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#include "ec_version.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "host_command.h"
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#include "i2c.h"
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#include "inductive_charging.h"
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#include "lid_switch.h"
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#include "power.h"
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#include "power_button.h"
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#include "registers.h"
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#include "spi.h"
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#include "task.h"
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#include "usb.h"
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#include "usb_pd.h"
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#include "usb_pd_config.h"
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#include "usb_spi.h"
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#include "usb-stm32f3.h"
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#include "usb-stream.h"
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#include "usart-stm32f3.h"
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#include "util.h"
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#include "pi3usb9281.h"
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#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
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/* Default input current limit when VBUS is present */
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#define DEFAULT_CURR_LIMIT 500 /* mA */
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/* VBUS too low threshold */
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#define VBUS_LOW_THRESHOLD_MV 4600
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/* Input current error margin */
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#define IADP_ERROR_MARGIN_MA 100
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static int charge_current_limit;
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static void vbus_log(void)
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{
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CPRINTS("VBUS %d", gpio_get_level(GPIO_CHGR_ACOK));
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}
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DECLARE_DEFERRED(vbus_log);
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void vbus_evt(enum gpio_signal signal)
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{
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struct charge_port_info charge;
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int vbus_level = gpio_get_level(signal);
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/*
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* If VBUS is low, or VBUS is high and we are not outputting VBUS
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* ourselves, then update the VBUS supplier.
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*/
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if (!vbus_level || !gpio_get_level(GPIO_USBC_5V_EN)) {
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charge.voltage = USB_BC12_CHARGE_VOLTAGE;
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charge.current = vbus_level ? DEFAULT_CURR_LIMIT : 0;
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charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0, &charge);
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}
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hook_call_deferred(vbus_log, 0);
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if (task_start_called())
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task_wake(TASK_ID_PD);
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}
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/* Wait 200ms after a charger is detected to debounce pin contact order */
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#define USB_CHG_DEBOUNCE_DELAY_MS 200
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/*
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* Wait 100ms after reset, before re-enabling attach interrupt, so that the
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* spurious attach interrupt from certain ports is ignored.
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*/
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#define USB_CHG_RESET_DELAY_MS 100
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void usb_charger_task(void)
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{
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int device_type, charger_status;
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struct charge_port_info charge;
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int type;
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charge.voltage = USB_BC12_CHARGE_VOLTAGE;
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while (1) {
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/* Read interrupt register to clear */
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pi3usb9281_get_interrupts(0);
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/* Set device type */
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device_type = pi3usb9281_get_device_type(0);
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charger_status = pi3usb9281_get_charger_status(0);
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/* Debounce pin plug order if we detect a charger */
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if (device_type || PI3USB9281_CHG_STATUS_ANY(charger_status)) {
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msleep(USB_CHG_DEBOUNCE_DELAY_MS);
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/* Trigger chip reset to refresh detection registers */
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pi3usb9281_reset(0);
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/* Clear possible disconnect interrupt */
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pi3usb9281_get_interrupts(0);
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/* Mask attach interrupt */
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pi3usb9281_set_interrupt_mask(0,
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0xff &
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~PI3USB9281_INT_ATTACH);
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/* Re-enable interrupts */
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pi3usb9281_enable_interrupts(0);
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msleep(USB_CHG_RESET_DELAY_MS);
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/* Clear possible attach interrupt */
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pi3usb9281_get_interrupts(0);
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/* Re-enable attach interrupt */
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pi3usb9281_set_interrupt_mask(0, 0xff);
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/* Re-read ID registers */
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device_type = pi3usb9281_get_device_type(0);
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charger_status = pi3usb9281_get_charger_status(0);
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}
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if (PI3USB9281_CHG_STATUS_ANY(charger_status))
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type = CHARGE_SUPPLIER_PROPRIETARY;
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else if (device_type & PI3USB9281_TYPE_CDP)
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type = CHARGE_SUPPLIER_BC12_CDP;
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else if (device_type & PI3USB9281_TYPE_DCP)
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type = CHARGE_SUPPLIER_BC12_DCP;
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else if (device_type & PI3USB9281_TYPE_SDP)
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type = CHARGE_SUPPLIER_BC12_SDP;
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else
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type = CHARGE_SUPPLIER_OTHER;
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/* Attachment: decode + update available charge */
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if (device_type || PI3USB9281_CHG_STATUS_ANY(charger_status)) {
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charge.current = pi3usb9281_get_ilim(device_type,
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charger_status);
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charge_manager_update_charge(type, 0, &charge);
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} else { /* Detachment: update available charge to 0 */
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charge.current = 0;
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charge_manager_update_charge(
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CHARGE_SUPPLIER_PROPRIETARY,
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0,
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&charge);
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charge_manager_update_charge(
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CHARGE_SUPPLIER_BC12_CDP,
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0,
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&charge);
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charge_manager_update_charge(
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CHARGE_SUPPLIER_BC12_DCP,
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0,
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&charge);
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charge_manager_update_charge(
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CHARGE_SUPPLIER_BC12_SDP,
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0,
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&charge);
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charge_manager_update_charge(
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CHARGE_SUPPLIER_OTHER,
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0,
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&charge);
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}
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/* notify host of power info change */
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/* pd_send_host_event(PD_EVENT_POWER_CHANGE); */
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/* Wait for interrupt */
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task_wait_event(-1);
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}
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}
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void usb_evt(enum gpio_signal signal)
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{
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task_wake(TASK_ID_USB_CHG);
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}
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#include "gpio_list.h"
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const void *const usb_strings[] = {
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[USB_STR_DESC] = usb_string_desc,
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[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
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[USB_STR_PRODUCT] = USB_STRING_DESC("Ryu debug"),
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[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
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[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC_PD"),
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[USB_STR_AP_STREAM_NAME] = USB_STRING_DESC("AP"),
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[USB_STR_SH_STREAM_NAME] = USB_STRING_DESC("SH"),
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};
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BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
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/*
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* Define AP and SH console forwarding queues and associated USART and USB
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* stream endpoints.
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*/
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QUEUE_CONFIG(ap_usart_to_usb, 64, uint8_t);
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QUEUE_CONFIG(usb_to_ap_usart, 64, uint8_t);
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QUEUE_CONFIG(sh_usart_to_usb, 64, uint8_t);
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QUEUE_CONFIG(usb_to_sh_usart, 64, uint8_t);
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struct usb_stream_config const usb_ap_stream;
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struct usb_stream_config const usb_sh_stream;
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USART_CONFIG(usart1,
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usart1_hw,
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115200,
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ap_usart_to_usb,
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usb_to_ap_usart,
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usb_ap_stream.consumer,
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usb_ap_stream.producer)
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USART_CONFIG(usart3,
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usart3_hw,
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115200,
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sh_usart_to_usb,
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usb_to_sh_usart,
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usb_sh_stream.consumer,
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usb_sh_stream.producer)
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#define AP_USB_STREAM_RX_SIZE 16
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#define AP_USB_STREAM_TX_SIZE 16
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USB_STREAM_CONFIG(usb_ap_stream,
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USB_IFACE_AP_STREAM,
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USB_STR_AP_STREAM_NAME,
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USB_EP_AP_STREAM,
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AP_USB_STREAM_RX_SIZE,
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AP_USB_STREAM_TX_SIZE,
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usb_to_ap_usart,
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ap_usart_to_usb,
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usart1.consumer,
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usart1.producer)
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#define SH_USB_STREAM_RX_SIZE 16
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#define SH_USB_STREAM_TX_SIZE 16
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USB_STREAM_CONFIG(usb_sh_stream,
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USB_IFACE_SH_STREAM,
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USB_STR_SH_STREAM_NAME,
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USB_EP_SH_STREAM,
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SH_USB_STREAM_RX_SIZE,
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SH_USB_STREAM_TX_SIZE,
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usb_to_sh_usart,
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sh_usart_to_usb,
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usart3.consumer,
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usart3.producer)
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/* Initialize board. */
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static void board_init(void)
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{
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struct charge_port_info charge_none, charge_vbus;
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/* Initialize all pericom charge suppliers to 0 */
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charge_none.voltage = USB_BC12_CHARGE_VOLTAGE;
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charge_none.current = 0;
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charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY,
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0,
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&charge_none);
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charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, 0, &charge_none);
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charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, 0, &charge_none);
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charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, 0, &charge_none);
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charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, 0, &charge_none);
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/* Initialize VBUS supplier based on whether or not VBUS is present */
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charge_vbus.voltage = USB_BC12_CHARGE_VOLTAGE;
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charge_vbus.current = DEFAULT_CURR_LIMIT;
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if (gpio_get_level(GPIO_CHGR_ACOK))
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charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0,
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&charge_vbus);
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else
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charge_manager_update_charge(CHARGE_SUPPLIER_VBUS, 0,
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&charge_none);
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/* Enable pericom BC1.2 interrupts. */
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gpio_enable_interrupt(GPIO_USBC_BC12_INT_L);
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pi3usb9281_set_interrupt_mask(0, 0xff);
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pi3usb9281_enable_interrupts(0);
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/*
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* Determine recovery mode is requested by the power, volup, and
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* voldown buttons being pressed.
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*/
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if (power_button_signal_asserted() &&
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!gpio_get_level(GPIO_BTN_VOLD_L) &&
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!gpio_get_level(GPIO_BTN_VOLU_L))
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host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
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/*
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* Initialize AP and SH console forwarding USARTs and queues.
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*/
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queue_init(&ap_usart_to_usb);
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queue_init(&usb_to_ap_usart);
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queue_init(&sh_usart_to_usb);
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queue_init(&usb_to_sh_usart);
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usart_init(&usart1);
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usart_init(&usart3);
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/*
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* Enable CC lines after all GPIO have been initialized. Note, it is
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* important that this is enabled after the CC_DEVICE_ODL lines are
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* set low to specify device mode.
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*/
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gpio_set_level(GPIO_USBC_CC_EN, 1);
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/* Enable interrupts on VBUS transitions. */
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gpio_enable_interrupt(GPIO_CHGR_ACOK);
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/*
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* TODO(crosbug.com/p/38689) Workaround for PMIC issue on P5.
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* remove when P5 are de-commissioned.
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* We are re-using EXTINT1 for the new power sequencing workaround
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* this is killing the base closing detection on P5
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* we won't charge it.
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*/
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if (board_get_version() == 5)
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gpio_enable_interrupt(GPIO_HPD_IN);
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}
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DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
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/* power signal list. Must match order of enum power_signal. */
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const struct power_signal_info power_signal_list[] = {
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{GPIO_AP_HOLD, 1, "AP_HOLD"},
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{GPIO_AP_IN_SUSPEND, 1, "SUSPEND_ASSERTED"},
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};
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BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
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/*
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* TODO(crosbug.com/p/38689) Workaround for MAX77620 PMIC EN_PP3300 issue.
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* remove when P5 are de-commissioned.
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*/
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void pp1800_on_off_evt(enum gpio_signal signal)
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{
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int level = gpio_get_level(signal);
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gpio_set_level(GPIO_EN_PP3300_RSVD, level);
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}
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/* ADC channels */
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const struct adc_t adc_channels[] = {
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/* Vbus sensing. Converted to mV, /10 voltage divider. */
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[ADC_VBUS] = {"VBUS", 30000, 4096, 0, STM32_AIN(0)},
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/* USB PD CC lines sensing. Converted to mV (3000mV/4096). */
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[ADC_CC1_PD] = {"CC1_PD", 3000, 4096, 0, STM32_AIN(1)},
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[ADC_CC2_PD] = {"CC2_PD", 3000, 4096, 0, STM32_AIN(3)},
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/* Charger current sensing. Converted to mA. */
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[ADC_IADP] = {"IADP", 7500, 4096, 0, STM32_AIN(8)},
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[ADC_IBAT] = {"IBAT", 37500, 4096, 0, STM32_AIN(13)},
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};
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BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
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/* Charge supplier priority: lower number indicates higher priority. */
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const int supplier_priority[] = {
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[CHARGE_SUPPLIER_PD] = 0,
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[CHARGE_SUPPLIER_TYPEC] = 1,
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[CHARGE_SUPPLIER_PROPRIETARY] = 1,
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[CHARGE_SUPPLIER_BC12_DCP] = 1,
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[CHARGE_SUPPLIER_BC12_CDP] = 2,
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[CHARGE_SUPPLIER_BC12_SDP] = 3,
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[CHARGE_SUPPLIER_OTHER] = 3,
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[CHARGE_SUPPLIER_VBUS] = 4
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};
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BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
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/* I2C ports */
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const struct i2c_port_t i2c_ports[] = {
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{"master", I2C_PORT_MASTER, 100,
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GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
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{"slave", I2C_PORT_SLAVE, 100,
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GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
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};
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const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
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/* TODO(crosbug.com/p/38333) remove me */
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#define GPIO_USBC_SS1_USB_MODE_L GPIO_USBC_MUX_CONF0
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#define GPIO_USBC_SS2_USB_MODE_L GPIO_USBC_MUX_CONF1
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#define GPIO_USBC_SS_EN_L GPIO_USBC_MUX_CONF2
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void p4_board_set_usb_mux(int port, enum typec_mux mux, int polarity)
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{
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/* reset everything */
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gpio_set_level(GPIO_USBC_SS_EN_L, 1);
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gpio_set_level(GPIO_USBC_DP_MODE_L, 1);
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gpio_set_level(GPIO_USBC_DP_POLARITY, 1);
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gpio_set_level(GPIO_USBC_SS1_USB_MODE_L, 1);
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gpio_set_level(GPIO_USBC_SS2_USB_MODE_L, 1);
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if (mux == TYPEC_MUX_NONE)
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/* everything is already disabled, we can return */
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return;
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if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK) {
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/* USB 3.0 uses 2 superspeed lanes */
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gpio_set_level(polarity ? GPIO_USBC_SS2_USB_MODE_L :
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GPIO_USBC_SS1_USB_MODE_L, 0);
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}
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if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK) {
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/* DP uses available superspeed lanes (x2 or x4) */
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gpio_set_level(GPIO_USBC_DP_POLARITY, polarity);
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gpio_set_level(GPIO_USBC_DP_MODE_L, 0);
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}
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/* switch on superspeed lanes */
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gpio_set_level(GPIO_USBC_SS_EN_L, 0);
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}
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void board_set_usb_mux(int port, enum typec_mux mux, int polarity)
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{
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if (board_get_version() < 5) {
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/* P4/EVT or older boards */
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/* TODO(crosbug.com/p/38333) remove this */
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p4_board_set_usb_mux(port, mux, polarity);
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return;
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}
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/* reset everything */
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gpio_set_level(GPIO_USBC_MUX_CONF0, 0);
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gpio_set_level(GPIO_USBC_MUX_CONF1, 0);
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gpio_set_level(GPIO_USBC_MUX_CONF2, 0);
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if (mux == TYPEC_MUX_NONE)
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/* everything is already disabled, we can return */
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return;
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gpio_set_level(GPIO_USBC_MUX_CONF0, polarity);
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if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK)
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/* USB 3.0 uses 2 superspeed lanes */
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gpio_set_level(GPIO_USBC_MUX_CONF2, 1);
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if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK)
|
|
/* DP uses available superspeed lanes (x2 or x4) */
|
|
gpio_set_level(GPIO_USBC_MUX_CONF1, 1);
|
|
}
|
|
|
|
int p4_board_get_usb_mux(int port, const char **dp_str, const char **usb_str)
|
|
{
|
|
int has_ss = !gpio_get_level(GPIO_USBC_SS_EN_L);
|
|
int has_usb = !gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ||
|
|
!gpio_get_level(GPIO_USBC_SS2_USB_MODE_L);
|
|
int has_dp = !gpio_get_level(GPIO_USBC_DP_MODE_L);
|
|
|
|
if (has_dp)
|
|
*dp_str = gpio_get_level(GPIO_USBC_DP_POLARITY) ? "DP2" : "DP1";
|
|
else
|
|
*dp_str = NULL;
|
|
|
|
if (has_usb)
|
|
*usb_str = gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ?
|
|
"USB2" : "USB1";
|
|
else
|
|
*usb_str = NULL;
|
|
|
|
return has_ss;
|
|
}
|
|
|
|
int board_get_usb_mux(int port, const char **dp_str, const char **usb_str)
|
|
{
|
|
int has_usb, has_dp, polarity;
|
|
|
|
if (board_get_version() < 5) {
|
|
/* P4/EVT or older boards */
|
|
/* TODO(crosbug.com/p/38333) remove this */
|
|
return p4_board_get_usb_mux(port, dp_str, usb_str);
|
|
}
|
|
|
|
has_usb = gpio_get_level(GPIO_USBC_MUX_CONF2);
|
|
has_dp = gpio_get_level(GPIO_USBC_MUX_CONF1);
|
|
polarity = gpio_get_level(GPIO_USBC_MUX_CONF0);
|
|
|
|
if (has_dp)
|
|
*dp_str = polarity ? "DP2" : "DP1";
|
|
else
|
|
*dp_str = NULL;
|
|
|
|
if (has_usb)
|
|
*usb_str = polarity ? "USB2" : "USB1";
|
|
else
|
|
*usb_str = NULL;
|
|
|
|
return has_dp || has_usb;
|
|
}
|
|
|
|
/**
|
|
* Discharge battery when on AC power for factory test.
|
|
*/
|
|
int board_discharge_on_ac(int enable)
|
|
{
|
|
return charger_discharge_on_ac(enable);
|
|
}
|
|
|
|
int extpower_is_present(void)
|
|
{
|
|
return gpio_get_level(GPIO_CHGR_ACOK);
|
|
}
|
|
|
|
void usb_board_connect(void)
|
|
{
|
|
gpio_set_level(GPIO_USB_PU_EN_L, 0);
|
|
}
|
|
|
|
void usb_board_disconnect(void)
|
|
{
|
|
gpio_set_level(GPIO_USB_PU_EN_L, 1);
|
|
}
|
|
|
|
/* Charge manager callback function, called on delayed override timeout */
|
|
void board_charge_manager_override_timeout(void)
|
|
{
|
|
/* TODO: Implement me! */
|
|
}
|
|
DECLARE_DEFERRED(board_charge_manager_override_timeout);
|
|
|
|
/**
|
|
* Set active charge port -- only one port can be active at a time.
|
|
*
|
|
* @param charge_port Charge port to enable.
|
|
*
|
|
* Returns EC_SUCCESS if charge port is accepted and made active,
|
|
* EC_ERROR_* otherwise.
|
|
*/
|
|
int board_set_active_charge_port(int charge_port)
|
|
{
|
|
int ret = EC_SUCCESS;
|
|
/* check if we are source vbus on that port */
|
|
int source = gpio_get_level(GPIO_USBC_5V_EN);
|
|
|
|
if (charge_port >= 0 && charge_port < PD_PORT_COUNT && source) {
|
|
CPRINTS("Port %d is not a sink, skipping enable", charge_port);
|
|
charge_port = CHARGE_PORT_NONE;
|
|
ret = EC_ERROR_INVAL;
|
|
}
|
|
if (charge_port == CHARGE_PORT_NONE) {
|
|
/* Disable charging */
|
|
charge_set_input_current_limit(0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Set the charge limit based upon desired maximum.
|
|
*
|
|
* @param charge_ma Desired charge limit (mA).
|
|
*/
|
|
void board_set_charge_limit(int charge_ma)
|
|
{
|
|
int rv;
|
|
|
|
charge_current_limit = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
|
|
rv = charge_set_input_current_limit(charge_current_limit);
|
|
if (rv < 0)
|
|
CPRINTS("Failed to set input current limit for PD");
|
|
}
|
|
|
|
/**
|
|
* Return whether ramping is allowed for given supplier
|
|
*/
|
|
int board_is_ramp_allowed(int supplier)
|
|
{
|
|
return supplier == CHARGE_SUPPLIER_BC12_DCP ||
|
|
supplier == CHARGE_SUPPLIER_BC12_SDP ||
|
|
supplier == CHARGE_SUPPLIER_BC12_CDP ||
|
|
supplier == CHARGE_SUPPLIER_PROPRIETARY;
|
|
}
|
|
|
|
/**
|
|
* Return the maximum allowed input current
|
|
*/
|
|
int board_get_ramp_current_limit(int supplier, int sup_curr)
|
|
{
|
|
switch (supplier) {
|
|
case CHARGE_SUPPLIER_BC12_DCP:
|
|
return 2000;
|
|
case CHARGE_SUPPLIER_BC12_SDP:
|
|
return 1000;
|
|
case CHARGE_SUPPLIER_BC12_CDP:
|
|
case CHARGE_SUPPLIER_PROPRIETARY:
|
|
return sup_curr;
|
|
default:
|
|
return 500;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Return if board is consuming full amount of input current
|
|
*/
|
|
int board_is_consuming_full_charge(void)
|
|
{
|
|
return adc_read_channel(ADC_IADP) >= charge_current_limit -
|
|
IADP_ERROR_MARGIN_MA;
|
|
}
|
|
|
|
/**
|
|
* Return if VBUS is sagging low enough that we should stop ramping
|
|
*/
|
|
int board_is_vbus_too_low(enum chg_ramp_vbus_state ramp_state)
|
|
{
|
|
return adc_read_channel(ADC_VBUS) < VBUS_LOW_THRESHOLD_MV;
|
|
}
|
|
|
|
/*
|
|
* Enable and disable SPI for case closed debugging. This forces the AP into
|
|
* reset while SPI is enabled, thus preventing contention on the SPI interface.
|
|
*/
|
|
void usb_spi_board_enable(struct usb_spi_config const *config)
|
|
{
|
|
/* Place AP into reset */
|
|
gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
|
|
|
|
/* Configure SPI GPIOs */
|
|
gpio_config_module(MODULE_SPI_MASTER, 1);
|
|
gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_OUT_HIGH);
|
|
|
|
/* Set all four SPI pins to high speed */
|
|
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000;
|
|
|
|
/* Enable clocks to SPI2 module */
|
|
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
|
|
|
|
/* Reset SPI2 */
|
|
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
|
|
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
|
|
|
|
/* Enable SPI LDO to power the flash chip */
|
|
gpio_set_level(GPIO_VDDSPI_EN, 1);
|
|
|
|
spi_enable(1);
|
|
}
|
|
|
|
void usb_spi_board_disable(struct usb_spi_config const *config)
|
|
{
|
|
spi_enable(0);
|
|
|
|
/* Disable SPI LDO */
|
|
gpio_set_level(GPIO_VDDSPI_EN, 0);
|
|
|
|
/* Disable clocks to SPI2 module */
|
|
STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
|
|
|
|
/* Release SPI GPIOs */
|
|
gpio_config_module(MODULE_SPI_MASTER, 0);
|
|
gpio_set_flags(GPIO_SPI_FLASH_NSS, GPIO_INPUT);
|
|
|
|
/* Release AP from reset */
|
|
gpio_set_level(GPIO_PMIC_WARM_RESET_L, 1);
|
|
}
|
|
|
|
int board_get_version(void)
|
|
{
|
|
static int ver;
|
|
|
|
if (!ver) {
|
|
/*
|
|
* read the board EC ID on the tristate strappings
|
|
* using ternary encoding: 0 = 0, 1 = 1, Hi-Z = 2
|
|
*/
|
|
uint8_t id0 = 0, id1 = 0;
|
|
gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_DOWN | GPIO_INPUT);
|
|
gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_DOWN | GPIO_INPUT);
|
|
usleep(100);
|
|
id0 = gpio_get_level(GPIO_BOARD_ID0);
|
|
id1 = gpio_get_level(GPIO_BOARD_ID1);
|
|
gpio_set_flags(GPIO_BOARD_ID0, GPIO_PULL_UP | GPIO_INPUT);
|
|
gpio_set_flags(GPIO_BOARD_ID1, GPIO_PULL_UP | GPIO_INPUT);
|
|
usleep(100);
|
|
id0 = gpio_get_level(GPIO_BOARD_ID0) && !id0 ? 2 : id0;
|
|
id1 = gpio_get_level(GPIO_BOARD_ID1) && !id1 ? 2 : id1;
|
|
gpio_set_flags(GPIO_BOARD_ID0, GPIO_INPUT);
|
|
gpio_set_flags(GPIO_BOARD_ID1, GPIO_INPUT);
|
|
ver = id1 * 3 + id0;
|
|
CPRINTS("Board ID = %d\n", ver);
|
|
}
|
|
|
|
return ver;
|
|
}
|