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ebf92ecc83
On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep and EC is eligable to enter heavy sleep idle task. Wakeup from S0ix by lid open, any key press, power button or track pad will be done by PCH block by asserting SLP_S0. At S0ix, 1 msec pulse will be generated every 8sec and this signal should be ignored since this is NOT S0ix entry/exit related and defered interrupt for SLP_S0 were added. BRANCH=master BUG=none TEST=in OS shell, run following commands. Following command is valid with coreboot with S0ix patches. "echo freeze > /sys/power/state" then, Measure EC power consumption and compare it with one in S0. And on EC console, there should be NO periodic message, "power state 4 = S0ix, in 0x001d" every 8 sec. Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307947 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
141 lines
3.5 KiB
C
141 lines
3.5 KiB
C
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Common power interface for all chipsets */
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#ifndef __CROS_EC_POWER_H
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#define __CROS_EC_POWER_H
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#include "common.h"
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#include "gpio.h"
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enum power_state {
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/* Steady states */
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POWER_G3 = 0, /*
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* System is off (not technically all the way into G3,
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* which means totally unpowered...)
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*/
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POWER_S5, /* System is soft-off */
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POWER_S3, /* Suspend; RAM on, processor is asleep */
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POWER_S0, /* System is on */
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#ifdef CONFIG_POWER_S0IX
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POWER_S0ix,
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#endif
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/* Transitions */
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POWER_G3S5, /* G3 -> S5 (at system init time) */
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POWER_S5S3, /* S5 -> S3 */
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POWER_S3S0, /* S3 -> S0 */
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POWER_S0S3, /* S0 -> S3 */
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POWER_S3S5, /* S3 -> S5 */
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POWER_S5G3, /* S5 -> G3 */
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#ifdef CONFIG_POWER_S0IX
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POWER_S0ixS0, /* S0ix -> S0 */
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POWER_S0S0ix, /* S0 -> S0ix */
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#endif
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};
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/* Information on an power signal */
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struct power_signal_info {
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enum gpio_signal gpio; /* GPIO for signal */
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int level; /* GPIO level which sets signal bit */
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const char *name; /* Name of signal */
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};
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/*
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* Each board must provide its signal list and a corresponding enum
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* power_signal.
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*/
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extern const struct power_signal_info power_signal_list[];
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/* Convert enum power_signal to a mask for signal functions */
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#define POWER_SIGNAL_MASK(signal) (1 << (signal))
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/**
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* Return current input signal state (one or more POWER_SIGNAL_MASK()s).
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*/
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uint32_t power_get_signals(void);
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/**
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* Check for required inputs
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*
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* @param want Mask of signals which must be present (one or more
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* POWER_SIGNAL_MASK()s).
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*
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* @return Non-zero if all present; zero if a required signal is missing.
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*/
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int power_has_signals(uint32_t want);
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/**
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* Wait for power input signals to be present
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*
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* @param want Mask of signals which must be present (one or more
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* POWER_SIGNAL_MASK()s). If want=0, stops waiting for
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* signals.
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* @return EC_SUCCESS when all inputs are present, or ERROR_TIMEOUT if timeout
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* before reaching the desired state.
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*/
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int power_wait_signals(uint32_t want);
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/**
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* Set the low-level power chipset state.
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*
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* @param new_state New chipset state.
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*/
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void power_set_state(enum power_state new_state);
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/**
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* Chipset-specific initialization
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*
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* @return The state the chipset should start in. Usually POWER_G3, but may
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* be POWER_G0 if the chipset was already on and we've jumped to this image.
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*/
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enum power_state power_chipset_init(void);
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/**
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* Chipset-specific state handler
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*
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* @return The updated state for the chipset.
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*/
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enum power_state power_handle_state(enum power_state state);
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/**
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* Interrupt handler for power signal GPIOs.
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*/
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#ifdef HAS_TASK_CHIPSET
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void power_signal_interrupt(enum gpio_signal signal);
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#ifdef CONFIG_POWER_S0IX
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void power_signal_interrupt_S0(enum gpio_signal signal);
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#endif
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#else
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static inline void power_signal_interrupt(enum gpio_signal signal) { }
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#ifdef CONFIG_POWER_S0IX
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static inline void power_signal_interrupt_S0(enum gpio_signal signal) { }
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#endif
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#endif /* !HAS_TASK_CHIPSET */
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#ifdef CONFIG_POWER_S0IX
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int chipset_get_ps_debounced_level(enum gpio_signal signal);
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#endif
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/**
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* pause_in_s5 getter method.
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*
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* @return Whether we should pause in S5 when shutting down.
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*/
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inline int power_get_pause_in_s5(void);
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/**
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* pause_in_s5 setter method.
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*
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* @param pause True if we should pause in S5 when shutting down.
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*/
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inline void power_set_pause_in_s5(int pause);
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#ifdef CONFIG_LOW_POWER_PSEUDO_G3
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void enter_pseudo_g3(void);
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#endif
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#endif /* __CROS_EC_POWER_H */
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