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It might be that you want an early console in romstage before RAM is up, but you can't or don't want to support the console all the way back in the bootblock. By making the console in those two different environments configurable seperately that becomes possible. On the 5250 console output as early as the bootblock works, but on the 5420 it only starts working in the ROM stage after clocks have been initialized. Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3671 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
391 lines
10 KiB
Plaintext
391 lines
10 KiB
Plaintext
menu "Console"
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config DEFAULT_BOOTBLOCK_CONSOLE
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bool
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default n
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config BOOTBLOCK_CONSOLE
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bool "Enable early (bootblock) console output."
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default DEFAULT_BOOTBLOCK_CONSOLE
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help
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Use console during the bootblock if supported
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config DEFAULT_EARLY_CONSOLE
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bool
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default n
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config EARLY_CONSOLE
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bool "Enable early (pre-RAM) console output."
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default DEFAULT_EARLY_CONSOLE
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help
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Use console during early (pre-RAM) boot stages
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config CONSOLE_SERIAL
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bool "Serial port console output"
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default y
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help
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Send coreboot debug output to a serial port (should be one or more of
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CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART)
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config CONSOLE_SERIAL8250
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bool "Serial port console output (I/O mapped, 8250-compatible)"
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depends on CONSOLE_SERIAL
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depends on HAVE_UART_IO_MAPPED
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default y
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help
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Send coreboot debug output to an I/O mapped serial port console.
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config CONSOLE_SERIAL8250MEM
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bool "Serial port console output (memory mapped, 8250-compatible)"
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depends on CONSOLE_SERIAL
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depends on HAVE_UART_MEMORY_MAPPED
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help
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Send coreboot debug output to a memory mapped serial port console.
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config CONSOLE_SERIAL_UART
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bool "Serial port console output (device-specific UART)"
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depends on CONSOLE_SERIAL
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depends on HAVE_UART_SPECIAL
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default y
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help
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Send coreboot debug output to a device-specific serial port console.
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choice
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prompt "Serial port for 8250"
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default CONSOLE_SERIAL_COM1
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depends on CONSOLE_SERIAL8250
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config CONSOLE_SERIAL_COM1
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bool "COM1/ttyS0, I/O port 0x3f8"
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help
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Serial console on COM1/ttyS0 at I/O port 0x3f8.
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config CONSOLE_SERIAL_COM2
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bool "COM2/ttyS1, I/O port 0x2f8"
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help
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Serial console on COM2/ttyS1 at I/O port 0x2f8.
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config CONSOLE_SERIAL_COM3
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bool "COM3/ttyS2, I/O port 0x3e8"
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help
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Serial console on COM3/ttyS2 at I/O port 0x3e8.
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config CONSOLE_SERIAL_COM4
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bool "COM4/ttyS3, I/O port 0x2e8"
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help
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Serial console on COM4/ttyS3 at I/O port 0x2e8.
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endchoice
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config TTYS0_BASE
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hex
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depends on CONSOLE_SERIAL8250
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default 0x3f8 if CONSOLE_SERIAL_COM1
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default 0x2f8 if CONSOLE_SERIAL_COM2
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default 0x3e8 if CONSOLE_SERIAL_COM3
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default 0x2e8 if CONSOLE_SERIAL_COM4
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help
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Map the COM port names to the respective I/O port.
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choice
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prompt "Baud rate"
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default CONSOLE_SERIAL_115200
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depends on CONSOLE_SERIAL
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config CONSOLE_SERIAL_115200
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bool "115200"
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help
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Set serial port Baud rate to 115200.
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config CONSOLE_SERIAL_57600
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bool "57600"
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help
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Set serial port Baud rate to 57600.
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config CONSOLE_SERIAL_38400
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bool "38400"
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help
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Set serial port Baud rate to 38400.
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config CONSOLE_SERIAL_19200
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bool "19200"
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help
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Set serial port Baud rate to 19200.
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config CONSOLE_SERIAL_9600
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bool "9600"
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help
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Set serial port Baud rate to 9600.
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endchoice
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#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
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config TTYS0_BAUD
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int
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default 115200 if CONSOLE_SERIAL_115200
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default 57600 if CONSOLE_SERIAL_57600
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default 38400 if CONSOLE_SERIAL_38400
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default 19200 if CONSOLE_SERIAL_19200
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default 9600 if CONSOLE_SERIAL_9600
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help
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Map the Baud rates to an integer.
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# TODO: Allow user-friendly selection of settings other than 8n1.
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config TTYS0_LCS
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int
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default 3
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depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM
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config SPKMODEM
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bool "spkmodem (console on speaker) console output"
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default n
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help
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Send coreboot debug output through speaker
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# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
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config HAVE_USBDEBUG
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def_bool n
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config USBDEBUG
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def_bool n
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config USBDEBUG
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bool "USB 2.0 EHCI debug dongle support"
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default n
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depends on HAVE_USBDEBUG
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help
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This option allows you to use a so-called USB EHCI Debug device
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(such as the Ajays NET20DC, AMIDebug RX, or a system using the
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Linux "EHCI Debug Device gadget" driver found in recent kernel)
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to retrieve the coreboot debug messages (instead, or in addition
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to, a serial port).
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This feature is NOT supported on all chipsets in coreboot!
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It also requires a USB2 controller which supports the EHCI
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Debug Port capability.
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See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
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of supported controllers.
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If unsure, say N.
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# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
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# as those hardcode the physical USB port to be used as Debug Port to 1.
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# It cannot be changed by coreboot.
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config USBDEBUG_DEFAULT_PORT
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int "Default USB port to use as Debug Port"
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default 1
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depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
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help
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This option selects which physical USB port coreboot will try to
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use as EHCI Debug Port first (valid values are: 1-15).
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If coreboot doesn't detect an EHCI Debug Port dongle on this port,
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it will try all the other ports one after the other. This will take
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a few seconds of time though, and thus slow down the booting process.
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Hence, if you select the correct port here, you can speed up
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your boot time. Which USB port number (1-15) refers to which
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actual port on your mainboard (potentially also USB pin headers
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on your mainboard) is highly board-specific, and you'll likely
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have to find out by trial-and-error.
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# TODO: Deps?
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# TODO: Improve description.
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config ONBOARD_VGA_IS_PRIMARY
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bool "Use onboard VGA as primary video device"
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default n
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help
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If not selected, the last adapter found will be used.
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config CONSOLE_NE2K
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bool "Network console over NE2000 compatible Ethernet adapter"
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default n
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help
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Send coreboot debug output to a Ethernet console, it works
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same way as Linux netconsole, packets are received to UDP
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port 6666 on IP/MAC specified with options bellow.
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Use following netcat command: nc -u -l -p 6666
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config CONSOLE_NE2K_DST_MAC
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depends on CONSOLE_NE2K
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string "Destination MAC address of remote system"
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default "00:13:d4:76:a2:ac"
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help
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Type in either MAC address of logging system or MAC address
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of the router.
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config CONSOLE_NE2K_DST_IP
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depends on CONSOLE_NE2K
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string "Destination IP of logging system"
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default "10.0.1.27"
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help
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This is IP adress of the system running for example
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netcat command to dump the packets.
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config CONSOLE_NE2K_SRC_IP
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depends on CONSOLE_NE2K
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string "IP address of coreboot system"
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default "10.0.1.253"
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help
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This is the IP of the coreboot system
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config CONSOLE_NE2K_IO_PORT
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depends on CONSOLE_NE2K
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hex "NE2000 adapter fixed IO port address"
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default 0xe00
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help
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This is the IO port address for the IO port
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on the card, please select some non-conflicting region,
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32 bytes of IO spaces will be used (and align on 32 bytes
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boundary, qemu needs broader align)
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config CONSOLE_CBMEM
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depends on (EARLY_CBMEM_INIT || DYNAMIC_CBMEM)
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bool "Send console output to a CBMEM buffer"
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default n
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help
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Enable this to save the console output in a CBMEM buffer. This would
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allow to see coreboot console output from Linux space.
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config CONSOLE_CBMEM_BUFFER_SIZE
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depends on CONSOLE_CBMEM
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hex "Room allocated for console output in CBMEM"
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default 0x10000
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help
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Space allocated for console output storage in CBMEM. The default
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value (64K or 0x10000 bytes) is large enough to accommodate
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even the BIOS_SPEW level.
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config CONSOLE_CAR_BUFFER_SIZE
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depends on CONSOLE_CBMEM
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hex "Room allocated for console output in Cache as RAM"
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default 0xc00
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help
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Console is used before RAM is initialized. This is the room reserved
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in the DCACHE based RAM to keep console output before it can be
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saved in a CBMEM buffer. 3K bytes should be enough even for the
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BIOS_SPEW level.
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config CONSOLE_QEMU_DEBUGCON
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bool "QEMU debug console output"
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depends on BOARD_EMULATION_QEMU_X86
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default y
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help
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Send coreboot debug output to QEMU's isa-debugcon device:
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qemu-system-x86_64 \
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-chardev file,id=debugcon,path=/dir/file.log \
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-device isa-debugcon,iobase=0x402,chardev=debugcon
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config CONSOLE_QEMU_DEBUGCON_PORT
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hex "QEMU debug console port"
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depends on CONSOLE_QEMU_DEBUGCON
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default 0x402
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choice
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prompt "Default console log level"
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default DEFAULT_CONSOLE_LOGLEVEL_8
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config DEFAULT_CONSOLE_LOGLEVEL_8
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bool "8: SPEW"
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help
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Way too many details.
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config DEFAULT_CONSOLE_LOGLEVEL_7
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bool "7: DEBUG"
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help
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Debug-level messages.
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config DEFAULT_CONSOLE_LOGLEVEL_6
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bool "6: INFO"
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help
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Informational messages.
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config DEFAULT_CONSOLE_LOGLEVEL_5
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bool "5: NOTICE"
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help
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Normal but significant conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_4
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bool "4: WARNING"
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help
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Warning conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_3
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bool "3: ERR"
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help
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Error conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_2
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bool "2: CRIT"
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help
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Critical conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_1
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bool "1: ALERT"
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help
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Action must be taken immediately.
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config DEFAULT_CONSOLE_LOGLEVEL_0
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bool "0: EMERG"
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help
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System is unusable.
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endchoice
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config DEFAULT_CONSOLE_LOGLEVEL
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int
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default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
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default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
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default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
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default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
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default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
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default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
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default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
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default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
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default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
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help
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Map the log level config names to an integer.
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config CONSOLE_LOGBUF
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bool
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default n
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config NO_POST
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bool "Don't show any POST codes"
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default n
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config CONSOLE_POST
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bool "Show POST codes on the debug console"
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depends on !NO_POST
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default n
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help
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If enabled, coreboot will additionally print POST codes (which are
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usually displayed using a so-called "POST card" ISA/PCI/PCI-E
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device) on the debug console.
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config CMOS_POST
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bool "Store post codes in CMOS for debugging"
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depends on !NO_POST && PC80_SYSTEM
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default n
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help
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If enabled, coreboot will store post codes in CMOS and switch between
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two offsets on each boot so the last post code in the previous boot
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can be retrieved. This uses 3 bytes of CMOS.
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config CMOS_POST_OFFSET
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hex "Offset into CMOS to store POST codes"
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depends on CMOS_POST
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default 0
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help
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If CMOS_POST is enabled then an offset into CMOS must be provided.
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If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
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defined in the mainboard option table.
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config IO_POST
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bool "Send POST codes to an IO port"
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depends on PC80_SYSTEM
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default y
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help
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If enabled, POST codes will be written to an IO port.
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config IO_POST_PORT
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depends on IO_POST
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hex "IO port for POST codes"
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default 0x80
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help
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POST codes on x86 are typically written to the LPC bus on port
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0x80. However, it may be desireable to change the port number
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depending on the presence of coprocessors/microcontrollers or if the
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platform does not support IO in the conventional x86 manner.
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endmenu
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