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https://github.com/Telecominfraproject/OpenCellular.git
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74dce7fa6e
The back end GIC driver converts and assigns the interrupt type to suitable group. For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which determines to which type Group 0 interrupts maps to. - When the build option is set 0 (the default), Group 0 interrupts are meant for Secure EL1. This is presently the case. - Otherwise, Group 0 interrupts are meant for EL3. This means the SPD will have to synchronously hand over the interrupt to Secure EL1. The query API allows the platform to query whether the platform supports interrupts of a given type. API documentation updated. Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
159 lines
4.5 KiB
Makefile
159 lines
4.5 KiB
Makefile
#
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# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Default, static values for build variables, listed in alphabetic order.
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# Dependencies between build options, if any, are handled in the top-level
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# Makefile, after this file is included. This ensures that the former is better
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# poised to handle dependencies, as all build variables would have a default
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# value by then.
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# The AArch32 Secure Payload to be built as BL32 image
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AARCH32_SP := none
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# The Target build architecture. Supported values are: aarch64, aarch32.
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ARCH := aarch64
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# ARM Architecture major and minor versions: 8.0 by default.
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ARM_ARCH_MAJOR := 8
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ARM_ARCH_MINOR := 0
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# Determine the version of ARM GIC architecture to use for interrupt management
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# in EL3. The platform port can change this value if needed.
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ARM_GIC_ARCH := 2
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# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
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ASM_ASSERTION := 0
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# Base commit to perform code check on
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BASE_COMMIT := origin/master
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# By default, consider that the platform may release several CPUs out of reset.
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# The platform Makefile is free to override this value.
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COLD_BOOT_SINGLE_CPU := 0
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# For Chain of Trust
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CREATE_KEYS := 1
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# Build flag to include AArch32 registers in cpu context save and restore during
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# world switch. This flag must be set to 0 for AArch64-only platforms.
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CTX_INCLUDE_AARCH32_REGS := 1
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# Include FP registers in cpu context
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CTX_INCLUDE_FPREGS := 0
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# Debug build
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DEBUG := 0
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# Build platform
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DEFAULT_PLAT := fvp
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# Flag to enable Performance Measurement Framework
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ENABLE_PMF := 0
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# Flag to enable PSCI STATs functionality
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ENABLE_PSCI_STAT := 0
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# Flag to enable runtime instrumentation using PMF
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ENABLE_RUNTIME_INSTRUMENTATION := 0
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# Flag to enable stack corruption protection
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ENABLE_STACK_PROTECTOR := 0
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# Build flag to treat usage of deprecated platform and framework APIs as error.
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ERROR_DEPRECATED := 0
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# Byte alignment that each component in FIP is aligned to
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FIP_ALIGN := 0
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# Default FIP file name
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FIP_NAME := fip.bin
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# Default FWU_FIP file name
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FWU_FIP_NAME := fwu_fip.bin
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# For Chain of Trust
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GENERATE_COT := 0
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# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
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# default, they are for Secure EL1.
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GICV2_G0_FOR_EL3 := 0
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# Whether system coherency is managed in hardware, without explicit software
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# operations.
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HW_ASSISTED_COHERENCY := 0
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# Set the default algorithm for the generation of Trusted Board Boot keys
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KEY_ALG := rsa
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# Flag to enable new version of image loading
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LOAD_IMAGE_V2 := 0
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# NS timer register save and restore
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NS_TIMER_SWITCH := 0
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# Build PL011 UART driver in minimal generic UART mode
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PL011_GENERIC_UART := 0
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# By default, consider that the platform's reset address is not programmable.
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# The platform Makefile is free to override this value.
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PROGRAMMABLE_RESET_ADDRESS := 0
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# Flag used to choose the power state format viz Extended State-ID or the
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# Original format.
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PSCI_EXTENDED_STATE_ID := 0
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# By default, BL1 acts as the reset handler, not BL31
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RESET_TO_BL31 := 0
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# For Chain of Trust
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SAVE_KEYS := 0
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# Whether code and read-only data should be put on separate memory pages. The
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# platform Makefile is free to override this value.
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SEPARATE_CODE_AND_RODATA := 0
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# SPD choice
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SPD := none
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# Flag to introduce an infinite loop in BL1 just before it exits into the next
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# image. This is meant to help debugging the post-BL2 phase.
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SPIN_ON_BL1_EXIT := 0
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# Flags to build TF with Trusted Boot support
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TRUSTED_BOARD_BOOT := 0
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# Build option to choose whether Trusted firmware uses Coherent memory or not.
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USE_COHERENT_MEM := 1
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# Use tbbr_oid.h instead of platform_oid.h
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USE_TBBR_DEFS = $(ERROR_DEPRECATED)
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# Build verbosity
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V := 0
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# Whether to enable D-Cache early during warm boot. This is usually
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# applicable for platforms wherein interconnect programming is not
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# required to enable cache coherency after warm reset (eg: single cluster
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# platforms).
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WARMBOOT_ENABLE_DCACHE_EARLY := 0
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# By default, enable Statistical Profiling Extensions.
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# The top level Makefile will disable this feature depending on
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# the target architecture and version number.
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ENABLE_SPE_FOR_LOWER_ELS := 1
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# SPE is enabled by default but only supported on AArch64 8.2 onwards.
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# Disable it in all other cases.
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ifeq (${ARCH},aarch32)
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override ENABLE_SPE_FOR_LOWER_ELS := 0
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else
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ifeq (${ARM_ARCH_MAJOR},8)
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ifeq ($(ARM_ARCH_MINOR),$(filter $(ARM_ARCH_MINOR),0 1))
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ENABLE_SPE_FOR_LOWER_ELS := 0
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endif
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endif
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endif
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