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31a0130f59
This counter will count the number of times the system enters deep sleep. This is mainly for debugging purposes. With access to the deep sleep count you can start a s3 suspend stress for hundreds of iterations and verify that cr50 entered and resumed from deep sleep the right number of times. BUG=none BRANCH=cr50 TEST=Wait until cr50 enters deep sleep. Wake it up and verify the counter increased. Run 'idle C' and verify it is reset to 0. Change-Id: Icb70a2fefedd82ea10934093f4c917da16b8d4ea Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448334 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_INIT_CHIP_H
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#define __CROS_EC_INIT_CHIP_H
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/**
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* This is the current state of the PMU persistent registers. There are two
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* types: long life and pwrdn scratch. Long life will persist through any
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* reset other than POR. PWRDN scratch only survives deep sleep.
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*
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* LONG_LIFE_SCRATCH 0 - 2
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* SCRATCH0 - Rollback counter
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* SCRATCH1 - Board properties
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* SCRATCH2
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*
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* PWRDN_SCRATCH 0 - 15 - Locked
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*
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* PWRDN_SCRATCH 16 - 27 - Can be used by RW
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* SCRATCH16 - Indicator that firmware is running for debug purposes
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* SCRATCH17 - deep sleep count
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* SCRATCH18 - Preserving USB_DCFG through deep sleep
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*
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* PWRDN_SCRATCH 28 - 31 - Reserved for boot rom
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*/
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enum permission_level {
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PERMISSION_LOW = 0x00,
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PERMISSION_MEDIUM = 0x33, /* APPS run at medium */
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PERMISSION_HIGH = 0x3C,
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PERMISSION_HIGHEST = 0x55
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};
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int runlevel_is_high(void);
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void init_runlevel(const enum permission_level desired_level);
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void init_jittery_clock(int highsec);
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void init_sof_clock(void);
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#endif /* __CROS_EC_INIT_CHIP_H */
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