From 9a9cb17fb757a09ce7318e49a0e44db19021e5bf Mon Sep 17 00:00:00 2001 From: Jonathan Tsai Date: Fri, 19 May 2017 09:39:59 +0800 Subject: [PATCH 1/4] Add Quanta IX2 Platform: 1. Port IX2 platform driver 2. Add class OnlPlatformPortConfig_48x25_8x100 at base.py 3. Port IX2 ONLP: board info 4. Port IX2 ONLP: thermal 5. Port IX2 ONLP: fan 6. Port IX2 ONLP: psu 7. Port IX2 ONLP: sfp 8. Port IX2 ONLP: modify gpio calling from low-level to onlp-lib 9. Port IX2 ONLP: led --- .../src/python/onl/platform/base.py | 4 + .../x86-64-quanta-ix2-rangeley/.gitignore | 2 + .../x86-64-quanta-ix2-rangeley/Makefile | 1 + .../modules/Makefile | 1 + .../modules/PKG.yml | 1 + .../modules/builds/.gitignore | 1 + .../modules/builds/Makefile | 6 + .../modules/builds/quanta_platform_ix2.c | 361 ++++++++++++++++++ .../x86-64-quanta-ix2-rangeley/onlp/Makefile | 1 + .../x86-64-quanta-ix2-rangeley/onlp/PKG.yml | 1 + .../onlp/builds/Makefile | 2 + .../onlp/builds/lib/Makefile | 45 +++ .../onlp/builds/onlpdump/Makefile | 45 +++ .../src/x86_64_quanta_ix2_rangeley/.module | 1 + .../src/x86_64_quanta_ix2_rangeley/Makefile | 9 + .../module/auto/make.mk | 9 + .../auto/x86_64_quanta_ix2_rangeley.yml | 134 +++++++ .../x86_64_quanta_ix2_rangeley.x | 14 + .../x86_64_quanta_ix2_rangeley_config.h | 167 ++++++++ .../x86_64_quanta_ix2_rangeley_dox.h | 26 ++ .../x86_64_quanta_ix2_rangeley_gpio_table.h | 63 +++ .../x86_64_quanta_ix2_rangeley_porting.h | 87 +++++ .../x86_64_quanta_ix2_rangeley/module/make.mk | 10 + .../module/src/Makefile | 9 + .../module/src/fani.c | 172 +++++++++ .../module/src/ledi.c | 229 +++++++++++ .../module/src/make.mk | 9 + .../module/src/psui.c | 118 ++++++ .../module/src/sfpi.c | 222 +++++++++++ .../module/src/sysi.c | 288 ++++++++++++++ .../module/src/thermali.c | 146 +++++++ .../src/x86_64_quanta_ix2_rangeley_config.c | 95 +++++ .../src/x86_64_quanta_ix2_rangeley_enums.c | 10 + .../src/x86_64_quanta_ix2_rangeley_int.h | 308 +++++++++++++++ .../src/x86_64_quanta_ix2_rangeley_log.c | 18 + .../src/x86_64_quanta_ix2_rangeley_log.h | 12 + .../src/x86_64_quanta_ix2_rangeley_module.c | 24 ++ .../src/x86_64_quanta_ix2_rangeley_ucli.c | 50 +++ .../platform-config/Makefile | 1 + .../platform-config/r0/Makefile | 1 + .../platform-config/r0/PKG.yml | 1 + .../src/lib/x86-64-quanta-ix2-rangeley-r0.yml | 31 ++ .../x86_64_quanta_ix2_rangeley_r0/__init__.py | 20 + 43 files changed, 2755 insertions(+) mode change 100644 => 100755 packages/base/all/vendor-config-onl/src/python/onl/platform/base.py create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/.gitignore create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/PKG.yml create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/.gitignore create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/PKG.yml create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/lib/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/onlpdump/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/.module create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/make.mk create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/x86_64_quanta_ix2_rangeley.yml create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley.x create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_config.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_dox.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_porting.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/make.mk create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/fani.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/ledi.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/make.mk create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/psui.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sysi.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/thermali.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_config.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_enums.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_int.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.h create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_module.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_ucli.c create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/Makefile create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/PKG.yml create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/lib/x86-64-quanta-ix2-rangeley-r0.yml create mode 100755 packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py diff --git a/packages/base/all/vendor-config-onl/src/python/onl/platform/base.py b/packages/base/all/vendor-config-onl/src/python/onl/platform/base.py old mode 100644 new mode 100755 index 090af42f..d7b78e22 --- a/packages/base/all/vendor-config-onl/src/python/onl/platform/base.py +++ b/packages/base/all/vendor-config-onl/src/python/onl/platform/base.py @@ -487,6 +487,10 @@ class OnlPlatformPortConfig_48x25_6x100(object): PORT_COUNT=54 PORT_CONFIG="48x25 + 6x100" +class OnlPlatformPortConfig_48x25_8x100(object): + PORT_COUNT=56 + PORT_CONFIG="48x25 + 8x100" + class OnlPlatformPortConfig_32x40(object): PORT_COUNT=32 PORT_CONFIG="32x40" diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/.gitignore b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/.gitignore new file mode 100755 index 00000000..05b8d758 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/.gitignore @@ -0,0 +1,2 @@ +*x86*64*quanta*ix2*rangeley.mk +onlpdump.mk diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/Makefile new file mode 100755 index 00000000..003238cf --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/Makefile @@ -0,0 +1 @@ +include $(ONL)/make/pkg.mk \ No newline at end of file diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/Makefile new file mode 100755 index 00000000..003238cf --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/Makefile @@ -0,0 +1 @@ +include $(ONL)/make/pkg.mk \ No newline at end of file diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/PKG.yml b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/PKG.yml new file mode 100755 index 00000000..5417a2dc --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/PKG.yml @@ -0,0 +1 @@ +!include $ONL_TEMPLATES/platform-modules.yml ARCH=amd64 VENDOR=quanta BASENAME=x86-64-quanta-ix2-rangeley KERNELS="onl-kernel-3.16-lts-x86-64-all:amd64" diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/.gitignore b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/.gitignore new file mode 100755 index 00000000..a65b4177 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/.gitignore @@ -0,0 +1 @@ +lib diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/Makefile new file mode 100755 index 00000000..4af778a2 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/Makefile @@ -0,0 +1,6 @@ +KERNELS := onl-kernel-3.16-lts-x86-64-all:amd64 +KMODULES := $(wildcard *.c) +VENDOR := quanta +BASENAME := x86-64-quanta-ix2-rangeley +ARCH := x86_64 +include $(ONL)/make/kmodule.mk diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c new file mode 100755 index 00000000..0b98b52e --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c @@ -0,0 +1,361 @@ +/* + * Quanta Switch platform driver + * + * + * Copyright (C) 2017 Quanta Computer inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRIVER_NAME "quanta-platform-ix2" + +#define MAX_I2C_CLIENTS 512 +#define I2C_GPIO_BASE 0x80 +#define XSTR(x) STR(X) +#define STR(x) #x + +enum i2c_types { + i2c_type_spd, + i2c_type_rtc, + i2c_type_pca9546, + i2c_type_pca9548, + i2c_type_pca9554, + i2c_type_pca9555, + i2c_type_pca9698, + i2c_type_qci_cpld, + i2c_type_24c02, + i2c_type_qci_pmbus_ix2, + i2c_type_quanta_ix2_hwmon, +}; + +char *i2c_type_names[] = { + "spd", + "ds1339", + "pca9546", + "pca9548", + "pca9554", + "pca9555", + "pca9698", + "CPLD-QSFP28", + "24c02", + "qci_pmbus_ix2", + "quanta_ix2_hwmon", +}; + +struct i2c_init_data { + int parent_bus; + int type; + int addr; + int busno; + int gpio_base; + char name[I2C_NAME_SIZE]; +}; + +static struct i2c_init_data quanta_ix2_i2c_init_data[] = { + { .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x71, .busno = 0x02, .name = "PCA9546(CPU)\0" }, + { .parent_bus = (0x02 + 0), .type = i2c_type_pca9555, .addr = 0x20, .gpio_base = 0x40, .name = "PCA9555_1(CPU)\0" }, + + { .parent_bus = (0x00 + 0), .type = i2c_type_quanta_ix2_hwmon, .addr = 0x4e, .name = "PSoc\0" }, + { .parent_bus = (0x00 + 0), .type = i2c_type_spd, .addr = 0x52, .name = "SPD(DDR3-SODIMM0)\0" }, + { .parent_bus = (0x00 + 0), .type = i2c_type_spd, .addr = 0x53, .name = "SPD(DDR3-SODIMM1)\0" }, + { .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x77, .busno = 0x10, .name = "PCA9546_1\0" }, + + { .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x73, .busno = 0x20, .name = "PCA9548_1\0" }, + { .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x74, .busno = 0x28, .name = "PCA9548_2\0" }, + { .parent_bus = (0x10 + 0), .type = i2c_type_pca9548, .addr = 0x75, .busno = 0x30, .name = "PCA9548_3\0" }, + { .parent_bus = (0x10 + 1), .type = i2c_type_pca9548, .addr = 0x73, .busno = 0x38, .name = "PCA9548_4\0" }, + { .parent_bus = (0x10 + 1), .type = i2c_type_pca9548, .addr = 0x74, .busno = 0x40, .name = "PCA9548_5\0" }, + { .parent_bus = (0x10 + 1), .type = i2c_type_pca9548, .addr = 0x75, .busno = 0x48, .name = "PCA9548_6\0" }, + { .parent_bus = (0x10 + 0), .type = i2c_type_qci_cpld, .addr = 0x38, .name = "qci_cpld(1-16)\0" }, + { .parent_bus = (0x10 + 0), .type = i2c_type_qci_cpld, .addr = 0x39, .name = "qci_cpld(17-32)\0" }, + { .parent_bus = (0x10 + 1), .type = i2c_type_qci_cpld, .addr = 0x38, .name = "qci_cpld(33-48)\0" }, + { .parent_bus = (0x20 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_1_EEPROM\0" }, + { .parent_bus = (0x20 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_2_EEPROM\0" }, + { .parent_bus = (0x20 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_3_EEPROM\0" }, + { .parent_bus = (0x20 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_4_EEPROM\0" }, + { .parent_bus = (0x20 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_5_EEPROM\0" }, + { .parent_bus = (0x20 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_6_EEPROM\0" }, + { .parent_bus = (0x20 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_7_EEPROM\0" }, + { .parent_bus = (0x20 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_8_EEPROM\0" }, + { .parent_bus = (0x28 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_9_EEPROM\0" }, + { .parent_bus = (0x28 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_10_EEPROM\0" }, + { .parent_bus = (0x28 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_11_EEPROM\0" }, + { .parent_bus = (0x28 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_12_EEPROM\0" }, + { .parent_bus = (0x28 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_13_EEPROM\0" }, + { .parent_bus = (0x28 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_14_EEPROM\0" }, + { .parent_bus = (0x28 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_15_EEPROM\0" }, + { .parent_bus = (0x28 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_16_EEPROM\0" }, + { .parent_bus = (0x30 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_17_EEPROM\0" }, + { .parent_bus = (0x30 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_18_EEPROM\0" }, + { .parent_bus = (0x30 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_19_EEPROM\0" }, + { .parent_bus = (0x30 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_20_EEPROM\0" }, + { .parent_bus = (0x30 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_21_EEPROM\0" }, + { .parent_bus = (0x30 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_22_EEPROM\0" }, + { .parent_bus = (0x30 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_23_EEPROM\0" }, + { .parent_bus = (0x30 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_24_EEPROM\0" }, + { .parent_bus = (0x38 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_25_EEPROM\0" }, + { .parent_bus = (0x38 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_26_EEPROM\0" }, + { .parent_bus = (0x38 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_27_EEPROM\0" }, + { .parent_bus = (0x38 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_28_EEPROM\0" }, + { .parent_bus = (0x38 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_29_EEPROM\0" }, + { .parent_bus = (0x38 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_30_EEPROM\0" }, + { .parent_bus = (0x38 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_31_EEPROM\0" }, + { .parent_bus = (0x38 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_32_EEPROM\0" }, + { .parent_bus = (0x40 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_33_EEPROM\0" }, + { .parent_bus = (0x40 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_34_EEPROM\0" }, + { .parent_bus = (0x40 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_35_EEPROM\0" }, + { .parent_bus = (0x40 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_36_EEPROM\0" }, + { .parent_bus = (0x40 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_37_EEPROM\0" }, + { .parent_bus = (0x40 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_38_EEPROM\0" }, + { .parent_bus = (0x40 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_39_EEPROM\0" }, + { .parent_bus = (0x40 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_40_EEPROM\0" }, + { .parent_bus = (0x48 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_41_EEPROM\0" }, + { .parent_bus = (0x48 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_42_EEPROM\0" }, + { .parent_bus = (0x48 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_43_EEPROM\0" }, + { .parent_bus = (0x48 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_44_EEPROM\0" }, + { .parent_bus = (0x48 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_45_EEPROM\0" }, + { .parent_bus = (0x48 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_46_EEPROM\0" }, + { .parent_bus = (0x48 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_47_EEPROM\0" }, + { .parent_bus = (0x48 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "SFP_48_EEPROM\0" }, + + { .parent_bus = (0x10 + 2), .type = i2c_type_pca9548, .addr = 0x73, .busno = 0x50, .name = "PCA9548_7\0" }, + { .parent_bus = (0x10 + 1), .type = i2c_type_pca9698, .addr = 0x21, .gpio_base = 0x50, .name = "PCA9698(QSFP_1-8)\0" }, + { .parent_bus = (0x50 + 0), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_1_EEPROM\0" }, + { .parent_bus = (0x50 + 1), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_2_EEPROM\0" }, + { .parent_bus = (0x50 + 2), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_3_EEPROM\0" }, + { .parent_bus = (0x50 + 3), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_4_EEPROM\0" }, + { .parent_bus = (0x50 + 4), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_5_EEPROM\0" }, + { .parent_bus = (0x50 + 5), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_6_EEPROM\0" }, + { .parent_bus = (0x50 + 6), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_7_EEPROM\0" }, + { .parent_bus = (0x50 + 7), .type = i2c_type_24c02, .addr = 0x50, .name = "QSFP_8_EEPROM\0" }, + + { .parent_bus = (0x00 + 0), .type = i2c_type_pca9546, .addr = 0x72, .busno = 0x14, .name = "PCA9546_2\0" }, + { .parent_bus = (0x14 + 0), .type = i2c_type_qci_pmbus_ix2, .addr = 0x5f, .name = "PSU_1\0" }, + { .parent_bus = (0x14 + 1), .type = i2c_type_qci_pmbus_ix2, .addr = 0x59, .name = "PSU_2\0" }, + { .parent_bus = (0x14 + 2), .type = i2c_type_pca9555, .addr = 0x26, .gpio_base = 0x10, .name = "PCA9555-1(PSU)\0" }, + { .parent_bus = (0x14 + 2), .type = i2c_type_24c02, .addr = 0x54, .name = "Board_EEPROM\0" }, + { .parent_bus = (0x14 + 2), .type = i2c_type_pca9555, .addr = 0x23, .gpio_base = 0x20, .name = "PCA9555-2(Board ID)\0" }, + { .parent_bus = (0x14 + 3), .type = i2c_type_pca9555, .addr = 0x25, .gpio_base = 0x30, .name = "PCA9555-3(FAN IO)\0" }, + { .parent_bus = (0x14 + 3), .type = i2c_type_pca9555, .addr = 0x26, .name = "PCA9555-6(BMC)\0" }, +}; + +static inline struct pca954x_platform_data *pca954x_platform_data_get(int type, int busno) { + static struct pca954x_platform_mode platform_modes[8]; + static struct pca954x_platform_data platform_data; + int num_modes, i; + + switch(type) { + case i2c_type_pca9546: + num_modes = 4; + break; + + case i2c_type_pca9548: + num_modes = 8; + break; + + default: + return (struct pca954x_platform_data *) NULL; + break; + } + + for(i=0;i +# +# Copyright 2014 BigSwitch Networks, Inc. +# +# Licensed under the Eclipse Public License, Version 1.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.eclipse.org/legal/epl-v10.html +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific +# language governing permissions and limitations under the +# License. +# +# +############################################################ +# +# +############################################################ +include $(ONL)/make/config.amd64.mk + +MODULE := libonlp-x86-64-quanta-ix2-rangeley +include $(BUILDER)/standardinit.mk + +DEPENDMODULES := AIM IOF x86_64_quanta_ix2_rangeley quanta_sys_eeprom onlplib +DEPENDMODULE_HEADERS := sff + +include $(BUILDER)/dependmodules.mk + +SHAREDLIB := libonlp-x86-64-quanta-ix2-rangeley.so +$(SHAREDLIB)_TARGETS := $(ALL_TARGETS) +include $(BUILDER)/so.mk +.DEFAULT_GOAL := $(SHAREDLIB) + +GLOBAL_CFLAGS += -I$(onlp_BASEDIR)/module/inc +GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1 +GLOBAL_CFLAGS += -fPIC +GLOBAL_LINK_LIBS += -lpthread + +include $(BUILDER)/targets.mk + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/onlpdump/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/onlpdump/Makefile new file mode 100755 index 00000000..d0b7317b --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/onlpdump/Makefile @@ -0,0 +1,45 @@ +############################################################ +# +# +# Copyright 2014 BigSwitch Networks, Inc. +# +# Licensed under the Eclipse Public License, Version 1.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.eclipse.org/legal/epl-v10.html +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific +# language governing permissions and limitations under the +# License. +# +# +############################################################ +# +# +# +############################################################ +include $(ONL)/make/config.amd64.mk + +.DEFAULT_GOAL := onlpdump + +MODULE := onlpdump +include $(BUILDER)/standardinit.mk + +DEPENDMODULES := AIM IOF onlp x86_64_quanta_ix2_rangeley quanta_sys_eeprom onlplib onlp_platform_defaults sff cjson cjson_util timer_wheel OS + +include $(BUILDER)/dependmodules.mk + +BINARY := onlpdump +$(BINARY)_LIBRARIES := $(LIBRARY_TARGETS) +include $(BUILDER)/bin.mk + +GLOBAL_CFLAGS += -DAIM_CONFIG_AIM_MAIN_FUNCTION=onlpdump_main +GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MODULES_INIT=1 +GLOBAL_CFLAGS += -DAIM_CONFIG_INCLUDE_MAIN=1 +GLOBAL_LINK_LIBS += -lpthread -lm + +include $(BUILDER)/targets.mk diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/.module b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/.module new file mode 100755 index 00000000..dd498b7f --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/.module @@ -0,0 +1 @@ +name: x86_64_quanta_ix2_rangeley diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/Makefile new file mode 100755 index 00000000..e371c7e4 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/Makefile @@ -0,0 +1,9 @@ +############################################################################### +# +# +# +############################################################################### +include $(ONL)/make/config.mk +MODULE := x86_64_quanta_ix2_rangeley +AUTOMODULE := x86_64_quanta_ix2_rangeley +include $(BUILDER)/definemodule.mk diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/make.mk b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/make.mk new file mode 100755 index 00000000..83066587 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/make.mk @@ -0,0 +1,9 @@ +############################################################################### +# +# x86_64_quanta_ix2_rangeley Autogeneration +# +############################################################################### +x86_64_quanta_ix2_rangeley_AUTO_DEFS := module/auto/x86_64_quanta_ix2_rangeley.yml +x86_64_quanta_ix2_rangeley_AUTO_DIRS := module/inc/x86_64_quanta_ix2_rangeley module/src +include $(BUILDER)/auto.mk + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/x86_64_quanta_ix2_rangeley.yml b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/x86_64_quanta_ix2_rangeley.yml new file mode 100755 index 00000000..9774022e --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/auto/x86_64_quanta_ix2_rangeley.yml @@ -0,0 +1,134 @@ +############################################################################### +# +# x86_64_quanta_ix2_rangeley Autogeneration Definitions. +# +############################################################################### + +cdefs: &cdefs +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING: + doc: "Include or exclude logging." + default: 1 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT: + doc: "Default enabled log options." + default: AIM_LOG_OPTIONS_DEFAULT +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT: + doc: "Default enabled log bits." + default: AIM_LOG_BITS_DEFAULT +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT: + doc: "Default enabled custom log bits." + default: 0 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB: + doc: "Default all porting macros to use the C standard libraries." + default: 1 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS: + doc: "Include standard library headers for stdlib porting macros." + default: X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI: + doc: "Include generic uCli support." + default: 0 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD: + doc: "RPM Threshold at which the fan is considered to have failed." + default: 3000 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX: + doc: "Maximum system front-to-back fan speed." + default: 18000 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX: + doc: "Maximum system back-to-front fan speed." + default: 18000 +- X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS: + doc: "Time to hold Phy GPIO in reset, in ms" + default: 100 + +definitions: + cdefs: + X86_64_QUANTA_IX2_RANGELEY_CONFIG_HEADER: + defs: *cdefs + basename: x86_64_quanta_ix2_rangeley_config + + enum: &enums + + fan_id: + members: + - FAN1 : 1 + - FAN2 : 2 + - FAN3 : 3 + - FAN4 : 4 + - FAN5 : 5 + - FAN6 : 6 + - FAN7 : 7 + - FAN8 : 8 + - FAN9 : 9 + - FAN10 : 10 + + fan_oid: + members: + - FAN1 : ONLP_FAN_ID_CREATE(1) + - FAN2 : ONLP_FAN_ID_CREATE(2) + - FAN3 : ONLP_FAN_ID_CREATE(3) + - FAN4 : ONLP_FAN_ID_CREATE(4) + - FAN5 : ONLP_FAN_ID_CREATE(5) + - FAN6 : ONLP_FAN_ID_CREATE(6) + - FAN7 : ONLP_FAN_ID_CREATE(7) + - FAN8 : ONLP_FAN_ID_CREATE(8) + - FAN9 : ONLP_FAN_ID_CREATE(9) + - FAN10 : ONLP_FAN_ID_CREATE(10) + + psu_id: + members: + - PSU1 : 1 + - PSU2 : 2 + + psu_oid: + members: + - PSU1 : ONLP_PSU_ID_CREATE(1) + - PSU2 : ONLP_PSU_ID_CREATE(2) + + thermal_id: + members: + - THERMAL1 : 1 + - THERMAL2 : 2 + - THERMAL3 : 3 + - THERMAL4 : 4 + - THERMAL5 : 5 + - THERMAL6 : 6 + - THERMAL7 : 7 + - THERMAL8 : 8 + - THERMAL9 : 9 + - THERMAL10 : 10 + - THERMAL11 : 11 + - THERMAL12 : 12 + - THERMAL13 : 13 + - THERMAL14 : 14 + - THERMAL15 : 15 + - THERMAL16 : 16 + + + thermal_oid: + members: + - THERMAL1 : ONLP_THERMAL_ID_CREATE(1) + - THERMAL2 : ONLP_THERMAL_ID_CREATE(2) + - THERMAL3 : ONLP_THERMAL_ID_CREATE(3) + - THERMAL4 : ONLP_THERMAL_ID_CREATE(4) + - THERMAL5 : ONLP_THERMAL_ID_CREATE(5) + - THERMAL6 : ONLP_THERMAL_ID_CREATE(6) + - THERMAL7 : ONLP_THERMAL_ID_CREATE(7) + - THERMAL8 : ONLP_THERMAL_ID_CREATE(8) + - THERMAL9 : ONLP_THERMAL_ID_CREATE(9) + - THERMAL10 : ONLP_THERMAL_ID_CREATE(10) + - THERMAL11 : ONLP_THERMAL_ID_CREATE(11) + - THERMAL12 : ONLP_THERMAL_ID_CREATE(12) + - THERMAL13 : ONLP_THERMAL_ID_CREATE(13) + - THERMAL14 : ONLP_THERMAL_ID_CREATE(14) + - THERMAL15 : ONLP_THERMAL_ID_CREATE(15) + - THERMAL16 : ONLP_THERMAL_ID_CREATE(16) + + + portingmacro: + X86_64_QUANTA_IX2_RANGELEY: + macros: + - memset + - memcpy + - strncpy + - vsnprintf + - snprintf + - strlen diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley.x b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley.x new file mode 100755 index 00000000..abaf5abf --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley.x @@ -0,0 +1,14 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +/* <--auto.start.xmacro(ALL).define> */ +/* */ + +/* <--auto.start.xenum(ALL).define> */ +/* */ + + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_config.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_config.h new file mode 100755 index 00000000..ecc11080 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_config.h @@ -0,0 +1,167 @@ +/**************************************************************************//** + * + * @file + * @brief x86_64_quanta_ix2_rangeley Configuration Header + * + * @addtogroup x86_64_quanta_ix2_rangeley-config + * @{ + * + *****************************************************************************/ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_CONFIG_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_CONFIG_H__ + +#ifdef GLOBAL_INCLUDE_CUSTOM_CONFIG +#include +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_INCLUDE_CUSTOM_CONFIG +#include +#endif + +/* */ +#include +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING + * + * Include or exclude logging. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING 1 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT + * + * Default enabled log options. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT AIM_LOG_OPTIONS_DEFAULT +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT + * + * Default enabled log bits. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT AIM_LOG_BITS_DEFAULT +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT + * + * Default enabled custom log bits. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT 0 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB + * + * Default all porting macros to use the C standard libraries. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB 1 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS + * + * Include standard library headers for stdlib porting macros. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI + * + * Include generic uCli support. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI 0 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD + * + * RPM Threshold at which the fan is considered to have failed. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD 3000 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX + * + * Maximum system front-to-back fan speed. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX 18000 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX + * + * Maximum system back-to-front fan speed. */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX 18000 +#endif + +/** + * X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS + * + * Time to hold Phy GPIO in reset, in ms */ + + +#ifndef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS +#define X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS 100 +#endif + + + +/** + * All compile time options can be queried or displayed + */ + +/** Configuration settings structure. */ +typedef struct x86_64_quanta_ix2_rangeley_config_settings_s { + /** name */ + const char* name; + /** value */ + const char* value; +} x86_64_quanta_ix2_rangeley_config_settings_t; + +/** Configuration settings table. */ +/** x86_64_quanta_ix2_rangeley_config_settings table. */ +extern x86_64_quanta_ix2_rangeley_config_settings_t x86_64_quanta_ix2_rangeley_config_settings[]; + +/** + * @brief Lookup a configuration setting. + * @param setting The name of the configuration option to lookup. + */ +const char* x86_64_quanta_ix2_rangeley_config_lookup(const char* setting); + +/** + * @brief Show the compile-time configuration. + * @param pvs The output stream. + */ +int x86_64_quanta_ix2_rangeley_config_show(struct aim_pvs_s* pvs); + +/* */ + +#include "x86_64_quanta_ix2_rangeley_porting.h" + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_CONFIG_H__ */ +/* @} */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_dox.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_dox.h new file mode 100755 index 00000000..871a3c0b --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_dox.h @@ -0,0 +1,26 @@ +/**************************************************************************//** + * + * x86_64_quanta_ix2_rangeley Doxygen Header + * + *****************************************************************************/ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_DOX_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_DOX_H__ + +/** + * @defgroup x86_64_quanta_ix2_rangeley x86_64_quanta_ix2_rangeley - x86_64_quanta_ix2_rangeley Description + * + +The documentation overview for this module should go here. + + * + * @{ + * + * @defgroup x86_64_quanta_ix2_rangeley-x86_64_quanta_ix2_rangeley Public Interface + * @defgroup x86_64_quanta_ix2_rangeley-config Compile Time Configuration + * @defgroup x86_64_quanta_ix2_rangeley-porting Porting Macros + * + * @} + * + */ + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_DOX_H__ */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h new file mode 100755 index 00000000..053b4606 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h @@ -0,0 +1,63 @@ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_GPIO_TABLE_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_GPIO_TABLE_H__ + +/* + * defined within platform/quanta_switch.c + * Quanta Switch Platform driver + */ +#define QUANTA_IX2_PCA953x_GPIO(P1, P2) (P1*8+P2) + +#define QUANTA_IX2_PCA9555_GPIO_SIZE 0x10 + +#define QUANTA_IX2_I2C_GPIO_CPU_BASE 0x40 + +#define QUANTA_IX2_CPU_BOARD_GPIO_BASE (QUANTA_IX2_I2C_GPIO_CPU_BASE) +#define QUANTA_IX2_CPU_BOARD_SYS_P1 (QUANTA_IX2_CPU_BOARD_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) +#define QUANTA_IX2_CPU_BOARD_SYS_P2 (QUANTA_IX2_CPU_BOARD_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,3)) + +#define QUANTA_IX2_PSU_GPIO_BASE 0x10 +#define QUANTA_IX2_PSU_GPIO_SIZE QUANTA_IX2_PCA9555_GPIO_SIZE +#define QUANTA_IX2_PSU_GPIO_PSU1_PRSNT_N (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,0)) +#define QUANTA_IX2_PSU_GPIO_PSU1_PWRGD (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,1)) +#define QUANTA_IX2_PSU_GPIO_PSU2_PRSNT_N (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,3)) +#define QUANTA_IX2_PSU_GPIO_PSU2_PWRGD (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,4)) +#define QUANTA_IX2_PSU_GPIO_PSU1_AC_OK (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,6)) +#define QUANTA_IX2_PSU_GPIO_PSU2_AC_OK (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,7)) +#define QUANTA_IX2_PSU_GPIO_PSU1_GREEN_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) +#define QUANTA_IX2_PSU_GPIO_PSU1_RED_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,3)) +#define QUANTA_IX2_PSU_GPIO_PSU2_GREEN_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,4)) +#define QUANTA_IX2_PSU_GPIO_PSU2_RED_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,5)) +#define QUANTA_IX2_PSU_GPIO_FAN_GREEN_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,6)) +#define QUANTA_IX2_PSU_GPIO_FAN_RED_R (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,7)) + +#define QUANTA_IX2_ZQSFP_EN_GPIO_BASE (QUANTA_IX2_PSU_GPIO_BASE + QUANTA_IX2_PSU_GPIO_SIZE) +#define QUANTA_IX2_ZQSFP_EN_GPIO_SIZE QUANTA_IX2_PCA9555_GPIO_SIZE +#define QUANTA_IX2_ZQSFP_EN_GPIO_P3V3_PW_GD (QUANTA_IX2_ZQSFP_EN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,4)) +#define QUANTA_IX2_ZQSFP_EN_GPIO_P3V3_PW_EN (QUANTA_IX2_ZQSFP_EN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,5)) + +#define QUANTA_IX2_FAN_GPIO_BASE (QUANTA_IX2_ZQSFP_EN_GPIO_BASE + QUANTA_IX2_ZQSFP_EN_GPIO_SIZE) +#define QUANTA_IX2_FAN_GPIO_SIZE QUANTA_IX2_PCA9555_GPIO_SIZE +#define QUANTA_IX2_FAN_PRSNT_N_1 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,4)) +#define QUANTA_IX2_FAN_PRSNT_N_2 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,5)) +#define QUANTA_IX2_FAN_PRSNT_N_3 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,6)) +#define QUANTA_IX2_FAN_PRSNT_N_4 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,7)) +#define QUANTA_IX2_FAN_BF_DET1 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,0)) +#define QUANTA_IX2_FAN_BF_DET2 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,1)) +#define QUANTA_IX2_FAN_BF_DET3 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) +#define QUANTA_IX2_FAN_BF_DET4 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,3)) +#define QUANTA_IX2_FAN_FAIL_LED_1 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,4)) +#define QUANTA_IX2_FAN_FAIL_LED_2 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,5)) +#define QUANTA_IX2_FAN_FAIL_LED_3 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,6)) +#define QUANTA_IX2_FAN_FAIL_LED_4 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,7)) + +#define QUANTA_IX2_PCA9698_1_GPIO_BASE 0x50 +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_1_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_2_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_3_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_4_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_5_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_6_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_7_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_8_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,6)) + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_GPIO_TABLE_H__ */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_porting.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_porting.h new file mode 100755 index 00000000..f98fe673 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_porting.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * + * @file + * @brief x86_64_quanta_ix2_rangeley Porting Macros. + * + * @addtogroup x86_64_quanta_ix2_rangeley-porting + * @{ + * + *****************************************************************************/ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_PORTING_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_PORTING_H__ + + +/* */ +#if X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS == 1 +#include +#include +#include +#include +#include +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_MEMSET + #if defined(GLOBAL_MEMSET) + #define X86_64_QUANTA_IX2_RANGELEY_MEMSET GLOBAL_MEMSET + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_MEMSET memset + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_MEMSET is required but cannot be defined. + #endif +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_MEMCPY + #if defined(GLOBAL_MEMCPY) + #define X86_64_QUANTA_IX2_RANGELEY_MEMCPY GLOBAL_MEMCPY + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_MEMCPY memcpy + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_MEMCPY is required but cannot be defined. + #endif +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_STRNCPY + #if defined(GLOBAL_STRNCPY) + #define X86_64_QUANTA_IX2_RANGELEY_STRNCPY GLOBAL_STRNCPY + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_STRNCPY strncpy + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_STRNCPY is required but cannot be defined. + #endif +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_VSNPRINTF + #if defined(GLOBAL_VSNPRINTF) + #define X86_64_QUANTA_IX2_RANGELEY_VSNPRINTF GLOBAL_VSNPRINTF + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_VSNPRINTF vsnprintf + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_VSNPRINTF is required but cannot be defined. + #endif +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_SNPRINTF + #if defined(GLOBAL_SNPRINTF) + #define X86_64_QUANTA_IX2_RANGELEY_SNPRINTF GLOBAL_SNPRINTF + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_SNPRINTF snprintf + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_SNPRINTF is required but cannot be defined. + #endif +#endif + +#ifndef X86_64_QUANTA_IX2_RANGELEY_STRLEN + #if defined(GLOBAL_STRLEN) + #define X86_64_QUANTA_IX2_RANGELEY_STRLEN GLOBAL_STRLEN + #elif X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB == 1 + #define X86_64_QUANTA_IX2_RANGELEY_STRLEN strlen + #else + #error The macro X86_64_QUANTA_IX2_RANGELEY_STRLEN is required but cannot be defined. + #endif +#endif + +/* */ + + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_PORTING_H__ */ +/* @} */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/make.mk b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/make.mk new file mode 100755 index 00000000..ad096ba5 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/make.mk @@ -0,0 +1,10 @@ +############################################################################### +# +# +# +############################################################################### +THIS_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +x86_64_quanta_ix2_rangeley_INCLUDES := -I $(THIS_DIR)inc +x86_64_quanta_ix2_rangeley_INTERNAL_INCLUDES := -I $(THIS_DIR)src +x86_64_quanta_ix2_rangeley_DEPENDMODULE_ENTRIES := init:x86_64_quanta_ix2_rangeley ucli:x86_64_quanta_ix2_rangeley + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/Makefile new file mode 100755 index 00000000..aa08362c --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/Makefile @@ -0,0 +1,9 @@ +############################################################################### +# +# Local source generation targets. +# +############################################################################### + +ucli: + @../../../../tools/uclihandlers.py x86_64_quanta_ix2_rangeley_ucli.c + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/fani.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/fani.c new file mode 100755 index 00000000..184e7199 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/fani.c @@ -0,0 +1,172 @@ +/************************************************************ + * + * + * Copyright 2014 Big Switch Networks, Inc. + * + * Licensed under the Eclipse Public License, Version 1.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.eclipse.org/legal/epl-v10.html + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific + * language governing permissions and limitations under the + * License. + * + * + ************************************************************ + * + * + * + ***********************************************************/ +#include +#include +#include + +#include "x86_64_quanta_ix2_rangeley_int.h" +#include "x86_64_quanta_ix2_rangeley_log.h" + +#include +#include + +int +onlp_fani_init(void) +{ + return ONLP_STATUS_OK; +} + +struct fan_gpio_s { + int present; + int fan_dir_detect; +}; + +static struct fan_gpio_s fan_gpio[] = { + {}, /* Not used */ + { .present = QUANTA_IX2_FAN_PRSNT_N_1, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET1 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_2, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET2 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_3, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET3 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_4, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET4 }, + //{}, /* Not used */ + { .present = QUANTA_IX2_FAN_PRSNT_N_1, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET1 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_2, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET2 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_3, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET3 }, + { .present = QUANTA_IX2_FAN_PRSNT_N_4, .fan_dir_detect = QUANTA_IX2_FAN_BF_DET4 }, + //{}, /* Not used */ +}; + +static int +sys_fan_info_get__(onlp_fan_info_t* info, int id) +{ + int value = 0; + int rv; + + if(onlp_gpio_get(fan_gpio[id].present, &value) == ONLP_STATUS_OK + && value == 0) { + info->status = ONLP_FAN_STATUS_PRESENT; + if(onlp_gpio_get(fan_gpio[id].fan_dir_detect, &value) == ONLP_STATUS_OK + && value == 0) { + info->status |= ONLP_FAN_STATUS_F2B; + info->caps |= ONLP_FAN_CAPS_F2B; + } + else { + info->status |= ONLP_FAN_STATUS_B2F; + info->caps |= ONLP_FAN_CAPS_B2F; + } + } + else { + info->status = ONLP_FAN_STATUS_FAILED; + } + + rv = onlp_file_read_int(&info->rpm, + SYS_HWMON_PREFIX "/fan%d_input", id); + + if(rv == ONLP_STATUS_E_INTERNAL) { + return rv; + } + + if(rv == ONLP_STATUS_E_MISSING) { + info->status &= ~1; + return 0; + } + + if(info->rpm <= X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD) { + info->status |= ONLP_FAN_STATUS_FAILED; + } + + /* + * Calculate percentage based on current speed and the maximum. + */ + info->caps |= ONLP_FAN_CAPS_GET_PERCENTAGE; + if(info->status & ONLP_FAN_STATUS_F2B) { + info->percentage = (int) ((double) info->rpm * (double)100 / (double)X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX); + } + if(info->status & ONLP_FAN_STATUS_B2F) { + info->percentage = (int) ((double) info->rpm * (double)100 / (double)X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX); + } + + return 0; +} + +static int +psu_fan_info_get__(onlp_fan_info_t* info, int id) +{ + extern struct psu_info_s psu_info[]; + char* dir = psu_info[id].path; + + return onlp_file_read_int(&info->rpm, "%s*fan1_input", dir); +} + + +/* Onboard Fans */ +static onlp_fan_info_t fans__[] = { + { }, /* Not used */ + { { FAN_OID_FAN1, "Left (Module/Fan 1/1)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN2, "Center-L(Module/Fan 2/1)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN3, "Center-R(Module/Fan 3/1)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN4, "Right (Module/Fan 4/1)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN5, "Left (Module/Fan 1/2)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN6, "Center-L(Module/Fan 2/2)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN7, "Center-R(Module/Fan 3/2)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN8, "Right (Module/Fan 4/2)", 0}, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN9, "PSU-1 Fan", 0 }, ONLP_FAN_STATUS_PRESENT }, + { { FAN_OID_FAN10, "PSU-2 Fan", 0 }, ONLP_FAN_STATUS_PRESENT }, + +}; + +int +onlp_fani_info_get(onlp_oid_t id, onlp_fan_info_t* rv) +{ + int fid = ONLP_OID_ID_GET(id); + + *rv = fans__[ONLP_OID_ID_GET(id)]; + rv->caps |= ONLP_FAN_CAPS_GET_RPM; + + switch(fid) { + case FAN_ID_FAN1: + case FAN_ID_FAN2: + case FAN_ID_FAN3: + case FAN_ID_FAN4: + case FAN_ID_FAN5: + case FAN_ID_FAN6: + case FAN_ID_FAN7: + case FAN_ID_FAN8: + return sys_fan_info_get__(rv, fid); + break; + + case FAN_ID_FAN9: + case FAN_ID_FAN10: + return psu_fan_info_get__(rv, fid - FAN_ID_FAN9 + 1); + break; + + default: + return ONLP_STATUS_E_INVALID; + break; + } + + return ONLP_STATUS_E_INVALID; +} + + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/ledi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/ledi.c new file mode 100755 index 00000000..2b616aad --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/ledi.c @@ -0,0 +1,229 @@ +#include +#include +#include +#include +#include + +#include "x86_64_quanta_ix2_rangeley_int.h" +#include +#include + +/* + * Get the information for the given LED OID. + */ +static onlp_led_info_t led_info[] = +{ + { }, /* Not used */ + { + { LED_OID_SYSTEM, "System LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_ORANGE | ONLP_LED_CAPS_GREEN, + }, + { + { LED_OID_FAN, "Front FAN LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN, + }, + { + { LED_OID_PSU_1, "Front PSU(1) LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN, + }, + { + { LED_OID_PSU_2, "Front PSU(2) LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED | ONLP_LED_CAPS_GREEN, + }, + { + { LED_OID_FAN_FAIL_1, "FAN(1) fail LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED, + }, + { + { LED_OID_FAN_FAIL_2, "FAN(2) fail LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED, + }, + { + { LED_OID_FAN_FAIL_3, "FAN(3) fail LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED, + }, + { + { LED_OID_FAN_FAIL_4, "FAN(4) fail LED", 0 }, + ONLP_LED_STATUS_PRESENT, + ONLP_LED_CAPS_ON_OFF | ONLP_LED_CAPS_RED, + } +}; + +int +onlp_ledi_init(void) +{ + return ONLP_STATUS_OK; +} + +int +onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info) +{ + + int led_id; + + led_id = ONLP_OID_ID_GET(id); + + *info = led_info[led_id]; + info->status |= ONLP_LED_STATUS_ON; + info->mode |= ONLP_LED_MODE_ON; + + return ONLP_STATUS_OK; +} + +void +Sysfs_Set_System_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_GREEN){ + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P1, 0); + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P2, 1); + } + else if(mode == ONLP_LED_MODE_ORANGE){ + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P1, 1); + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P2, 0); + } + else{ + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P1, 1); + onlp_gpio_set(QUANTA_IX2_CPU_BOARD_SYS_P2, 1); + } +} + +void +Sysfs_Set_Fan_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_GREEN){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_GREEN_R, 1); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_RED_R, 0); + } + else if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_RED_R, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_FAN_RED_R, 0); + } +} + +void +Sysfs_Set_Psu1_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_GREEN){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_GREEN_R, 1); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_RED_R, 0); + } + else if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_RED_R, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU1_RED_R, 0); + } +} + +void +Sysfs_Set_Psu2_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_GREEN){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_GREEN_R, 1); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_RED_R, 0); + } + else if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_RED_R, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_GREEN_R, 0); + onlp_gpio_set(QUANTA_IX2_PSU_GPIO_PSU2_RED_R, 0); + } +} + +void +Sysfs_Set_Fan_Fail1_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_1, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_1, 0); + } +} + +void +Sysfs_Set_Fan_Fail2_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_2, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_2, 0); + } +} + +void +Sysfs_Set_Fan_Fail3_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_3, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_3, 0); + } +} + +void +Sysfs_Set_Fan_Fail4_LED(onlp_led_mode_t mode) +{ + if(mode == ONLP_LED_MODE_RED){ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_4, 1); + } + else{ + onlp_gpio_set(QUANTA_IX2_FAN_FAIL_LED_4, 0); + } +} + +int +onlp_ledi_mode_set(onlp_oid_t id, onlp_led_mode_t mode) +{ + int led_id; + + led_id = ONLP_OID_ID_GET(id); + switch (led_id) { + case LED_ID_SYSTEM: + Sysfs_Set_System_LED(mode); + break; + case LED_ID_FAN: + Sysfs_Set_Fan_LED(mode); + break; + case LED_ID_PSU_1: + Sysfs_Set_Psu1_LED(mode); + break; + case LED_ID_PSU_2: + Sysfs_Set_Psu2_LED(mode); + break; + case LED_ID_FAN_FAIL_1: + Sysfs_Set_Fan_Fail1_LED(mode); + break; + case LED_ID_FAN_FAIL_2: + Sysfs_Set_Fan_Fail2_LED(mode); + break; + case LED_ID_FAN_FAIL_3: + Sysfs_Set_Fan_Fail3_LED(mode); + break; + case LED_ID_FAN_FAIL_4: + Sysfs_Set_Fan_Fail4_LED(mode); + break; + default: + return ONLP_STATUS_E_INTERNAL; + break; + } + + return ONLP_STATUS_OK; +} diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/make.mk b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/make.mk new file mode 100755 index 00000000..df3c695d --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/make.mk @@ -0,0 +1,9 @@ +############################################################################### +# +# +# +############################################################################### + +LIBRARY := x86_64_quanta_ix2_rangeley +$(LIBRARY)_SUBDIR := $(dir $(lastword $(MAKEFILE_LIST))) +include $(BUILDER)/lib.mk diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/psui.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/psui.c new file mode 100755 index 00000000..eab99789 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/psui.c @@ -0,0 +1,118 @@ +/************************************************************ + * + * + ************************************************************ + * + * + * + ***********************************************************/ +#include +#include +#include +#include +#include +#include "x86_64_quanta_ix2_rangeley_int.h" +#include "x86_64_quanta_ix2_rangeley_log.h" + +struct psu_info_s psu_info[] = { + {}, /* Not used */ + { .path = "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-20/20-005f", .present = QUANTA_IX2_PSU_GPIO_PSU1_PRSNT_N, .busno = 20, .addr = 0x5f}, + { .path = "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-21/21-0059", .present = QUANTA_IX2_PSU_GPIO_PSU2_PRSNT_N, .busno = 21, .addr = 0x59}, +}; + +int +onlp_psui_init(void) +{ + return 0; +} + +static onlp_psu_info_t psus__[] = { + { }, /* Not used */ + { + { + PSU_OID_PSU1, + "Quanta IX2 RPSU-1", + 0, + { + FAN_OID_FAN9, + }, + } + }, + { + { + PSU_OID_PSU2, + "Quanta IX2 RPSU-2", + 0, + { + FAN_OID_FAN10, + }, + } + }, +}; + +#define PMBUS_MFR_MODEL 0x9A +#define PMBUS_MFR_SERIAL 0x9E +#define PMBUS_MFR_MODEL_LEN 20 +#define PMBUS_MFR_SERIAL_LEN 19 + +int +onlp_psui_info_get(onlp_oid_t id, onlp_psu_info_t* info) +{ + int rv; + int pid = ONLP_OID_ID_GET(id); + *info = psus__[pid]; + const char* dir = psu_info[pid].path; + unsigned char buffer[ONLP_CONFIG_INFO_STR_MAX]; + int value = -1, len; + + rv = onlp_gpio_get(psu_info[pid].present, &value); + if(rv < 0) { + return rv; + } + else if(value == 1) { + info->status &= ~1; + return 0; + } + + if(onlp_file_read_int(&info->mvin, "%s*in1_input", dir) == 0 && info->mvin >= 0) { + info->caps |= ONLP_PSU_CAPS_VIN; + } + + /* PSU is present and powered. */ + info->status |= 1; + + len = PMBUS_MFR_MODEL_LEN; + if(onlp_file_read(buffer, sizeof(buffer), &len, "%s*mfr_model", dir) != 0){ + AIM_LOG_ERROR("Read PMBUS_MFR_MODEL ###ERROR###");; + } + aim_strlcpy(info->model, (char *) buffer, 16); + + len = PMBUS_MFR_SERIAL_LEN; + if(onlp_file_read(buffer, sizeof(buffer), &len, "%s*mfr_serial", dir) != 0){ + AIM_LOG_ERROR("Read PMBUS_MFR_SERIAL ###ERROR###");; + } + aim_strlcpy(info->serial, (char *) buffer, 14);; + + info->caps |= ONLP_PSU_CAPS_AC; + + if(onlp_file_read_int(&info->miin, "%s*curr1_input", dir) == 0 && info->miin >= 0) { + info->caps |= ONLP_PSU_CAPS_IIN; + } + if(onlp_file_read_int(&info->miout, "%s*curr2_input", dir) == 0 && info->miout >= 0) { + info->caps |= ONLP_PSU_CAPS_IOUT; + } + if(onlp_file_read_int(&info->mvout, "%s*in2_input", dir) == 0 && info->mvout >= 0) { + info->caps |= ONLP_PSU_CAPS_VOUT; + } + if(onlp_file_read_int(&info->mpin, "%s*power1_input", dir) == 0 && info->mpin >= 0) { + info->caps |= ONLP_PSU_CAPS_PIN; + /* The pmbus driver reports power in micro-units */ + info->mpin /= 1000; + } + if(onlp_file_read_int(&info->mpout, "%s*power2_input", dir) == 0 && info->mpout >= 0) { + info->caps |= ONLP_PSU_CAPS_POUT; + /* the pmbus driver reports power in micro-units */ + info->mpout /= 1000; + } + return ONLP_STATUS_OK; +} diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c new file mode 100755 index 00000000..05243a0f --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c @@ -0,0 +1,222 @@ +/************************************************************ + * + * + * Copyright 2014 Big Switch Networks, Inc. + * + * Licensed under the Eclipse Public License, Version 1.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.eclipse.org/legal/epl-v10.html + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific + * language governing permissions and limitations under the + * License. + * + * + ************************************************************ + * + * SFPI Interface for the Quanta IX2 + * + ***********************************************************/ +#include +#include +#include +#include +#include +#include "x86_64_quanta_ix2_rangeley_log.h" + +#include +#include + +/** + * This table maps the presence gpio, reset gpio, and eeprom file + * for each SFP port. + */ +typedef struct sfpmap_s { + int port; + const char* present_cpld; + const char* reset_gpio; + const char* eeprom; + const char* dom; +} sfpmap_t; + +static sfpmap_t sfpmap__[] = + { + { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-1/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, + { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-2/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, + { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-3/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, + { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-4/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, + { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-5/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, + { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-6/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, + { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-7/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, + { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-8/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, + { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-9/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, + { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-10/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, + { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-11/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, + { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-12/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, + { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-13/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, + { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-14/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, + { 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-15/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL }, + { 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-16/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL }, + { 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-17/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL }, + { 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-18/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL }, + { 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-19/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL }, + { 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-20/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL }, + { 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-21/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL }, + { 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-22/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL }, + { 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-23/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, + { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-24/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, + { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-25/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, + { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-26/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, + { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-27/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, + { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-28/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, + { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-29/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, + { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-30/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, + { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-31/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, + { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-32/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, + { 33, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-33/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-64/64-0050/eeprom", NULL }, + { 34, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-34/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-65/65-0050/eeprom", NULL }, + { 35, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-35/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-66/66-0050/eeprom", NULL }, + { 36, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-36/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-67/67-0050/eeprom", NULL }, + { 37, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-37/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-68/68-0050/eeprom", NULL }, + { 38, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-38/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-69/69-0050/eeprom", NULL }, + { 39, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-39/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-70/70-0050/eeprom", NULL }, + { 40, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-40/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-71/71-0050/eeprom", NULL }, + { 41, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-41/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-72/72-0050/eeprom", NULL }, + { 42, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-42/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-73/73-0050/eeprom", NULL }, + { 43, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-43/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-74/74-0050/eeprom", NULL }, + { 44, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-44/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-75/75-0050/eeprom", NULL }, + { 45, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-45/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-76/76-0050/eeprom", NULL }, + { 46, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-46/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-77/77-0050/eeprom", NULL }, + { 47, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-47/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-78/78-0050/eeprom", NULL }, + { 48, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-qsfp28/port-48/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-79/79-0050/eeprom", NULL }, + }; + +typedef struct qsfpmap_s { + int port; + int present_gpio; + const char* reset_gpio; + const char* eeprom; + const char* dom; +} qsfpmap_t; + +static qsfpmap_t qsfpmap__[] = + { + { 49, QUANTA_IX2_PCA9698_1_GPIO_QSFP_1_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-80/80-0050/eeprom", NULL }, + { 50, QUANTA_IX2_PCA9698_1_GPIO_QSFP_2_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-81/81-0050/eeprom", NULL }, + { 51, QUANTA_IX2_PCA9698_1_GPIO_QSFP_3_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-82/82-0050/eeprom", NULL }, + { 52, QUANTA_IX2_PCA9698_1_GPIO_QSFP_4_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-83/83-0050/eeprom", NULL }, + { 53, QUANTA_IX2_PCA9698_1_GPIO_QSFP_5_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-84/84-0050/eeprom", NULL }, + { 54, QUANTA_IX2_PCA9698_1_GPIO_QSFP_6_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-85/85-0050/eeprom", NULL }, + { 55, QUANTA_IX2_PCA9698_1_GPIO_QSFP_7_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-86/86-0050/eeprom", NULL }, + { 56, QUANTA_IX2_PCA9698_1_GPIO_QSFP_8_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-87/87-0050/eeprom", NULL }, + }; + +#define SFP_GET(_port) (sfpmap__ + _port - 1) +#define QSFP_GET(_port) (qsfpmap__ + _port - 49) + +int +onlp_sfpi_init(void) +{ + int ret, i; + qsfpmap_t* qsfp; + + onlp_gpio_export(QUANTA_IX2_ZQSFP_EN_GPIO_P3V3_PW_EN, ONLP_GPIO_DIRECTION_OUT); + ret = onlp_gpio_set(QUANTA_IX2_ZQSFP_EN_GPIO_P3V3_PW_EN, 1); + sleep(1); + + for(i = 49; i < 57 ; i ++) { + qsfp = QSFP_GET(i); + onlp_gpio_export(qsfp->present_gpio, ONLP_GPIO_DIRECTION_IN); + } + + return ret; +} + +int +onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap) +{ + int p; + + for(p = 1; p < 57; p++) { + AIM_BITMAP_SET(bmap, p); + } + + return ONLP_STATUS_OK; +} + +int +onlp_sfpi_is_present(int port) +{ + if(port > 48){ + int value = 0; + qsfpmap_t* qsfp = QSFP_GET(port); + + if(qsfp->present_gpio > 0) { + if(onlp_gpio_get(qsfp->present_gpio, &value) == ONLP_STATUS_OK) + return (value == 0); + else + return ONLP_STATUS_E_MISSING; + } + else { + /** + * If we can open and read a byte from the EEPROM file + * then we consider it present. + */ + int fd = open(qsfp->eeprom, O_RDONLY); + if (fd < 0) { + /* Not Present */ + return 0; + } + int rv; + uint8_t byte; + + if(read(fd, &byte, 1) == 1) { + /* Present */ + rv = 1; + } + else { + /* No Present */ + rv = 0; + } + close(fd); + return rv; + } + } + else{ + sfpmap_t* sfp = SFP_GET(port); + + return onlplib_sfp_is_present_file(sfp->present_cpld, /* Present */ "1\n", /* Absent */ "0\n"); + } +} + +int +onlp_sfpi_eeprom_read(int port, uint8_t data[256]) +{ + if(port > 48){ + qsfpmap_t* qsfp = QSFP_GET(port); + return onlplib_sfp_eeprom_read_file(qsfp->eeprom, data); + } + else{ + sfpmap_t* sfp = SFP_GET(port); + return onlplib_sfp_eeprom_read_file(sfp->eeprom, data); + } +} + +int +onlp_sfpi_dom_read(int port, uint8_t data[256]) +{ + if(port > 48){ + qsfpmap_t* qsfp = QSFP_GET(port); + return onlplib_sfp_eeprom_read_file(qsfp->dom, data); + } + else{ + sfpmap_t* sfp = SFP_GET(port); + return onlplib_sfp_eeprom_read_file(sfp->dom, data); + } +} + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sysi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sysi.c new file mode 100755 index 00000000..3455aad3 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sysi.c @@ -0,0 +1,288 @@ +/************************************************************ + * + * + ************************************************************ + * + * + * + ***********************************************************/ +#include +#include "x86_64_quanta_ix2_rangeley_int.h" +#include "x86_64_quanta_ix2_rangeley_log.h" +#include +#include +#include +#include +#include + +struct led_control_s led_control; + +#define QUANTA_HWMON_REG_TEMP_ALERT_MASK 0x1E +#define QUANTA_HWMON_REG_TEMP_ALERT_CTRL 0x1D +#define QUANTA_HWMON_REG_FAN_ALERT_MASK 0x31 +#define QUANTA_HWMON_REG_FAN_ALERT_CTRL 0x30 +#define PSOC_REG_FAN_ALERT_STATUS 0x32 + +#define QUANTA_FAN_1_1 0x01 +#define QUANTA_FAN_1_2 0x10 +#define QUANTA_FAN_2_1 0x02 +#define QUANTA_FAN_2_2 0x20 +#define QUANTA_FAN_3_1 0x04 +#define QUANTA_FAN_3_2 0x40 +#define QUANTA_FAN_4_1 0x08 +#define QUANTA_FAN_4_2 0x80 + +const char* +onlp_sysi_platform_get(void) +{ + return "x86-64-quanta-ix2-rangeley-r0"; +} + +int +onlp_sysi_init(void) +{ + /* Initial value */ + led_control.PMCnt = 0; + led_control.fan_alert = 0xff; + led_control.psu1_present = 0; + led_control.psu2_present = 0; + led_control.psu1_power_good = 0; + led_control.psu2_power_good = 0; + + /* Set PSoc Fan-Alert Enable */ + onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_TEMP_ALERT_MASK, 0x77, ONLP_I2C_F_FORCE); + onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_TEMP_ALERT_CTRL, 0x3, ONLP_I2C_F_FORCE); + onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_FAN_ALERT_MASK, 0xff, ONLP_I2C_F_FORCE); + onlp_i2c_writeb(0, 0x4e, QUANTA_HWMON_REG_FAN_ALERT_CTRL, 0x1, ONLP_I2C_F_FORCE); + + /* Config GPIO */ + /* LED Output */ + onlp_gpio_export(QUANTA_IX2_CPU_BOARD_SYS_P1, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_CPU_BOARD_SYS_P2, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU1_GREEN_R, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU1_RED_R, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU2_GREEN_R, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU2_RED_R, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_FAN_FAIL_LED_1, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_FAN_FAIL_LED_2, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_FAN_FAIL_LED_3, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_FAN_FAIL_LED_4, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_FAN_GREEN_R, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_FAN_RED_R, ONLP_GPIO_DIRECTION_OUT); + /* PSU Input */ + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU1_PRSNT_N, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU1_PWRGD, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU2_PRSNT_N, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_PSU_GPIO_PSU2_PWRGD, ONLP_GPIO_DIRECTION_IN); + /* FAN Input */ + onlp_gpio_export(QUANTA_IX2_FAN_PRSNT_N_1, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_FAN_PRSNT_N_2, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_FAN_PRSNT_N_3, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(QUANTA_IX2_FAN_PRSNT_N_4, ONLP_GPIO_DIRECTION_IN); + + /* Set LED to green */ + onlp_ledi_mode_set(LED_OID_SYSTEM, ONLP_LED_MODE_GREEN); + led_control.psu_status_changed = 1; + led_control.fan_status_changed = 1; + onlp_sysi_platform_manage_leds(); + + return ONLP_STATUS_OK; +} + +#define QUANTA_SYS_EEPROM_PATH \ +"/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-22/22-0054/eeprom" + +int +onlp_sysi_onie_info_get(onlp_onie_info_t* onie) +{ + int rv; + + rv = onlp_onie_decode_file(onie, QUANTA_SYS_EEPROM_PATH); + if(rv >= 0) { + onie->platform_name = aim_strdup("x86-64-quanta-ix2-rangeley-r0"); + rv = quanta_onie_sys_eeprom_custom_format(onie); + } + return rv; +} + +int +onlp_sysi_oids_get(onlp_oid_t* table, int max) +{ + onlp_oid_t* e = table; + memset(table, 0, max*sizeof(onlp_oid_t)); + + /* + * 6 Chassis Thermal Sensors + */ + *e++ = THERMAL_OID_THERMAL1; + *e++ = THERMAL_OID_THERMAL2; + *e++ = THERMAL_OID_THERMAL3; + *e++ = THERMAL_OID_THERMAL5; + *e++ = THERMAL_OID_THERMAL6; + *e++ = THERMAL_OID_THERMAL7; + + /* + * 8 Fans + */ + *e++ = FAN_OID_FAN1; + *e++ = FAN_OID_FAN2; + *e++ = FAN_OID_FAN3; + *e++ = FAN_OID_FAN4; + *e++ = FAN_OID_FAN5; + *e++ = FAN_OID_FAN6; + *e++ = FAN_OID_FAN7; + *e++ = FAN_OID_FAN8; + + /* + * 2 PSUs + */ + *e++ = PSU_OID_PSU1; + *e++ = PSU_OID_PSU2; + + /* + * 8 LEDs + */ + *e++ = LED_OID_SYSTEM; + *e++ = LED_OID_FAN; + *e++ = LED_OID_PSU_1; + *e++ = LED_OID_PSU_2; + *e++ = LED_OID_FAN_FAIL_1; + *e++ = LED_OID_FAN_FAIL_2; + *e++ = LED_OID_FAN_FAIL_3; + *e++ = LED_OID_FAN_FAIL_4; + + return 0; +} + +int +update_rpsu_fan_status(void){ + int last_status, rv, value = -1, tmp; + + last_status = led_control.psu1_present; + rv = onlp_gpio_get(QUANTA_IX2_PSU_GPIO_PSU1_PRSNT_N, &value); + if(rv < 0) { + AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX2_PSU_GPIO_PSU1_PRSNT_N); + return rv; + } + led_control.psu1_present = (value ? 0 : 1); + if(last_status != led_control.psu1_present) + led_control.psu_status_changed = 1; + + last_status = led_control.psu1_power_good; + rv = onlp_gpio_get(QUANTA_IX2_PSU_GPIO_PSU1_PWRGD, &value); + if(rv < 0) { + AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX2_PSU_GPIO_PSU1_PWRGD); + return rv; + } + led_control.psu1_power_good = (value ? 1 : 0); + if(last_status != led_control.psu1_power_good) + led_control.psu_status_changed = 1; + + last_status = led_control.psu2_present; + rv = onlp_gpio_get(QUANTA_IX2_PSU_GPIO_PSU2_PRSNT_N, &value); + if(rv < 0) { + AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX2_PSU_GPIO_PSU2_PRSNT_N); + return rv; + } + led_control.psu2_present = (value ? 0 : 1); + if(last_status != led_control.psu2_present) + led_control.psu_status_changed = 1; + + last_status = led_control.psu2_power_good; + rv = onlp_gpio_get(QUANTA_IX2_PSU_GPIO_PSU2_PWRGD, &value); + if(rv < 0) { + AIM_LOG_ERROR("GPIO %d read Error!", QUANTA_IX2_PSU_GPIO_PSU2_PWRGD); + return rv; + } + led_control.psu2_power_good = (value ? 1 : 0); + if(last_status != led_control.psu2_power_good) + led_control.psu_status_changed = 1; + + tmp = led_control.fan_alert; + led_control.fan_alert = onlp_i2c_readb(0, 0x4e, PSOC_REG_FAN_ALERT_STATUS, ONLP_I2C_F_FORCE); + if(tmp != led_control.fan_alert) + led_control.fan_status_changed = 1; + + return ONLP_STATUS_OK; +} + +int +onlp_sysi_platform_manage_leds(void) +{ + int rv; + + led_control.PMCnt++; + if(led_control.PMCnt>300) + led_control.PMCnt = 0; + if(led_control.PMCnt % 5 == 1){/* Each 10 seconds detect one time */ + + rv = update_rpsu_fan_status(); + if(rv < 0){ + printf("onlp_sysi_platform_manage_leds error\n"); + return ONLP_STATUS_E_INVALID; + } + + if(led_control.psu_status_changed){ + if(led_control.psu1_present && led_control.psu1_power_good) { + onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_GREEN); + } + else if(!led_control.psu1_present){ + onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_PSU_1, ONLP_LED_MODE_RED); + } + + if(led_control.psu2_present && led_control.psu2_power_good) { + onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_GREEN); + } + else if(!led_control.psu2_present){ + onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_PSU_2, ONLP_LED_MODE_RED); + } + led_control.psu_status_changed = 0; + } + + if(led_control.fan_status_changed){ + if(!(led_control.fan_alert & QUANTA_FAN_1_1) && !(led_control.fan_alert & QUANTA_FAN_1_2)) { + onlp_ledi_mode_set(LED_ID_FAN_FAIL_1, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_FAN_FAIL_1, ONLP_LED_MODE_RED); + } + + if(!(led_control.fan_alert & QUANTA_FAN_2_1) && !(led_control.fan_alert & QUANTA_FAN_2_2)) { + onlp_ledi_mode_set(LED_ID_FAN_FAIL_2, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_FAN_FAIL_2, ONLP_LED_MODE_RED); + } + + if(!(led_control.fan_alert & QUANTA_FAN_3_1) && !(led_control.fan_alert & QUANTA_FAN_3_2)) { + onlp_ledi_mode_set(LED_ID_FAN_FAIL_3, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_FAN_FAIL_3, ONLP_LED_MODE_RED); + } + + if(!(led_control.fan_alert & QUANTA_FAN_4_1) && !(led_control.fan_alert & QUANTA_FAN_4_2)) { + onlp_ledi_mode_set(LED_ID_FAN_FAIL_4, ONLP_LED_MODE_OFF); + } + else{ + onlp_ledi_mode_set(LED_ID_FAN_FAIL_4, ONLP_LED_MODE_RED); + } + + if(!led_control.fan_alert){ + onlp_ledi_mode_set(LED_ID_FAN, ONLP_LED_MODE_GREEN); + } + else{ + onlp_ledi_mode_set(LED_ID_FAN, ONLP_LED_MODE_RED); + } + led_control.fan_status_changed = 0; + } + } + + return ONLP_STATUS_OK; +} diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/thermali.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/thermali.c new file mode 100755 index 00000000..f130b960 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/thermali.c @@ -0,0 +1,146 @@ +/************************************************************ + * + * + * Copyright 2014 Big Switch Networks, Inc. + * + * Licensed under the Eclipse Public License, Version 1.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.eclipse.org/legal/epl-v10.html + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific + * language governing permissions and limitations under the + * License. + * + * + ************************************************************ + * + * + * + ***********************************************************/ +#include +#include +#include "x86_64_quanta_ix2_rangeley_int.h" +#include "x86_64_quanta_ix2_rangeley_log.h" + +int +onlp_thermali_init(void) +{ + return ONLP_STATUS_OK; +} + +static int +sys_thermal_info_get__(onlp_thermal_info_t* info, int id) +{ + int rv; + + rv = onlp_file_read_int(&info->mcelsius, + SYS_HWMON_PREFIX "/temp%d_input", id); + + if(rv == ONLP_STATUS_E_INTERNAL) { + return rv; + } + + if(rv == ONLP_STATUS_E_MISSING) { + info->status &= ~1; + return 0; + } + + return ONLP_STATUS_OK; +} + +static int +psu_thermal_info_get__(onlp_thermal_info_t* info, int pid, int id) +{ + /* THERMAL6 -> PSU1 */ + /* THERMAL7 -> PSU2 */ + extern struct psu_info_s psu_info[]; + char* dir = psu_info[pid].path; + + info->status |= 1; + return onlp_file_read_int(&info->mcelsius, "%s/temp%d_input", dir, id); +} + +int +onlp_thermali_info_get(onlp_oid_t id, onlp_thermal_info_t* rv) +{ + int tid = ONLP_OID_ID_GET(id); + + static onlp_thermal_info_t info[] = { + { }, /* Not used */ + { { ONLP_THERMAL_ID_CREATE(1), "Chassis Thermal 1", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(2), "Chassis Thermal 2", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(3), "Chassis Thermal 3", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(4), "Chassis Thermal 4", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(5), "Chassis Thermal 5", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(6), "Chassis Thermal 6", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(7), "Chassis Thermal 7", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(8), "Chassis Thermal 8", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(9), "Chassis Thermal 9", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + { { ONLP_THERMAL_ID_CREATE(10), "Chassis Thermal 10", 0}, ONLP_THERMAL_STATUS_PRESENT, + ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS + }, + + { { ONLP_THERMAL_ID_CREATE(11), "PSU-1 Thermal 1", 0 } }, + { { ONLP_THERMAL_ID_CREATE(12), "PSU-1 Thermal 2", 0 } }, + { { ONLP_THERMAL_ID_CREATE(13), "PSU-1 Thermal 3", 0 } }, + + { { ONLP_THERMAL_ID_CREATE(14), "PSU-2 Thermal 1", 0 } }, + { { ONLP_THERMAL_ID_CREATE(15), "PSU-2 Thermal 2", 0 } }, + { { ONLP_THERMAL_ID_CREATE(16), "PSU-2 Thermal 3", 0 } }, + }; + + *rv = info[tid]; + rv->caps |= ONLP_THERMAL_CAPS_GET_TEMPERATURE; + + switch(tid) + { + case THERMAL_ID_THERMAL1: + case THERMAL_ID_THERMAL2: + case THERMAL_ID_THERMAL3: + case THERMAL_ID_THERMAL4: + case THERMAL_ID_THERMAL5: + case THERMAL_ID_THERMAL6: + case THERMAL_ID_THERMAL7: + case THERMAL_ID_THERMAL8: + case THERMAL_ID_THERMAL9: + case THERMAL_ID_THERMAL10: + return sys_thermal_info_get__(rv, tid); + + case THERMAL_ID_THERMAL11: + case THERMAL_ID_THERMAL12: + case THERMAL_ID_THERMAL13: + return psu_thermal_info_get__(rv, 1, tid - THERMAL_ID_THERMAL11 + 1); + + + case THERMAL_ID_THERMAL14: + case THERMAL_ID_THERMAL15: + case THERMAL_ID_THERMAL16: + return psu_thermal_info_get__(rv, 2, tid - THERMAL_ID_THERMAL14 + 1); + + } + + return ONLP_STATUS_E_INVALID; +} diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_config.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_config.c new file mode 100755 index 00000000..c414758b --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_config.c @@ -0,0 +1,95 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +/* */ +#define __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(_x) #_x +#define __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(_x) __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(_x) +x86_64_quanta_ix2_rangeley_config_settings_t x86_64_quanta_ix2_rangeley_config_settings[] = +{ +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_LOGGING(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_STDLIB(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_PORTING_INCLUDE_STDLIB_HEADERS(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_RPM_FAILURE_THRESHOLD(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_F2B_RPM_MAX(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_SYSFAN_B2F_RPM_MAX(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif +#ifdef X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS + { __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS), __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE(X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS) }, +#else +{ X86_64_QUANTA_IX2_RANGELEY_CONFIG_PHY_RESET_DELAY_MS(__x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME), "__undefined__" }, +#endif + { NULL, NULL } +}; +#undef __x86_64_quanta_ix2_rangeley_config_STRINGIFY_VALUE +#undef __x86_64_quanta_ix2_rangeley_config_STRINGIFY_NAME + +const char* +x86_64_quanta_ix2_rangeley_config_lookup(const char* setting) +{ + int i; + for(i = 0; x86_64_quanta_ix2_rangeley_config_settings[i].name; i++) { + if(strcmp(x86_64_quanta_ix2_rangeley_config_settings[i].name, setting)) { + return x86_64_quanta_ix2_rangeley_config_settings[i].value; + } + } + return NULL; +} + +int +x86_64_quanta_ix2_rangeley_config_show(struct aim_pvs_s* pvs) +{ + int i; + for(i = 0; x86_64_quanta_ix2_rangeley_config_settings[i].name; i++) { + aim_printf(pvs, "%s = %s\n", x86_64_quanta_ix2_rangeley_config_settings[i].name, x86_64_quanta_ix2_rangeley_config_settings[i].value); + } + return i; +} + +/* */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_enums.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_enums.c new file mode 100755 index 00000000..33e7fdfd --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_enums.c @@ -0,0 +1,10 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +/* <--auto.start.enum(ALL).source> */ +/* */ + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_int.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_int.h new file mode 100755 index 00000000..27757bb2 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_int.h @@ -0,0 +1,308 @@ +/**************************************************************************//** + * + * x86_64_quanta_ix2_rangeley Internal Header + * + *****************************************************************************/ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_INT_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_INT_H__ + +#include +#include + +/* */ +/** thermal_oid */ +typedef enum thermal_oid_e { + THERMAL_OID_THERMAL1 = ONLP_THERMAL_ID_CREATE(1), + THERMAL_OID_THERMAL2 = ONLP_THERMAL_ID_CREATE(2), + THERMAL_OID_THERMAL3 = ONLP_THERMAL_ID_CREATE(3), + THERMAL_OID_THERMAL4 = ONLP_THERMAL_ID_CREATE(4), + THERMAL_OID_THERMAL5 = ONLP_THERMAL_ID_CREATE(5), + THERMAL_OID_THERMAL6 = ONLP_THERMAL_ID_CREATE(6), + THERMAL_OID_THERMAL7 = ONLP_THERMAL_ID_CREATE(7), + THERMAL_OID_THERMAL8 = ONLP_THERMAL_ID_CREATE(8), + THERMAL_OID_THERMAL9 = ONLP_THERMAL_ID_CREATE(9), + THERMAL_OID_THERMAL10 = ONLP_THERMAL_ID_CREATE(10), + THERMAL_OID_THERMAL11 = ONLP_THERMAL_ID_CREATE(11), + THERMAL_OID_THERMAL12 = ONLP_THERMAL_ID_CREATE(12), + THERMAL_OID_THERMAL13 = ONLP_THERMAL_ID_CREATE(13), + THERMAL_OID_THERMAL14 = ONLP_THERMAL_ID_CREATE(14), + THERMAL_OID_THERMAL15 = ONLP_THERMAL_ID_CREATE(15), + THERMAL_OID_THERMAL16 = ONLP_THERMAL_ID_CREATE(16), +} thermal_oid_t; + +/** Enum names. */ +const char* thermal_oid_name(thermal_oid_t e); + +/** Enum values. */ +int thermal_oid_value(const char* str, thermal_oid_t* e, int substr); + +/** Enum descriptions. */ +const char* thermal_oid_desc(thermal_oid_t e); + +/** Enum validator. */ +int thermal_oid_valid(thermal_oid_t e); + +/** validator */ +#define THERMAL_OID_VALID(_e) \ + (thermal_oid_valid((_e))) + +/** thermal_oid_map table. */ +extern aim_map_si_t thermal_oid_map[]; +/** thermal_oid_desc_map table. */ +extern aim_map_si_t thermal_oid_desc_map[]; + +/** psu_oid */ +typedef enum psu_oid_e { + PSU_OID_PSU1 = ONLP_PSU_ID_CREATE(1), + PSU_OID_PSU2 = ONLP_PSU_ID_CREATE(2), +} psu_oid_t; + +/** Enum names. */ +const char* psu_oid_name(psu_oid_t e); + +/** Enum values. */ +int psu_oid_value(const char* str, psu_oid_t* e, int substr); + +/** Enum descriptions. */ +const char* psu_oid_desc(psu_oid_t e); + +/** Enum validator. */ +int psu_oid_valid(psu_oid_t e); + +/** validator */ +#define PSU_OID_VALID(_e) \ + (psu_oid_valid((_e))) + +/** psu_oid_map table. */ +extern aim_map_si_t psu_oid_map[]; +/** psu_oid_desc_map table. */ +extern aim_map_si_t psu_oid_desc_map[]; + +/** thermal_id */ +typedef enum thermal_id_e { + THERMAL_ID_THERMAL1 = 1, + THERMAL_ID_THERMAL2 = 2, + THERMAL_ID_THERMAL3 = 3, + THERMAL_ID_THERMAL4 = 4, + THERMAL_ID_THERMAL5 = 5, + THERMAL_ID_THERMAL6 = 6, + THERMAL_ID_THERMAL7 = 7, + THERMAL_ID_THERMAL8 = 8, + THERMAL_ID_THERMAL9 = 9, + THERMAL_ID_THERMAL10 = 10, + THERMAL_ID_THERMAL11 = 11, + THERMAL_ID_THERMAL12 = 12, + THERMAL_ID_THERMAL13 = 13, + THERMAL_ID_THERMAL14 = 14, + THERMAL_ID_THERMAL15 = 15, + THERMAL_ID_THERMAL16 = 16, +} thermal_id_t; + +/** Enum names. */ +const char* thermal_id_name(thermal_id_t e); + +/** Enum values. */ +int thermal_id_value(const char* str, thermal_id_t* e, int substr); + +/** Enum descriptions. */ +const char* thermal_id_desc(thermal_id_t e); + +/** Enum validator. */ +int thermal_id_valid(thermal_id_t e); + +/** validator */ +#define THERMAL_ID_VALID(_e) \ + (thermal_id_valid((_e))) + +/** thermal_id_map table. */ +extern aim_map_si_t thermal_id_map[]; +/** thermal_id_desc_map table. */ +extern aim_map_si_t thermal_id_desc_map[]; + +/** fan_id */ +typedef enum fan_id_e { + FAN_ID_FAN1 = 1, + FAN_ID_FAN2 = 2, + FAN_ID_FAN3 = 3, + FAN_ID_FAN4 = 4, + FAN_ID_FAN5 = 5, + FAN_ID_FAN6 = 6, + FAN_ID_FAN7 = 7, + FAN_ID_FAN8 = 8, + FAN_ID_FAN9 = 9, + FAN_ID_FAN10 = 10, +} fan_id_t; + +/** Enum names. */ +const char* fan_id_name(fan_id_t e); + +/** Enum values. */ +int fan_id_value(const char* str, fan_id_t* e, int substr); + +/** Enum descriptions. */ +const char* fan_id_desc(fan_id_t e); + +/** Enum validator. */ +int fan_id_valid(fan_id_t e); + +/** validator */ +#define FAN_ID_VALID(_e) \ + (fan_id_valid((_e))) + +/** fan_id_map table. */ +extern aim_map_si_t fan_id_map[]; +/** fan_id_desc_map table. */ +extern aim_map_si_t fan_id_desc_map[]; + +/** psu_id */ +typedef enum psu_id_e { + PSU_ID_PSU1 = 1, + PSU_ID_PSU2 = 2, +} psu_id_t; + +/** Enum names. */ +const char* psu_id_name(psu_id_t e); + +/** Enum values. */ +int psu_id_value(const char* str, psu_id_t* e, int substr); + +/** Enum descriptions. */ +const char* psu_id_desc(psu_id_t e); + +/** Enum validator. */ +int psu_id_valid(psu_id_t e); + +/** validator */ +#define PSU_ID_VALID(_e) \ + (psu_id_valid((_e))) + +/** psu_id_map table. */ +extern aim_map_si_t psu_id_map[]; +/** psu_id_desc_map table. */ +extern aim_map_si_t psu_id_desc_map[]; + +/** fan_oid */ +typedef enum fan_oid_e { + FAN_OID_FAN1 = ONLP_FAN_ID_CREATE(1), + FAN_OID_FAN2 = ONLP_FAN_ID_CREATE(2), + FAN_OID_FAN3 = ONLP_FAN_ID_CREATE(3), + FAN_OID_FAN4 = ONLP_FAN_ID_CREATE(4), + FAN_OID_FAN5 = ONLP_FAN_ID_CREATE(5), + FAN_OID_FAN6 = ONLP_FAN_ID_CREATE(6), + FAN_OID_FAN7 = ONLP_FAN_ID_CREATE(7), + FAN_OID_FAN8 = ONLP_FAN_ID_CREATE(8), + FAN_OID_FAN9 = ONLP_FAN_ID_CREATE(9), + FAN_OID_FAN10 = ONLP_FAN_ID_CREATE(10), +} fan_oid_t; + +/** Enum names. */ +const char* fan_oid_name(fan_oid_t e); + +/** Enum values. */ +int fan_oid_value(const char* str, fan_oid_t* e, int substr); + +/** Enum descriptions. */ +const char* fan_oid_desc(fan_oid_t e); + +/** Enum validator. */ +int fan_oid_valid(fan_oid_t e); + +/** validator */ +#define FAN_OID_VALID(_e) \ + (fan_oid_valid((_e))) + +/** fan_oid_map table. */ +extern aim_map_si_t fan_oid_map[]; +/** fan_oid_desc_map table. */ +extern aim_map_si_t fan_oid_desc_map[]; +/* */ + +/* psu info table */ +struct psu_info_s { + char path[PATH_MAX]; + int present; + int busno; + int addr; +}; + +/** led_id */ +typedef enum led_id_e { + LED_ID_SYSTEM = 1, + LED_ID_FAN = 2, + LED_ID_PSU_1 = 3, + LED_ID_PSU_2 = 4, + LED_ID_FAN_FAIL_1 = 5, + LED_ID_FAN_FAIL_2 = 6, + LED_ID_FAN_FAIL_3 = 7, + LED_ID_FAN_FAIL_4 = 8, +} led_id_t; + +/** Enum names. */ +const char* led_id_name(led_id_t e); + +/** Enum values. */ +int led_id_value(const char* str, led_id_t* e, int substr); + +/** Enum descriptions. */ +const char* led_id_desc(led_id_t e); + +/** Enum validator. */ +int led_id_valid(led_id_t e); + +/** validator */ +#define LED_ID_VALID(_e) \ + (led_id_valid((_e))) + +/** led_id_map table. */ +extern aim_map_si_t led_id_map[]; +/** led_id_desc_map table. */ +extern aim_map_si_t led_id_desc_map[]; + +/** led_oid */ +typedef enum led_oid_e { + LED_OID_SYSTEM = ONLP_LED_ID_CREATE(LED_ID_SYSTEM), + LED_OID_FAN = ONLP_LED_ID_CREATE(LED_ID_FAN), + LED_OID_PSU_1 = ONLP_LED_ID_CREATE(LED_ID_PSU_1), + LED_OID_PSU_2 = ONLP_LED_ID_CREATE(LED_ID_PSU_2), + LED_OID_FAN_FAIL_1 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_1), + LED_OID_FAN_FAIL_2 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_2), + LED_OID_FAN_FAIL_3 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_3), + LED_OID_FAN_FAIL_4 = ONLP_LED_ID_CREATE(LED_ID_FAN_FAIL_4), +} led_oid_t; + +/** Enum names. */ +const char* led_oid_name(led_oid_t e); + +/** Enum values. */ +int led_oid_value(const char* str, led_oid_t* e, int substr); + +/** Enum descriptions. */ +const char* led_oid_desc(led_oid_t e); + +/** Enum validator. */ +int led_oid_valid(led_oid_t e); + +/** validator */ +#define LED_OID_VALID(_e) \ + (led_oid_valid((_e))) + +/** led_oid_map table. */ +extern aim_map_si_t led_oid_map[]; +/** led_oid_desc_map table. */ +extern aim_map_si_t led_oid_desc_map[]; +/* */ + +struct led_control_s{ + int PMCnt; + int psu_status_changed; + int fan_status_changed; + int fan_alert; + int psu1_present; + int psu2_present; + int psu1_power_good; + int psu2_power_good; +}; + +#define SYS_HWMON_PREFIX "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/0-004e" + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_INT_H__ */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.c new file mode 100755 index 00000000..5673120d --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.c @@ -0,0 +1,18 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +#include "x86_64_quanta_ix2_rangeley_log.h" +/* + * x86_64_quanta_ix2_rangeley log struct. + */ +AIM_LOG_STRUCT_DEFINE( + X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_OPTIONS_DEFAULT, + X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_BITS_DEFAULT, + NULL, /* Custom log map */ + X86_64_QUANTA_IX2_RANGELEY_CONFIG_LOG_CUSTOM_BITS_DEFAULT + ); + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.h new file mode 100755 index 00000000..e66008e6 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_log.h @@ -0,0 +1,12 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#ifndef __X86_64_QUANTA_IX2_RANGELEY_LOG_H__ +#define __X86_64_QUANTA_IX2_RANGELEY_LOG_H__ + +#define AIM_LOG_MODULE_NAME x86_64_quanta_ix2_rangeley +#include + +#endif /* __X86_64_QUANTA_IX2_RANGELEY_LOG_H__ */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_module.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_module.c new file mode 100755 index 00000000..3eac4372 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_module.c @@ -0,0 +1,24 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +#include "x86_64_quanta_ix2_rangeley_log.h" + +static int +datatypes_init__(void) +{ +#define X86_64_QUANTA_IX2_RANGELEY_ENUMERATION_ENTRY(_enum_name, _desc) AIM_DATATYPE_MAP_REGISTER(_enum_name, _enum_name##_map, _desc, AIM_LOG_INTERNAL); +#include + return 0; +} + +void __x86_64_quanta_ix2_rangeley_module_init__(void) +{ + AIM_LOG_STRUCT_REGISTER(); + datatypes_init__(); +} + +int __onlp_platform_version__ = 1; diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_ucli.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_ucli.c new file mode 100755 index 00000000..d13ec42d --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/x86_64_quanta_ix2_rangeley_ucli.c @@ -0,0 +1,50 @@ +/**************************************************************************//** + * + * + * + *****************************************************************************/ +#include + +#if X86_64_QUANTA_IX2_RANGELEY_CONFIG_INCLUDE_UCLI == 1 + +#include +#include +#include + +static ucli_status_t +x86_64_quanta_ix2_rangeley_ucli_ucli__config__(ucli_context_t* uc) +{ + UCLI_HANDLER_MACRO_MODULE_CONFIG(x86_64_quanta_ix2_rangeley) +} + +/* */ +/* */ + +static ucli_module_t +x86_64_quanta_ix2_rangeley_ucli_module__ = + { + "x86_64_quanta_ix2_rangeley_ucli", + NULL, + x86_64_quanta_ix2_rangeley_ucli_ucli_handlers__, + NULL, + NULL, + }; + +ucli_node_t* +x86_64_quanta_ix2_rangeley_ucli_node_create(void) +{ + ucli_node_t* n; + ucli_module_init(&x86_64_quanta_ix2_rangeley_ucli_module__); + n = ucli_node_create("x86_64_quanta_ix2_rangeley", NULL, &x86_64_quanta_ix2_rangeley_ucli_module__); + ucli_node_subnode_add(n, ucli_module_log_node_create("x86_64_quanta_ix2_rangeley")); + return n; +} + +#else +void* +x86_64_quanta_ix2_rangeley_ucli_node_create(void) +{ + return NULL; +} +#endif + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/Makefile new file mode 100755 index 00000000..003238cf --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/Makefile @@ -0,0 +1 @@ +include $(ONL)/make/pkg.mk \ No newline at end of file diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/Makefile b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/Makefile new file mode 100755 index 00000000..003238cf --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/Makefile @@ -0,0 +1 @@ +include $(ONL)/make/pkg.mk \ No newline at end of file diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/PKG.yml b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/PKG.yml new file mode 100755 index 00000000..665b3f67 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/PKG.yml @@ -0,0 +1 @@ +!include $ONL_TEMPLATES/platform-config-platform.yml ARCH=amd64 VENDOR=quanta BASENAME=x86-64-quanta-ix2-rangeley REVISION=r0 diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/lib/x86-64-quanta-ix2-rangeley-r0.yml b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/lib/x86-64-quanta-ix2-rangeley-r0.yml new file mode 100755 index 00000000..725e03a8 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/lib/x86-64-quanta-ix2-rangeley-r0.yml @@ -0,0 +1,31 @@ +--- + +###################################################################### +# +# platform-config for IX2 +# +###################################################################### + +x86-64-quanta-ix2-rangeley-r0: + + grub: + + serial: >- + --port=0x2f8 + --speed=115200 + --word=8 + --parity=no + --stop=1 + + kernel: + <<: *kernel-3-16 + + args: >- + console=ttyS1,115200n8 + reboot=c,p + + ##network: + ## interfaces: + ## ma1: + ## name: ~ + ## syspath: pci0000:00/0000:00:14.0 diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py new file mode 100755 index 00000000..186013e1 --- /dev/null +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py @@ -0,0 +1,20 @@ +from onl.platform.base import * +from onl.platform.quanta import * + +class OnlPlatform_x86_64_quanta_ix2_rangeley_r0(OnlPlatformQuanta, + OnlPlatformPortConfig_48x25_8x100): + PLATFORM='x86-64-quanta-ix2-rangeley-r0' + MODEL="IX2" + SYS_OBJECT_ID=".8.1" + + def baseconfig(self): + # Expose PSOC that behind PCA9641 + os.system("i2cset -y 0 0x8 0x5 0xfb") + os.system("i2cset -y 0 0x8 0x1 0x5") + + self.insmod("qci_pmbus") + self.insmod("qci_cpld") + self.insmod("quanta_hwmon_ix_series") + self.insmod("quanta_platform_ix2") + + return True From e0eff419ca2c502ac7ae04569e6511f8b2e980bd Mon Sep 17 00:00:00 2001 From: Jonathan Tsai Date: Thu, 8 Jun 2017 17:21:53 +0800 Subject: [PATCH 2/4] [Quanta-IX2] Update CPLD from qci_cpld.c to qci_cpld_sfp28.c --- .../x86-64/modules/builds/qci_cpld_sfp28.c | 400 ++++++++++++++++++ .../modules/builds/quanta_platform_ix2.c | 2 +- .../module/src/sfpi.c | 96 ++--- .../x86_64_quanta_ix2_rangeley_r0/__init__.py | 2 +- 4 files changed, 450 insertions(+), 50 deletions(-) create mode 100755 packages/platforms/quanta/x86-64/modules/builds/qci_cpld_sfp28.c diff --git a/packages/platforms/quanta/x86-64/modules/builds/qci_cpld_sfp28.c b/packages/platforms/quanta/x86-64/modules/builds/qci_cpld_sfp28.c new file mode 100755 index 00000000..f2f2c0d8 --- /dev/null +++ b/packages/platforms/quanta/x86-64/modules/builds/qci_cpld_sfp28.c @@ -0,0 +1,400 @@ +/* + * A CPLD driver for monitor SFP28 module I/O + * + * The CPLD is customize by Quanta for controlling SFP28 module signals, + * they are TX_FAULT , TX_DIS , PRE_N , RX_LOS + * Each CPLD control 16 modules, each module use 4 bits in register. + * + * Copyright (C) 2015 Quanta Inc. + * + * Author: Luffy Cheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_IDA(cpld_ida); + +enum platform_type { + SFP = 0, + SFP28, + NONE +}; + +static struct class *cpld_class = NULL; + +struct sfp_data { + struct i2c_client *cpld_client; + char name[8]; + char type[8]; + u8 port_id; + u8 cpld_port; +}; + +struct cpld_data { + struct mutex lock; + struct device *port_dev[16]; + struct sfp_data *port_data[16]; +}; + +static int cpld_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int cpld_remove(struct i2c_client *client); + +static const struct i2c_device_id cpld_id[] = { + { "CPLD-SFP", SFP }, + { "CPLD-SFP28", SFP28 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, cpld_id); + +static struct i2c_driver cpld_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "qci_cpld_sfp28", + }, + .probe = cpld_probe, + .remove = cpld_remove, + .id_table = cpld_id, +// .address_list = normal_i2c, +}; + +#define CPLD_ID_PREFIX "port-" +#define CPLD_ID_FORMAT CPLD_ID_PREFIX "%d" + +//SFP28 +#define TX_FAULT_MASK 0x08 +#define TX_DIS_MASK 0x04 +#define PRE_N_MASK 0x02 +#define RX_LOS_MASK 0x01 + +static inline u8 get_group_cmd(u8 group) +{ + //FIXME: if group cmd change + return (group + 1); +} + +static inline u8 port_remapping(u8 phy_port) +{ + /* FIXME: implement by hardware design */ + /* The CPLD register port mapping is weird : + * MSB -------- LSB (word data) + * P3 P4 P1 P2 (per port 4 bits) + * For easy coding bit shift, we treat it as hw port swap + */ + return (phy_port % 2) ? (phy_port - 1) : (phy_port + 1); +} + +//SFP +static ssize_t get_tx_fault(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sfp_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->cpld_client; + u8 group = (u8)(data->cpld_port / 4); + u8 group_port = data->cpld_port % 4; + s32 value; + + dev_dbg(&client->dev, "port_id %d => cpld_port %d, group %d(%d)\n", data->port_id, + data->cpld_port + 1, group + 1, group_port + 1); + + value = i2c_smbus_read_word_data(client, get_group_cmd(group)); + if (value < 0) + return -ENODEV; + + dev_dbg(&client->dev, "read group%d value= %x\n", group + 1, value); + + value >>= (group_port * 4); + value &= TX_FAULT_MASK; + + return sprintf(buf, "%d\n", value ? 1 : 0); +} + +static ssize_t get_tx_dis(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sfp_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->cpld_client; + u8 group = (u8)(data->cpld_port / 4); + u8 group_port = data->cpld_port % 4; + s32 value; + + dev_dbg(&client->dev, "port_id %d => cpld_port %d, group %d(%d)\n", data->port_id, + data->cpld_port + 1, group + 1, group_port + 1); + + value = i2c_smbus_read_word_data(client, get_group_cmd(group)); + if (value < 0) + return -ENODEV; + + dev_dbg(&client->dev, "read group%d value= %x\n", group + 1, value); + + value >>= (group_port * 4); + value &= TX_DIS_MASK; + + return sprintf(buf, "%d\n", value ? 1 : 0); +} + +static ssize_t get_pre_n(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sfp_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->cpld_client; + u8 group = (u8)(data->cpld_port / 4); + u8 group_port = data->cpld_port % 4; + s32 value; + + dev_dbg(&client->dev, "port_id %d => cpld_port %d, group %d(%d)\n", data->port_id, + data->cpld_port + 1, group + 1, group_port + 1); + + value = i2c_smbus_read_word_data(client, get_group_cmd(group)); + if (value < 0) + return -ENODEV; + + dev_dbg(&client->dev, "read group%d value= %x\n", group + 1, value); + + value >>= (group_port * 4); + value &= PRE_N_MASK; + + //FIXME: if present is not low active + return sprintf(buf, "%d\n", value ? 0 : 1); +} + +static ssize_t get_rx_los(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct sfp_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->cpld_client; + u8 group = (u8)(data->cpld_port / 4); + u8 group_port = data->cpld_port % 4; + s32 value; + + dev_dbg(&client->dev, "port_id %d => cpld_port %d, group %d(%d)\n", data->port_id, + data->cpld_port + 1, group + 1, group_port + 1); + + value = i2c_smbus_read_word_data(client, get_group_cmd(group)); + if (value < 0) + return -ENODEV; + + dev_dbg(&client->dev, "read group%d value= %x\n", group + 1, value); + + value >>= (group_port * 4); + value &= RX_LOS_MASK; + + return sprintf(buf, "%d\n", value ? 1 : 0); +} +static ssize_t set_tx_dis(struct device *dev, + struct device_attribute *devattr, + const char *buf, + size_t count) +{ + struct sfp_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->cpld_client; + u8 group = (u8)(data->cpld_port / 4); + u8 group_port = data->cpld_port % 4; + s32 value; + long disable; + + dev_dbg(&client->dev, "port_id %d => cpld_port %d, group %d(%d)\n", data->port_id, + data->cpld_port + 1, group + 1, group_port + 1); + + if (kstrtol(buf, 0, &disable)) + return -EINVAL; + + if ((disable != 1) && (disable != 0)) + return -EINVAL; + +// mutex_lock(&data->lock); + value = i2c_smbus_read_word_data(client, get_group_cmd(group)); + if (value < 0) + return -ENODEV; + + dev_dbg(&client->dev, "read group%d value= %x\n", group + 1, value); + + value &= ~(TX_DIS_MASK << (group_port * 4)); + if (disable) + value |= (TX_DIS_MASK << (group_port * 4)); + + dev_dbg(&client->dev, "write group%d value= %x\n", group + 1, value); + + i2c_smbus_write_word_data(client, get_group_cmd(group), (u16)value); +// mutex_unlock(&data->lock); + + return count; +} +//SFP + +//static DEVICE_ATTR(led_enable, S_IWUSR | S_IRUGO, get_led_enable, set_led_enable); +//static DEVICE_ATTR(monitor_enable, S_IWUSR | S_IRUGO, get_monitor_enable, set_monitor_enable); +//SFP +static DEVICE_ATTR(tx_fault, S_IRUGO, get_tx_fault, NULL); +static DEVICE_ATTR(tx_dis, S_IWUSR | S_IRUGO, get_tx_dis, set_tx_dis); +static DEVICE_ATTR(pre_n, S_IRUGO, get_pre_n, NULL); +static DEVICE_ATTR(rx_los, S_IRUGO, get_rx_los, NULL); + +static const struct attribute *sfp_attrs[] = { +// &dev_attr_led_enable.attr, + &dev_attr_tx_fault.attr, + &dev_attr_tx_dis.attr, + &dev_attr_pre_n.attr, + &dev_attr_rx_los.attr, + NULL, +}; + +static const struct attribute_group sfp_attr_group = { + .attrs = (struct attribute **) sfp_attrs, +}; + +static int cpld_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cpld_data *data; + struct sfp_data *port_data; +// struct i2c_monitor_data *monitor_data; + struct device *port_dev; +// struct device *i2c_dev; + int port_nr, i=0, err; + char name[I2C_NAME_SIZE], type[I2C_NAME_SIZE]; + + printk("cpld cpld_probe\n"); + + while(id->name[i]) + { + name[i]=tolower(id->name[i]); + i++; + } + name[i]='\0'; + strncpy(type,name+5,strlen(name)-5); + type[strlen(name)-5]='\0'; + + if (!cpld_class) + { + cpld_class = class_create(THIS_MODULE, name); + if (IS_ERR(cpld_class)) { + pr_err("couldn't create sysfs class\n"); + return PTR_ERR(cpld_class); + } + } + + data = devm_kzalloc(&client->dev, sizeof(struct cpld_data), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* register sfp port data to sysfs */ + for (i = 0; i < 16; i++) + { + port_nr = ida_simple_get(&cpld_ida, 1, 99, GFP_KERNEL); + if (port_nr < 0) + return ERR_PTR(port_nr); + + port_data = kzalloc(sizeof(struct sfp_data), GFP_KERNEL); + + port_dev = device_create(cpld_class, &client->dev, MKDEV(0,0), port_data, CPLD_ID_FORMAT, port_nr); + if (IS_ERR(port_dev)) { + err = PTR_ERR(port_dev); + printk("err_status\n"); + } + + data->port_dev[i] = port_dev; + data->port_data[i] = port_data; + + strcpy(port_data->type, type); + + dev_info(&client->dev, "Register %s port-%d\n", port_data->type , port_nr); + + /* FIXME: implement Logical/Physical port remapping */ + //port_data->cpld_port = i; + port_data->cpld_port = port_remapping(i); + sprintf(port_data->name, "port-%d", port_nr); + port_data->port_id = port_nr; + dev_set_drvdata(port_dev, port_data); + port_dev->init_name = port_data->name; + port_data->cpld_client = client; + + err = sysfs_create_group(&port_dev->kobj, &sfp_attr_group); + // if (status) printk("err status\n"); + } + + i2c_set_clientdata(client, data); + mutex_init(&data->lock); + + dev_info(&client->dev, "%s device found\n", client->name); + + + return 0; + +//FIXME: implement error check +//exit_remove: +// sysfs_remove_group(&client->dev.kobj, &data->attrs); + return err; +} + +/* FIXME: for older kernel doesn't with idr_is_empty function, implement here */ +#if 1 +static int idr_has_entry(int id, void *p, void *data) +{ + return 1; +} + +static bool cpld_idr_is_empty(struct idr *idp) +{ + return !idr_for_each(idp, idr_has_entry, NULL); +} +#endif + +static int cpld_remove(struct i2c_client *client) +{ + struct cpld_data *data = i2c_get_clientdata(client); + int i; +// int id; + + for (i = 15; i >= 0; i--) + { + dev_info(data->port_dev[i], "Remove %s port-%d\n", data->port_data[i]->type , data->port_data[i]->port_id); + device_unregister(data->port_dev[i]); + ida_simple_remove(&cpld_ida, data->port_data[i]->port_id); + kfree(data->port_data[i]); + } + + if (cpld_idr_is_empty(&cpld_ida.idr)) + class_destroy(cpld_class); + + return 0; +} + +module_i2c_driver(cpld_driver); + +MODULE_AUTHOR("Jonathan Tsai "); +MODULE_VERSION("1.0"); +MODULE_DESCRIPTION("Quanta Switch SFP28 CPLD driver"); +MODULE_LICENSE("GPL"); diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c index 0b98b52e..d102817d 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/modules/builds/quanta_platform_ix2.c @@ -63,7 +63,7 @@ char *i2c_type_names[] = { "pca9554", "pca9555", "pca9698", - "CPLD-QSFP28", + "CPLD-SFP28", "24c02", "qci_pmbus_ix2", "quanta_ix2_hwmon", diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c index 05243a0f..b507c460 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c @@ -46,54 +46,54 @@ typedef struct sfpmap_s { static sfpmap_t sfpmap__[] = { - { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-1/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, - { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-2/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, - { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-3/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, - { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-4/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, - { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-5/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, - { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-6/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, - { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-7/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, - { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-8/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, - { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-9/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, - { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-10/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, - { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-11/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, - { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-12/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, - { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-13/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, - { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-14/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, - { 15, 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NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, + { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-24/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, + { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-25/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, + { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-26/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, + { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-27/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, + { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-28/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, + { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-29/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, + { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-30/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, + { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-31/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, + { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-32/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, + { 33, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-33/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-64/64-0050/eeprom", NULL }, + { 34, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-34/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-65/65-0050/eeprom", NULL }, + { 35, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-35/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-66/66-0050/eeprom", NULL }, + { 36, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-36/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-67/67-0050/eeprom", NULL }, + { 37, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-37/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-68/68-0050/eeprom", NULL }, + { 38, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-38/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-69/69-0050/eeprom", NULL }, + { 39, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-39/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-70/70-0050/eeprom", NULL }, + { 40, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-40/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-71/71-0050/eeprom", NULL }, + { 41, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-41/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-72/72-0050/eeprom", NULL }, + { 42, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-42/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-73/73-0050/eeprom", NULL }, + { 43, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-43/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-74/74-0050/eeprom", NULL }, + { 44, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-44/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-75/75-0050/eeprom", NULL }, + { 45, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-45/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-76/76-0050/eeprom", NULL }, + { 46, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-46/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-77/77-0050/eeprom", NULL }, + { 47, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-47/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-78/78-0050/eeprom", NULL }, + { 48, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-48/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-79/79-0050/eeprom", NULL }, }; typedef struct qsfpmap_s { diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py index 186013e1..39ed6904 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py @@ -13,7 +13,7 @@ class OnlPlatform_x86_64_quanta_ix2_rangeley_r0(OnlPlatformQuanta, os.system("i2cset -y 0 0x8 0x1 0x5") self.insmod("qci_pmbus") - self.insmod("qci_cpld") + self.insmod("qci_cpld_sfp28") self.insmod("quanta_hwmon_ix_series") self.insmod("quanta_platform_ix2") From 109eae5e9609a7dd250657df6dcec2e589272be2 Mon Sep 17 00:00:00 2001 From: Jonathan Tsai Date: Tue, 27 Jun 2017 11:10:38 +0800 Subject: [PATCH 3/4] Update Quanta SYS_OBJECT_ID for each platform --- .../r0/src/python/powerpc_quanta_lb9_r0/__init__.py | 10 +++++++++- .../r0/src/python/powerpc_quanta_ly2_r0/__init__.py | 10 +++++++++- .../python/x86_64_quanta_ix1_rangeley_r0/__init__.py | 10 +++++++++- .../python/x86_64_quanta_ix2_rangeley_r0/__init__.py | 10 +++++++++- .../r0/src/python/x86_64_quanta_ly4r_r0/__init__.py | 10 +++++++++- .../python/x86_64_quanta_ly6_rangeley_r0/__init__.py | 10 +++++++++- .../python/x86_64_quanta_ly8_rangeley_r0/__init__.py | 10 +++++++++- .../python/x86_64_quanta_ly9_rangeley_r0/__init__.py | 10 +++++++++- 8 files changed, 72 insertions(+), 8 deletions(-) mode change 100644 => 100755 packages/platforms/quanta/powerpc/powerpc-quanta-lb9/platform-config/r0/src/python/powerpc_quanta_lb9_r0/__init__.py mode change 100644 => 100755 packages/platforms/quanta/powerpc/powerpc-quanta-ly2/platform-config/r0/src/python/powerpc_quanta_ly2_r0/__init__.py diff --git a/packages/platforms/quanta/powerpc/powerpc-quanta-lb9/platform-config/r0/src/python/powerpc_quanta_lb9_r0/__init__.py b/packages/platforms/quanta/powerpc/powerpc-quanta-lb9/platform-config/r0/src/python/powerpc_quanta_lb9_r0/__init__.py old mode 100644 new mode 100755 index abb2c5ac..4063f7ce --- a/packages/platforms/quanta/powerpc/powerpc-quanta-lb9/platform-config/r0/src/python/powerpc_quanta_lb9_r0/__init__.py +++ b/packages/platforms/quanta/powerpc/powerpc-quanta-lb9/platform-config/r0/src/python/powerpc_quanta_lb9_r0/__init__.py @@ -7,7 +7,15 @@ class OnlPlatform_powerpc_quanta_lb9_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x1_4x10): PLATFORM='powerpc-quanta-lb9-r0' MODEL="LB9" - SYS_OBJECT_ID=".1048.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".1048.1900" def baseconfig(self): platform_fancontrol="%s/etc/fancontrol" % self.basedir_onl() diff --git a/packages/platforms/quanta/powerpc/powerpc-quanta-ly2/platform-config/r0/src/python/powerpc_quanta_ly2_r0/__init__.py b/packages/platforms/quanta/powerpc/powerpc-quanta-ly2/platform-config/r0/src/python/powerpc_quanta_ly2_r0/__init__.py old mode 100644 new mode 100755 index 202f214d..50aa756a --- a/packages/platforms/quanta/powerpc/powerpc-quanta-ly2/platform-config/r0/src/python/powerpc_quanta_ly2_r0/__init__.py +++ b/packages/platforms/quanta/powerpc/powerpc-quanta-ly2/platform-config/r0/src/python/powerpc_quanta_ly2_r0/__init__.py @@ -8,7 +8,15 @@ class OnlPlatform_powerpc_quanta_ly2_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x10_4x40): PLATFORM='powerpc-quanta-ly2-r0' MODEL="LY2" - SYS_OBJECT_ID=".3048.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".3048.2200" def baseconfig(self): self.insmod("quanta-ly2-i2c-mux.ko") diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/python/x86_64_quanta_ix1_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/python/x86_64_quanta_ix1_rangeley_r0/__init__.py index 56954b5b..e77628c7 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/python/x86_64_quanta_ix1_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/platform-config/r0/src/python/x86_64_quanta_ix1_rangeley_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ix1_rangeley_r0(OnlPlatformQuanta, OnlPlatformPortConfig_32x100): PLATFORM='x86-64-quanta-ix1-rangeley-r0' MODEL="IX1" - SYS_OBJECT_ID=".8.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".7032.3100" def baseconfig(self): self.insmod("qci_pmbus") diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py index 39ed6904..3b134782 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/platform-config/r0/src/python/x86_64_quanta_ix2_rangeley_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ix2_rangeley_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x25_8x100): PLATFORM='x86-64-quanta-ix2-rangeley-r0' MODEL="IX2" - SYS_OBJECT_ID=".8.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".4048.3200" def baseconfig(self): # Expose PSOC that behind PCA9641 diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/platform-config/r0/src/python/x86_64_quanta_ly4r_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/platform-config/r0/src/python/x86_64_quanta_ly4r_r0/__init__.py index a15781f6..a88370af 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/platform-config/r0/src/python/x86_64_quanta_ly4r_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/platform-config/r0/src/python/x86_64_quanta_ly4r_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ly4r_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x1_4x10): PLATFORM='x86-64-quanta-ly4r-r0' MODEL="LY4R" - SYS_OBJECT_ID=".8.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".1048.2418" def baseconfig(self): self.insmod("quanta_platform_ly4r") diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly6-rangeley/platform-config/r0/src/python/x86_64_quanta_ly6_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ly6-rangeley/platform-config/r0/src/python/x86_64_quanta_ly6_rangeley_r0/__init__.py index a507afba..06df97c9 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly6-rangeley/platform-config/r0/src/python/x86_64_quanta_ly6_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly6-rangeley/platform-config/r0/src/python/x86_64_quanta_ly6_rangeley_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ly6_rangeley_r0(OnlPlatformQuanta, OnlPlatformPortConfig_32x40): PLATFORM='x86-64-quanta-ly6-rangeley-r0' MODEL='LY6' - SYS_OBJECT_ID='.6.1' + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID='.5032.2600' def baseconfig(self): self.insmod("quanta_hwmon_ly_series") diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly8-rangeley/platform-config/r0/src/python/x86_64_quanta_ly8_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ly8-rangeley/platform-config/r0/src/python/x86_64_quanta_ly8_rangeley_r0/__init__.py index a8cdbdd2..8a203a5e 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly8-rangeley/platform-config/r0/src/python/x86_64_quanta_ly8_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly8-rangeley/platform-config/r0/src/python/x86_64_quanta_ly8_rangeley_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ly8_rangeley_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x10_6x40): PLATFORM='x86-64-quanta-ly8-rangeley-r0' MODEL="LY8" - SYS_OBJECT_ID=".8.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".3048.2800" def baseconfig(self): self.insmod("emerson700") diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly9-rangeley/platform-config/r0/src/python/x86_64_quanta_ly9_rangeley_r0/__init__.py b/packages/platforms/quanta/x86-64/x86-64-quanta-ly9-rangeley/platform-config/r0/src/python/x86_64_quanta_ly9_rangeley_r0/__init__.py index 6cff7f46..b8b49511 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly9-rangeley/platform-config/r0/src/python/x86_64_quanta_ly9_rangeley_r0/__init__.py +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly9-rangeley/platform-config/r0/src/python/x86_64_quanta_ly9_rangeley_r0/__init__.py @@ -5,7 +5,15 @@ class OnlPlatform_x86_64_quanta_ly9_rangeley_r0(OnlPlatformQuanta, OnlPlatformPortConfig_48x10_6x40): PLATFORM='x86-64-quanta-ly9-rangeley-r0' MODEL="LY9" - SYS_OBJECT_ID=".9.1" + """ Define Quanta SYS_OBJECT_ID rule. + + SYS_OBJECT_ID = .xxxx.ABCC + "xxxx" define QCT device mark. For example, LB9->1048, LY2->3048 + "A" define QCT switch series name: LB define 1, LY define 2, IX define 3 + "B" define QCT switch series number 1: For example, LB9->9, LY2->2 + "CC" define QCT switch series number 2: For example, LY2->00, LY4R->18(R is 18th english letter) + """ + SYS_OBJECT_ID=".3048.2900" def baseconfig(self): self.insmod("emerson700") From f08a606527d91c86700c57220f049dc6120b525f Mon Sep 17 00:00:00 2001 From: Jonathan Tsai Date: Tue, 27 Jun 2017 11:13:41 +0800 Subject: [PATCH 4/4] [Quanta-IX2] Add sfp functions of onlp_sfpi_control_set() and onlp_sfpi_control_get() --- .../x86_64_quanta_ix2_rangeley_gpio_table.h | 32 +- .../module/src/sfpi.c | 307 ++++++++++++++---- 2 files changed, 270 insertions(+), 69 deletions(-) diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h index 053b4606..e31cb400 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/inc/x86_64_quanta_ix2_rangeley/x86_64_quanta_ix2_rangeley_gpio_table.h @@ -51,13 +51,29 @@ #define QUANTA_IX2_FAN_FAIL_LED_4 (QUANTA_IX2_FAN_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,7)) #define QUANTA_IX2_PCA9698_1_GPIO_BASE 0x50 -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_1_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,2)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_2_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,6)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_3_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_4_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,6)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_5_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,2)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_6_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,6)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_7_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,2)) -#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_8_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,0)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,3)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,4)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(0,7)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,0)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,3)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,4)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(1,7)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,0)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,3)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,4)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(2,7)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,0)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,2)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,3)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_RESET_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,4)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_PRSNT_N (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,6)) +#define QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_LPMOD_P (QUANTA_IX2_PCA9698_1_GPIO_BASE + QUANTA_IX2_PCA953x_GPIO(3,7)) #endif /* __X86_64_QUANTA_IX2_RANGELEY_GPIO_TABLE_H__ */ diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c index b507c460..0d9d3e4a 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix2-rangeley/onlp/builds/src/x86_64_quanta_ix2_rangeley/module/src/sfpi.c @@ -28,7 +28,7 @@ #include #include #include "x86_64_quanta_ix2_rangeley_log.h" - +#include #include #include @@ -46,78 +46,91 @@ typedef struct sfpmap_s { static sfpmap_t sfpmap__[] = { - { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-1/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, - { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-2/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, - { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-3/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, - { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-4/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, - { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-5/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, - { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-6/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, - { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-7/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, - { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-8/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, - { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-9/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, - { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-10/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, - { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-11/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, - { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-12/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, - { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-13/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, - { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-14/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, - { 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-15/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL }, - { 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-16/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL }, - { 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-17/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL }, - { 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-18/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL }, - { 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-19/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL }, - { 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-20/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL }, - { 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-21/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL }, - { 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-22/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL }, - { 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-23/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, - { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-24/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, - { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-25/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, - { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-26/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, - { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-27/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, - { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-28/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, - { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-29/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, - { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-30/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, - { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-31/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, - { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-32/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, - { 33, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-33/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-64/64-0050/eeprom", NULL }, - { 34, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-34/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-65/65-0050/eeprom", NULL }, - { 35, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-35/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-66/66-0050/eeprom", NULL }, - { 36, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-36/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-67/67-0050/eeprom", NULL }, - { 37, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-37/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-68/68-0050/eeprom", NULL }, - { 38, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-38/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-69/69-0050/eeprom", NULL }, - { 39, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-39/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-70/70-0050/eeprom", NULL }, - { 40, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-40/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-71/71-0050/eeprom", NULL }, - { 41, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-41/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-72/72-0050/eeprom", NULL }, - { 42, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-42/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-73/73-0050/eeprom", NULL }, - { 43, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-43/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-74/74-0050/eeprom", NULL }, - { 44, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-44/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-75/75-0050/eeprom", NULL }, - { 45, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-45/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-76/76-0050/eeprom", NULL }, - { 46, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-46/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-77/77-0050/eeprom", NULL }, - { 47, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-47/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-78/78-0050/eeprom", NULL }, - { 48, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-48/pre_n", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-79/79-0050/eeprom", NULL }, + { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-1/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, + { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-2/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, + { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-3/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, + { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-4/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, + { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-5/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, + { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-6/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, + { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-7/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, + { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-8/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, + { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-9/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, + { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-10/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, + { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-11/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, + { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-12/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, + { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-13/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, + { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-14/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, + { 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-15/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL }, + { 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-sfp28/port-16/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL }, + { 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-17/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL }, + { 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-18/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL }, + { 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-19/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL }, + { 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-20/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL }, + { 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-21/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL }, + { 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-22/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL }, + { 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-23/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, + { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-24/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, + { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-25/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, + { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-26/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, + { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-27/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, + { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-28/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, + { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-29/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, + { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-30/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, + { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-31/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, + { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-sfp28/port-32/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, + { 33, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-33/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-64/64-0050/eeprom", NULL }, + { 34, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-34/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-65/65-0050/eeprom", NULL }, + { 35, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-35/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-66/66-0050/eeprom", NULL }, + { 36, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-36/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-67/67-0050/eeprom", NULL }, + { 37, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-37/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-68/68-0050/eeprom", NULL }, + { 38, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-38/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-69/69-0050/eeprom", NULL }, + { 39, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-39/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-70/70-0050/eeprom", NULL }, + { 40, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-40/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-71/71-0050/eeprom", NULL }, + { 41, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-41/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-72/72-0050/eeprom", NULL }, + { 42, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-42/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-73/73-0050/eeprom", NULL }, + { 43, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-43/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-74/74-0050/eeprom", NULL }, + { 44, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-44/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-75/75-0050/eeprom", NULL }, + { 45, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-45/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-76/76-0050/eeprom", NULL }, + { 46, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-46/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-77/77-0050/eeprom", NULL }, + { 47, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-47/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-78/78-0050/eeprom", NULL }, + { 48, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/17-0038/cpld-sfp28/port-48/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-79/79-0050/eeprom", NULL }, }; typedef struct qsfpmap_s { int port; int present_gpio; - const char* reset_gpio; + int reset_gpio; + int lplmod_gpio; const char* eeprom; const char* dom; } qsfpmap_t; static qsfpmap_t qsfpmap__[] = { - { 49, QUANTA_IX2_PCA9698_1_GPIO_QSFP_1_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-80/80-0050/eeprom", NULL }, - { 50, QUANTA_IX2_PCA9698_1_GPIO_QSFP_2_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-81/81-0050/eeprom", NULL }, - { 51, QUANTA_IX2_PCA9698_1_GPIO_QSFP_3_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-82/82-0050/eeprom", NULL }, - { 52, QUANTA_IX2_PCA9698_1_GPIO_QSFP_4_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-83/83-0050/eeprom", NULL }, - { 53, QUANTA_IX2_PCA9698_1_GPIO_QSFP_5_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-84/84-0050/eeprom", NULL }, - { 54, QUANTA_IX2_PCA9698_1_GPIO_QSFP_6_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-85/85-0050/eeprom", NULL }, - { 55, QUANTA_IX2_PCA9698_1_GPIO_QSFP_7_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-86/86-0050/eeprom", NULL }, - { 56, QUANTA_IX2_PCA9698_1_GPIO_QSFP_8_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-87/87-0050/eeprom", NULL }, + { 49, QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_49_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-80/80-0050/eeprom", NULL }, + { 50, QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_50_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-81/81-0050/eeprom", NULL }, + { 51, QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_51_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-82/82-0050/eeprom", NULL }, + { 52, QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_52_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-83/83-0050/eeprom", NULL }, + { 53, QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_53_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-84/84-0050/eeprom", NULL }, + { 54, QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_54_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-85/85-0050/eeprom", NULL }, + { 55, QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_55_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-86/86-0050/eeprom", NULL }, + { 56, QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_PRSNT_N, QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_RESET_P, QUANTA_IX2_PCA9698_1_GPIO_QSFP_56_LPMOD_P, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-18/i2c-87/87-0050/eeprom", NULL }, }; #define SFP_GET(_port) (sfpmap__ + _port - 1) #define QSFP_GET(_port) (qsfpmap__ + _port - 49) +#define MAX_SFP_PATH 128 +static char sfp_node_path[MAX_SFP_PATH] = {0}; + +static char* +sfp_get_port_path(int port, char *node_name) +{ + sfpmap_t* sfp = SFP_GET(port); + + sprintf(sfp_node_path, sfp->present_cpld, + node_name); + return sfp_node_path; +} int onlp_sfpi_init(void) @@ -132,6 +145,10 @@ onlp_sfpi_init(void) for(i = 49; i < 57 ; i ++) { qsfp = QSFP_GET(i); onlp_gpio_export(qsfp->present_gpio, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(qsfp->reset_gpio, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_set(qsfp->reset_gpio, 0); + onlp_gpio_export(qsfp->lplmod_gpio, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_set(qsfp->lplmod_gpio, 0); } return ret; @@ -188,9 +205,7 @@ onlp_sfpi_is_present(int port) } } else{ - sfpmap_t* sfp = SFP_GET(port); - - return onlplib_sfp_is_present_file(sfp->present_cpld, /* Present */ "1\n", /* Absent */ "0\n"); + return onlplib_sfp_is_present_file(sfp_get_port_path(port, "pre_n"), /* Present */ "1\n", /* Absent */ "0\n"); } } @@ -220,3 +235,173 @@ onlp_sfpi_dom_read(int port, uint8_t data[256]) } } +int +onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value) +{ + int rv; + + if(port > 48){ + qsfpmap_t* qsfp = QSFP_GET(port); + switch(control){ + case ONLP_SFP_CONTROL_RESET_STATE: + { + if(onlp_gpio_set(qsfp->reset_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to set reset status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + case ONLP_SFP_CONTROL_LP_MODE: + { + if(onlp_gpio_set(qsfp->lplmod_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to set lp_mode status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + } + else{ + switch(control){ + case ONLP_SFP_CONTROL_TX_DISABLE: + { + char* path = sfp_get_port_path(port, "tx_dis"); + + if (onlp_file_write_int(value, path) != 0) { + AIM_LOG_ERROR("Unable to set tx_disable status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + break; + } + } + + return rv; +} + +int +onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value) +{ + int rv; + char* path = NULL; + + if(port > 48){ + qsfpmap_t* qsfp = QSFP_GET(port); + + switch(control){ + case ONLP_SFP_CONTROL_RESET_STATE: + { + if(onlp_gpio_get(qsfp->reset_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to read reset status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + case ONLP_SFP_CONTROL_LP_MODE: + { + if(onlp_gpio_get(qsfp->lplmod_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to read lp_mode status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + case ONLP_SFP_CONTROL_RX_LOS: + { + *value = 0; + rv = ONLP_STATUS_OK; + break; + } + + case ONLP_SFP_CONTROL_TX_DISABLE: + { + *value = 0; + rv = ONLP_STATUS_OK; + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + } + else{ + switch(control){ + case ONLP_SFP_CONTROL_RX_LOS: + { + path = sfp_get_port_path(port, "rx_los"); + + if (onlp_file_read_int(value, path) < 0) { + AIM_LOG_ERROR("Unable to read rx_los status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + case ONLP_SFP_CONTROL_TX_FAULT: + { + path = sfp_get_port_path(port, "tx_fault"); + + if (onlp_file_read_int(value, path) < 0) { + AIM_LOG_ERROR("Unable to read tx_fault status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + case ONLP_SFP_CONTROL_TX_DISABLE: + { + path = sfp_get_port_path(port, "tx_dis"); + + if (onlp_file_read_int(value, path) < 0) { + AIM_LOG_ERROR("Unable to read tx_disabled status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + if(*value == 0){ + *value = 1; + } + else{ + *value = 0; + } + rv = ONLP_STATUS_OK; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + } + + return rv; +}