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modify onlpi function

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Signed-off-by: johnson <JOHNSON.LU@deltaww.com>
This commit is contained in:
johnson
2019-04-19 15:49:42 +08:00
parent ca9f55844d
commit 430294d0b5
10 changed files with 158 additions and 1470 deletions
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119
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/modules/builds/delta_agc7646slv1b_platform.c
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@@ -24,10 +24,10 @@
#define MUX_VAL_IDEEPROM 0xFC #define MUX_VAL_IDEEPROM 0xFC
#define MUX_VAL_PCA9547 0xFD #define MUX_VAL_PCA9547 0xFD
#define MUX_VAL_FAN1_EEPROM 0x00 #define MUX_VAL_FAN1_EEPROM 0x08
#define MUX_VAL_FAN2_EEPROM 0x01 #define MUX_VAL_FAN2_EEPROM 0x09
#define MUX_VAL_FAN3_EEPROM 0x02 #define MUX_VAL_FAN3_EEPROM 0x0a
#define MUX_VAL_FAN4_EEPROM 0x03 #define MUX_VAL_FAN4_EEPROM 0x0b
#define MUX_VAL_FAN_CTL 0x05 #define MUX_VAL_FAN_CTL 0x05
#define MUX_VAL_FAN_TMP75 0x06 #define MUX_VAL_FAN_TMP75 0x06
#define MUX_VAL_FAN_IO_CTL 0x07 #define MUX_VAL_FAN_IO_CTL 0x07
@@ -43,7 +43,7 @@
#define BUS2_QSFP_DEV_NUM 6 #define BUS2_QSFP_DEV_NUM 6
#define BUS2_QSFP_BASE_NUM 41 #define BUS2_QSFP_BASE_NUM 41
#define BUS2_QSFP_MUX_REG 0x20 #define BUS2_QSFP_MUX_REG 0x20
#define BUS2_SFP_DEV_NUM 48 #define BUS2_SFP_DEV_NUM 46
#define BUS2_SFP_BASE_NUM 51 #define BUS2_SFP_BASE_NUM 51
#define BUS2_SFP_MUX_REG 0x21 #define BUS2_SFP_MUX_REG 0x21
#define BUS5_DEV_NUM 7 #define BUS5_DEV_NUM 7
@@ -68,7 +68,7 @@
#define SWPLD3_SFP_PORT_19 19 #define SWPLD3_SFP_PORT_19 19
#define SWPLD3_SFP_PORT_29 29 #define SWPLD3_SFP_PORT_29 29
#define SWPLD3_SFP_PORT_39 39 #define SWPLD3_SFP_PORT_39 39
#define SWPLD3_SFP_PORT_48 48 #define SWPLD3_SFP_PORT_46 46
/* on SWPLD2 */ /* on SWPLD2 */
#define SFP_PRESENCE_1 0x30 #define SFP_PRESENCE_1 0x30
@@ -751,7 +751,7 @@ static struct i2c_device_platform_data agc7646slv1b_i2c_device_platform_data[] =
{ {
// tmp75 // tmp75
.parent = 8, .parent = 8,
.info = { I2C_BOARD_INFO("tmp75", 0x4b) }, .info = { I2C_BOARD_INFO("tmp75", 0x4d) },
.client = NULL, .client = NULL,
}, },
{ {
@@ -760,12 +760,6 @@ static struct i2c_device_platform_data agc7646slv1b_i2c_device_platform_data[] =
.info = { I2C_BOARD_INFO("tmp431", 0x4c) }, .info = { I2C_BOARD_INFO("tmp431", 0x4c) },
.client = NULL, .client = NULL,
}, },
{
// tmp432
.parent = 8,
.info = { I2C_BOARD_INFO("tmp432", 0x4d) },
.client = NULL,
},
{ {
// tmp75 // tmp75
.parent = 8, .parent = 8,
@@ -817,13 +811,13 @@ static struct i2c_device_platform_data agc7646slv1b_i2c_device_platform_data[] =
{ {
// PSU 1 control // PSU 1 control
.parent = 31, .parent = 31,
.info = { I2C_BOARD_INFO("dni_agc7646slv1b_psu", 0x58) }, .info = { I2C_BOARD_INFO("agc7646slv1b_psu", 0x58) },
.client = NULL, .client = NULL,
}, },
{ {
// PSU 2 control // PSU 2 control
.parent = 32, .parent = 32,
.info = { I2C_BOARD_INFO("dni_agc7646slv1b_psu", 0x58) }, .info = { I2C_BOARD_INFO("agc7646slv1b_psu", 0x58) },
.client = NULL, .client = NULL,
}, },
{ {
@@ -1138,18 +1132,6 @@ static struct i2c_device_platform_data agc7646slv1b_i2c_device_platform_data[] =
.info = { .type = "optoe2", .addr = 0x50 }, .info = { .type = "optoe2", .addr = 0x50 },
.client = NULL, .client = NULL,
}, },
{
// sfp 47 (0x50)
.parent = 97,
.info = { .type = "optoe2", .addr = 0x50 },
.client = NULL,
},
{
// sfp 48 (0x50)
.parent = 98,
.info = { .type = "optoe2", .addr = 0x50 },
.client = NULL,
},
}; };
static struct platform_device agc7646slv1b_i2c_device[] = { static struct platform_device agc7646slv1b_i2c_device[] = {
@@ -1218,9 +1200,6 @@ static struct platform_device agc7646slv1b_i2c_device[] = {
agc7646slv1b_i2c_device_num(62), agc7646slv1b_i2c_device_num(62),
agc7646slv1b_i2c_device_num(63), agc7646slv1b_i2c_device_num(63),
agc7646slv1b_i2c_device_num(64), agc7646slv1b_i2c_device_num(64),
agc7646slv1b_i2c_device_num(65),
agc7646slv1b_i2c_device_num(66),
agc7646slv1b_i2c_device_num(67),
}; };
/* ---------------- I2C device - end ------------- */ /* ---------------- I2C device - end ------------- */
@@ -1297,6 +1276,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
struct cpld_platform_data *pdata2 = i2cdev_2->platform_data; struct cpld_platform_data *pdata2 = i2cdev_2->platform_data;
long port_t = 0; long port_t = 0;
u8 reg_t = 0x00; u8 reg_t = 0x00;
u8 save_bytes = 0x00;
int values[7] = {'\0'}; int values[7] = {'\0'};
int bit_t = 0x00; int bit_t = 0x00;
mutex_lock(&dni_lock); mutex_lock(&dni_lock);
@@ -1314,9 +1294,9 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
reg_t = SFP_PRESENCE_4; reg_t = SFP_PRESENCE_4;
} else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */ } else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */
reg_t = SFP_PRESENCE_5; reg_t = SFP_PRESENCE_5;
} else if (port_t > 40 && port_t < 49) { /* SFP Port 41-48 */ } else if (port_t > 40 && port_t < 47) { /* SFP Port 41-46 */
reg_t = SFP_PRESENCE_6; reg_t = SFP_PRESENCE_6;
} else if (port_t > 48 && port_t < 55) { /* QSFP Port 1-6 */ } else if (port_t > 46 && port_t < 53) { /* QSFP Port 1-6 */
reg_t = QSFP_PRESENCE; reg_t = QSFP_PRESENCE;
} else { } else {
values[0] = 1; /* return 1, module NOT present */ values[0] = 1; /* return 1, module NOT present */
@@ -1324,11 +1304,10 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
if (port_t > 48 && port_t < 55) { /* QSFP */ if (port_t > 46 && port_t < 53) { /* QSFP */
VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0); VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0);
mutex_unlock(&dni_lock); mutex_unlock(&dni_lock);
port_t = port_t - 1; bit_t = 1 << (port_t % 47);
bit_t = 1 << (port_t % 8);
values[0] = values[0] & bit_t; values[0] = values[0] & bit_t;
values[0] = values[0] / bit_t; values[0] = values[0] / bit_t;
} }
@@ -1366,14 +1345,20 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
/* SFP_PRESENT Ports 33-40 */ /* SFP_PRESENT Ports 33-40 */
VALIDATED_READ(buf, values[4], VALIDATED_READ(buf, values[4],
i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_PRESENCE_5), 0); i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_PRESENCE_5), 0);
/* SFP_PRESENT Ports 41-48 */ /* SFP_PRESENT Ports 41-46 */
VALIDATED_READ(buf, values[5], VALIDATED_READ(buf, values[5],
i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_PRESENCE_6), 0); i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_PRESENCE_6), 0);
/* QSFP_PRESENT Ports 49-54 */ /* QSFP_PRESENT Ports 47-52 */
VALIDATED_READ(buf, values[6], VALIDATED_READ(buf, values[6],
i2c_smbus_read_byte_data(pdata1[swpld1].client, QSFP_PRESENCE), 0); i2c_smbus_read_byte_data(pdata1[swpld1].client, QSFP_PRESENCE), 0);
values[6] = values[6] & 0x3F; values[6] &= 0x3F;
values[5] &= 0x3F;
save_bytes = values[6] & 0x03;
save_bytes = save_bytes << 6;
values[5] |= save_bytes;
values[6] &= 0x3c;
values[6] = values[6] >> 2;
/* sfp_is_present_all value /* sfp_is_present_all value
* return 0 is module present * return 0 is module present
@@ -1383,7 +1368,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
case SFP_LP_MODE: case SFP_LP_MODE:
port_t = sfp_port_data; port_t = sfp_port_data;
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_LPMODE; reg_t = QSFP_LPMODE;
} else { } else {
values[0] = 0; /* return 0, module is NOT in LP mode */ values[0] = 0; /* return 0, module is NOT in LP mode */
@@ -1391,15 +1376,14 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 47-52 */
VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0); VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0);
} else { /* In agc7646slv1b only QSFP support control LP MODE */ } else { /* In agc7646slv1b only QSFP support control LP MODE */
values[0] = 0; values[0] = 0;
mutex_unlock(&dni_lock); mutex_unlock(&dni_lock);
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
port_t = port_t - 1; bit_t = 1 << (port_t % 47);
bit_t = 1 << (port_t % 8);
values[0] = values[0] & bit_t; values[0] = values[0] & bit_t;
values[0] = values[0] / bit_t; values[0] = values[0] / bit_t;
@@ -1411,7 +1395,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
case SFP_RESET: case SFP_RESET:
port_t = sfp_port_data; port_t = sfp_port_data;
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 49-54 */
reg_t = QSFP_RESET; reg_t = QSFP_RESET;
} else { } else {
values[0] = 1; /* return 1, module NOT in reset mode */ values[0] = 1; /* return 1, module NOT in reset mode */
@@ -1419,15 +1403,14 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 49-54 */
VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0); VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata1[swpld1].client, reg_t), 0);
} else { /* In agc7646slv1b only QSFP support control RESET MODE */ } else { /* In agc7646slv1b only QSFP support control RESET MODE */
values[0] = 1; values[0] = 1;
mutex_unlock(&dni_lock); mutex_unlock(&dni_lock);
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
port_t = port_t - 1; bit_t = 1 << (port_t % 47);
bit_t = 1 << (port_t % 8);
values[0] = values[0] & bit_t; values[0] = values[0] & bit_t;
values[0] = values[0] / bit_t; values[0] = values[0] / bit_t;
@@ -1449,7 +1432,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
reg_t = SFP_RXLOS_4; reg_t = SFP_RXLOS_4;
} else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */ } else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */
reg_t = SFP_RXLOS_5; reg_t = SFP_RXLOS_5;
} else if (port_t > 40 && port_t < 49) { /* SFP Port 41-48 */ } else if (port_t > 40 && port_t < 47) { /* SFP Port 41-46 */
reg_t = SFP_RXLOS_6; reg_t = SFP_RXLOS_6;
} else { } else {
values[0] = 1; /* return 1, module Error */ values[0] = 1; /* return 1, module Error */
@@ -1457,7 +1440,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
if (port_t > 0 && port_t < 49) { /* SFP */ if (port_t > 0 && port_t < 47) { /* SFP */
VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata2[swpld2].client, reg_t), 0); VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata2[swpld2].client, reg_t), 0);
} else { /* In agc7646slv1b only SFP support control RX_LOS MODE */ } else { /* In agc7646slv1b only SFP support control RX_LOS MODE */
values[0] = 1; values[0] = 1;
@@ -1494,7 +1477,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
/* SFP_RXLOS Ports 33-40 */ /* SFP_RXLOS Ports 33-40 */
VALIDATED_READ(buf, values[4], VALIDATED_READ(buf, values[4],
i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_RXLOS_5), 0); i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_RXLOS_5), 0);
/* SFP_RXLOS Ports 41-48 */ /* SFP_RXLOS Ports 41-47 */
VALIDATED_READ(buf, values[5], VALIDATED_READ(buf, values[5],
i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_RXLOS_6), 0); i2c_smbus_read_byte_data(pdata2[swpld2].client, SFP_RXLOS_6), 0);
@@ -1516,7 +1499,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
reg_t = SFP_TXDIS_4; reg_t = SFP_TXDIS_4;
} else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */ } else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXDIS_5; reg_t = SFP_TXDIS_5;
} else if (port_t > 40 && port_t < 49) { /* SFP Port 41-48 */ } else if (port_t > 40 && port_t < 47) { /* SFP Port 41-48 */
reg_t = SFP_TXDIS_6; reg_t = SFP_TXDIS_6;
} else { } else {
values[0] = 1; /* return 1, module Transmitter Disabled */ values[0] = 1; /* return 1, module Transmitter Disabled */
@@ -1524,7 +1507,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
return sprintf(buf, "%d\n", values[0]); return sprintf(buf, "%d\n", values[0]);
} }
if (port_t > 0 && port_t < 49) { /* SFP */ if (port_t > 0 && port_t < 47) { /* SFP */
VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata2[swpld2].client, reg_t), 0); VALIDATED_READ(buf, values[0], i2c_smbus_read_byte_data(pdata2[swpld2].client, reg_t), 0);
} else { /* In agc7646slv1b only SFP support control TX_DISABLE MODE */ } else { /* In agc7646slv1b only SFP support control TX_DISABLE MODE */
values[0] = 1; values[0] = 1;
@@ -1554,7 +1537,7 @@ static ssize_t for_status(struct device *dev, struct device_attribute *dev_attr,
reg_t = SFP_TXFAULT_4; reg_t = SFP_TXFAULT_4;
} else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */ } else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXFAULT_5; reg_t = SFP_TXFAULT_5;
} else if (port_t > 40 && port_t < 49) { /* SFP Port 41-48 */ } else if (port_t > 40 && port_t < 47) { /* SFP Port 41-46 */
reg_t = SFP_TXFAULT_6; reg_t = SFP_TXFAULT_6;
} else { } else {
values[0] = 1; /* return 1, module is Fault */ values[0] = 1; /* return 1, module is Fault */
@@ -1600,9 +1583,9 @@ static ssize_t set_port_data(struct device *dev, struct device_attribute *dev_at
if(error) if(error)
return error; return error;
if(data < 1 || data > 54) /* valid port is 1-54 */ if(data < 1 || data > 52) /* valid port is 1-52 */
{ {
printk(KERN_ALERT "select port out of range (1-54)\n"); printk(KERN_ALERT "select port out of range (1-52)\n");
return count; return count;
} }
else else
@@ -1627,7 +1610,7 @@ static ssize_t set_lpmode_data(struct device *dev, struct device_attribute *dev_
return error; return error;
mutex_lock(&dni_lock); mutex_lock(&dni_lock);
port_t = sfp_port_data; port_t = sfp_port_data;
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_LPMODE; reg_t = QSFP_LPMODE;
} else { } else {
values = 0; /* return 0, module NOT in LP mode */ values = 0; /* return 0, module NOT in LP mode */
@@ -1643,14 +1626,13 @@ static ssize_t set_lpmode_data(struct device *dev, struct device_attribute *dev_
/* Indicate the module is in LP mode or not /* Indicate the module is in LP mode or not
* 0 = Disable * 0 = Disable
* 1 = Enable */ * 1 = Enable */
port_t = port_t - 1;
if (data == 0) if (data == 0)
{ {
bit_t = ~(1 << (port_t % 8)); bit_t = ~(1 << (port_t % 47));
values = values & bit_t; values = values & bit_t;
} }
else if (data == 1){ else if (data == 1){
bit_t = (1 << (port_t % 8)); bit_t = (1 << (port_t % 47));
values = values | bit_t; values = values | bit_t;
} }
else else
@@ -1685,7 +1667,7 @@ static ssize_t set_reset_data(struct device *dev, struct device_attribute *dev_a
mutex_lock(&dni_lock); mutex_lock(&dni_lock);
port_t = sfp_port_data; port_t = sfp_port_data;
if (port_t > 48 && port_t < 55) { /* QSFP Port 49-54 */ if (port_t > 46 && port_t < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_RESET; reg_t = QSFP_RESET;
} else { } else {
values = 1; /* return 1, module NOT in reset mode */ values = 1; /* return 1, module NOT in reset mode */
@@ -1701,15 +1683,14 @@ static ssize_t set_reset_data(struct device *dev, struct device_attribute *dev_a
/* Indicate the module is in reset mode or not /* Indicate the module is in reset mode or not
* 0 = Reset * 0 = Reset
* 1 = Normal */ * 1 = Normal */
port_t = port_t - 1;
if (data == 0) if (data == 0)
{ {
bit_t = ~(1 << (port_t % 8)); bit_t = ~(1 << (port_t % 47));
values = values & bit_t; values = values & bit_t;
} }
else if (data == 1) else if (data == 1)
{ {
bit_t = (1 << (port_t % 8)); bit_t = (1 << (port_t % 47));
values = values | bit_t; values = values | bit_t;
} }
else else
@@ -1754,7 +1735,7 @@ static ssize_t set_tx_disable(struct device *dev, struct device_attribute *dev_a
reg_t = SFP_TXDIS_4; reg_t = SFP_TXDIS_4;
} else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */ } else if (port_t > 32 && port_t < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXDIS_5; reg_t = SFP_TXDIS_5;
} else if (port_t > 40 && port_t < 49) { /* SFP Port 41-48 */ } else if (port_t > 40 && port_t < 47) { /* SFP Port 41-46 */
reg_t = SFP_TXDIS_6; reg_t = SFP_TXDIS_6;
} else { } else {
values = 1; /* return 1, module NOT in reset mode */ values = 1; /* return 1, module NOT in reset mode */
@@ -2651,16 +2632,16 @@ static int swpld1_mux_select(struct i2c_mux_core *muxc, u32 chan)
bmc_swpld1_mux_val = MUX_VAL_FAN_IO_CTL; bmc_swpld1_mux_val = MUX_VAL_FAN_IO_CTL;
break; break;
case 2: case 2:
bmc_swpld1_mux_val = (MUX_VAL_FAN1_EEPROM + 0x08); bmc_swpld1_mux_val = MUX_VAL_FAN1_EEPROM;
break; break;
case 3: case 3:
bmc_swpld1_mux_val = (MUX_VAL_FAN2_EEPROM + 0x09); bmc_swpld1_mux_val = MUX_VAL_FAN2_EEPROM;
break; break;
case 4: case 4:
bmc_swpld1_mux_val = (MUX_VAL_FAN3_EEPROM + 0x09); bmc_swpld1_mux_val = MUX_VAL_FAN3_EEPROM;
break; break;
case 5: case 5:
bmc_swpld1_mux_val = (MUX_VAL_FAN4_EEPROM + 0x09); bmc_swpld1_mux_val = MUX_VAL_FAN4_EEPROM;
break; break;
case 6: case 6:
bmc_swpld1_mux_val = (MUX_VAL_FAN_CTL + 0x08); bmc_swpld1_mux_val = (MUX_VAL_FAN_CTL + 0x08);
@@ -2837,8 +2818,8 @@ static int swpld3_mux_select(struct i2c_mux_core *muxc, u32 chan)
swpld3_qsfp_ch_en |= SWPLD3_SFP_CH4_EN << 4; swpld3_qsfp_ch_en |= SWPLD3_SFP_CH4_EN << 4;
swpld3_mux_val = swpld3_qsfp_ch_en | (chan - SWPLD3_SFP_PORT_29); swpld3_mux_val = swpld3_qsfp_ch_en | (chan - SWPLD3_SFP_PORT_29);
} }
/* SFP port 90-98, 9 ports, chan 39-47 */ /* SFP port 90-96, 7 ports, chan 39-45 */
else if ( chan >= SWPLD3_SFP_PORT_39 && chan < SWPLD3_SFP_PORT_48 ){ else if ( chan >= SWPLD3_SFP_PORT_39 && chan < SWPLD3_SFP_PORT_46 ){
swpld3_qsfp_ch_en |= SWPLD3_SFP_CH5_EN << 4; swpld3_qsfp_ch_en |= SWPLD3_SFP_CH5_EN << 4;
swpld3_mux_val = swpld3_qsfp_ch_en | (chan - SWPLD3_SFP_PORT_39); swpld3_mux_val = swpld3_qsfp_ch_en | (chan - SWPLD3_SFP_PORT_39);
} }

4
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/modules/builds/dni_agc7646slv1b_psu.c
View File

@@ -453,12 +453,12 @@ static int dps_800ab_16_d_remove(struct i2c_client *client)
} }
enum id_name { enum id_name {
dni_agc7646slv1b_psu, agc7646slv1b_psu,
dps_800ab_16_d dps_800ab_16_d
}; };
static const struct i2c_device_id dps_800ab_16_d_id[] = { static const struct i2c_device_id dps_800ab_16_d_id[] = {
{ "dni_agc7646slv1b_psu", dni_agc7646slv1b_psu }, { "agc7646slv1b_psu", agc7646slv1b_psu },
{ "dps_800ab_16_d", dps_800ab_16_d }, { "dps_800ab_16_d", dps_800ab_16_d },
{} {}
}; };

154
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/fani.c
View File

@@ -34,23 +34,6 @@ typedef struct fan_path_S
char *ctrl_speed; char *ctrl_speed;
}fan_path_T; }fan_path_T;
#ifdef I2C
static fan_path_T fan_path[] = /* must map with onlp_fan_id */
{
{ NULL, NULL, NULL },
{ "25-002c/fan4_fault", "25-002c/fan4_input", "25-002c/fan4_input_percentage" },
{ "25-002c/fan3_fault", "25-002c/fan3_input", "25-002c/fan3_input_percentage" },
{ "25-002c/fan2_fault", "25-002c/fan2_input", "25-002c/fan2_input_percentage" },
{ "25-002c/fan1_fault", "25-002c/fan1_input", "25-002c/fan1_input_percentage" },
{ "25-002d/fan4_fault", "25-002d/fan4_input", "25-002d/fan4_input_percentage" },
{ "25-002d/fan3_fault", "25-002d/fan3_input", "25-002d/fan3_input_percentage" },
{ "25-002d/fan2_fault", "25-002d/fan2_input", "25-002d/fan2_input_percentage" },
{ "25-002d/fan1_fault", "25-002d/fan1_input", "25-002d/fan1_input_percentage" },
{ "31-0058/psu_fan1_fault", "31-0058/psu_fan1_speed_rpm", "31-0058/psu_fan1_duty_cycle_percentage" },
{ "32-0058/psu_fan1_fault", "32-0058/psu_fan1_speed_rpm", "32-0058/psu_fan1_duty_cycle_percentage" }
};
#endif
#define MAKE_FAN_INFO_NODE_ON_FAN_BOARD(id) \ #define MAKE_FAN_INFO_NODE_ON_FAN_BOARD(id) \
{ \ { \
{ ONLP_FAN_ID_CREATE(FAN_##id##_ON_FAN_BOARD), "Chassis Fan "#id, 0 }, \ { ONLP_FAN_ID_CREATE(FAN_##id##_ON_FAN_BOARD), "Chassis Fan "#id, 0 }, \
@@ -96,7 +79,6 @@ onlp_fan_info_t linfo[] = {
static int dni_fani_info_get_fan(int local_id, onlp_fan_info_t* info, char *dev_name) static int dni_fani_info_get_fan(int local_id, onlp_fan_info_t* info, char *dev_name)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef BMC
uint8_t bit_data = 0x00; uint8_t bit_data = 0x00;
UINT4 u4Data = 0; UINT4 u4Data = 0;
UINT4 multiplier = 1; UINT4 multiplier = 1;
@@ -144,64 +126,12 @@ static int dni_fani_info_get_fan(int local_id, onlp_fan_info_t* info, char *dev_
info->status |= ONLP_FAN_STATUS_FAILED; info->status |= ONLP_FAN_STATUS_FAILED;
break; break;
} }
#elif defined I2C
int rpm = 0;
int fantray_present = -1;
char fullpath[100] = {0};
sprintf(fullpath, "%s%s", PREFIX_PATH, fan_path[local_id].speed);
rpm = dni_i2c_lock_read_attribute(NULL, fullpath);
info->rpm = rpm;
/* If rpm is FAN_ZERO_TACH, then the rpm value is zero. */
if(info->rpm == 960)
info->rpm = 0;
/* get speed percentage from rpm */
info->percentage = (info->rpm * 100)/MAX_FRONT_FAN_SPEED;
switch(local_id) {
case FAN_4_ON_FAN_BOARD:
case FAN_8_ON_FAN_BOARD:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN4_PRESENT_PATH);
if(fantray_present == 0)
info->status |= ONLP_FAN_STATUS_PRESENT;
else
info->status |= ONLP_FAN_STATUS_FAILED;
break;
case FAN_3_ON_FAN_BOARD:
case FAN_7_ON_FAN_BOARD:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN3_PRESENT_PATH);
if(fantray_present == 0)
info->status |= ONLP_FAN_STATUS_PRESENT;
else
info->status |= ONLP_FAN_STATUS_FAILED;
break;
case FAN_2_ON_FAN_BOARD:
case FAN_6_ON_FAN_BOARD:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN2_PRESENT_PATH);
if(fantray_present == 0)
info->status |= ONLP_FAN_STATUS_PRESENT;
else
info->status |= ONLP_FAN_STATUS_FAILED;
break;
case FAN_1_ON_FAN_BOARD:
case FAN_5_ON_FAN_BOARD:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN1_PRESENT_PATH);
if(fantray_present == 0)
info->status |= ONLP_FAN_STATUS_PRESENT;
else
info->status |= ONLP_FAN_STATUS_FAILED;
break;
}
#endif
return rv; return rv;
} }
static int dni_fani_info_get_fan_on_psu(int local_id, onlp_fan_info_t* info, char *dev_name) static int dni_fani_info_get_fan_on_psu(int local_id, onlp_fan_info_t* info, char *dev_name)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef BMC
UINT4 multiplier = 1; UINT4 multiplier = 1;
UINT4 u4Data = 0; UINT4 u4Data = 0;
uint8_t psu_present_bit = 0x00; uint8_t psu_present_bit = 0x00;
@@ -242,34 +172,6 @@ static int dni_fani_info_get_fan_on_psu(int local_id, onlp_fan_info_t* info, cha
} }
break; break;
} }
#elif defined I2C
int psu_present = 0;
int r_data = 0;
char fullpath[100] = {0};
switch(local_id) {
case FAN_1_ON_PSU1:
psu_present = dni_i2c_lock_read_attribute(NULL, PSU1_PRESENT_PATH);
break;
case FAN_1_ON_PSU2:
psu_present = dni_i2c_lock_read_attribute(NULL, PSU2_PRESENT_PATH);
break;
default:
break;
}
if(psu_present == 0)
info->status |= ONLP_FAN_STATUS_PRESENT | ONLP_FAN_STATUS_B2F;
else if(psu_present == 1)
info->status |= ONLP_FAN_STATUS_FAILED;
/* Read PSU FAN speed from psu_fan1_speed_rpm */
sprintf(fullpath, "%s%s", PREFIX_PATH, fan_path[local_id].speed);
r_data = dni_i2c_lock_read_attribute(NULL, fullpath);
info->rpm = r_data;
/* Calculate psu fan duty cycle based on rpm */
info->percentage = (info->rpm * 100) / MAX_PSU_FAN_SPEED;
#endif
return rv; return rv;
} }
@@ -341,33 +243,6 @@ int onlp_fani_info_get(onlp_oid_t id, onlp_fan_info_t* info)
int onlp_fani_rpm_set(onlp_oid_t id, int rpm) int onlp_fani_rpm_set(onlp_oid_t id, int rpm)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef I2C
int local_id;
char data[10] = {0};
char fullpath[70] = {0};
VALIDATE(id);
local_id = ONLP_OID_ID_GET(id);
/* get fullpath */
switch (local_id) {
case FAN_1_ON_FAN_BOARD:
case FAN_2_ON_FAN_BOARD:
case FAN_3_ON_FAN_BOARD:
case FAN_4_ON_FAN_BOARD:
case FAN_5_ON_FAN_BOARD:
case FAN_6_ON_FAN_BOARD:
case FAN_7_ON_FAN_BOARD:
case FAN_8_ON_FAN_BOARD:
sprintf(fullpath, "%s%s", PREFIX_PATH, fan_path[local_id].speed);
break;
default:
return ONLP_STATUS_E_INVALID;
}
sprintf(data, "%d", rpm);
dni_i2c_lock_write_attribute(NULL, data, fullpath);
#endif
return rv; return rv;
} }
@@ -382,35 +257,6 @@ int onlp_fani_rpm_set(onlp_oid_t id, int rpm)
int onlp_fani_percentage_set(onlp_oid_t id, int p) int onlp_fani_percentage_set(onlp_oid_t id, int p)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef I2C
int local_id;
char data[10] = {0};
char fullpath[70] = {0};
VALIDATE(id);
local_id = ONLP_OID_ID_GET(id);
/* Select PSU member */
switch (local_id) {
case FAN_1_ON_FAN_BOARD:
case FAN_2_ON_FAN_BOARD:
case FAN_3_ON_FAN_BOARD:
case FAN_4_ON_FAN_BOARD:
case FAN_5_ON_FAN_BOARD:
case FAN_6_ON_FAN_BOARD:
case FAN_7_ON_FAN_BOARD:
case FAN_8_ON_FAN_BOARD:
case FAN_1_ON_PSU1:
case FAN_1_ON_PSU2:
break;
default:
return ONLP_STATUS_E_INVALID;
}
sprintf(fullpath, "%s%s", PREFIX_PATH, fan_path[local_id].ctrl_speed);
/* Write percentage to psu_fan1_duty_cycle_percentage */
sprintf(data, "%d", p);
dni_i2c_lock_write_attribute(NULL, data, fullpath);
#endif
return rv; return rv;
} }

270
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/ledi.c
View File

@@ -89,12 +89,9 @@ int onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
{ {
int local_id; int local_id;
int r_data = 0; int r_data = 0;
VALIDATE(id); VALIDATE(id);
local_id = ONLP_OID_ID_GET(id); local_id = ONLP_OID_ID_GET(id);
*info = linfo[ONLP_OID_ID_GET(id)]; *info = linfo[ONLP_OID_ID_GET(id)];
#ifdef BMC
int bit_data = 0; int bit_data = 0;
switch(local_id) { switch(local_id) {
@@ -154,10 +151,11 @@ int onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
} }
r_data = bit_data; r_data = bit_data;
if(dni_fan_present(LED_REAR_FAN_TRAY_1) == ONLP_STATUS_OK){ if(dni_fan_present(LED_REAR_FAN_TRAY_1) == ONLP_STATUS_OK){
if((r_data & 0xc0) == 0x40) if((r_data & 0xc0) == 0x80)
info->mode = ONLP_LED_MODE_GREEN; info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0xc0) == 0x80) else if((r_data & 0xc0) == 0x40)
info->mode = ONLP_LED_MODE_RED; info->mode = ONLP_LED_MODE_RED;
} }
else else
@@ -169,10 +167,11 @@ int onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
} }
r_data = bit_data; r_data = bit_data;
if(dni_fan_present(LED_REAR_FAN_TRAY_2) == ONLP_STATUS_OK){ if(dni_fan_present(LED_REAR_FAN_TRAY_2) == ONLP_STATUS_OK){
if((r_data & 0x30) == 0x10) if((r_data & 0x30) == 0x20)
info->mode = ONLP_LED_MODE_GREEN; info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x30) == 0x20) else if((r_data & 0x30) == 0x10)
info->mode = ONLP_LED_MODE_RED; info->mode = ONLP_LED_MODE_RED;
} }
else else
@@ -183,10 +182,11 @@ int onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
} }
r_data = bit_data; r_data = bit_data;
if(dni_fan_present(LED_REAR_FAN_TRAY_3) == ONLP_STATUS_OK){ if(dni_fan_present(LED_REAR_FAN_TRAY_3) == ONLP_STATUS_OK){
if((r_data & 0x0c) == 0x04) if((r_data & 0x0c) == 0x08)
info->mode = ONLP_LED_MODE_GREEN; info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x0c) == 0x08) else if((r_data & 0x0c) == 0x04)
info->mode = ONLP_LED_MODE_RED; info->mode = ONLP_LED_MODE_RED;
} }
else else
@@ -198,110 +198,17 @@ int onlp_ledi_info_get(onlp_oid_t id, onlp_led_info_t* info)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
} }
r_data = bit_data; r_data = bit_data;
if(dni_fan_present(LED_REAR_FAN_TRAY_4) == ONLP_STATUS_OK){ if(dni_fan_present(LED_REAR_FAN_TRAY_4) == ONLP_STATUS_OK){
if((r_data & 0x03) == 0x01) if((r_data & 0x03) == 0x02)
info->mode = ONLP_LED_MODE_GREEN; info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x03) == 0x02) else if((r_data & 0x03) == 0x01)
info->mode = ONLP_LED_MODE_RED; info->mode = ONLP_LED_MODE_RED;
} }
else else
info->mode = ONLP_LED_MODE_OFF; info->mode = ONLP_LED_MODE_OFF;
break; break;
} }
#elif defined I2C
switch(local_id)
{
case LED_FRONT_FAN:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
if((r_data & 0x03) == 0x01)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x03) == 0x02)
info->mode = ONLP_LED_MODE_YELLOW;
else if((r_data & 0x03) == 0x03)
info->mode = ONLP_LED_MODE_YELLOW_BLINKING;
else if((r_data & 0x03) == 0x00)
info->mode = ONLP_LED_MODE_OFF;
else
return ONLP_STATUS_E_INTERNAL;
break;
case LED_FRONT_PWR:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
if((r_data & 0x0c) == 0x4)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x0c) == 0x8)
info->mode = ONLP_LED_MODE_YELLOW;
else if((r_data & 0x0c) == 0xc || (r_data & 0x0c) == 0x00)
info->mode = ONLP_LED_MODE_OFF;
else
return ONLP_STATUS_E_INTERNAL;
break;
case LED_FRONT_SYS:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
if((r_data & 0xf0) == 0x10)
info->mode = ONLP_LED_MODE_YELLOW;
else if((r_data & 0xf0) == 0x20)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0xf0) == 0x90) // 0.5S
info->mode = ONLP_LED_MODE_GREEN_BLINKING;
else if((r_data & 0xf0) == 0xa0) // 0.5S
info->mode = ONLP_LED_MODE_YELLOW_BLINKING;
else if ((r_data & 0xf0) == 0x00)
info->mode = ONLP_LED_MODE_OFF;
else
return ONLP_STATUS_E_INTERNAL;
break;
case LED_REAR_FAN_TRAY_1:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
if(dni_fan_present(LED_REAR_FAN_TRAY_1) == ONLP_STATUS_OK){
if((r_data & 0xc0) == 0x40)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0xc0) == 0x80)
info->mode = ONLP_LED_MODE_RED;
}
else
info->mode = ONLP_LED_MODE_OFF;
break;
case LED_REAR_FAN_TRAY_2:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
if(dni_fan_present(LED_REAR_FAN_TRAY_2) == ONLP_STATUS_OK){
if((r_data & 0x30) == 0x10)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x30) == 0x20)
info->mode = ONLP_LED_MODE_RED;
}
else
info->mode = ONLP_LED_MODE_OFF;
break;
case LED_REAR_FAN_TRAY_3:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
if(dni_fan_present(LED_REAR_FAN_TRAY_3) == ONLP_STATUS_OK){
if((r_data & 0x0c) == 0x04)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x0c) == 0x08)
info->mode = ONLP_LED_MODE_RED;
}
else
info->mode = ONLP_LED_MODE_OFF;
break;
case LED_REAR_FAN_TRAY_4:
r_data = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
if(dni_fan_present(LED_REAR_FAN_TRAY_4) == ONLP_STATUS_OK){
if((r_data & 0x03) == 0x01)
info->mode = ONLP_LED_MODE_GREEN;
else if((r_data & 0x03) == 0x02)
info->mode = ONLP_LED_MODE_RED;
}
else
info->mode = ONLP_LED_MODE_OFF;
break;
}
#endif
/* Set the on/off status */ /* Set the on/off status */
if (info->mode == ONLP_LED_MODE_OFF) if (info->mode == ONLP_LED_MODE_OFF)
info->status = ONLP_LED_STATUS_FAILED; info->status = ONLP_LED_STATUS_FAILED;
@@ -334,159 +241,6 @@ int onlp_ledi_set(onlp_oid_t id, int on_or_off)
int onlp_ledi_mode_set(onlp_oid_t id, onlp_led_mode_t mode) int onlp_ledi_mode_set(onlp_oid_t id, onlp_led_mode_t mode)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef I2C
VALIDATE(id);
int local_id = ONLP_OID_ID_GET(id);
uint8_t front_panel_led_value = 0;
uint8_t fan_tray_led_reg_value = 0;
switch(local_id)
{
case LED_FRONT_FAN:
front_panel_led_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
front_panel_led_value &= ~0x03;
if(mode == ONLP_LED_MODE_GREEN){
front_panel_led_value |= 0x01;
}
else if(mode == ONLP_LED_MODE_YELLOW){
front_panel_led_value |= 0x02;
}
else{
front_panel_led_value = front_panel_led_value;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, SYS_LED_REGISTER, front_panel_led_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_FRONT_PWR:
front_panel_led_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
front_panel_led_value &= ~0x0c;
if(mode == ONLP_LED_MODE_GREEN){
front_panel_led_value |= 0x04;
}
else if(mode == ONLP_LED_MODE_YELLOW){
front_panel_led_value |= 0x08;
}
else{
front_panel_led_value = front_panel_led_value;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, SYS_LED_REGISTER, front_panel_led_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_FRONT_SYS:
front_panel_led_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, SYS_LED_REGISTER);
front_panel_led_value &= ~0xf0;
if(mode == ONLP_LED_MODE_YELLOW){
front_panel_led_value |= 0x10;
}
else if(mode == ONLP_LED_MODE_GREEN){
front_panel_led_value |= 0x20;
}
else if(mode == ONLP_LED_MODE_GREEN_BLINKING){ // 0.5S
front_panel_led_value |= 0x90;
}
else if(mode == ONLP_LED_MODE_YELLOW_BLINKING){ // 0.5S
front_panel_led_value |= 0xa0;
}
else{
front_panel_led_value = front_panel_led_value;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, SYS_LED_REGISTER, front_panel_led_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_REAR_FAN_TRAY_1:
fan_tray_led_reg_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
fan_tray_led_reg_value &= ~0xc0;
if(mode == ONLP_LED_MODE_GREEN){
fan_tray_led_reg_value |= 0x40;
}
else if(mode == ONLP_LED_MODE_RED){
fan_tray_led_reg_value |= 0x80;
}
else{
fan_tray_led_reg_value = fan_tray_led_reg_value;;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, FAN_LED_REGISTER, fan_tray_led_reg_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_REAR_FAN_TRAY_2:
fan_tray_led_reg_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
fan_tray_led_reg_value &= ~0x30;
if(mode == ONLP_LED_MODE_GREEN){
fan_tray_led_reg_value |= 0x10;
}
else if(mode == ONLP_LED_MODE_RED){
fan_tray_led_reg_value |= 0x20;
}
else{
fan_tray_led_reg_value = fan_tray_led_reg_value;;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, FAN_LED_REGISTER, fan_tray_led_reg_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_REAR_FAN_TRAY_3:
fan_tray_led_reg_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
fan_tray_led_reg_value &= ~0x0c;
if(mode == ONLP_LED_MODE_GREEN){
fan_tray_led_reg_value |= 0x04;
}
else if(mode == ONLP_LED_MODE_RED){
fan_tray_led_reg_value |= 0x08;
}
else{
fan_tray_led_reg_value = fan_tray_led_reg_value;;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, FAN_LED_REGISTER, fan_tray_led_reg_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
case LED_REAR_FAN_TRAY_4:
fan_tray_led_reg_value = dni_lock_cpld_read_attribute(SWPLD1_PATH, FAN_LED_REGISTER);
fan_tray_led_reg_value &= ~0x03;
if(mode == ONLP_LED_MODE_GREEN){
fan_tray_led_reg_value |= 0x01;
}
else if(mode == ONLP_LED_MODE_RED){
fan_tray_led_reg_value |= 0x02;
}
else{
fan_tray_led_reg_value = fan_tray_led_reg_value;;
}
if(dni_lock_cpld_write_attribute(SWPLD1_PATH, FAN_LED_REGISTER, fan_tray_led_reg_value) != 0){
AIM_LOG_ERROR("Unable to set led(%d) status\r\n", local_id);
return ONLP_STATUS_E_INTERNAL;
}
break;
}
#endif
return rv; return rv;
} }

251
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/platform_lib.c
View File

@@ -64,7 +64,6 @@ void lockinit()
} }
} }
#ifdef BMC
int dni_ipmi_data_time_check(long last_time, long new_time, int time_threshold) int dni_ipmi_data_time_check(long last_time, long new_time, int time_threshold)
{ {
int ipmi_data_update = 0; int ipmi_data_update = 0;
@@ -144,14 +143,12 @@ bmc_info_t dev[] =
{"PSU2_Pin",0}, {"PSU2_Pin",0},
{"PSU2_Pout",0}, {"PSU2_Pout",0},
{"Fan_Temp", 0}, {"Fan_Temp", 0},
{"Temp_Sensor_1", 0}, {"TMP75_CPU-4d", 0},
{"Temp_Sensor_2", 0}, {"TMP75_FAN-4f", 0},
{"Temp_Sensor_3", 0}, {"TMP75-4e", 0},
{"Temp_Sensor_4", 0}, {"TMP75-4b", 0},
{"Temp_Sensor_5", 0}, {"TMP431_REMOTE-4c", 0},
{"Temp_Sensor_6", 0}, {"TMP431_LOCAL-4c", 0},
{"Temp_Sensor_7", 0},
{"Temp_Sensor_8", 0},
{"PSU1_Temp_1", 0}, {"PSU1_Temp_1", 0},
{"PSU2_Temp_1", 0} {"PSU2_Temp_1", 0}
}; };
@@ -498,51 +495,6 @@ int dni_bmc_psueeprom_info_get(char * r_data, char *device_name, int number)
END: END:
return rv; return rv;
} }
#endif
int hex_to_int(char hex_input)
{
int first = hex_input / 16 - 3;
int second = hex_input % 16;
int result = first * 10 + second;
if(result > 9) result--;
return result;
}
int hex_to_ascii(char hex_high, char hex_low)
{
int high = hex_to_int(hex_high) * 16;
int low = hex_to_int(hex_low);
return high + low;
}
int dni_i2c_lock_read(mux_info_t * mux_info, dev_info_t * dev_info)
{
int r_data = 0;
DNI_LOCK();
if(dev_info->size == 1)
r_data = onlp_i2c_readb(dev_info->bus, dev_info->addr, dev_info->offset, dev_info->flags);
else
r_data = onlp_i2c_readw(dev_info->bus, dev_info->addr, dev_info->offset, dev_info->flags);
DNI_UNLOCK();
return r_data;
}
int dni_i2c_lock_write(mux_info_t * mux_info, dev_info_t * dev_info)
{
DNI_LOCK();
/* Write size */
if(dev_info->size == 1)
onlp_i2c_write(dev_info->bus, dev_info->addr, dev_info->offset, 1, &dev_info->data_8, dev_info->flags);
else
onlp_i2c_writew(dev_info->bus, dev_info->addr, dev_info->offset, dev_info->data_16, dev_info->flags);
DNI_UNLOCK();
return 0;
}
int dni_i2c_lock_read_attribute(mux_info_t * mux_info, char * fullpath) int dni_i2c_lock_read_attribute(mux_info_t * mux_info, char * fullpath)
{ {
@@ -553,96 +505,8 @@ int dni_i2c_lock_read_attribute(mux_info_t * mux_info, char * fullpath)
if ((fd = open(fullpath, O_RDONLY)) >= 0) if ((fd = open(fullpath, O_RDONLY)) >= 0)
{ {
if ((read(fd, r_data, nbytes)) > 0) if ((read(fd, r_data, nbytes)) > 0)
{
rv = atoi(r_data); rv = atoi(r_data);
}
close(fd);
DNI_UNLOCK();
return rv;
}
int dni_i2c_lock_write_attribute(mux_info_t * mux_info, char * data,char * fullpath)
{
int fd, rv = -1;
DNI_LOCK();
/* Create output file descriptor */
if ((fd = open(fullpath, O_WRONLY, 0644)) >= 0)
{
if (write(fd, data, strlen(data)) > 0)
{
fsync(fd);
rv = 0;
}
}
close(fd);
DNI_UNLOCK();
return rv;
}
/* Use this function to select MUX and read data on CPLD */
int dni_lock_cpld_read_attribute(char *cpld_path, int addr)
{
int fd, fd1, nbytes = 10, data = 0, rv = -1;
char r_data[10] = {0};
char address[10] = {0};
char cpld_data_path[100] = {0};
char cpld_addr_path[100] = {0};
sprintf(cpld_data_path, "%s/swpld1_reg_value", cpld_path);
sprintf(cpld_addr_path, "%s/swpld1_reg_addr", cpld_path);
sprintf(address, "0x%02x", addr);
DNI_LOCK();
/* Create output file descriptor */
if ((fd = open(cpld_addr_path, O_WRONLY, 0644)) >= 0)
{
if (write(fd, address, strlen(address)) > 0)
{
fsync(fd);
if ((fd1 = open(cpld_data_path, O_RDONLY, 0644)) >= 0)
{
if ((read(fd1, r_data, nbytes)) > 0)
{
sscanf(r_data, "%x", &data);
rv = data;
}
}
close(fd1);
}
}
close(fd);
DNI_UNLOCK();
return rv;
}
/* Use this function to select MUX and write data on CPLD */
int dni_lock_cpld_write_attribute(char *cpld_path, int addr, int data)
{
int fd, fd1, rv = -1;
char address[10] = {0};
char datas[10] = {0};
char cpld_data_path[100] = {0};
char cpld_addr_path[100] = {0};
sprintf(cpld_data_path, "%s/swpld1_reg_value", cpld_path);
sprintf(cpld_addr_path, "%s/swpld1_reg_addr", cpld_path);
sprintf(address, "0x%02x", addr);
DNI_LOCK();
/* Create output file descriptor */
if ((fd = open(cpld_addr_path, O_WRONLY, 0644)) >= 0)
{
if ((write(fd, address, strlen(address))) > 0)
{
fsync(fd);
if ((fd1 = open(cpld_data_path, O_WRONLY, 0644)) >= 0)
{
sprintf(datas, "0x%02x", data);
if (write(fd1, datas, strlen(datas)) > 0)
{
fsync(fd1);
rv = 0;
}
}
close(fd1);
} }
} }
close(fd); close(fd);
@@ -653,7 +517,6 @@ int dni_lock_cpld_write_attribute(char *cpld_path, int addr, int data)
int dni_fan_present(int id) int dni_fan_present(int id)
{ {
int rv; int rv;
#ifdef BMC
uint8_t bit_data = 0; uint8_t bit_data = 0;
int data = 0; int data = 0;
uint8_t present_bit = 0x00; uint8_t present_bit = 0x00;
@@ -670,105 +533,5 @@ int dni_fan_present(int id)
} }
else else
rv = ONLP_STATUS_E_INVALID; rv = ONLP_STATUS_E_INVALID;
#elif defined I2C
int fantray_present = -1;
switch(id) {
case LED_REAR_FAN_TRAY_1:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN1_PRESENT_PATH);
break;
case LED_REAR_FAN_TRAY_2:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN2_PRESENT_PATH);
break;
case LED_REAR_FAN_TRAY_3:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN3_PRESENT_PATH);
break;
case LED_REAR_FAN_TRAY_4:
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN4_PRESENT_PATH);
break;
}
if(fantray_present == 0)
rv = ONLP_STATUS_OK;
else if(fantray_present == 1)
rv = ONLP_STATUS_E_INVALID;
#endif
return rv; return rv;
} }
int dni_fan_speed_good()
{
int rpm = 0, rpm1 = 0, speed_good = 0;
rpm = dni_i2c_lock_read_attribute(NULL, FAN1_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN1_REAR);
if(rpm != 0 && rpm != 960 && rpm1 != 0 && rpm1 != 960)
speed_good++;
rpm = dni_i2c_lock_read_attribute(NULL, FAN2_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN2_REAR);
if(rpm != 0 && rpm != 960 && rpm1 != 0 && rpm1 != 960)
speed_good++;
rpm = dni_i2c_lock_read_attribute(NULL, FAN3_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN3_REAR);
if(rpm != 0 && rpm != 960 && rpm1 != 0 && rpm1 != 960)
speed_good++;
rpm = dni_i2c_lock_read_attribute(NULL, FAN4_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN4_REAR);
if(rpm != 0 && rpm != 960 && rpm1 != 0 && rpm1 != 960)
speed_good++;
return speed_good;
}
int dni_i2c_read_attribute_binary(char *filename, char *buffer, int buf_size, int data_len)
{
int fd, rv = 0;
int len;
DNI_LOCK();
if ((buffer == NULL) || (buf_size < 0)) {
rv = -1;
goto ERROR;
}
if ((fd = open(filename, O_RDONLY)) == -1) {
rv = -1;
goto ERROR;
}
if ((len = read(fd, buffer, buf_size)) < 0) {
close(fd);
rv = -1;
goto ERROR;
}
if ((close(fd) == -1)) {
rv = -1;
goto ERROR;
}
if ((len > buf_size) || (data_len != 0 && len != data_len)) {
rv = -1;
goto ERROR;
}
ERROR:
DNI_UNLOCK();
return rv;
}
int dni_i2c_read_attribute_string(char *filename, char *buffer, int buf_size, int data_len)
{
int ret;
if (data_len >= buf_size)
return -1;
ret = dni_i2c_read_attribute_binary(filename, buffer, buf_size-1, data_len);
if (ret == 0)
buffer[buf_size-1] = '\0';
return ret;
}

68
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/platform_lib.h
View File

@@ -30,23 +30,19 @@
#include <onlp/onlp.h> #include <onlp/onlp.h>
#include <onlplib/shlocks.h> #include <onlplib/shlocks.h>
#define BMC
//#define I2C
typedef unsigned int UINT4; typedef unsigned int UINT4;
/* CPLD numbrt & peripherals */ /* CPLD numbrt & peripherals */
#define NUM_OF_SFP (48) #define NUM_OF_SFP (46)
#define NUM_OF_QSFP (6) #define NUM_OF_QSFP (6)
#define NUM_OF_PORT NUM_OF_SFP + NUM_OF_QSFP #define NUM_OF_PORT NUM_OF_SFP + NUM_OF_QSFP
#define NUM_OF_THERMAL_ON_MAIN_BROAD (9) #define NUM_OF_THERMAL_ON_MAIN_BROAD (6)
#define NUM_OF_LED_ON_MAIN_BROAD (7) #define NUM_OF_LED_ON_MAIN_BROAD (7)
#define NUM_OF_FAN_ON_MAIN_BROAD (8) #define NUM_OF_FAN_ON_MAIN_BROAD (8)
#define NUM_OF_PSU_ON_MAIN_BROAD (2) #define NUM_OF_PSU_ON_MAIN_BROAD (2)
#define NUM_OF_SENSORS (47)
#define CHASSIS_FAN_COUNT (8) #define CHASSIS_FAN_COUNT (8)
#define CHASSIS_THERMAL_COUNT (9) #define CHASSIS_THERMAL_COUNT (6)
#define NUM_OF_THERMAL (11) #define NUM_OF_THERMAL (8)
#define PSU1_ID (1) #define PSU1_ID (1)
#define PSU2_ID (2) #define PSU2_ID (2)
#define PSU_NUM_LENGTH (15) #define PSU_NUM_LENGTH (15)
@@ -54,50 +50,18 @@ typedef unsigned int UINT4;
#define MAX_PSU_FAN_SPEED (18380) #define MAX_PSU_FAN_SPEED (18380)
#define MAX_REAR_FAN_SPEED (20500) #define MAX_REAR_FAN_SPEED (20500)
#define FAN_ZERO_RPM (960) #define FAN_ZERO_RPM (960)
#define FAN_SPEED_NORMALLY (4)
#define ALL_FAN_TRAY_EXIST (4)
#define BMC_OFF (1)
#define BMC_ON (0)
#define PSU_NODE_MAX_PATH_LEN (64)
#define FAN_TIME_THRESHOLD (5) #define FAN_TIME_THRESHOLD (5)
#define PSU_TIME_THRESHOLD (5) #define PSU_TIME_THRESHOLD (5)
#define THERMAL_TIME_THRESHOLD (10) #define THERMAL_TIME_THRESHOLD (10)
#define PSU_EEPROM_TIME_THRESHOLD (10) #define PSU_EEPROM_TIME_THRESHOLD (10)
#define SWPLD_DATA_TIME_THRESHOLD (5) #define SWPLD_DATA_TIME_THRESHOLD (5)
#define DEV_NUM (33) #define DEV_NUM (32)
#define CPU_CPLD_VERSION "/sys/devices/platform/delta-agc7646slv1b-cpld.0/cpuld_ver" #define CPU_CPLD_VERSION "/sys/devices/platform/delta-agc7646slv1b-cpld.0/cpuld_ver"
#define IDPROM_PATH "/sys/class/i2c-adapter/i2c-1/1-0053/eeprom" #define IDPROM_PATH "/sys/class/i2c-adapter/i2c-1/1-0053/eeprom"
#define SWPLD1_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0" #define SWPLD1_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0"
#define SWPLD2_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld2.0" #define SWPLD2_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld2.0"
#define FAN1_FRONT "/sys/bus/i2c/devices/i2c-25/25-002c/fan4_input"
#define FAN1_REAR "/sys/bus/i2c/devices/i2c-25/25-002d/fan4_input"
#define FAN2_FRONT "/sys/bus/i2c/devices/i2c-25/25-002c/fan3_input"
#define FAN2_REAR "/sys/bus/i2c/devices/i2c-25/25-002d/fan3_input"
#define FAN3_FRONT "/sys/bus/i2c/devices/i2c-25/25-002c/fan2_input"
#define FAN3_REAR "/sys/bus/i2c/devices/i2c-25/25-002d/fan2_input"
#define FAN4_FRONT "/sys/bus/i2c/devices/i2c-25/25-002c/fan1_input"
#define FAN4_REAR "/sys/bus/i2c/devices/i2c-25/25-002d/fan1_input"
#define PORT_EEPROM_FORMAT "/sys/bus/i2c/devices/%d-0050/eeprom" #define PORT_EEPROM_FORMAT "/sys/bus/i2c/devices/%d-0050/eeprom"
#define SFP_SELECT_PORT_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_select_port"
#define SFP_IS_PRESENT_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_is_present"
#define SFP_IS_PRESENT_ALL_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_is_present_all"
#define SFP_RX_LOS_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_rx_los"
#define SFP_RX_LOS_ALL_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_rx_los_all"
#define SFP_TX_DISABLE_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_tx_disable"
#define SFP_TX_FAULT_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_tx_fault"
#define QSFP_RESET_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_reset"
#define QSFP_LP_MODE_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/sfp_lp_mode"
#define PREFIX_PATH "/sys/bus/i2c/devices/"
#define PSU1_AC_PMBUS_PREFIX "/sys/bus/i2c/devices/31-0058/"
#define PSU2_AC_PMBUS_PREFIX "/sys/bus/i2c/devices/32-0058/"
#define PSU2_AC_PMBUS_NODE(node) PSU2_AC_PMBUS_PREFIX#node
#define FAN1_PRESENT_PATH "/sys/class/gpio/gpio499/value"
#define FAN2_PRESENT_PATH "/sys/class/gpio/gpio498/value"
#define FAN3_PRESENT_PATH "/sys/class/gpio/gpio497/value"
#define FAN4_PRESENT_PATH "/sys/class/gpio/gpio496/value"
#define PSU1_PRESENT_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/psu1_present"
#define PSU2_PRESENT_PATH "/sys/devices/platform/delta-agc7646slv1b-swpld1.0/psu2_present"
#define CHECK_TIME_FILE "/tmp/check_time_file" #define CHECK_TIME_FILE "/tmp/check_time_file"
#define BMC_INFO_TABLE "/tmp/bmc_info" #define BMC_INFO_TABLE "/tmp/bmc_info"
@@ -214,18 +178,11 @@ typedef struct onlp_psu_dev_s
eeprom_info_t psu_eeprom_table[2]; eeprom_info_t psu_eeprom_table[2];
}onlp_psu_dev_t; }onlp_psu_dev_t;
int dni_i2c_read_attribute_binary(char *filename, char *buffer, int buf_size, int data_len);
int dni_lock_cpld_write_attribute(char *cpld_path, int addr, int data);
int dni_lock_cpld_read_attribute(char *cpld_path, int addr);
int dni_fan_present(int id); int dni_fan_present(int id);
int dni_fan_speed_good();
int dni_i2c_read_attribute_string(char *filename, char *buffer, int buf_size, int data_len);
int dni_bmc_sensor_read(char *device_name, UINT4 *num, UINT4 multiplier, int sensor_type); int dni_bmc_sensor_read(char *device_name, UINT4 *num, UINT4 multiplier, int sensor_type);
int dni_bmc_psueeprom_info_get(char *r_data,char *device_name,int number); int dni_bmc_psueeprom_info_get(char *r_data,char *device_name,int number);
int dni_bmc_fanpresent_info_get(uint8_t *fan_present_bit); int dni_bmc_fanpresent_info_get(uint8_t *fan_present_bit);
int dni_i2c_lock_read( mux_info_t * mux_info, dev_info_t * dev_info);
int dni_i2c_lock_read_attribute(mux_info_t * mux_info, char * fullpath); int dni_i2c_lock_read_attribute(mux_info_t * mux_info, char * fullpath);
int dni_i2c_lock_write_attribute(mux_info_t * mux_info, char * data,char * fullpath);
int dni_bmc_data_get(int bus, int addr, int reg, int *r_data); int dni_bmc_data_get(int bus, int addr, int reg, int *r_data);
int dni_bmc_data_set(int bus, int addr, int reg, uint8_t w_data); int dni_bmc_data_set(int bus, int addr, int reg, uint8_t w_data);
void lockinit(); void lockinit();
@@ -236,17 +193,14 @@ float dev_sensor[50];
enum onlp_thermal_id enum onlp_thermal_id
{ {
THERMAL_RESERVED = 0, THERMAL_RESERVED = 0,
THERMAL_1_ON_FAN_BOARD, THERMAL_1_ON_CPU_BOARD,
THERMAL_2_ON_CPU_BOARD, THERMAL_2_ON_FAN_BOARD,
THERMAL_3_ON_MAIN_BOARD_TEMP_1, THERMAL_3_ON_MAIN_BOARD_TEMP_1,
THERMAL_4_ON_MAIN_BOARD_TEMP_2, THERMAL_4_ON_MAIN_BOARD_TEMP_2,
THERMAL_5_ON_MAIN_BOARD_TEMP_1, THERMAL_5_ON_MAIN_BOARD_TEMP_3_1,
THERMAL_6_ON_MAIN_BOARD_TEMP_2, THERMAL_6_ON_MAIN_BOARD_TEMP_3_2,
THERMAL_7_ON_MAIN_BOARD_TEMP_3, THERMAL_7_ON_PSU1,
THERMAL_8_ON_MAIN_BOARD, THERMAL_8_ON_PSU2
THERMAL_9_ON_MAIN_BOARD,
THERMAL_10_ON_PSU1,
THERMAL_11_ON_PSU2
}; };
typedef enum typedef enum

135
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/psui.c
View File

@@ -49,32 +49,6 @@ static onlp_psu_info_t pinfo[] =
} }
}; };
#ifdef I2C
static int dni_psu_pmbus_info_get(int id, char *node, int *value)
{
int ret = ONLP_STATUS_OK;
char node_path[PSU_NODE_MAX_PATH_LEN] = {0};
*value = 0;
switch(id)
{
case PSU1_ID:
sprintf(node_path, "%s%s", PSU1_AC_PMBUS_PREFIX, node);
break;
case PSU2_ID:
sprintf(node_path, "%s%s", PSU2_AC_PMBUS_PREFIX, node);
break;
default:
break;
}
/* Read attribute value */
*value = dni_i2c_lock_read_attribute(NULL, node_path);
return ret;
}
#endif
int onlp_psui_init(void) int onlp_psui_init(void)
{ {
lockinit(); lockinit();
@@ -92,7 +66,6 @@ static int dni_psu_info_get(onlp_oid_t id, onlp_psu_info_t* info)
* Set PSU's fan and thermal to child OID */ * Set PSU's fan and thermal to child OID */
info->hdr.coids[0] = ONLP_FAN_ID_CREATE(local_id + CHASSIS_FAN_COUNT); info->hdr.coids[0] = ONLP_FAN_ID_CREATE(local_id + CHASSIS_FAN_COUNT);
info->hdr.coids[1] = ONLP_THERMAL_ID_CREATE(local_id + CHASSIS_THERMAL_COUNT); info->hdr.coids[1] = ONLP_THERMAL_ID_CREATE(local_id + CHASSIS_THERMAL_COUNT);
#ifdef BMC
int i = 0; int i = 0;
char device_name[10] = {0}; char device_name[10] = {0};
UINT4 u4Data = 0; UINT4 u4Data = 0;
@@ -102,7 +75,6 @@ static int dni_psu_info_get(onlp_oid_t id, onlp_psu_info_t* info)
char *module_name = name; char *module_name = name;
char *module_name1 = name1; char *module_name1 = name1;
/* get psu model name */ /* get psu model name */
if(dni_bmc_psueeprom_info_get(name, "Product Name", local_id) == ONLP_STATUS_OK) if(dni_bmc_psueeprom_info_get(name, "Product Name", local_id) == ONLP_STATUS_OK)
{ {
@@ -186,74 +158,6 @@ static int dni_psu_info_get(onlp_oid_t id, onlp_psu_info_t* info)
else else
info->caps |= ONLP_PSU_STATUS_UNPLUGGED; info->caps |= ONLP_PSU_STATUS_UNPLUGGED;
#elif defined I2C
int val = 0;
char val_char[15] = {'\0'};
char node_path[PSU_NODE_MAX_PATH_LEN] = {'\0'};
char psu_path[PSU_NODE_MAX_PATH_LEN] = {'\0'};
int index = ONLP_OID_ID_GET(info->hdr.id);
switch(index)
{
case PSU1_ID:
sprintf(psu_path, "%s", PSU1_AC_PMBUS_PREFIX);
break;
case PSU2_ID:
sprintf(psu_path, "%s", PSU2_AC_PMBUS_PREFIX);
break;
default:
break;
}
/* Read PSU product name from attribute */
sprintf(node_path, "%s%s", psu_path, "psu_mfr_model");
dni_i2c_read_attribute_string(node_path, val_char, sizeof(val_char), 0);
strcpy(info->model, val_char);
/* Read PSU serial number from attribute */
sprintf(node_path, "%s%s", psu_path, "psu_mfr_serial");
dni_i2c_read_attribute_string(node_path, val_char, sizeof(val_char), 0);
strcpy(info->serial, val_char);
/* Read voltage, current and power */
if (dni_psu_pmbus_info_get(index, "psu_v_in", &val) == 0)
{
info->mvin = val;
info->caps |= ONLP_PSU_CAPS_VIN;
}
if (dni_psu_pmbus_info_get(index, "psu_v_out", &val) == 0)
{
info->mvout = val;
info->caps |= ONLP_PSU_CAPS_VOUT;
}
if (dni_psu_pmbus_info_get(index, "psu_i_in", &val) == 0)
{
info->miin = val;
info->caps |= ONLP_PSU_CAPS_IIN;
}
if (dni_psu_pmbus_info_get(index, "psu_i_out", &val) == 0)
{
info->miout = val;
info->caps |= ONLP_PSU_CAPS_IOUT;
}
if (dni_psu_pmbus_info_get(index, "psu_p_in", &val) == 0)
{
info->mpin = val;
info->caps |= ONLP_PSU_CAPS_PIN;
}
if (dni_psu_pmbus_info_get(index, "psu_p_out", &val) == 0)
{
info->mpout = val;
info->caps |= ONLP_PSU_CAPS_POUT;
}
#endif
return ret; return ret;
} }
@@ -261,13 +165,11 @@ int onlp_psui_info_get(onlp_oid_t id, onlp_psu_info_t* info)
{ {
int ret = ONLP_STATUS_OK; int ret = ONLP_STATUS_OK;
int index = ONLP_OID_ID_GET(id); int index = ONLP_OID_ID_GET(id);
VALIDATE(id); VALIDATE(id);
/* Set the onlp_oid_hdr_t */ /* Set the onlp_oid_hdr_t */
memset(info, 0, sizeof(onlp_psu_info_t)); memset(info, 0, sizeof(onlp_psu_info_t));
*info = pinfo[index]; *info = pinfo[index];
#ifdef BMC
char device_name[10] = {0}; char device_name[10] = {0};
UINT4 u4Data = 0; UINT4 u4Data = 0;
UINT4 multiplier = 1000; UINT4 multiplier = 1000;
@@ -285,43 +187,6 @@ int onlp_psui_info_get(onlp_oid_t id, onlp_psu_info_t* info)
info->status = ONLP_PSU_STATUS_PRESENT; info->status = ONLP_PSU_STATUS_PRESENT;
info->caps |= ONLP_PSU_CAPS_VIN; info->caps |= ONLP_PSU_CAPS_VIN;
} }
#elif defined I2C
int psu_present = -1;
int val = 0;
switch(index)
{
case PSU1_ID:
psu_present = dni_i2c_lock_read_attribute(NULL, PSU1_PRESENT_PATH);
break;
case PSU2_ID:
psu_present = dni_i2c_lock_read_attribute(NULL, PSU2_PRESENT_PATH);
break;
default:
break;
}
/* Check PSU have voltage input or not */
dni_psu_pmbus_info_get(index, "psu_v_in", &val);
/* Check PSU is PRESENT or not */
if(val == 0 && psu_present == 1)
{
/* PSU is not PRESENT */
/* Able to read PSU VIN(psu_power_not_good) */
info->status |= ONLP_PSU_STATUS_FAILED;
return ret;
}
else if(val == 0 && psu_present == 0)
{
/* Unable to read PSU VIN(psu_power_good) */
info->status |= ONLP_PSU_STATUS_UNPLUGGED;
}
else
{
info->status |= ONLP_PSU_STATUS_PRESENT;
}
#endif
ret = dni_psu_info_get(id, info); ret = dni_psu_info_get(id, info);
return ret; return ret;
} }

299
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/sfpi.c
View File

@@ -40,7 +40,7 @@ int sfp_map_bus[] = {
61, 62, 63, 64, 65, 66, 67, 68, 69, 70, /* SFP */ 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, /* SFP */
71, 72, 73, 74, 75, 76, 77, 78, 79, 80, /* SFP */ 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, /* SFP */
81, 82, 83, 84, 85, 86, 87, 88, 89, 90, /* SFP */ 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, /* SFP */
91, 92, 93, 94, 95, 96, 97, 98, /* SFP */ 91, 92, 93, 94, 95, 96, /* SFP */
41, 42, 43, 44, 45, 46, /* QSFP */ 41, 42, 43, 44, 45, 46, /* QSFP */
}; };
@@ -58,14 +58,14 @@ int onlp_sfpi_init(void)
int onlp_sfpi_map_bus_index(int port) int onlp_sfpi_map_bus_index(int port)
{ {
if(port < 0 || port > 54) if(port < 0 || port > 52)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
return sfp_map_bus[port-1]; return sfp_map_bus[port-1];
} }
int onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap) int onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap)
{ {
/* Ports {1, 54} */ /* Ports {1, 52} */
int p; int p;
AIM_BITMAP_CLR_ALL(bmap); AIM_BITMAP_CLR_ALL(bmap);
@@ -78,7 +78,6 @@ int onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap)
int onlp_sfpi_is_present(int port) int onlp_sfpi_is_present(int port)
{ {
int present, present_bit = 0x00; int present, present_bit = 0x00;
#ifdef BMC
uint8_t reg_t = 0x00; uint8_t reg_t = 0x00;
int bit_t = 0x00; int bit_t = 0x00;
@@ -92,22 +91,21 @@ int onlp_sfpi_is_present(int port)
reg_t = SFP_PRESENCE_4; reg_t = SFP_PRESENCE_4;
} else if (port > 32 && port < 41) { /* SFP Port 33-40 */ } else if (port > 32 && port < 41) { /* SFP Port 33-40 */
reg_t = SFP_PRESENCE_5; reg_t = SFP_PRESENCE_5;
} else if (port > 40 && port < 49) { /* SFP Port 41-48 */ } else if (port > 40 && port < 47) { /* SFP Port 41-46 */
reg_t = SFP_PRESENCE_6; reg_t = SFP_PRESENCE_6;
} else if (port > 48 && port < 55) { /* QSFP Port 1-6 */ } else if (port > 46 && port < 53) { /* QSFP Port 1-6 */
reg_t = QSFP_PRESENCE; reg_t = QSFP_PRESENCE;
} else { } else {
present_bit = 1; /* return 1, module is not present */ present_bit = 1; /* return 1, module is not present */
} }
if (port > 48 && port < 55) { /* QSFP */ if (port > 46 && port < 53) { /* QSFP */
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &present_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &present_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
port = port - 1; bit_t = 1 << (port % 47);
bit_t = 1 << (port % 8);
present_bit = present_bit & bit_t; present_bit = present_bit & bit_t;
present_bit = present_bit / bit_t; present_bit = present_bit / bit_t;
} }
else { /* SFP */ else { /* SFP */
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &present_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &present_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
@@ -116,24 +114,6 @@ int onlp_sfpi_is_present(int port)
present_bit = present_bit & bit_t; present_bit = present_bit & bit_t;
present_bit = present_bit / bit_t; present_bit = present_bit / bit_t;
} }
#elif defined I2C
char port_data[3] = {'\0'};
if(port > 0 && port < 55)
{
/* Select QSFP/SFP port */
sprintf(port_data, "%d", port );
if(dni_i2c_lock_write_attribute(NULL, port_data, SFP_SELECT_PORT_PATH) < 0){
AIM_LOG_ERROR("Unable to select port(%d)\r\n", port);
}
/* Read QSFP/SFP MODULE is present or not */
present_bit = dni_i2c_lock_read_attribute(NULL, SFP_IS_PRESENT_PATH);
if(present_bit < 0){
AIM_LOG_ERROR("Unable to read present or not from port(%d)\r\n", port);
}
}
#endif
/* From sfp_is_present value, /* From sfp_is_present value,
* return 0 = The module is preset * return 0 = The module is preset
@@ -144,7 +124,7 @@ int onlp_sfpi_is_present(int port)
present = 0; present = 0;
AIM_LOG_ERROR("Unble to present status from port(%d)\r\n", port); AIM_LOG_ERROR("Unble to present status from port(%d)\r\n", port);
} else { } else {
/* Port range over 1-54, return -1 */ /* Port range over 1-52, return -1 */
AIM_LOG_ERROR("Error to present status from port(%d)\r\n", port); AIM_LOG_ERROR("Error to present status from port(%d)\r\n", port);
present = -1; present = -1;
} }
@@ -155,23 +135,22 @@ int onlp_sfpi_presence_bitmap_get(onlp_sfp_bitmap_t* dst)
{ {
int count = 0; int count = 0;
uint8_t bytes[7] = {0}; uint8_t bytes[7] = {0};
#ifdef BMC
uint8_t reg_t = 0x00; uint8_t reg_t = 0x00;
int present_data = 0x00; int present_data = 0x00;
uint8_t r_array[7] = {0}; uint8_t r_array[7] = {0};
/* Read presence bitmap from SWPLD2 SFP+ and SWPLD1 QSFP28 Presence Register /* Read presence bitmap from SWPLD2 SFP+ and SWPLD1 QSFP28 Presence Register
* if only port 0 is present, return 3F FF FF FF FF FF FE * if only port 0 is present, return F FF FF FF FF FF FE
* if only port 0 and 1 present, return 3F FF FF FF FF FF FC */ * if only port 0 and 1 present, return F FF FF FF FF FF FC */
for (count = 0; count < 7; count++) { for (count = 0; count < 7; count++) {
if (count < 6) { /* SFP Port 1-48 */ if (count < 6) { /* SFP Port 1-46 */
reg_t = SFP_PRESENCE_1 + count; reg_t = SFP_PRESENCE_1 + count;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &present_data) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &present_data) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
r_array[count] = present_data; r_array[count] = present_data;
} }
else { /* QSFP Port 49-54 */ else { /* QSFP Port 47-52 */
reg_t = QSFP_PRESENCE; reg_t = QSFP_PRESENCE;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &present_data) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &present_data) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
@@ -183,47 +162,25 @@ int onlp_sfpi_presence_bitmap_get(onlp_sfp_bitmap_t* dst)
for (count = 0; count < 7; count++) { for (count = 0; count < 7; count++) {
bytes[count] = ~r_array[6 - count]; bytes[count] = ~r_array[6 - count];
} }
#elif defined I2C
char present_all_data[21] = {'\0'};
char *r_byte;
char *r_array[7];
/* Read presence bitmap from SWPLD2 SFP+ and SWPLD1 QSFP28 Presence Register
* if only port 0 is present, return 3F FF FF FF FF FF FE
* if only port 0 and 1 present, return 3F FF FF FF FF FF FC */
if(dni_i2c_read_attribute_string(SFP_IS_PRESENT_ALL_PATH, present_all_data,
sizeof(present_all_data), 0) < 0) {
return -1;
}
/* String split */
r_byte = strtok(present_all_data, " ");
while (r_byte != NULL) {
r_array[count++] = r_byte;
r_byte = strtok(NULL, " ");
}
/* Convert a string to unsigned 8 bit integer
* and saved into bytes[] */
for (count = 0; count < 7; count++) {
bytes[count] = ~strtol(r_array[count], NULL, 16);
}
#endif
/* Mask out non-existant SFP/QSFP ports */ /* Mask out non-existant SFP/QSFP ports */
uint8_t save_bytes = 0x00;
bytes[1] &= 0x3F;
bytes[0] &= 0x3F; bytes[0] &= 0x3F;
save_bytes = bytes[0] & 0x03;
save_bytes = save_bytes << 6;
bytes[1] |= save_bytes;
bytes[0] &= 0x3c;
bytes[0] = bytes[0] >> 2;
/* Convert to 64 bit integer in port order */ /* Convert to 64 bit integer in port order */
int i = 0; int i = 0;
uint64_t presence_all = 0; uint64_t presence_all = 0;
for(i = 0; i < AIM_ARRAYSIZE(bytes); i++) { for(i = 0; i < AIM_ARRAYSIZE(bytes); i++) {
presence_all <<= 8; presence_all <<= 8;
presence_all |= bytes[i]; presence_all |= bytes[i];
} }
/* Populate bitmap & remap */ /* Populate bitmap & remap */
for(i = 0; presence_all; i++) for(i = 0; presence_all; i++)
{ {
@@ -260,7 +217,6 @@ int onlp_sfpi_port_map(int port, int* rport)
int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value) int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
{ {
int value_t; int value_t;
#ifdef BMC
uint8_t reg_t = 0x00; uint8_t reg_t = 0x00;
int rdata_bit = 0x00; int rdata_bit = 0x00;
int bit_t = 0x00; int bit_t = 0x00;
@@ -271,12 +227,11 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
* return 0 = The module is in Reset * return 0 = The module is in Reset
* return 1 = The module is not in Reset */ * return 1 = The module is not in Reset */
if (port > 48 && port < 55) { /* QSFP Port 49-54 */ if (port > 46 && port < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_RESET; reg_t = QSFP_RESET;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
port = port - 1; bit_t = 1 << (port % 47);
bit_t = 1 << (port % 8);
rdata_bit = rdata_bit & bit_t; rdata_bit = rdata_bit & bit_t;
rdata_bit = rdata_bit / bit_t; rdata_bit = rdata_bit / bit_t;
} else { /* In agc7646slv1b only QSFP support control RESET MODE */ } else { /* In agc7646slv1b only QSFP support control RESET MODE */
@@ -295,7 +250,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
* return 0 = The module is Normal Operation * return 0 = The module is Normal Operation
* return 1 = The module is Error */ * return 1 = The module is Error */
if (port > 0 && port < 49) { /* SFP */ if (port > 0 && port < 47) { /* SFP */
if (port > 0 && port < 9) { /* SFP Port 1-8 */ if (port > 0 && port < 9) { /* SFP Port 1-8 */
reg_t = SFP_RXLOS_1; reg_t = SFP_RXLOS_1;
} else if (port > 8 && port < 17) { /* SFP Port 9-16 */ } else if (port > 8 && port < 17) { /* SFP Port 9-16 */
@@ -306,7 +261,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
reg_t = SFP_RXLOS_4; reg_t = SFP_RXLOS_4;
} else if (port > 32 && port < 41) { /* SFP Port 33-40 */ } else if (port > 32 && port < 41) { /* SFP Port 33-40 */
reg_t = SFP_RXLOS_5; reg_t = SFP_RXLOS_5;
} else if (port > 40 && port < 49) { /* SFP Port 41-48 */ } else if (port > 40 && port < 47) { /* SFP Port 41-46 */
reg_t = SFP_RXLOS_6; reg_t = SFP_RXLOS_6;
} }
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK)
@@ -328,7 +283,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
* return 0 = The module is Enable Transmitter on * return 0 = The module is Enable Transmitter on
* return 1 = The module is Transmitter Disabled */ * return 1 = The module is Transmitter Disabled */
if (port > 0 && port < 49) { /* SFP */ if (port > 0 && port < 47) { /* SFP */
if (port > 0 && port < 9) { /* SFP Port 1-8 */ if (port > 0 && port < 9) { /* SFP Port 1-8 */
reg_t = SFP_TXDIS_1; reg_t = SFP_TXDIS_1;
} else if (port > 8 && port < 17) { /* SFP Port 9-16 */ } else if (port > 8 && port < 17) { /* SFP Port 9-16 */
@@ -339,7 +294,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
reg_t = SFP_TXDIS_4; reg_t = SFP_TXDIS_4;
} else if (port > 32 && port < 41) { /* SFP Port 33-40 */ } else if (port > 32 && port < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXDIS_5; reg_t = SFP_TXDIS_5;
} else if (port > 40 && port < 49) { /* SFP Port 41-48 */ } else if (port > 40 && port < 47) { /* SFP Port 41-46 */
reg_t = SFP_TXDIS_6; reg_t = SFP_TXDIS_6;
} }
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK)
@@ -361,7 +316,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
* return 0 = The module is Normal * return 0 = The module is Normal
* return 1 = The module is Fault */ * return 1 = The module is Fault */
if (port > 0 && port < 49) { /* SFP */ if (port > 0 && port < 47) { /* SFP */
if (port > 0 && port < 9) { /* SFP Port 1-8 */ if (port > 0 && port < 9) { /* SFP Port 1-8 */
reg_t = SFP_TXFAULT_1; reg_t = SFP_TXFAULT_1;
} else if (port > 8 && port < 17) { /* SFP Port 9-16 */ } else if (port > 8 && port < 17) { /* SFP Port 9-16 */
@@ -372,7 +327,7 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
reg_t = SFP_TXFAULT_4; reg_t = SFP_TXFAULT_4;
} else if (port > 32 && port < 41) { /* SFP Port 33-40 */ } else if (port > 32 && port < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXFAULT_5; reg_t = SFP_TXFAULT_5;
} else if (port > 40 && port < 49) { /* SFP Port 41-48 */ } else if (port > 40 && port < 47) { /* SFP Port 41-46 */
reg_t = SFP_TXFAULT_6; reg_t = SFP_TXFAULT_6;
} }
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK)
@@ -394,12 +349,11 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
* return 0 = The module is not in LP mode * return 0 = The module is not in LP mode
* return 1 = The module is in LP mode */ * return 1 = The module is in LP mode */
if (port > 48 && port < 55) { /* QSFP Port 49-54 */ if (port > 46 && port < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_LPMODE; reg_t = QSFP_LPMODE;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &rdata_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
port = port - 1; bit_t = 1 << (port % 47);
bit_t = 1 << (port % 8);
rdata_bit = rdata_bit & bit_t; rdata_bit = rdata_bit & bit_t;
rdata_bit = rdata_bit / bit_t; rdata_bit = rdata_bit / bit_t;
} else { /* In agc7646slv1b only QSFP support control LP MODE */ } else { /* In agc7646slv1b only QSFP support control LP MODE */
@@ -413,95 +367,31 @@ int onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value)
value_t = ONLP_STATUS_E_UNSUPPORTED; value_t = ONLP_STATUS_E_UNSUPPORTED;
break; break;
} }
#elif defined I2C
char port_data[3] = {'\0'};
if(port > 0 && port < 55)
{
/* Select SFP(1-48), QSFP(49-54) port */
sprintf(port_data, "%d", port );
if(dni_i2c_lock_write_attribute(NULL, port_data, SFP_SELECT_PORT_PATH) < 0){
AIM_LOG_INFO("Unable to select port(%d)\r\n", port);
return ONLP_STATUS_E_INTERNAL;
}
}
switch (control) {
case ONLP_SFP_CONTROL_RESET_STATE:
/* From sfp_reset value,
* return 0 = The module is in Reset
* return 1 = The module is NOT in Reset */
*value = dni_i2c_lock_read_attribute(NULL, QSFP_RESET_PATH);
if (*value == 0)
{
*value = 1;
}
else if (*value == 1)
{
*value = 0;
}
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_RX_LOS:
/* From sfp_rx_los value,
* return 0 = The module is Normal Operation
* return 1 = The module is Error */
*value = dni_i2c_lock_read_attribute(NULL, SFP_RX_LOS_PATH);
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_TX_DISABLE:
/* From sfp_tx_disable value,
* return 0 = The module is Enable Transmitter on
* return 1 = The module is Transmitter Disabled */
*value = dni_i2c_lock_read_attribute(NULL, SFP_TX_DISABLE_PATH);
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_TX_FAULT:
/* From sfp_tx_fault value,
* return 0 = The module is Normal
* return 1 = The module is Fault */
*value = dni_i2c_lock_read_attribute(NULL, SFP_TX_FAULT_PATH);
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_LP_MODE:
/* From sfp_lp_mode value,
* return 0 = The module is NOT in LP mode
* return 1 = The module is in LP mode */
*value = dni_i2c_lock_read_attribute(NULL, QSFP_LP_MODE_PATH);
value_t = ONLP_STATUS_OK;
break;
default:
value_t = ONLP_STATUS_E_UNSUPPORTED;
break;
}
#endif
return value_t; return value_t;
} }
int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value) int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
{ {
int value_t; int value_t;
#ifdef BMC
uint8_t reg_t = 0x00; uint8_t reg_t = 0x00;
int data_bit = 0x00; int data_bit = 0x00;
int bit_t = 0x00; int bit_t = 0x00;
switch (control) { switch (control) {
case ONLP_SFP_CONTROL_RESET_STATE: case ONLP_SFP_CONTROL_RESET_STATE:
if (port > 48 && port < 55) { /* QSFP Port 49-54 */ if (port > 46 && port < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_RESET; reg_t = QSFP_RESET;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &data_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &data_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
/* Indicate the module is in reset mode or not /* Indicate the module is in reset mode or not
* 0 = Reset * 0 = Reset
* 1 = Normal */ * 1 = Normal */
port = port - 1;
if (value == 0) { if (value == 0) {
bit_t = ~(1 << (port % 8)); bit_t = ~(1 << (port % 47));
data_bit = data_bit & bit_t; data_bit = data_bit & bit_t;
} }
else if (value == 1) { else if (value == 1) {
bit_t = (1 << (port % 8)); bit_t = (1 << (port % 47));
data_bit = data_bit | bit_t; data_bit = data_bit | bit_t;
} }
if (dni_bmc_data_set(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, (uint8_t)data_bit) != ONLP_STATUS_OK) if (dni_bmc_data_set(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, (uint8_t)data_bit) != ONLP_STATUS_OK)
@@ -516,7 +406,7 @@ int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
value_t = ONLP_STATUS_E_UNSUPPORTED; value_t = ONLP_STATUS_E_UNSUPPORTED;
break; break;
case ONLP_SFP_CONTROL_TX_DISABLE: case ONLP_SFP_CONTROL_TX_DISABLE:
if (port > 0 && port < 49) { /* SFP */ if (port > 0 && port < 47) { /* SFP */
if (port > 0 && port < 9) { /* SFP Port 1-8 */ if (port > 0 && port < 9) { /* SFP Port 1-8 */
reg_t = SFP_TXDIS_1; reg_t = SFP_TXDIS_1;
} else if (port > 8 && port < 17) { /* SFP Port 9-16 */ } else if (port > 8 && port < 17) { /* SFP Port 9-16 */
@@ -527,7 +417,7 @@ int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
reg_t = SFP_TXDIS_4; reg_t = SFP_TXDIS_4;
} else if (port > 32 && port < 41) { /* SFP Port 33-40 */ } else if (port > 32 && port < 41) { /* SFP Port 33-40 */
reg_t = SFP_TXDIS_5; reg_t = SFP_TXDIS_5;
} else if (port > 40 && port < 49) { /* SFP Port 41-48 */ } else if (port > 40 && port < 47) { /* SFP Port 41-46 */
reg_t = SFP_TXDIS_6; reg_t = SFP_TXDIS_6;
} }
@@ -557,20 +447,19 @@ int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
value_t = ONLP_STATUS_E_UNSUPPORTED; value_t = ONLP_STATUS_E_UNSUPPORTED;
break; break;
case ONLP_SFP_CONTROL_LP_MODE: case ONLP_SFP_CONTROL_LP_MODE:
if (port > 48 && port < 55) { /* QSFP Port 49-54 */ if (port > 46 && port < 53) { /* QSFP Port 47-52 */
reg_t = QSFP_LPMODE; reg_t = QSFP_LPMODE;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &data_bit) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, &data_bit) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
/* Indicate the module is in LP mode or not /* Indicate the module is in LP mode or not
* 0 = Disable * 0 = Disable
* 1 = Enable */ * 1 = Enable */
port = port - 1;
if (value == 0) { if (value == 0) {
bit_t = ~(1 << (port % 8)); bit_t = ~(1 << (port % 47));
data_bit = data_bit & bit_t; data_bit = data_bit & bit_t;
} }
else if (value == 1) { else if (value == 1) {
bit_t = (1 << (port % 8)); bit_t = (1 << (port % 47));
data_bit = data_bit | bit_t; data_bit = data_bit | bit_t;
} }
if (dni_bmc_data_set(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, (uint8_t)data_bit) != ONLP_STATUS_OK) if (dni_bmc_data_set(BMC_SWPLD_BUS, SWPLD_1_ADDR, reg_t, (uint8_t)data_bit) != ONLP_STATUS_OK)
@@ -585,55 +474,6 @@ int onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value)
value_t = ONLP_STATUS_E_UNSUPPORTED; value_t = ONLP_STATUS_E_UNSUPPORTED;
break; break;
} }
#elif defined I2C
char port_data[3] = {'\0'};
if(port > 0 && port < 55)
{
/* Select SFP(1-48), QSFP(49-54) port */
sprintf(port_data, "%d", port );
if(dni_i2c_lock_write_attribute(NULL, port_data, SFP_SELECT_PORT_PATH) < 0){
AIM_LOG_INFO("Unable to select port(%d)\r\n", port);
return ONLP_STATUS_E_INTERNAL;
}
}
switch (control) {
case ONLP_SFP_CONTROL_RESET_STATE:
sprintf(port_data, "%d", value);
if(dni_i2c_lock_write_attribute(NULL, port_data, QSFP_RESET_PATH) < 0){
AIM_LOG_INFO("Unable to control reset state from port(%d)\r\n", port);
value_t = ONLP_STATUS_E_INTERNAL;
}
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_RX_LOS:
value_t = ONLP_STATUS_E_UNSUPPORTED;
break;
case ONLP_SFP_CONTROL_TX_DISABLE:
sprintf(port_data, "%d", value);
if(dni_i2c_lock_write_attribute(NULL, port_data, SFP_TX_DISABLE_PATH) < 0){
AIM_LOG_INFO("Unable to control tx disable from port(%d)\r\n", port);
value_t = ONLP_STATUS_E_INTERNAL;
}
value_t = ONLP_STATUS_OK;
break;
case ONLP_SFP_CONTROL_TX_FAULT:
value_t = ONLP_STATUS_E_UNSUPPORTED;
break;
case ONLP_SFP_CONTROL_LP_MODE:
sprintf(port_data, "%d", value);
if(dni_i2c_lock_write_attribute(NULL, port_data, QSFP_LP_MODE_PATH) < 0){
AIM_LOG_INFO("Unable to control LP mode from port(%d)\r\n", port);
value_t = ONLP_STATUS_E_INTERNAL;
}
value_t = ONLP_STATUS_OK;
break;
default:
value_t = ONLP_STATUS_E_UNSUPPORTED;
break;
}
#endif
return value_t; return value_t;
} }
@@ -672,46 +512,33 @@ int onlp_sfpi_dev_writew(int port, uint8_t devaddr, uint8_t addr, uint16_t value
int onlp_sfpi_control_supported(int port, onlp_sfp_control_t control, int* rv) int onlp_sfpi_control_supported(int port, onlp_sfp_control_t control, int* rv)
{ {
#ifdef I2C
char port_data[3] = {'\0'};
if(port > 0 && port < 55)
{
/* Select SFP(1-48), QSFP(49-54) port */
sprintf(port_data, "%d", port);
if(dni_i2c_lock_write_attribute(NULL, port_data, SFP_SELECT_PORT_PATH) < 0){
AIM_LOG_INFO("Unable to select port(%d)\r\n", port);
return ONLP_STATUS_E_INTERNAL;
}
}
#endif
switch (control) { switch (control) {
case ONLP_SFP_CONTROL_RESET_STATE: case ONLP_SFP_CONTROL_RESET_STATE:
if(port > 48 && port < 55) /* QSFP */ if(port > 46 && port < 53) /* QSFP */
*rv = 1; *rv = 1;
else else
*rv = 0; *rv = 0;
break; break;
case ONLP_SFP_CONTROL_RX_LOS: case ONLP_SFP_CONTROL_RX_LOS:
if(port > 0 && port < 49) /* SFP */ if(port > 0 && port < 47) /* SFP */
*rv = 1; *rv = 1;
else else
*rv = 0; *rv = 0;
break; break;
case ONLP_SFP_CONTROL_TX_DISABLE: case ONLP_SFP_CONTROL_TX_DISABLE:
if(port > 0 && port < 49) /* SFP */ if(port > 0 && port < 47) /* SFP */
*rv = 1; *rv = 1;
else else
*rv = 0; *rv = 0;
break; break;
case ONLP_SFP_CONTROL_TX_FAULT: case ONLP_SFP_CONTROL_TX_FAULT:
if(port > 0 && port < 49) /* SFP */ if(port > 0 && port < 47) /* SFP */
*rv = 1; *rv = 1;
else else
*rv = 0; *rv = 0;
break; break;
case ONLP_SFP_CONTROL_LP_MODE: case ONLP_SFP_CONTROL_LP_MODE:
if(port > 48 && port < 55) /* QSFP */ if(port > 46 && port < 53) /* QSFP */
*rv = 1; *rv = 1;
else else
*rv = 0; *rv = 0;
@@ -731,7 +558,6 @@ int onlp_sfpi_rx_los_bitmap_get(onlp_sfp_bitmap_t* dst)
{ {
int count = 0; int count = 0;
uint8_t bytes[6] = {0}; uint8_t bytes[6] = {0};
#ifdef BMC
uint8_t reg_t = 0x00; uint8_t reg_t = 0x00;
int rxlos_data = 0x00; int rxlos_data = 0x00;
uint8_t r_array[6] = {0}; uint8_t r_array[6] = {0};
@@ -740,7 +566,7 @@ int onlp_sfpi_rx_los_bitmap_get(onlp_sfp_bitmap_t* dst)
* if only port 0 is normal operation, return FF FF FF FF FF FE * if only port 0 is normal operation, return FF FF FF FF FF FE
* if only port 0 and 1 normal operation, return FF FF FF FF FF FC */ * if only port 0 and 1 normal operation, return FF FF FF FF FF FC */
for (count = 0; count < 6; count++) { /* SFP Port 1-48 */ for (count = 0; count < 6; count++) { /* SFP Port 1-46 */
reg_t = SFP_RXLOS_1 + count; reg_t = SFP_RXLOS_1 + count;
if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rxlos_data) != ONLP_STATUS_OK) if (dni_bmc_data_get(BMC_SWPLD_BUS, SWPLD_2_ADDR, reg_t, &rxlos_data) != ONLP_STATUS_OK)
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
@@ -751,36 +577,11 @@ int onlp_sfpi_rx_los_bitmap_get(onlp_sfp_bitmap_t* dst)
for (count = 0; count < 6; count++) { for (count = 0; count < 6; count++) {
bytes[count] = r_array[5 - count]; bytes[count] = r_array[5 - count];
} }
#elif defined I2C
char rxlos_all_data[18] = {'\0'};
char *r_byte;
char *r_array[6];
/* Read rx_los bitmap from SWPLD2 SFP+ LOSS Register bytes[0] &= 0x3F;
* if only port 0 is normal operation, return FF FF FF FF FF FE
* if only port 0 and 1 normal operation, return FF FF FF FF FF FC */
if(dni_i2c_read_attribute_string(SFP_RX_LOS_ALL_PATH, rxlos_all_data,
sizeof(rxlos_all_data), 0) < 0) {
return -1;
}
/* String split */
r_byte = strtok(rxlos_all_data, " ");
while (r_byte != NULL) {
r_array[count++] = r_byte;
r_byte = strtok(NULL, " ");
}
/* Convert a string to unsigned 8 bit integer
* and saved into bytes[] */
for (count = 0; count < 6; count++) {
bytes[count] = strtol(r_array[count], NULL, 16);
}
#endif
/* Convert to 64 bit integer in port order */ /* Convert to 64 bit integer in port order */
int i = 0; int i = 6;
uint64_t rxlos_all = 0; uint64_t rxlos_all = 0;
for(i = 0; i < AIM_ARRAYSIZE(bytes); i++) { for(i = 0; i < AIM_ARRAYSIZE(bytes); i++) {
@@ -788,14 +589,14 @@ int onlp_sfpi_rx_los_bitmap_get(onlp_sfp_bitmap_t* dst)
rxlos_all |= bytes[i]; rxlos_all |= bytes[i];
} }
for(i = 0; i < 48; i++) for(i = 0; i < 46; i++)
{ {
AIM_BITMAP_MOD(dst, i+1, (rxlos_all & 1)); AIM_BITMAP_MOD(dst, i+1, (rxlos_all & 1));
rxlos_all >>= 1; rxlos_all >>= 1;
} }
/* Mask out non-existant QSFP ports */ /* Mask out non-existant QSFP ports */
for(i = 48; i < 54; i++) for(i = 46; i < 52; i++)
AIM_BITMAP_MOD(dst, i+1, 0); AIM_BITMAP_MOD(dst, i+1, 0);
return ONLP_STATUS_OK; return ONLP_STATUS_OK;

204
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/sysi.c
View File

@@ -38,46 +38,6 @@
#include <onlp/platformi/fani.h> #include <onlp/platformi/fani.h>
#include <onlp/platformi/psui.h> #include <onlp/platformi/psui.h>
#ifdef I2C
int decide_percentage(int *percentage, int temper)
{
int level;
if(temper <= 50)
{
*percentage = 50;
level = 1;
}
else if(temper > 50 && temper <= 55)
{
*percentage = 58;
level = 2;
}
else if(temper > 55 && temper <= 60)
{
*percentage = 65;
level = 3;
}
else if(temper > 60 && temper <= 65)
{
*percentage = 80;
level = 4;
}
else if(temper > 65)
{
*percentage = 100;
level = 5;
}
else
{
*percentage = 100;
level = 6;
}
return level;
}
#endif
const char* onlp_sysi_platform_get(void) const char* onlp_sysi_platform_get(void)
{ {
return "x86-64-delta-agc7646slv1b-r0"; return "x86-64-delta-agc7646slv1b-r0";
@@ -110,7 +70,7 @@ int onlp_sysi_onie_data_get(uint8_t** data, int* size)
int onlp_sysi_platform_info_get(onlp_platform_info_t* pi) int onlp_sysi_platform_info_get(onlp_platform_info_t* pi)
{ {
int cpld_version = 6; int cpld_version = 0x0;
cpld_version = dni_i2c_lock_read_attribute(NULL, CPU_CPLD_VERSION); cpld_version = dni_i2c_lock_read_attribute(NULL, CPU_CPLD_VERSION);
pi->cpld_versions = aim_fstrdup("%d", cpld_version); pi->cpld_versions = aim_fstrdup("%d", cpld_version);
@@ -159,173 +119,11 @@ int onlp_sysi_oids_get(onlp_oid_t* table, int max)
int onlp_sysi_platform_manage_fans(void) int onlp_sysi_platform_manage_fans(void)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef I2C
int i, new_percentage, highest_temp = 0;
onlp_thermal_info_t thermal;
/* Get all thermal current temperature and decide fan percentage */
for(i = 1; i <= NUM_OF_THERMAL; ++i)
{
if(onlp_thermali_info_get(ONLP_THERMAL_ID_CREATE(i), &thermal) != ONLP_STATUS_OK)
{
AIM_LOG_ERROR("Unable to read thermal status");
return ONLP_STATUS_E_INTERNAL;
}
thermal.mcelsius /= 1000;
if(thermal.mcelsius > highest_temp)
{
highest_temp = thermal.mcelsius;
}
decide_percentage(&new_percentage, highest_temp);
}
/* Set fantray RPM and PSU fan percentage */
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_1_ON_FAN_BOARD), MAX_FRONT_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_2_ON_FAN_BOARD), MAX_FRONT_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_3_ON_FAN_BOARD), MAX_FRONT_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_4_ON_FAN_BOARD), MAX_FRONT_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_5_ON_FAN_BOARD), MAX_REAR_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_6_ON_FAN_BOARD), MAX_REAR_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_7_ON_FAN_BOARD), MAX_REAR_FAN_SPEED * new_percentage / 100);
onlp_fani_rpm_set(ONLP_FAN_ID_CREATE(FAN_8_ON_FAN_BOARD), MAX_REAR_FAN_SPEED * new_percentage / 100);
onlp_fani_percentage_set(ONLP_FAN_ID_CREATE(FAN_1_ON_PSU1), new_percentage);
onlp_fani_percentage_set(ONLP_FAN_ID_CREATE(FAN_1_ON_PSU2), new_percentage);
#endif
return rv; return rv;
} }
int onlp_sysi_platform_manage_leds(void) int onlp_sysi_platform_manage_leds(void)
{ {
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
#ifdef I2C
int rpm = 0, rpm1 = 0, count = 0;
int fantray_count;
char fantray_count_str[2] = {'\0'};
uint8_t psu1_state, psu2_state;
int psu_pwr_status = 0;
int psu_pwr_int = 0;
int fantray_present = -1;
char fullpath[50] = {'\0'};
/* Fan tray 1 */
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN1_PRESENT_PATH);
rpm = dni_i2c_lock_read_attribute(NULL, FAN1_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN1_REAR);
if(fantray_present == 0 && rpm != FAN_ZERO_RPM && rpm != 0 && rpm1 != FAN_ZERO_RPM && rpm1 != 0 )
{
/* Green */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_1),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Red */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_1),ONLP_LED_MODE_RED) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
/* Fan tray 2 */
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN2_PRESENT_PATH);
rpm = dni_i2c_lock_read_attribute(NULL, FAN2_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN2_REAR);
if(fantray_present == 0 && rpm != FAN_ZERO_RPM && rpm != 0 && rpm1 != FAN_ZERO_RPM && rpm1 != 0 )
{
/* Green */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_2),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Red */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_2),ONLP_LED_MODE_RED) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
/* Fan tray 3 */
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN3_PRESENT_PATH);
rpm = dni_i2c_lock_read_attribute(NULL, FAN3_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN3_REAR);
if(fantray_present == 0 && rpm != FAN_ZERO_RPM && rpm != 0 && rpm1 != FAN_ZERO_RPM && rpm1 != 0 )
{
/* Green */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_3),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Red */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_3),ONLP_LED_MODE_RED) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
/* Fan tray 4 */
fantray_present = dni_i2c_lock_read_attribute(NULL, FAN4_PRESENT_PATH);
rpm = dni_i2c_lock_read_attribute(NULL, FAN4_FRONT);
rpm1 = dni_i2c_lock_read_attribute(NULL, FAN4_REAR);
if(fantray_present == 0 && rpm != FAN_ZERO_RPM && rpm != 0 && rpm1 != FAN_ZERO_RPM && rpm1 != 0 )
{
/* Green */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_4),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Red */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_REAR_FAN_TRAY_4),ONLP_LED_MODE_RED) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
/* FRONT FAN & SYS LED */
for(fantray_count = 9; fantray_count > 5 ; fantray_count--)
{
sprintf(fantray_count_str, "%d", fantray_count);
sprintf(fullpath, "/sys/class/gpio/gpio49%s/value", fantray_count_str);
fantray_present = dni_i2c_lock_read_attribute(NULL, fullpath);
if(fantray_present == 0)
count++;
}
if(count == ALL_FAN_TRAY_EXIST && dni_fan_speed_good() == FAN_SPEED_NORMALLY)
{
/* Green */
if((onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_FAN),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK) ||
(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_SYS),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK))
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Solid Amber FAN or more failed*/
if((onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_FAN),ONLP_LED_MODE_YELLOW) != ONLP_STATUS_OK) ||
(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_SYS),ONLP_LED_MODE_YELLOW) != ONLP_STATUS_OK))
rv = ONLP_STATUS_E_INTERNAL;
}
/* Set front light of PWR */
psu1_state = dni_i2c_lock_read_attribute(NULL, PSU1_PRESENT_PATH);
psu2_state = dni_i2c_lock_read_attribute(NULL, PSU2_PRESENT_PATH);
psu_pwr_status = dni_lock_cpld_read_attribute(SWPLD1_PATH,POWER_STATUS_REGISTER);
psu_pwr_int = dni_lock_cpld_read_attribute(SWPLD1_PATH,POWER_INT_REGISTER);
if(psu1_state == 0 && psu2_state == 0 && (psu_pwr_status & 0xc0) == 0xc0 && (psu_pwr_int & 0x30) == 0x30)
{
/* Green */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_PWR),ONLP_LED_MODE_GREEN) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
else
{
/* Amber */
if(onlp_ledi_mode_set(ONLP_LED_ID_CREATE(LED_FRONT_PWR),ONLP_LED_MODE_YELLOW) != ONLP_STATUS_OK)
rv = ONLP_STATUS_E_INTERNAL;
}
#endif
return rv; return rv;
} }

124
packages/platforms/delta/x86-64/x86-64-delta-agc7646slv1b/onlp/builds/src/module/src/thermali.c
View File

@@ -42,68 +42,39 @@
ERROR_DEFAULT, \ ERROR_DEFAULT, \
SHUTDOWN_DEFAULT, \ SHUTDOWN_DEFAULT, \
} }
#ifdef I2C
static char* path[] = /* must map with onlp_thermal_id */
{
"reserved",
"26-004f/hwmon/hwmon6/temp1_input",
"8-004b/hwmon/hwmon1/temp1_input",
"8-004c/hwmon/hwmon2/temp1_input",
"8-004c/hwmon/hwmon2/temp2_input",
"8-004d/hwmon/hwmon3/temp1_input",
"8-004d/hwmon/hwmon3/temp2_input",
"8-004d/hwmon/hwmon3/temp3_input",
"8-004e/hwmon/hwmon4/temp1_input",
"8-004f/hwmon/hwmon5/temp1_input",
"31-0058/psu_temp1_input",
"32-0058/psu_temp1_input"
};
#endif
/* Static values */ /* Static values */
static onlp_thermal_info_t linfo[] = { static onlp_thermal_info_t linfo[] = {
{ }, /* Not used */ { }, /* Not used */
{ { ONLP_THERMAL_ID_CREATE(THERMAL_1_ON_FAN_BOARD), "Board sensor on Fan_BD", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_1_ON_CPU_BOARD), "Board sensor near CPU (U36)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_2_ON_CPU_BOARD), "Board sensor near CPU", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_2_ON_FAN_BOARD), "Board sensor on Fan_BD (UT15)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_3_ON_MAIN_BOARD_TEMP_1), "Board sensor near MAC temp-1", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_3_ON_MAIN_BOARD_TEMP_1), "Board sensor near MAC (U24)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_4_ON_MAIN_BOARD_TEMP_2), "Board sensor near MAC temp-2", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_4_ON_MAIN_BOARD_TEMP_2), "Board sensor near MAC (U25)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_5_ON_MAIN_BOARD_TEMP_1), "Board sensor near SyncE temp-1", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_5_ON_MAIN_BOARD_TEMP_3_1), "Board sensor near MAC (U3 REMOTE)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_6_ON_MAIN_BOARD_TEMP_2), "Board sensor near SyncE temp-2", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_6_ON_MAIN_BOARD_TEMP_3_2), "Board sensor near MAC (U3 LOCAL)", 0},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_7_ON_MAIN_BOARD_TEMP_3), "Board sensor near SyncE temp-3", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_7_ON_PSU1), "PSU-1 internal sensor", ONLP_PSU_ID_CREATE(PSU1_ID)},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
}, },
{ { ONLP_THERMAL_ID_CREATE(THERMAL_8_ON_MAIN_BOARD), "Board sensor near MAC", 0}, { { ONLP_THERMAL_ID_CREATE(THERMAL_8_ON_PSU2), "PSU-2 internal Sensor", ONLP_PSU_ID_CREATE(PSU2_ID)},
ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(THERMAL_9_ON_MAIN_BOARD), "Board sensor near MAC", 0},
ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(THERMAL_10_ON_PSU1), "PSU-1 internal sensor", ONLP_PSU_ID_CREATE(PSU1_ID)},
ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
},
{ { ONLP_THERMAL_ID_CREATE(THERMAL_11_ON_PSU2), "PSU-2 internal Sensor", ONLP_PSU_ID_CREATE(PSU2_ID)},
ONLP_THERMAL_STATUS_PRESENT, ONLP_THERMAL_STATUS_PRESENT,
ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS ONLP_THERMAL_CAPS_ALL, 0, ONLP_THERMAL_THRESHOLD_INIT_DEFAULTS
} }
@@ -134,45 +105,43 @@ onlp_thermali_info_get(onlp_oid_t id, onlp_thermal_info_t* info)
{ {
uint8_t local_id = 0; uint8_t local_id = 0;
int rv = ONLP_STATUS_OK; int rv = ONLP_STATUS_OK;
VALIDATE(id); VALIDATE(id);
local_id = ONLP_OID_ID_GET(id); local_id = ONLP_OID_ID_GET(id);
*info = linfo[local_id]; *info = linfo[local_id];
#ifdef BMC
UINT4 multiplier = 1000; UINT4 multiplier = 1000;
UINT4 u4Data = 0; UINT4 u4Data = 0;
char device_buf[20] = {0}; char device_buf[20] = {0};
switch(local_id) { switch(local_id) {
case THERMAL_1_ON_FAN_BOARD: case THERMAL_1_ON_CPU_BOARD:
sprintf(device_buf, "Fan_Temp"); sprintf(device_buf, "TMP75_CPU-4d");
rv = dni_bmc_sensor_read(device_buf, &u4Data, multiplier, THERMAL_SENSOR); break;
case THERMAL_2_ON_FAN_BOARD:
sprintf(device_buf, "TMP75_FAN-4f");
break; break;
case THERMAL_2_ON_CPU_BOARD:
case THERMAL_3_ON_MAIN_BOARD_TEMP_1: case THERMAL_3_ON_MAIN_BOARD_TEMP_1:
sprintf(device_buf, "TMP75-4e");
break;
case THERMAL_4_ON_MAIN_BOARD_TEMP_2: case THERMAL_4_ON_MAIN_BOARD_TEMP_2:
case THERMAL_5_ON_MAIN_BOARD_TEMP_1: sprintf(device_buf, "TMP75-4b");
case THERMAL_6_ON_MAIN_BOARD_TEMP_2:
case THERMAL_7_ON_MAIN_BOARD_TEMP_3:
case THERMAL_8_ON_MAIN_BOARD:
case THERMAL_9_ON_MAIN_BOARD:
local_id--;
sprintf(device_buf, "Temp_Sensor_%d", local_id);
rv = dni_bmc_sensor_read(device_buf, &u4Data, multiplier, THERMAL_SENSOR);
break; break;
case THERMAL_10_ON_PSU1: case THERMAL_5_ON_MAIN_BOARD_TEMP_3_1:
sprintf(device_buf, "TMP431_REMOTE-4c");
break;
case THERMAL_6_ON_MAIN_BOARD_TEMP_3_2:
sprintf(device_buf, "TMP431_LOCAL-4c");
break;
case THERMAL_7_ON_PSU1:
sprintf(device_buf, "PSU1_Temp_1"); sprintf(device_buf, "PSU1_Temp_1");
rv = dni_bmc_sensor_read(device_buf, &u4Data, multiplier, THERMAL_SENSOR);
break; break;
case THERMAL_11_ON_PSU2: case THERMAL_8_ON_PSU2:
sprintf(device_buf, "PSU2_Temp_1"); sprintf(device_buf, "PSU2_Temp_1");
rv = dni_bmc_sensor_read(device_buf, &u4Data, multiplier, THERMAL_SENSOR);
break; break;
default: default:
AIM_LOG_ERROR("Invalid Thermal ID!!\n"); AIM_LOG_ERROR("Invalid Thermal ID!!\n");
return ONLP_STATUS_E_PARAM; return ONLP_STATUS_E_PARAM;
} }
rv = dni_bmc_sensor_read(device_buf, &u4Data, multiplier, THERMAL_SENSOR);
if (u4Data == 0 || rv == ONLP_STATUS_E_GENERIC){ if (u4Data == 0 || rv == ONLP_STATUS_E_GENERIC){
return ONLP_STATUS_E_INTERNAL; return ONLP_STATUS_E_INTERNAL;
@@ -181,48 +150,5 @@ onlp_thermali_info_get(onlp_oid_t id, onlp_thermal_info_t* info)
info->mcelsius = u4Data; info->mcelsius = u4Data;
return 0; return 0;
} }
#elif defined I2C
int temp_base = 1;
char fullpath[50] = {0};
int r_data = 0;
switch (local_id) {
case THERMAL_1_ON_FAN_BOARD:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_2_ON_CPU_BOARD:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_3_ON_MAIN_BOARD_TEMP_1:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_4_ON_MAIN_BOARD_TEMP_2:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_5_ON_MAIN_BOARD_TEMP_1:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_6_ON_MAIN_BOARD_TEMP_2:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_7_ON_MAIN_BOARD_TEMP_3:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_8_ON_MAIN_BOARD:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_9_ON_MAIN_BOARD:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_10_ON_PSU1:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
case THERMAL_11_ON_PSU2:
sprintf(fullpath,"%s%s", PREFIX_PATH, path[local_id]);
break;
}
r_data = dni_i2c_lock_read_attribute(NULL, fullpath);
info->mcelsius = r_data / temp_base;
#endif
return rv; return rv;
} }