diff --git a/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/.gitignore b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/.gitignore
new file mode 100644
index 00000000..c9f61e12
--- /dev/null
+++ b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/.gitignore
@@ -0,0 +1,2 @@
+linux-3.2.71*
+kernel-3.2*
diff --git a/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/Makefile b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/Makefile
new file mode 100644
index 00000000..06577e25
--- /dev/null
+++ b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/Makefile
@@ -0,0 +1,41 @@
+############################################################
+#
+#
+# Copyright 2015 Big Switch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+#
+############################################################
+
+THIS_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+include $(ONL)/make/config.mk
+
+ifndef K_TARGET_DIR
+K_TARGET_DIR := $(THIS_DIR)
+endif
+
+include ../../kconfig.mk
+K_CONFIG := arm-iproc-all.config
+K_BUILD_TARGET := Image
+K_COPY_SRC := arch/arm/boot/Image
+K_COPY_GZIP := 1
+ifndef K_COPY_DST
+K_COPY_DST := kernel-3.2-deb7-arm-iproc-all.bin.gz
+endif
+
+export ARCH=arm
+DTS_LIST := accton_as4610_54
+
+include $(ONL)/make/kbuild.mk
diff --git a/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/arm-iproc-all.config b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/arm-iproc-all.config
new file mode 100644
index 00000000..0cd2c429
--- /dev/null
+++ b/packages/base/any/kernels/3.2.71-1+deb7/configs/arm-iproc-all/arm-iproc-all.config
@@ -0,0 +1,2418 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.2.71 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
+CONFIG_LOCALVERSION="-OpenNetworkLinux"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="onl"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_RD_XZ=y
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_ZYNQ is not set
+CONFIG_ARCH_IPROC=y
+CONFIG_BCM_ZRELADDR=0x61008000
+CONFIG_GPIO_PCA953X=y
+
+#
+# Broadcom IPROC architecture based implementations
+#
+# CONFIG_ARCH_NORTHSTAR is not set
+CONFIG_MACH_IPROC=y
+# CONFIG_IPROC_64K_PAGE is not set
+CONFIG_GP_TIMER_COMPARATOR_LOAD_DELAY=y
+CONFIG_IPROC_DCACHE_INVALIDATION=y
+# CONFIG_IPROC_TIMER_UNIT_TESTS is not set
+# CONFIG_IPROC_SW_RESET_RECORD is not set
+# CONFIG_BRCM_PROP_MODULES is not set
+# CONFIG_BCM_STM is not set
+CONFIG_BCM_PARAMS_PHYS=0x61000000
+CONFIG_BCM_RAM_BASE=0x60000000
+CONFIG_BCM_RAM_START_RESERVED_SIZE=0x200000
+
+#
+# iProc SoC based Machine types
+#
+# CONFIG_MACH_CYGNUS is not set
+# CONFIG_MACH_NS is not set
+# CONFIG_MACH_HX4 is not set
+# CONFIG_MACH_HR2 is not set
+# CONFIG_MACH_NSP is not set
+# CONFIG_MACH_KT2 is not set
+# CONFIG_MACH_GH is not set
+# CONFIG_MACH_DNI_3448P is not set
+CONFIG_MACH_ACCTON_AS4610_54=y
+# CONFIG_MACH_IPROC_EMULATION is not set
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_CPU_HAS_PMU=y
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_LOAD_CIS is not set
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_LOCAL_TIMERS=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+# CONFIG_IP_PIMSM_V1 is not set
+CONFIG_IP_PIMSM_V2=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=y
+CONFIG_TCP_CONG_HTCP=y
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_VLAN_8021Q_MVRP is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+# CONFIG_NET_SCH_CODEL is not set
+# CONFIG_NET_SCH_FQ_CODEL is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+CONFIG_HAVE_BPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_OF_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_M25PXX_STAY_IN_3BYTE_MODE is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_EARLY_DMA_ALLOC is not set
+# CONFIG_RETIMER_CLASS is not set
+# CONFIG_DS100DF410 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_CLASS=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_SFF_8436 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_ATA_BMDMA is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+CONFIG_PATA_PCMCIA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_LINEAR=y
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+CONFIG_MD_RAID456=y
+# CONFIG_MULTICORE_RAID456 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+# CONFIG_DM_THIN_PROVISIONING is not set
+CONFIG_DM_MIRROR=y
+CONFIG_DM_RAID=y
+# CONFIG_DM_LOG_USERSPACE is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+CONFIG_DUMMY=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_VIRTIO_NET=y
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+CONFIG_NET_VENDOR_FUJITSU=y
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_NET_VENDOR_INTEL=y
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+CONFIG_NET_VENDOR_I825XX=y
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+CONFIG_NET_VENDOR_SMSC=y
+# CONFIG_SMC91X is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_XIRCOM is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_DPAA_ETH_USE_NDO_SELECT_QUEUE is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_CS=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+# CONFIG_SERIAL_8250_DW is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_HVC_DCC is not set
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_I2C_MUX_PCA9541=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_I2C_MUX_DNI_6448 is not set
+# CONFIG_I2C_MUX_QUANTA is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_EG20T is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_PL061 is not set
+# CONFIG_GPIO_VX855 is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+CONFIG_SENSORS_ADM1021=y
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CY8CXX is not set
+# CONFIG_SENSORS_CY8C3245R1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+CONFIG_SENSORS_LM85=y
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+CONFIG_SENSORS_LTC4215=y
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+CONFIG_SENSORS_MAX6650=y
+CONFIG_SENSORS_MAX6620=y
+CONFIG_SENSORS_MAX6697=y
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+CONFIG_SENSORS_EMC2305=y
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+CONFIG_SENSORS_W83781D=y
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_SDRICOH_CS is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1374=y
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_RING=y
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_MACH_CLKDEV=y
+
+#
+# Hardware Spinlock drivers
+#
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# Frame Manager support
+#
+# CONFIG_FSL_FMAN is not set
+
+#
+# Broadcom iProc Drivers
+#
+# CONFIG_IPROC_CCB_TIMER is not set
+CONFIG_IPROC_MDIO=y
+# CONFIG_IPROC_DMA is not set
+CONFIG_IPROC_GPIO=y
+CONFIG_IPROC_QSPI=y
+CONFIG_IPROC_QSPI_SINGLE_MODE=y
+# CONFIG_IPROC_QSPI_DUAL_MODE is not set
+# CONFIG_IPROC_QSPI_QUAD_MODE is not set
+CONFIG_IPROC_QSPI_MAX_HZ=62500000
+# CONFIG_IPROC_MTD_NAND is not set
+# CONFIG_IPROC_PWM is not set
+CONFIG_IPROC_USB2H=y
+CONFIG_USB_EHCI_BCM=y
+CONFIG_IPROC_GMAC=y
+
+#
+# Broadcom HND network devices
+#
+CONFIG_HND=y
+CONFIG_ET=y
+CONFIG_ET_47XX=y
+# CONFIG_ET_NAPI2_POLL is not set
+# CONFIG_BCM_CTF is not set
+# CONFIG_BCM_CTF2 is not set
+# CONFIG_BCM_IPROC_GMAC_ACP is not set
+# CONFIG_BCM_IPROC_GMAC_PREFETCH is not set
+# CONFIG_BCM_IPROC_GMAC_SKB_RECYCLING is not set
+# CONFIG_BCM_IPROC_GMAC_LOCK_OPT is not set
+# CONFIG_BCM_IPROC_GMAC_RWREG_OPT is not set
+# CONFIG_BCM_IPROC_GMAC_SG is not set
+# CONFIG_WL_EMULATOR is not set
+# CONFIG_BCM57XX is not set
+# CONFIG_WL is not set
+# CONFIG_WL_USBAP is not set
+CONFIG_WL_AP=""
+CONFIG_WL_AP_SDSTD=""
+CONFIG_WL_STA=""
+CONFIG_WL_APSTA=""
+CONFIG_WL_AP_ONCHIP_G=""
+CONFIG_WL_STA_ONCHIP_G=""
+CONFIG_WL_HIGH=""
+CONFIG_IPROC_SDK_MGT_PORT_HANDOFF=y
+# CONFIG_IPROC_2STAGE_RX is not set
+CONFIG_IPROC_I2C=y
+# CONFIG_IPROC_PMU is not set
+# CONFIG_BCM_IPROC_CA9_PREFETCH is not set
+# CONFIG_BCM_BARRIER_PERFORMANCE is not set
+# CONFIG_BCM_MEM_OPTIMIZATION is not set
+# CONFIG_BROADCOM_CUSTOM_SENDFILE is not set
+# CONFIG_BCM_CUSTOM_RECVFILE is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_OVERLAYFS_FS=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_AUFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_MASK=0x1
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_ASYNC_RAID6_TEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=y
+CONFIG_ASYNC_CORE=y
+CONFIG_ASYNC_MEMCPY=y
+CONFIG_ASYNC_XOR=y
+CONFIG_ASYNC_PQ=y
+CONFIG_ASYNC_RAID6_RECOV=y
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=y
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+# CONFIG_CORDIC is not set
diff --git a/packages/base/any/kernels/3.2.71-1+deb7/kconfig.mk b/packages/base/any/kernels/3.2.71-1+deb7/kconfig.mk
new file mode 100644
index 00000000..ded46b73
--- /dev/null
+++ b/packages/base/any/kernels/3.2.71-1+deb7/kconfig.mk
@@ -0,0 +1,27 @@
+############################################################
+#
+#
+# Copyright 2015 Big Switch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+#
+############################################################
+
+THIS_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+K_MAJOR_VERSION := 3
+K_PATCH_LEVEL := 2
+K_SUB_LEVEL := 71
+K_SUFFIX :=
+K_PATCH_DIR := $(THIS_DIR)/patches
diff --git a/packages/base/any/kernels/3.2.71-1+deb7/patches/kernel-3.2.71.patch b/packages/base/any/kernels/3.2.71-1+deb7/patches/kernel-3.2.71.patch
new file mode 100644
index 00000000..1be91f23
--- /dev/null
+++ b/packages/base/any/kernels/3.2.71-1+deb7/patches/kernel-3.2.71.patch
@@ -0,0 +1,880075 @@
+diff --git a/.gitignore b/.gitignore
+index 57af07c..7c40244 100644
+--- a/.gitignore
++++ b/.gitignore
+@@ -40,17 +40,13 @@ modules.builtin
+ /TAGS
+ /linux
+ /vmlinux
++/vmlinux.strip
+ /vmlinuz
+ /System.map
+ /Module.markers
+ /Module.symvers
+
+ #
+-# Debian directory (make deb-pkg)
+-#
+-/debian/
+-
+-#
+ # git files that we don't want to ignore even it they are dot-files
+ #
+ !.gitignore
+diff --git a/Documentation/ABI/testing/debugfs-aufs b/Documentation/ABI/testing/debugfs-aufs
+new file mode 100644
+index 0000000..a58f0d0
+--- /dev/null
++++ b/Documentation/ABI/testing/debugfs-aufs
+@@ -0,0 +1,50 @@
++What: /debug/aufs/si_/
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ Under /debug/aufs, a directory named si_ is created
++ per aufs mount, where is a unique id generated
++ internally.
++
++What: /debug/aufs/si_/plink
++Date: Apr 2013
++Contact: J. R. Okajima
++Description:
++ It has three lines and shows the information about the
++ pseudo-link. The first line is a single number
++ representing a number of buckets. The second line is a
++ number of pseudo-links per buckets (separated by a
++ blank). The last line is a single number representing a
++ total number of psedo-links.
++ When the aufs mount option 'noplink' is specified, it
++ will show "1\n0\n0\n".
++
++What: /debug/aufs/si_/xib
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ It shows the consumed blocks by xib (External Inode Number
++ Bitmap), its block size and file size.
++ When the aufs mount option 'noxino' is specified, it
++ will be empty. About XINO files, see the aufs manual.
++
++What: /debug/aufs/si_/xino0, xino1 ... xinoN
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ It shows the consumed blocks by xino (External Inode Number
++ Translation Table), its link count, block size and file
++ size.
++ When the aufs mount option 'noxino' is specified, it
++ will be empty. About XINO files, see the aufs manual.
++
++What: /debug/aufs/si_/xigen
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ It shows the consumed blocks by xigen (External Inode
++ Generation Table), its block size and file size.
++ If CONFIG_AUFS_EXPORT is disabled, this entry will not
++ be created.
++ When the aufs mount option 'noxino' is specified, it
++ will be empty. About XINO files, see the aufs manual.
+diff --git a/Documentation/ABI/testing/sysfs-aufs b/Documentation/ABI/testing/sysfs-aufs
+new file mode 100644
+index 0000000..7af6dc0
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-aufs
+@@ -0,0 +1,24 @@
++What: /sys/fs/aufs/si_/
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ Under /sys/fs/aufs, a directory named si_ is created
++ per aufs mount, where is a unique id generated
++ internally.
++
++What: /sys/fs/aufs/si_/br0, br1 ... brN
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ It shows the abolute path of a member directory (which
++ is called branch) in aufs, and its permission.
++
++What: /sys/fs/aufs/si_/xi_path
++Date: March 2009
++Contact: J. R. Okajima
++Description:
++ It shows the abolute path of XINO (External Inode Number
++ Bitmap, Translation Table and Generation Table) file
++ even if it is the default path.
++ When the aufs mount option 'noxino' is specified, it
++ will be empty. About XINO files, see the aufs manual.
+diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
+index 349ecf2..6572c41 100644
+--- a/Documentation/ABI/testing/sysfs-bus-pci
++++ b/Documentation/ABI/testing/sysfs-bus-pci
+@@ -66,6 +66,21 @@ Description:
+ re-discover previously removed devices.
+ Depends on CONFIG_HOTPLUG.
+
++What: /sys/bus/pci/devices/.../msi_irqs/
++Date: September, 2011
++Contact: Neil Horman
++Description:
++ The /sys/devices/.../msi_irqs directory contains a variable set
++ of files, with each file being named after a corresponding msi
++ irq vector allocated to that device.
++
++What: /sys/bus/pci/devices/.../msi_irqs/
++Date: September 2011
++Contact: Neil Horman
++Description:
++ This attribute indicates the mode that the irq vector named by
++ the file is in (msi vs. msix)
++
+ What: /sys/bus/pci/devices/.../remove
+ Date: January 2009
+ Contact: Linux PCI developers
+diff --git a/Documentation/ABI/testing/sysfs-driver-wacom b/Documentation/ABI/testing/sysfs-driver-wacom
+index 82d4df1..5e9cbdc 100644
+--- a/Documentation/ABI/testing/sysfs-driver-wacom
++++ b/Documentation/ABI/testing/sysfs-driver-wacom
+@@ -15,9 +15,10 @@ Contact: linux-input@vger.kernel.org
+ Description:
+ Attribute group for control of the status LEDs and the OLEDs.
+ This attribute group is only available for Intuos 4 M, L,
+- and XL (with LEDs and OLEDs) and Cintiq 21UX2 (LEDs only).
+- Therefore its presence implicitly signifies the presence of
+- said LEDs and OLEDs on the tablet device.
++ and XL (with LEDs and OLEDs), Intuos 5 (LEDs only), and Cintiq
++ 21UX2 and Cintiq 24HD (LEDs only). Therefore its presence
++ implicitly signifies the presence of said LEDs and OLEDs on the
++ tablet device.
+
+ What: /sys/bus/usb/devices/-:./wacom_led/status0_luminance
+ Date: August 2011
+@@ -40,17 +41,18 @@ What: /sys/bus/usb/devices/-:./wacom_led/status_led0
+ Date: August 2011
+ Contact: linux-input@vger.kernel.org
+ Description:
+- Writing to this file sets which one of the four (for Intuos 4)
+- or of the right four (for Cintiq 21UX2) status LEDs is active (0..3).
+- The other three LEDs on the same side are always inactive.
++ Writing to this file sets which one of the four (for Intuos 4
++ and Intuos 5) or of the right four (for Cintiq 21UX2 and Cintiq
++ 24HD) status LEDs is active (0..3). The other three LEDs on the
++ same side are always inactive.
+
+ What: /sys/bus/usb/devices/-:./wacom_led/status_led1_select
+ Date: September 2011
+ Contact: linux-input@vger.kernel.org
+ Description:
+- Writing to this file sets which one of the left four (for Cintiq 21UX2)
+- status LEDs is active (0..3). The other three LEDs on the left are always
+- inactive.
++ Writing to this file sets which one of the left four (for Cintiq 21UX2
++ and Cintiq 24HD) status LEDs is active (0..3). The other three LEDs on
++ the left are always inactive.
+
+ What: /sys/bus/usb/devices/-:./wacom_led/buttons_luminance
+ Date: August 2011
+diff --git a/Documentation/DMA-API-HOWTO.txt b/Documentation/DMA-API-HOWTO.txt
+index a0b6250..41753a4 100644
+--- a/Documentation/DMA-API-HOWTO.txt
++++ b/Documentation/DMA-API-HOWTO.txt
+@@ -101,14 +101,23 @@ style to do this even if your device holds the default setting,
+ because this shows that you did think about these issues wrt. your
+ device.
+
+-The query is performed via a call to dma_set_mask():
++The query is performed via a call to dma_set_mask_and_coherent():
+
+- int dma_set_mask(struct device *dev, u64 mask);
++ int dma_set_mask_and_coherent(struct device *dev, u64 mask);
+
+-The query for consistent allocations is performed via a call to
+-dma_set_coherent_mask():
++which will query the mask for both streaming and coherent APIs together.
++If you have some special requirements, then the following two separate
++queries can be used instead:
+
+- int dma_set_coherent_mask(struct device *dev, u64 mask);
++ The query for streaming mappings is performed via a call to
++ dma_set_mask():
++
++ int dma_set_mask(struct device *dev, u64 mask);
++
++ The query for consistent allocations is performed via a call
++ to dma_set_coherent_mask():
++
++ int dma_set_coherent_mask(struct device *dev, u64 mask);
+
+ Here, dev is a pointer to the device struct of your device, and mask
+ is a bit mask describing which bits of an address your device
+@@ -137,7 +146,7 @@ exactly why.
+
+ The standard 32-bit addressing device would do something like this:
+
+- if (dma_set_mask(dev, DMA_BIT_MASK(32))) {
++ if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) {
+ printk(KERN_WARNING
+ "mydev: No suitable DMA available.\n");
+ goto ignore_this_device;
+@@ -171,22 +180,20 @@ the case would look like this:
+
+ int using_dac, consistent_using_dac;
+
+- if (!dma_set_mask(dev, DMA_BIT_MASK(64))) {
++ if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) {
+ using_dac = 1;
+ consistent_using_dac = 1;
+- dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+- } else if (!dma_set_mask(dev, DMA_BIT_MASK(32))) {
++ } else if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) {
+ using_dac = 0;
+ consistent_using_dac = 0;
+- dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+ } else {
+ printk(KERN_WARNING
+ "mydev: No suitable DMA available.\n");
+ goto ignore_this_device;
+ }
+
+-dma_set_coherent_mask() will always be able to set the same or a
+-smaller mask as dma_set_mask(). However for the rare case that a
++The coherent coherent mask will always be able to set the same or a
++smaller mask as the streaming mask. However for the rare case that a
+ device driver only uses consistent allocations, one would have to
+ check the return value from dma_set_coherent_mask().
+
+@@ -199,9 +206,9 @@ address you might do something like:
+ goto ignore_this_device;
+ }
+
+-When dma_set_mask() is successful, and returns zero, the kernel saves
+-away this mask you have provided. The kernel will use this
+-information later when you make DMA mappings.
++When dma_set_mask() or dma_set_mask_and_coherent() is successful, and
++returns zero, the kernel saves away this mask you have provided. The
++kernel will use this information later when you make DMA mappings.
+
+ There is a case which we are aware of at this time, which is worth
+ mentioning in this documentation. If your device supports multiple
+diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt
+index 66bd97a..322bda4 100644
+--- a/Documentation/DMA-API.txt
++++ b/Documentation/DMA-API.txt
+@@ -142,6 +142,14 @@ internal API for use by the platform than an external API for use by
+ driver writers.
+
+ int
++dma_set_mask_and_coherent(struct device *dev, u64 mask)
++
++Checks to see if the mask is possible and updates the device
++streaming and coherent DMA mask parameters if it is.
++
++Returns: 0 if successful and a negative error if not.
++
++int
+ dma_set_mask(struct device *dev, u64 mask)
+
+ Checks to see if the mask is possible and updates the device
+diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile
+index 66725a3..79084fa 100644
+--- a/Documentation/DocBook/Makefile
++++ b/Documentation/DocBook/Makefile
+@@ -159,7 +159,7 @@ quiet_cmd_db2html = HTML $@
+ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
+
+ quiet_cmd_db2man = MAN $@
+- cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi
++ cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; fi
+ %.9 : %.xml
+ @(which xmlto > /dev/null 2>&1) || \
+ (echo "*** You need to install xmlto ***"; \
+diff --git a/Documentation/cgroups/memory.txt b/Documentation/cgroups/memory.txt
+index fd129f6..ac12481 100644
+--- a/Documentation/cgroups/memory.txt
++++ b/Documentation/cgroups/memory.txt
+@@ -47,6 +47,10 @@ Features:
+ Kernel memory and Hugepages are not under control yet. We just manage
+ pages on LRU. To add more controls, we have to take care of performance.
+
++NOTE: In Debian kernel packages, the memory resource controller is
++included but disabled by default. Use the kernel parameter
++'cgroup_enable=memory' to enable it.
++
+ Brief summary of control files.
+
+ tasks # attach a task(thread) and show list of threads
+diff --git a/Documentation/devicetree/bindings/hwmon/emc2305.txt b/Documentation/devicetree/bindings/hwmon/emc2305.txt
+new file mode 100644
+index 0000000..ee67372
+--- /dev/null
++++ b/Documentation/devicetree/bindings/hwmon/emc2305.txt
+@@ -0,0 +1,60 @@
++EMC2305 (I2C)
++
++This device is a RPM-based PWM Fan Speed Controller for up to 5 fans.
++
++Each fan can beconfigured individually:
++
++ - pwm-enable defines the PWM mode:
++ 0: PWM is disabled
++ 3: RPM based PWM
++
++ - fan-div sets the fan divisor (for RPM mesaurement)
++ 1, 2 ,4 or 8
++
++ - fan-target sets the target RPM speed (for RPM based PWM mode)
++ max 16000 (according to data sheet)
++
++
++1) The /emc2305 node
++
++ Required properties:
++
++ - compatible : must be "smsc,emc2305"
++ - reg : I2C bus address of the device
++ - #address-cells : must be <1>
++ - #size-cells : must be <0>
++
++ The node may contain child nodes for each fan that the platform uses.
++ If no child nodes are given, all possible fan control channels are exposed.
++ If at least one child node is given, only the configured fans are exposed.
++
++ Example EMC2305 node:
++
++ emc2305@2C {
++ compatible = "smsc,emc2305";
++ reg = <0x2C>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ [ child node definitions... ]
++ }
++
++2) fan nodes
++
++ Required properties:
++
++ - reg : the fan number (0 based)
++
++ Optional properties:
++
++ - fan-div : the fan divisor setting
++ - fan-target : the fan target speed
++ - pwm-enable : PWM mode
++
++ Example EMC2305 fan node:
++
++ fan@1 {
++ reg = <1>;
++ fan-div = <4>;
++ pwm-enable = <0>;
++ };
+diff --git a/Documentation/devicetree/bindings/i2c/max6697.txt b/Documentation/devicetree/bindings/i2c/max6697.txt
+new file mode 100644
+index 0000000..5f79399
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/max6697.txt
+@@ -0,0 +1,64 @@
++max6697 properties
++
++Required properties:
++- compatible:
++ Should be one of
++ maxim,max6581
++ maxim,max6602
++ maxim,max6622
++ maxim,max6636
++ maxim,max6689
++ maxim,max6693
++ maxim,max6694
++ maxim,max6697
++ maxim,max6698
++ maxim,max6699
++- reg: I2C address
++
++Optional properties:
++
++- smbus-timeout-disable
++ Set to disable SMBus timeout. If not specified, SMBus timeout will be
++ enabled.
++- extended-range-enable
++ Only valid for MAX6581. Set to enable extended temperature range.
++ Extended temperature will be disabled if not specified.
++- beta-compensation-enable
++ Only valid for MAX6693 and MX6694. Set to enable beta compensation on
++ remote temperature channel 1.
++ Beta compensation will be disabled if not specified.
++- alert-mask
++ Alert bit mask. Alert disabled for bits set.
++ Select bit 0 for local temperature, bit 1..7 for remote temperatures.
++ If not specified, alert will be enabled for all channels.
++- over-temperature-mask
++ Over-temperature bit mask. Over-temperature reporting disabled for
++ bits set.
++ Select bit 0 for local temperature, bit 1..7 for remote temperatures.
++ If not specified, over-temperature reporting will be enabled for all
++ channels.
++- resistance-cancellation
++ Boolean for all chips other than MAX6581. Set to enable resistance
++ cancellation on remote temperature channel 1.
++ For MAX6581, resistance cancellation enabled for all channels if
++ specified as boolean, otherwise as per bit mask specified.
++ Only supported for remote temperatures (bit 1..7).
++ If not specified, resistance cancellation will be disabled for all
++ channels.
++- transistor-ideality
++ For MAX6581 only. Two values; first is bit mask, second is ideality
++ select value as per MAX6581 data sheet. Select bit 1..7 for remote
++ channels.
++ Transistor ideality will be initialized to default (1.008) if not
++ specified.
++
++Example:
++
++temp-sensor@1a {
++ compatible = "maxim,max6697";
++ reg = <0x1a>;
++ smbus-timeout-disable;
++ resistance-cancellation;
++ alert-mask = <0x72>;
++ over-temperature-mask = <0x7f>;
++};
+diff --git a/Documentation/devicetree/bindings/i2c/mux.txt b/Documentation/devicetree/bindings/i2c/mux.txt
+new file mode 100644
+index 0000000..fc9b542
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/mux.txt
+@@ -0,0 +1,62 @@
++Common i2c bus multiplexer/switch properties.
++
++An i2c bus multiplexer/switch will have several child busses that are
++numbered uniquely in a device dependent manner. The nodes for an i2c bus
++multiplexer/switch will have one child node for each child
++bus.
++
++Required properties:
++- #address-cells = <1>;
++- #size-cells = <0>;
++
++Required properties for child nodes:
++- #address-cells = <1>;
++- #size-cells = <0>;
++- reg : The sub-bus number.
++
++Optional properties for child nodes:
++- Other properties specific to the multiplexer/switch hardware.
++- Child nodes conforming to i2c bus binding
++- deselect-on-exit -- if set deselect the mux after each transaction,
++ supported by the pca954x.c driver.
++
++Example :
++
++ /*
++ An NXP pca9548 8 channel I2C multiplexer at address 0x70
++ with two NXP pca8574 GPIO expanders attached, one each to
++ ports 3 and 4.
++ */
++
++ mux@70 {
++ compatible = "nxp,pca9548";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ deselect-on-exit;
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++
++ gpio1: gpio@38 {
++ compatible = "nxp,pca8574";
++ reg = <0x38>;
++ #gpio-cells = <2>;
++ gpio-controller;
++ };
++ };
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++
++ gpio2: gpio@38 {
++ compatible = "nxp,pca8574";
++ reg = <0x38>;
++ #gpio-cells = <2>;
++ gpio-controller;
++ };
++ };
++ };
+diff --git a/Documentation/filesystems/aufs/README b/Documentation/filesystems/aufs/README
+new file mode 100644
+index 0000000..c9f8097
+--- /dev/null
++++ b/Documentation/filesystems/aufs/README
+@@ -0,0 +1,333 @@
++
++Aufs3 -- advanced multi layered unification filesystem version 3.x
++http://aufs.sf.net
++Junjiro R. Okajima
++
++
++0. Introduction
++----------------------------------------
++In the early days, aufs was entirely re-designed and re-implemented
++Unionfs Version 1.x series. After many original ideas, approaches,
++improvements and implementations, it becomes totally different from
++Unionfs while keeping the basic features.
++Recently, Unionfs Version 2.x series begin taking some of the same
++approaches to aufs1's.
++Unionfs is being developed by Professor Erez Zadok at Stony Brook
++University and his team.
++
++Aufs3 supports linux-3.0 and later.
++If you want older kernel version support, try aufs2-2.6.git or
++aufs2-standalone.git repository, aufs1 from CVS on SourceForge.
++
++Note: it becomes clear that "Aufs was rejected. Let's give it up."
++According to Christoph Hellwig, linux rejects all union-type filesystems
++but UnionMount.
++
++
++
++1. Features
++----------------------------------------
++- unite several directories into a single virtual filesystem. The member
++ directory is called as a branch.
++- you can specify the permission flags to the branch, which are 'readonly',
++ 'readwrite' and 'whiteout-able.'
++- by upper writable branch, internal copyup and whiteout, files/dirs on
++ readonly branch are modifiable logically.
++- dynamic branch manipulation, add, del.
++- etc...
++
++Also there are many enhancements in aufs1, such as:
++- readdir(3) in userspace.
++- keep inode number by external inode number table
++- keep the timestamps of file/dir in internal copyup operation
++- seekable directory, supporting NFS readdir.
++- whiteout is hardlinked in order to reduce the consumption of inodes
++ on branch
++- do not copyup, nor create a whiteout when it is unnecessary
++- revert a single systemcall when an error occurs in aufs
++- remount interface instead of ioctl
++- maintain /etc/mtab by an external command, /sbin/mount.aufs.
++- loopback mounted filesystem as a branch
++- kernel thread for removing the dir who has a plenty of whiteouts
++- support copyup sparse file (a file which has a 'hole' in it)
++- default permission flags for branches
++- selectable permission flags for ro branch, whether whiteout can
++ exist or not
++- export via NFS.
++- support /fs/aufs and /aufs.
++- support multiple writable branches, some policies to select one
++ among multiple writable branches.
++- a new semantics for link(2) and rename(2) to support multiple
++ writable branches.
++- no glibc changes are required.
++- pseudo hardlink (hardlink over branches)
++- allow a direct access manually to a file on branch, e.g. bypassing aufs.
++ including NFS or remote filesystem branch.
++- userspace wrapper for pathconf(3)/fpathconf(3) with _PC_LINK_MAX.
++- and more...
++
++Currently these features are dropped temporary from aufs3.
++See design/08plan.txt in detail.
++- test only the highest one for the directory permission (dirperm1)
++- copyup on open (coo=)
++- nested mount, i.e. aufs as readonly no-whiteout branch of another aufs
++ (robr)
++- statistics of aufs thread (/sys/fs/aufs/stat)
++- delegation mode (dlgt)
++ a delegation of the internal branch access to support task I/O
++ accounting, which also supports Linux Security Modules (LSM) mainly
++ for Suse AppArmor.
++- intent.open/create (file open in a single lookup)
++
++Features or just an idea in the future (see also design/*.txt),
++- reorder the branch index without del/re-add.
++- permanent xino files for NFSD
++- an option for refreshing the opened files after add/del branches
++- 'move' policy for copy-up between two writable branches, after
++ checking free space.
++- light version, without branch manipulation. (unnecessary?)
++- copyup in userspace
++- inotify in userspace
++- readv/writev
++- xattr, acl
++
++
++2. Download
++----------------------------------------
++There were three GIT trees for aufs3, aufs3-linux.git,
++aufs3-standalone.git, and aufs-util.git. Note that there is no "3" in
++"aufs-util.git."
++While the aufs-util is always necessary, you need either of aufs3-linux
++or aufs3-standalone.
++
++The aufs3-linux tree includes the whole linux mainline GIT tree,
++git://git.kernel.org/.../torvalds/linux.git.
++And you cannot select CONFIG_AUFS_FS=m for this version, eg. you cannot
++build aufs3 as an external kernel module.
++
++On the other hand, the aufs3-standalone tree has only aufs source files
++and necessary patches, and you can select CONFIG_AUFS_FS=m.
++
++You will find GIT branches whose name is in form of "aufs3.x" where "x"
++represents the linux kernel version, "linux-3.x". For instance,
++"aufs3.0" is for linux-3.0. For latest "linux-3.x-rcN", use
++"aufs3.x-rcN" branch.
++
++o aufs3-linux tree
++$ git clone --reference /your/linux/git/tree \
++ git://git.code.sf.net/p/aufs/aufs3-linux aufs-aufs3-linux \
++ aufs3-linux.git
++- if you don't have linux GIT tree, then remove "--reference ..."
++$ cd aufs3-linux.git
++$ git checkout origin/aufs3.0
++
++o aufs3-standalone tree
++$ git clone git://git.code.sf.net/p/aufs/aufs3-standalone \
++ aufs3-standalone.git
++$ cd aufs3-standalone.git
++$ git checkout origin/aufs3.0
++
++o aufs-util tree
++$ git clone git://git.code.sf.net/p/aufs/aufs-util \
++ aufs-util.git
++$ cd aufs-util.git
++$ git checkout origin/aufs3.0
++
++Note: The 3.x-rcN branch is to be used with `rc' kernel versions ONLY.
++The minor version number, 'x' in '3.x', of aufs may not always
++follow the minor version number of the kernel.
++Because changes in the kernel that cause the use of a new
++minor version number do not always require changes to aufs-util.
++
++Since aufs-util has its own minor version number, you may not be
++able to find a GIT branch in aufs-util for your kernel's
++exact minor version number.
++In this case, you should git-checkout the branch for the
++nearest lower number.
++
++For (an unreleased) example:
++If you are using "linux-3.10" and the "aufs3.10" branch
++does not exist in aufs-util repository, then "aufs3.9", "aufs3.8"
++or something numerically smaller is the branch for your kernel.
++
++Also you can view all branches by
++ $ git branch -a
++
++
++3. Configuration and Compilation
++----------------------------------------
++Make sure you have git-checkout'ed the correct branch.
++
++For aufs3-linux tree,
++- enable CONFIG_EXPERIMENTAL and CONFIG_AUFS_FS.
++- set other aufs configurations if necessary.
++
++For aufs3-standalone tree,
++There are several ways to build.
++
++1.
++- apply ./aufs3-kbuild.patch to your kernel source files.
++- apply ./aufs3-base.patch too.
++- apply ./aufs3-proc_map.patch too, if you want to make /proc/PID/maps (and
++ others including lsof(1)) show the file path on aufs instead of the
++ path on the branch fs.
++- apply ./aufs3-standalone.patch too, if you have a plan to set
++ CONFIG_AUFS_FS=m. otherwise you don't need ./aufs3-standalone.patch.
++- copy ./{Documentation,fs,include/linux/aufs_type.h} files to your
++ kernel source tree. Never copy $PWD/include/linux/Kbuild.
++- enable CONFIG_EXPERIMENTAL and CONFIG_AUFS_FS, you can select either
++ =m or =y.
++- and build your kernel as usual.
++- install the built kernel.
++- install the header files too by "make headers_install" to the
++ directory where you specify. By default, it is $PWD/usr.
++ "make help" shows a brief note for headers_install.
++- and reboot your system.
++
++2.
++- module only (CONFIG_AUFS_FS=m).
++- apply ./aufs3-base.patch to your kernel source files.
++- apply ./aufs3-proc_map.patch too to your kernel source files,
++ if you want to make /proc/PID/maps (and others including lsof(1)) show
++ the file path on aufs instead of the path on the branch fs.
++- apply ./aufs3-standalone.patch too.
++- build your kernel, don't forget "make headers_install", and reboot.
++- edit ./config.mk and set other aufs configurations if necessary.
++ Note: You should read $PWD/fs/aufs/Kconfig carefully which describes
++ every aufs configurations.
++- build the module by simple "make".
++- you can specify ${KDIR} make variable which points to your kernel
++ source tree.
++- install the files
++ + run "make install" to install the aufs module, or copy the built
++ $PWD/aufs.ko to /lib/modules/... and run depmod -a (or reboot simply).
++ + run "make install_headers" (instead of headers_install) to install
++ the modified aufs header file (you can specify DESTDIR which is
++ available in aufs standalone version's Makefile only), or copy
++ $PWD/usr/include/linux/aufs_type.h to /usr/include/linux or wherever
++ you like manually. By default, the target directory is $PWD/usr.
++- no need to apply aufs3-kbuild.patch, nor copying source files to your
++ kernel source tree.
++
++Note: The header file aufs_type.h is necessary to build aufs-util
++ as well as "make headers_install" in the kernel source tree.
++ headers_install is subject to be forgotten, but it is essentially
++ necessary, not only for building aufs-util.
++ You may not meet problems without headers_install in some older
++ version though.
++
++And then,
++- read README in aufs-util, build and install it
++- note that your distribution may contain an obsoleted version of
++ aufs_type.h in /usr/include/linux or something. When you build aufs
++ utilities, make sure that your compiler refers the correct aufs header
++ file which is built by "make headers_install."
++- if you want to use readdir(3) in userspace or pathconf(3) wrapper,
++ then run "make install_ulib" too. And refer to the aufs manual in
++ detail.
++
++
++4. Usage
++----------------------------------------
++At first, make sure aufs-util are installed, and please read the aufs
++manual, aufs.5 in aufs-util.git tree.
++$ man -l aufs.5
++
++And then,
++$ mkdir /tmp/rw /tmp/aufs
++# mount -t aufs -o br=/tmp/rw:${HOME} none /tmp/aufs
++
++Here is another example. The result is equivalent.
++# mount -t aufs -o br=/tmp/rw=rw:${HOME}=ro none /tmp/aufs
++ Or
++# mount -t aufs -o br:/tmp/rw none /tmp/aufs
++# mount -o remount,append:${HOME} /tmp/aufs
++
++Then, you can see whole tree of your home dir through /tmp/aufs. If
++you modify a file under /tmp/aufs, the one on your home directory is
++not affected, instead the same named file will be newly created under
++/tmp/rw. And all of your modification to a file will be applied to
++the one under /tmp/rw. This is called the file based Copy on Write
++(COW) method.
++Aufs mount options are described in aufs.5.
++If you run chroot or something and make your aufs as a root directory,
++then you need to customize the shutdown script. See the aufs manual in
++detail.
++
++Additionally, there are some sample usages of aufs which are a
++diskless system with network booting, and LiveCD over NFS.
++See sample dir in CVS tree on SourceForge.
++
++
++5. Contact
++----------------------------------------
++When you have any problems or strange behaviour in aufs, please let me
++know with:
++- /proc/mounts (instead of the output of mount(8))
++- /sys/module/aufs/*
++- /sys/fs/aufs/* (if you have them)
++- /debug/aufs/* (if you have them)
++- linux kernel version
++ if your kernel is not plain, for example modified by distributor,
++ the url where i can download its source is necessary too.
++- aufs version which was printed at loading the module or booting the
++ system, instead of the date you downloaded.
++- configuration (define/undefine CONFIG_AUFS_xxx)
++- kernel configuration or /proc/config.gz (if you have it)
++- behaviour which you think to be incorrect
++- actual operation, reproducible one is better
++- mailto: aufs-users at lists.sourceforge.net
++
++Usually, I don't watch the Public Areas(Bugs, Support Requests, Patches,
++and Feature Requests) on SourceForge. Please join and write to
++aufs-users ML.
++
++
++6. Acknowledgements
++----------------------------------------
++Thanks to everyone who have tried and are using aufs, whoever
++have reported a bug or any feedback.
++
++Especially donators:
++Tomas Matejicek(slax.org) made a donation (much more than once).
++ Since Apr 2010, Tomas M (the author of Slax and Linux Live
++ scripts) is making "doubling" donations.
++ Unfortunately I cannot list all of the donators, but I really
++ appreciate.
++ It ends Aug 2010, but the ordinary donation URL is still available.
++
++Dai Itasaka made a donation (2007/8).
++Chuck Smith made a donation (2008/4, 10 and 12).
++Henk Schoneveld made a donation (2008/9).
++Chih-Wei Huang, ASUS, CTC donated Eee PC 4G (2008/10).
++Francois Dupoux made a donation (2008/11).
++Bruno Cesar Ribas and Luis Carlos Erpen de Bona, C3SL serves public
++ aufs2 GIT tree (2009/2).
++William Grant made a donation (2009/3).
++Patrick Lane made a donation (2009/4).
++The Mail Archive (mail-archive.com) made donations (2009/5).
++Nippy Networks (Ed Wildgoose) made a donation (2009/7).
++New Dream Network, LLC (www.dreamhost.com) made a donation (2009/11).
++Pavel Pronskiy made a donation (2011/2).
++Iridium and Inmarsat satellite phone retailer (www.mailasail.com), Nippy
++ Networks (Ed Wildgoose) made a donation for hardware (2011/3).
++Max Lekomcev (DOM-TV project) made a donation (2011/7, 12, 2012/3, 6 and
++11).
++Sam Liddicott made a donation (2011/9).
++
++Thank you very much.
++Donations are always, including future donations, very important and
++helpful for me to keep on developing aufs.
++
++
++7.
++----------------------------------------
++If you are an experienced user, no explanation is needed. Aufs is
++just a linux filesystem.
++
++
++Enjoy!
++
++# Local variables: ;
++# mode: text;
++# End: ;
+diff --git a/Documentation/filesystems/aufs/design/01intro.txt b/Documentation/filesystems/aufs/design/01intro.txt
+new file mode 100644
+index 0000000..e60f8c6
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/01intro.txt
+@@ -0,0 +1,162 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Introduction
++----------------------------------------
++
++aufs [ei ju: ef es] | [a u f s]
++1. abbrev. for "advanced multi-layered unification filesystem".
++2. abbrev. for "another unionfs".
++3. abbrev. for "auf das" in German which means "on the" in English.
++ Ex. "Butter aufs Brot"(G) means "butter onto bread"(E).
++ But "Filesystem aufs Filesystem" is hard to understand.
++
++AUFS is a filesystem with features:
++- multi layered stackable unification filesystem, the member directory
++ is called as a branch.
++- branch permission and attribute, 'readonly', 'real-readonly',
++ 'readwrite', 'whiteout-able', 'link-able whiteout' and their
++ combination.
++- internal "file copy-on-write".
++- logical deletion, whiteout.
++- dynamic branch manipulation, adding, deleting and changing permission.
++- allow bypassing aufs, user's direct branch access.
++- external inode number translation table and bitmap which maintains the
++ persistent aufs inode number.
++- seekable directory, including NFS readdir.
++- file mapping, mmap and sharing pages.
++- pseudo-link, hardlink over branches.
++- loopback mounted filesystem as a branch.
++- several policies to select one among multiple writable branches.
++- revert a single systemcall when an error occurs in aufs.
++- and more...
++
++
++Multi Layered Stackable Unification Filesystem
++----------------------------------------------------------------------
++Most people already knows what it is.
++It is a filesystem which unifies several directories and provides a
++merged single directory. When users access a file, the access will be
++passed/re-directed/converted (sorry, I am not sure which English word is
++correct) to the real file on the member filesystem. The member
++filesystem is called 'lower filesystem' or 'branch' and has a mode
++'readonly' and 'readwrite.' And the deletion for a file on the lower
++readonly branch is handled by creating 'whiteout' on the upper writable
++branch.
++
++On LKML, there have been discussions about UnionMount (Jan Blunck,
++Bharata B Rao and Valerie Aurora) and Unionfs (Erez Zadok). They took
++different approaches to implement the merged-view.
++The former tries putting it into VFS, and the latter implements as a
++separate filesystem.
++(If I misunderstand about these implementations, please let me know and
++I shall correct it. Because it is a long time ago when I read their
++source files last time).
++
++UnionMount's approach will be able to small, but may be hard to share
++branches between several UnionMount since the whiteout in it is
++implemented in the inode on branch filesystem and always
++shared. According to Bharata's post, readdir does not seems to be
++finished yet.
++There are several missing features known in this implementations such as
++- for users, the inode number may change silently. eg. copy-up.
++- link(2) may break by copy-up.
++- read(2) may get an obsoleted filedata (fstat(2) too).
++- fcntl(F_SETLK) may be broken by copy-up.
++- unnecessary copy-up may happen, for example mmap(MAP_PRIVATE) after
++ open(O_RDWR).
++
++Unionfs has a longer history. When I started implementing a stacking filesystem
++(Aug 2005), it already existed. It has virtual super_block, inode,
++dentry and file objects and they have an array pointing lower same kind
++objects. After contributing many patches for Unionfs, I re-started my
++project AUFS (Jun 2006).
++
++In AUFS, the structure of filesystem resembles to Unionfs, but I
++implemented my own ideas, approaches and enhancements and it became
++totally different one.
++
++Comparing DM snapshot and fs based implementation
++- the number of bytes to be copied between devices is much smaller.
++- the type of filesystem must be one and only.
++- the fs must be writable, no readonly fs, even for the lower original
++ device. so the compression fs will not be usable. but if we use
++ loopback mount, we may address this issue.
++ for instance,
++ mount /cdrom/squashfs.img /sq
++ losetup /sq/ext2.img
++ losetup /somewhere/cow
++ dmsetup "snapshot /dev/loop0 /dev/loop1 ..."
++- it will be difficult (or needs more operations) to extract the
++ difference between the original device and COW.
++- DM snapshot-merge may help a lot when users try merging. in the
++ fs-layer union, users will use rsync(1).
++
++
++Several characters/aspects of aufs
++----------------------------------------------------------------------
++
++Aufs has several characters or aspects.
++1. a filesystem, callee of VFS helper
++2. sub-VFS, caller of VFS helper for branches
++3. a virtual filesystem which maintains persistent inode number
++4. reader/writer of files on branches such like an application
++
++1. Callee of VFS Helper
++As an ordinary linux filesystem, aufs is a callee of VFS. For instance,
++unlink(2) from an application reaches sys_unlink() kernel function and
++then vfs_unlink() is called. vfs_unlink() is one of VFS helper and it
++calls filesystem specific unlink operation. Actually aufs implements the
++unlink operation but it behaves like a redirector.
++
++2. Caller of VFS Helper for Branches
++aufs_unlink() passes the unlink request to the branch filesystem as if
++it were called from VFS. So the called unlink operation of the branch
++filesystem acts as usual. As a caller of VFS helper, aufs should handle
++every necessary pre/post operation for the branch filesystem.
++- acquire the lock for the parent dir on a branch
++- lookup in a branch
++- revalidate dentry on a branch
++- mnt_want_write() for a branch
++- vfs_unlink() for a branch
++- mnt_drop_write() for a branch
++- release the lock on a branch
++
++3. Persistent Inode Number
++One of the most important issue for a filesystem is to maintain inode
++numbers. This is particularly important to support exporting a
++filesystem via NFS. Aufs is a virtual filesystem which doesn't have a
++backend block device for its own. But some storage is necessary to
++maintain inode number. It may be a large space and may not suit to keep
++in memory. Aufs rents some space from its first writable branch
++filesystem (by default) and creates file(s) on it. These files are
++created by aufs internally and removed soon (currently) keeping opened.
++Note: Because these files are removed, they are totally gone after
++ unmounting aufs. It means the inode numbers are not persistent
++ across unmount or reboot. I have a plan to make them really
++ persistent which will be important for aufs on NFS server.
++
++4. Read/Write Files Internally (copy-on-write)
++Because a branch can be readonly, when you write a file on it, aufs will
++"copy-up" it to the upper writable branch internally. And then write the
++originally requested thing to the file. Generally kernel doesn't
++open/read/write file actively. In aufs, even a single write may cause a
++internal "file copy". This behaviour is very similar to cp(1) command.
++
++Some people may think it is better to pass such work to user space
++helper, instead of doing in kernel space. Actually I am still thinking
++about it. But currently I have implemented it in kernel space.
+diff --git a/Documentation/filesystems/aufs/design/02struct.txt b/Documentation/filesystems/aufs/design/02struct.txt
+new file mode 100644
+index 0000000..f54d654
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/02struct.txt
+@@ -0,0 +1,226 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Basic Aufs Internal Structure
++
++Superblock/Inode/Dentry/File Objects
++----------------------------------------------------------------------
++As like an ordinary filesystem, aufs has its own
++superblock/inode/dentry/file objects. All these objects have a
++dynamically allocated array and store the same kind of pointers to the
++lower filesystem, branch.
++For example, when you build a union with one readwrite branch and one
++readonly, mounted /au, /rw and /ro respectively.
++- /au = /rw + /ro
++- /ro/fileA exists but /rw/fileA
++
++Aufs lookup operation finds /ro/fileA and gets dentry for that. These
++pointers are stored in a aufs dentry. The array in aufs dentry will be,
++- [0] = NULL
++- [1] = /ro/fileA
++
++This style of an array is essentially same to the aufs
++superblock/inode/dentry/file objects.
++
++Because aufs supports manipulating branches, ie. add/delete/change
++dynamically, these objects has its own generation. When branches are
++changed, the generation in aufs superblock is incremented. And a
++generation in other object are compared when it is accessed.
++When a generation in other objects are obsoleted, aufs refreshes the
++internal array.
++
++
++Superblock
++----------------------------------------------------------------------
++Additionally aufs superblock has some data for policies to select one
++among multiple writable branches, XIB files, pseudo-links and kobject.
++See below in detail.
++About the policies which supports copy-down a directory, see policy.txt
++too.
++
++
++Branch and XINO(External Inode Number Translation Table)
++----------------------------------------------------------------------
++Every branch has its own xino (external inode number translation table)
++file. The xino file is created and unlinked by aufs internally. When two
++members of a union exist on the same filesystem, they share the single
++xino file.
++The struct of a xino file is simple, just a sequence of aufs inode
++numbers which is indexed by the lower inode number.
++In the above sample, assume the inode number of /ro/fileA is i111 and
++aufs assigns the inode number i999 for fileA. Then aufs writes 999 as
++4(8) bytes at 111 * 4(8) bytes offset in the xino file.
++
++When the inode numbers are not contiguous, the xino file will be sparse
++which has a hole in it and doesn't consume as much disk space as it
++might appear. If your branch filesystem consumes disk space for such
++holes, then you should specify 'xino=' option at mounting aufs.
++
++Also a writable branch has three kinds of "whiteout bases". All these
++are existed when the branch is joined to aufs and the names are
++whiteout-ed doubly, so that users will never see their names in aufs
++hierarchy.
++1. a regular file which will be linked to all whiteouts.
++2. a directory to store a pseudo-link.
++3. a directory to store an "orphan-ed" file temporary.
++
++1. Whiteout Base
++ When you remove a file on a readonly branch, aufs handles it as a
++ logical deletion and creates a whiteout on the upper writable branch
++ as a hardlink of this file in order not to consume inode on the
++ writable branch.
++2. Pseudo-link Dir
++ See below, Pseudo-link.
++3. Step-Parent Dir
++ When "fileC" exists on the lower readonly branch only and it is
++ opened and removed with its parent dir, and then user writes
++ something into it, then aufs copies-up fileC to this
++ directory. Because there is no other dir to store fileC. After
++ creating a file under this dir, the file is unlinked.
++
++Because aufs supports manipulating branches, ie. add/delete/change
++dynamically, a branch has its own id. When the branch order changes, aufs
++finds the new index by searching the branch id.
++
++
++Pseudo-link
++----------------------------------------------------------------------
++Assume "fileA" exists on the lower readonly branch only and it is
++hardlinked to "fileB" on the branch. When you write something to fileA,
++aufs copies-up it to the upper writable branch. Additionally aufs
++creates a hardlink under the Pseudo-link Directory of the writable
++branch. The inode of a pseudo-link is kept in aufs super_block as a
++simple list. If fileB is read after unlinking fileA, aufs returns
++filedata from the pseudo-link instead of the lower readonly
++branch. Because the pseudo-link is based upon the inode, to keep the
++inode number by xino (see above) is important.
++
++All the hardlinks under the Pseudo-link Directory of the writable branch
++should be restored in a proper location later. Aufs provides a utility
++to do this. The userspace helpers executed at remounting and unmounting
++aufs by default.
++During this utility is running, it puts aufs into the pseudo-link
++maintenance mode. In this mode, only the process which began the
++maintenance mode (and its child processes) is allowed to operate in
++aufs. Some other processes which are not related to the pseudo-link will
++be allowed to run too, but the rest have to return an error or wait
++until the maintenance mode ends. If a process already acquires an inode
++mutex (in VFS), it has to return an error.
++
++
++XIB(external inode number bitmap)
++----------------------------------------------------------------------
++Addition to the xino file per a branch, aufs has an external inode number
++bitmap in a superblock object. It is also a file such like a xino file.
++It is a simple bitmap to mark whether the aufs inode number is in-use or
++not.
++To reduce the file I/O, aufs prepares a single memory page to cache xib.
++
++Aufs implements a feature to truncate/refresh both of xino and xib to
++reduce the number of consumed disk blocks for these files.
++
++
++Virtual or Vertical Dir, and Readdir in Userspace
++----------------------------------------------------------------------
++In order to support multiple layers (branches), aufs readdir operation
++constructs a virtual dir block on memory. For readdir, aufs calls
++vfs_readdir() internally for each dir on branches, merges their entries
++with eliminating the whiteout-ed ones, and sets it to file (dir)
++object. So the file object has its entry list until it is closed. The
++entry list will be updated when the file position is zero and becomes
++old. This decision is made in aufs automatically.
++
++The dynamically allocated memory block for the name of entries has a
++unit of 512 bytes (by default) and stores the names contiguously (no
++padding). Another block for each entry is handled by kmem_cache too.
++During building dir blocks, aufs creates hash list and judging whether
++the entry is whiteouted by its upper branch or already listed.
++The merged result is cached in the corresponding inode object and
++maintained by a customizable life-time option.
++
++Some people may call it can be a security hole or invite DoS attack
++since the opened and once readdir-ed dir (file object) holds its entry
++list and becomes a pressure for system memory. But I'd say it is similar
++to files under /proc or /sys. The virtual files in them also holds a
++memory page (generally) while they are opened. When an idea to reduce
++memory for them is introduced, it will be applied to aufs too.
++For those who really hate this situation, I've developed readdir(3)
++library which operates this merging in userspace. You just need to set
++LD_PRELOAD environment variable, and aufs will not consume no memory in
++kernel space for readdir(3).
++
++
++Workqueue
++----------------------------------------------------------------------
++Aufs sometimes requires privilege access to a branch. For instance,
++in copy-up/down operation. When a user process is going to make changes
++to a file which exists in the lower readonly branch only, and the mode
++of one of ancestor directories may not be writable by a user
++process. Here aufs copy-up the file with its ancestors and they may
++require privilege to set its owner/group/mode/etc.
++This is a typical case of a application character of aufs (see
++Introduction).
++
++Aufs uses workqueue synchronously for this case. It creates its own
++workqueue. The workqueue is a kernel thread and has privilege. Aufs
++passes the request to call mkdir or write (for example), and wait for
++its completion. This approach solves a problem of a signal handler
++simply.
++If aufs didn't adopt the workqueue and changed the privilege of the
++process, and if the mkdir/write call arises SIGXFSZ or other signal,
++then the user process might gain a privilege or the generated core file
++was owned by a superuser.
++
++Also aufs uses the system global workqueue ("events" kernel thread) too
++for asynchronous tasks, such like handling inotify/fsnotify, re-creating a
++whiteout base and etc. This is unrelated to a privilege.
++Most of aufs operation tries acquiring a rw_semaphore for aufs
++superblock at the beginning, at the same time waits for the completion
++of all queued asynchronous tasks.
++
++
++Whiteout
++----------------------------------------------------------------------
++The whiteout in aufs is very similar to Unionfs's. That is represented
++by its filename. UnionMount takes an approach of a file mode, but I am
++afraid several utilities (find(1) or something) will have to support it.
++
++Basically the whiteout represents "logical deletion" which stops aufs to
++lookup further, but also it represents "dir is opaque" which also stop
++lookup.
++
++In aufs, rmdir(2) and rename(2) for dir uses whiteout alternatively.
++In order to make several functions in a single systemcall to be
++revertible, aufs adopts an approach to rename a directory to a temporary
++unique whiteouted name.
++For example, in rename(2) dir where the target dir already existed, aufs
++renames the target dir to a temporary unique whiteouted name before the
++actual rename on a branch and then handles other actions (make it opaque,
++update the attributes, etc). If an error happens in these actions, aufs
++simply renames the whiteouted name back and returns an error. If all are
++succeeded, aufs registers a function to remove the whiteouted unique
++temporary name completely and asynchronously to the system global
++workqueue.
++
++
++Copy-up
++----------------------------------------------------------------------
++It is a well-known feature or concept.
++When user modifies a file on a readonly branch, aufs operate "copy-up"
++internally and makes change to the new file on the upper writable branch.
++When the trigger systemcall does not update the timestamps of the parent
++dir, aufs reverts it after copy-up.
+diff --git a/Documentation/filesystems/aufs/design/03lookup.txt b/Documentation/filesystems/aufs/design/03lookup.txt
+new file mode 100644
+index 0000000..d3ca527
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/03lookup.txt
+@@ -0,0 +1,106 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Lookup in a Branch
++----------------------------------------------------------------------
++Since aufs has a character of sub-VFS (see Introduction), it operates
++lookup for branches as VFS does. It may be a heavy work. Generally
++speaking struct nameidata is a bigger structure and includes many
++information. But almost all lookup operation in aufs is the simplest
++case, ie. lookup only an entry directly connected to its parent. Digging
++down the directory hierarchy is unnecessary.
++
++VFS has a function lookup_one_len() for that use, but it is not usable
++for a branch filesystem which requires struct nameidata. So aufs
++implements a simple lookup wrapper function. When a branch filesystem
++allows NULL as nameidata, it calls lookup_one_len(). Otherwise it builds
++a simplest nameidata and calls lookup_hash().
++Here aufs applies "a principle in NFSD", ie. if the filesystem supports
++NFS-export, then it has to support NULL as a nameidata parameter for
++->create(), ->lookup() and ->d_revalidate(). So the lookup wrapper in
++aufs tests if ->s_export_op in the branch is NULL or not.
++
++When a branch is a remote filesystem, aufs basically trusts its
++->d_revalidate(), also aufs forces the hardest revalidate tests for
++them.
++For d_revalidate, aufs implements three levels of revalidate tests. See
++"Revalidate Dentry and UDBA" in detail.
++
++
++Loopback Mount
++----------------------------------------------------------------------
++Basically aufs supports any type of filesystem and block device for a
++branch (actually there are some exceptions). But it is prohibited to add
++a loopback mounted one whose backend file exists in a filesystem which is
++already added to aufs. The reason is to protect aufs from a recursive
++lookup. If it was allowed, the aufs lookup operation might re-enter a
++lookup for the loopback mounted branch in the same context, and will
++cause a deadlock.
++
++
++Revalidate Dentry and UDBA (User's Direct Branch Access)
++----------------------------------------------------------------------
++Generally VFS helpers re-validate a dentry as a part of lookup.
++0. digging down the directory hierarchy.
++1. lock the parent dir by its i_mutex.
++2. lookup the final (child) entry.
++3. revalidate it.
++4. call the actual operation (create, unlink, etc.)
++5. unlock the parent dir
++
++If the filesystem implements its ->d_revalidate() (step 3), then it is
++called. Actually aufs implements it and checks the dentry on a branch is
++still valid.
++But it is not enough. Because aufs has to release the lock for the
++parent dir on a branch at the end of ->lookup() (step 2) and
++->d_revalidate() (step 3) while the i_mutex of the aufs dir is still
++held by VFS.
++If the file on a branch is changed directly, eg. bypassing aufs, after
++aufs released the lock, then the subsequent operation may cause
++something unpleasant result.
++
++This situation is a result of VFS architecture, ->lookup() and
++->d_revalidate() is separated. But I never say it is wrong. It is a good
++design from VFS's point of view. It is just not suitable for sub-VFS
++character in aufs.
++
++Aufs supports such case by three level of revalidation which is
++selectable by user.
++1. Simple Revalidate
++ Addition to the native flow in VFS's, confirm the child-parent
++ relationship on the branch just after locking the parent dir on the
++ branch in the "actual operation" (step 4). When this validation
++ fails, aufs returns EBUSY. ->d_revalidate() (step 3) in aufs still
++ checks the validation of the dentry on branches.
++2. Monitor Changes Internally by Inotify/Fsnotify
++ Addition to above, in the "actual operation" (step 4) aufs re-lookup
++ the dentry on the branch, and returns EBUSY if it finds different
++ dentry.
++ Additionally, aufs sets the inotify/fsnotify watch for every dir on branches
++ during it is in cache. When the event is notified, aufs registers a
++ function to kernel 'events' thread by schedule_work(). And the
++ function sets some special status to the cached aufs dentry and inode
++ private data. If they are not cached, then aufs has nothing to
++ do. When the same file is accessed through aufs (step 0-3) later,
++ aufs will detect the status and refresh all necessary data.
++ In this mode, aufs has to ignore the event which is fired by aufs
++ itself.
++3. No Extra Validation
++ This is the simplest test and doesn't add any additional revalidation
++ test, and skip therevalidatin in step 4. It is useful and improves
++ aufs performance when system surely hide the aufs branches from user,
++ by over-mounting something (or another method).
+diff --git a/Documentation/filesystems/aufs/design/04branch.txt b/Documentation/filesystems/aufs/design/04branch.txt
+new file mode 100644
+index 0000000..f85f3a8
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/04branch.txt
+@@ -0,0 +1,76 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Branch Manipulation
++
++Since aufs supports dynamic branch manipulation, ie. add/remove a branch
++and changing its permission/attribute, there are a lot of works to do.
++
++
++Add a Branch
++----------------------------------------------------------------------
++o Confirm the adding dir exists outside of aufs, including loopback
++ mount.
++- and other various attributes...
++o Initialize the xino file and whiteout bases if necessary.
++ See struct.txt.
++
++o Check the owner/group/mode of the directory
++ When the owner/group/mode of the adding directory differs from the
++ existing branch, aufs issues a warning because it may impose a
++ security risk.
++ For example, when a upper writable branch has a world writable empty
++ top directory, a malicious user can create any files on the writable
++ branch directly, like copy-up and modify manually. If something like
++ /etc/{passwd,shadow} exists on the lower readonly branch but the upper
++ writable branch, and the writable branch is world-writable, then a
++ malicious guy may create /etc/passwd on the writable branch directly
++ and the infected file will be valid in aufs.
++ I am afraid it can be a security issue, but nothing to do except
++ producing a warning.
++
++
++Delete a Branch
++----------------------------------------------------------------------
++o Confirm the deleting branch is not busy
++ To be general, there is one merit to adopt "remount" interface to
++ manipulate branches. It is to discard caches. At deleting a branch,
++ aufs checks the still cached (and connected) dentries and inodes. If
++ there are any, then they are all in-use. An inode without its
++ corresponding dentry can be alive alone (for example, inotify/fsnotify case).
++
++ For the cached one, aufs checks whether the same named entry exists on
++ other branches.
++ If the cached one is a directory, because aufs provides a merged view
++ to users, as long as one dir is left on any branch aufs can show the
++ dir to users. In this case, the branch can be removed from aufs.
++ Otherwise aufs rejects deleting the branch.
++
++ If any file on the deleting branch is opened by aufs, then aufs
++ rejects deleting.
++
++
++Modify the Permission of a Branch
++----------------------------------------------------------------------
++o Re-initialize or remove the xino file and whiteout bases if necessary.
++ See struct.txt.
++
++o rw --> ro: Confirm the modifying branch is not busy
++ Aufs rejects the request if any of these conditions are true.
++ - a file on the branch is mmap-ed.
++ - a regular file on the branch is opened for write and there is no
++ same named entry on the upper branch.
+diff --git a/Documentation/filesystems/aufs/design/05wbr_policy.txt b/Documentation/filesystems/aufs/design/05wbr_policy.txt
+new file mode 100644
+index 0000000..2bb8e58
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/05wbr_policy.txt
+@@ -0,0 +1,65 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Policies to Select One among Multiple Writable Branches
++----------------------------------------------------------------------
++When the number of writable branch is more than one, aufs has to decide
++the target branch for file creation or copy-up. By default, the highest
++writable branch which has the parent (or ancestor) dir of the target
++file is chosen (top-down-parent policy).
++By user's request, aufs implements some other policies to select the
++writable branch, for file creation two policies, round-robin and
++most-free-space policies. For copy-up three policies, top-down-parent,
++bottom-up-parent and bottom-up policies.
++
++As expected, the round-robin policy selects the branch in circular. When
++you have two writable branches and creates 10 new files, 5 files will be
++created for each branch. mkdir(2) systemcall is an exception. When you
++create 10 new directories, all will be created on the same branch.
++And the most-free-space policy selects the one which has most free
++space among the writable branches. The amount of free space will be
++checked by aufs internally, and users can specify its time interval.
++
++The policies for copy-up is more simple,
++top-down-parent is equivalent to the same named on in create policy,
++bottom-up-parent selects the writable branch where the parent dir
++exists and the nearest upper one from the copyup-source,
++bottom-up selects the nearest upper writable branch from the
++copyup-source, regardless the existence of the parent dir.
++
++There are some rules or exceptions to apply these policies.
++- If there is a readonly branch above the policy-selected branch and
++ the parent dir is marked as opaque (a variation of whiteout), or the
++ target (creating) file is whiteout-ed on the upper readonly branch,
++ then the result of the policy is ignored and the target file will be
++ created on the nearest upper writable branch than the readonly branch.
++- If there is a writable branch above the policy-selected branch and
++ the parent dir is marked as opaque or the target file is whiteouted
++ on the branch, then the result of the policy is ignored and the target
++ file will be created on the highest one among the upper writable
++ branches who has diropq or whiteout. In case of whiteout, aufs removes
++ it as usual.
++- link(2) and rename(2) systemcalls are exceptions in every policy.
++ They try selecting the branch where the source exists as possible
++ since copyup a large file will take long time. If it can't be,
++ ie. the branch where the source exists is readonly, then they will
++ follow the copyup policy.
++- There is an exception for rename(2) when the target exists.
++ If the rename target exists, aufs compares the index of the branches
++ where the source and the target exists and selects the higher
++ one. If the selected branch is readonly, then aufs follows the
++ copyup policy.
+diff --git a/Documentation/filesystems/aufs/design/06mmap.txt b/Documentation/filesystems/aufs/design/06mmap.txt
+new file mode 100644
+index 0000000..55524d6
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/06mmap.txt
+@@ -0,0 +1,47 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++mmap(2) -- File Memory Mapping
++----------------------------------------------------------------------
++In aufs, the file-mapped pages are handled by a branch fs directly, no
++interaction with aufs. It means aufs_mmap() calls the branch fs's
++->mmap().
++This approach is simple and good, but there is one problem.
++Under /proc, several entries show the mmap-ped files by its path (with
++device and inode number), and the printed path will be the path on the
++branch fs's instead of virtual aufs's.
++This is not a problem in most cases, but some utilities lsof(1) (and its
++user) may expect the path on aufs.
++
++To address this issue, aufs adds a new member called vm_prfile in struct
++vm_area_struct (and struct vm_region). The original vm_file points to
++the file on the branch fs in order to handle everything correctly as
++usual. The new vm_prfile points to a virtual file in aufs, and the
++show-functions in procfs refers to vm_prfile if it is set.
++Also we need to maintain several other places where touching vm_file
++such like
++- fork()/clone() copies vma and the reference count of vm_file is
++ incremented.
++- merging vma maintains the ref count too.
++
++This is not a good approach. It just faking the printed path. But it
++leaves all behaviour around f_mapping unchanged. This is surely an
++advantage.
++Actually aufs had adopted another complicated approach which calls
++generic_file_mmap() and handles struct vm_operations_struct. In this
++approach, aufs met a hard problem and I could not solve it without
++switching the approach.
+diff --git a/Documentation/filesystems/aufs/design/07export.txt b/Documentation/filesystems/aufs/design/07export.txt
+new file mode 100644
+index 0000000..ecf42a4
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/07export.txt
+@@ -0,0 +1,59 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Export Aufs via NFS
++----------------------------------------------------------------------
++Here is an approach.
++- like xino/xib, add a new file 'xigen' which stores aufs inode
++ generation.
++- iget_locked(): initialize aufs inode generation for a new inode, and
++ store it in xigen file.
++- destroy_inode(): increment aufs inode generation and store it in xigen
++ file. it is necessary even if it is not unlinked, because any data of
++ inode may be changed by UDBA.
++- encode_fh(): for a root dir, simply return FILEID_ROOT. otherwise
++ build file handle by
++ + branch id (4 bytes)
++ + superblock generation (4 bytes)
++ + inode number (4 or 8 bytes)
++ + parent dir inode number (4 or 8 bytes)
++ + inode generation (4 bytes))
++ + return value of exportfs_encode_fh() for the parent on a branch (4
++ bytes)
++ + file handle for a branch (by exportfs_encode_fh())
++- fh_to_dentry():
++ + find the index of a branch from its id in handle, and check it is
++ still exist in aufs.
++ + 1st level: get the inode number from handle and search it in cache.
++ + 2nd level: if not found, get the parent inode number from handle and
++ search it in cache. and then open the parent dir, find the matching
++ inode number by vfs_readdir() and get its name, and call
++ lookup_one_len() for the target dentry.
++ + 3rd level: if the parent dir is not cached, call
++ exportfs_decode_fh() for a branch and get the parent on a branch,
++ build a pathname of it, convert it a pathname in aufs, call
++ path_lookup(). now aufs gets a parent dir dentry, then handle it as
++ the 2nd level.
++ + to open the dir, aufs needs struct vfsmount. aufs keeps vfsmount
++ for every branch, but not itself. to get this, (currently) aufs
++ searches in current->nsproxy->mnt_ns list. it may not be a good
++ idea, but I didn't get other approach.
++ + test the generation of the gotten inode.
++- every inode operation: they may get EBUSY due to UDBA. in this case,
++ convert it into ESTALE for NFSD.
++- readdir(): call lockdep_on/off() because filldir in NFSD calls
++ lookup_one_len(), vfs_getattr(), encode_fh() and others.
+diff --git a/Documentation/filesystems/aufs/design/08shwh.txt b/Documentation/filesystems/aufs/design/08shwh.txt
+new file mode 100644
+index 0000000..18b889c
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/08shwh.txt
+@@ -0,0 +1,53 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Show Whiteout Mode (shwh)
++----------------------------------------------------------------------
++Generally aufs hides the name of whiteouts. But in some cases, to show
++them is very useful for users. For instance, creating a new middle layer
++(branch) by merging existing layers.
++
++(borrowing aufs1 HOW-TO from a user, Michael Towers)
++When you have three branches,
++- Bottom: 'system', squashfs (underlying base system), read-only
++- Middle: 'mods', squashfs, read-only
++- Top: 'overlay', ram (tmpfs), read-write
++
++The top layer is loaded at boot time and saved at shutdown, to preserve
++the changes made to the system during the session.
++When larger changes have been made, or smaller changes have accumulated,
++the size of the saved top layer data grows. At this point, it would be
++nice to be able to merge the two overlay branches ('mods' and 'overlay')
++and rewrite the 'mods' squashfs, clearing the top layer and thus
++restoring save and load speed.
++
++This merging is simplified by the use of another aufs mount, of just the
++two overlay branches using the 'shwh' option.
++# mount -t aufs -o ro,shwh,br:/livesys/overlay=ro+wh:/livesys/mods=rr+wh \
++ aufs /livesys/merge_union
++
++A merged view of these two branches is then available at
++/livesys/merge_union, and the new feature is that the whiteouts are
++visible!
++Note that in 'shwh' mode the aufs mount must be 'ro', which will disable
++writing to all branches. Also the default mode for all branches is 'ro'.
++It is now possible to save the combined contents of the two overlay
++branches to a new squashfs, e.g.:
++# mksquashfs /livesys/merge_union /path/to/newmods.squash
++
++This new squashfs archive can be stored on the boot device and the
++initramfs will use it to replace the old one at the next boot.
+diff --git a/Documentation/filesystems/aufs/design/10dynop.txt b/Documentation/filesystems/aufs/design/10dynop.txt
+new file mode 100644
+index 0000000..49e9a53
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/10dynop.txt
+@@ -0,0 +1,47 @@
++
++# Copyright (C) 2010-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Dynamically customizable FS operations
++----------------------------------------------------------------------
++Generally FS operations (struct inode_operations, struct
++address_space_operations, struct file_operations, etc.) are defined as
++"static const", but it never means that FS have only one set of
++operation. Some FS have multiple sets of them. For instance, ext2 has
++three sets, one for XIP, for NOBH, and for normal.
++Since aufs overrides and redirects these operations, sometimes aufs has
++to change its behaviour according to the branch FS type. More imporantly
++VFS acts differently if a function (member in the struct) is set or
++not. It means aufs should have several sets of operations and select one
++among them according to the branch FS definition.
++
++In order to solve this problem and not to affect the behavour of VFS,
++aufs defines these operations dynamically. For instance, aufs defines
++aio_read function for struct file_operations, but it may not be set to
++the file_operations. When the branch FS doesn't have it, aufs doesn't
++set it to its file_operations while the function definition itself is
++still alive. So the behaviour of io_submit(2) will not change, and it
++will return an error when aio_read is not defined.
++
++The lifetime of these dynamically generated operation object is
++maintained by aufs branch object. When the branch is removed from aufs,
++the reference counter of the object is decremented. When it reaches
++zero, the dynamically generated operation object will be freed.
++
++This approach is designed to support AIO (io_submit), Direcit I/O and
++XIP mainly.
++Currently this approach is applied to file_operations and
++vm_operations_struct for regular files only.
+diff --git a/Documentation/filesystems/aufs/design/99plan.txt b/Documentation/filesystems/aufs/design/99plan.txt
+new file mode 100644
+index 0000000..a21f133
+--- /dev/null
++++ b/Documentation/filesystems/aufs/design/99plan.txt
+@@ -0,0 +1,96 @@
++
++# Copyright (C) 2005-2013 Junjiro R. Okajima
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++Plan
++
++Restoring some features which was implemented in aufs1.
++They were dropped in aufs2 in order to make source files simpler and
++easier to be reviewed.
++
++
++Test Only the Highest One for the Directory Permission (dirperm1 option)
++----------------------------------------------------------------------
++Let's try case study.
++- aufs has two branches, upper readwrite and lower readonly.
++ /au = /rw + /ro
++- "dirA" exists under /ro, but /rw. and its mode is 0700.
++- user invoked "chmod a+rx /au/dirA"
++- then "dirA" becomes world readable?
++
++In this case, /ro/dirA is still 0700 since it exists in readonly branch,
++or it may be a natively readonly filesystem. If aufs respects the lower
++branch, it should not respond readdir request from other users. But user
++allowed it by chmod. Should really aufs rejects showing the entries
++under /ro/dirA?
++
++To be honest, I don't have a best solution for this case. So I
++implemented 'dirperm1' and 'nodirperm1' option in aufs1, and leave it to
++users.
++When dirperm1 is specified, aufs checks only the highest one for the
++directory permission, and shows the entries. Otherwise, as usual, checks
++every dir existing on all branches and rejects the request.
++
++As a side effect, dirperm1 option improves the performance of aufs
++because the number of permission check is reduced.
++
++
++Being Another Aufs's Readonly Branch (robr)
++----------------------------------------------------------------------
++Aufs1 allows aufs to be another aufs's readonly branch.
++This feature was developed by a user's request. But it may not be used
++currecnly.
++
++
++Copy-up on Open (coo=)
++----------------------------------------------------------------------
++By default the internal copy-up is executed when it is really necessary.
++It is not done when a file is opened for writing, but when write(2) is
++done. Users who have many (over 100) branches want to know and analyse
++when and what file is copied-up. To insert a new upper branch which
++contains such files only may improve the performance of aufs.
++
++Aufs1 implemented "coo=none | leaf | all" option.
++
++
++Refresh the Opened File (refrof)
++----------------------------------------------------------------------
++This option is implemented in aufs1 but incomplete.
++
++When user reads from a file, he expects to get its latest filedata
++generally. If the file is removed and a new same named file is created,
++the content he gets is unchanged, ie. the unlinked filedata.
++
++Let's try case study again.
++- aufs has two branches.
++ /au = /rw + /ro
++- "fileA" exists under /ro, but /rw.
++- user opened "/au/fileA".
++- he or someone else inserts a branch (/new) between /rw and /ro.
++ /au = /rw + /new + /ro
++- the new branch has "fileA".
++- user reads from the opened "fileA"
++- which filedata should aufs return, from /ro or /new?
++
++Some people says it has to be "from /ro" and it is a semantics of Unix.
++The others say it should be "from /new" because the file is not removed
++and it is equivalent to the case of someone else modifies the file.
++
++Here again I don't have a best and final answer. I got an idea to
++implement 'refrof' and 'norefrof' option. When 'refrof' (REFResh the
++Opened File) is specified (by default), aufs returns the filedata from
++/new.
++Otherwise from /new.
+diff --git a/Documentation/filesystems/debugfs.txt b/Documentation/filesystems/debugfs.txt
+index 742cc06..ad7eb40 100644
+--- a/Documentation/filesystems/debugfs.txt
++++ b/Documentation/filesystems/debugfs.txt
+@@ -14,7 +14,10 @@ Debugfs is typically mounted with a command like:
+
+ mount -t debugfs none /sys/kernel/debug
+
+-(Or an equivalent /etc/fstab line).
++(Or an equivalent /etc/fstab line).
++The debugfs root directory is accessible only to the root user by
++default. To change access to the tree the "uid", "gid" and "mode" mount
++options can be used.
+
+ Note that the debugfs API is exported GPL-only to modules.
+
+diff --git a/Documentation/filesystems/overlayfs.txt b/Documentation/filesystems/overlayfs.txt
+new file mode 100644
+index 0000000..7161dc3
+--- /dev/null
++++ b/Documentation/filesystems/overlayfs.txt
+@@ -0,0 +1,199 @@
++Written by: Neil Brown
++
++Overlay Filesystem
++==================
++
++This document describes a prototype for a new approach to providing
++overlay-filesystem functionality in Linux (sometimes referred to as
++union-filesystems). An overlay-filesystem tries to present a
++filesystem which is the result over overlaying one filesystem on top
++of the other.
++
++The result will inevitably fail to look exactly like a normal
++filesystem for various technical reasons. The expectation is that
++many use cases will be able to ignore these differences.
++
++This approach is 'hybrid' because the objects that appear in the
++filesystem do not all appear to belong to that filesystem. In many
++cases an object accessed in the union will be indistinguishable
++from accessing the corresponding object from the original filesystem.
++This is most obvious from the 'st_dev' field returned by stat(2).
++
++While directories will report an st_dev from the overlay-filesystem,
++all non-directory objects will report an st_dev from the lower or
++upper filesystem that is providing the object. Similarly st_ino will
++only be unique when combined with st_dev, and both of these can change
++over the lifetime of a non-directory object. Many applications and
++tools ignore these values and will not be affected.
++
++Upper and Lower
++---------------
++
++An overlay filesystem combines two filesystems - an 'upper' filesystem
++and a 'lower' filesystem. When a name exists in both filesystems, the
++object in the 'upper' filesystem is visible while the object in the
++'lower' filesystem is either hidden or, in the case of directories,
++merged with the 'upper' object.
++
++It would be more correct to refer to an upper and lower 'directory
++tree' rather than 'filesystem' as it is quite possible for both
++directory trees to be in the same filesystem and there is no
++requirement that the root of a filesystem be given for either upper or
++lower.
++
++The lower filesystem can be any filesystem supported by Linux and does
++not need to be writable. The lower filesystem can even be another
++overlayfs. The upper filesystem will normally be writable and if it
++is it must support the creation of trusted.* extended attributes, and
++must provide valid d_type in readdir responses, at least for symbolic
++links - so NFS is not suitable.
++
++A read-only overlay of two read-only filesystems may use any
++filesystem type.
++
++Directories
++-----------
++
++Overlaying mainly involved directories. If a given name appears in both
++upper and lower filesystems and refers to a non-directory in either,
++then the lower object is hidden - the name refers only to the upper
++object.
++
++Where both upper and lower objects are directories, a merged directory
++is formed.
++
++At mount time, the two directories given as mount options are combined
++into a merged directory:
++
++ mount -t overlayfs overlayfs -olowerdir=/lower,upperdir=/upper /overlay
++
++Then whenever a lookup is requested in such a merged directory, the
++lookup is performed in each actual directory and the combined result
++is cached in the dentry belonging to the overlay filesystem. If both
++actual lookups find directories, both are stored and a merged
++directory is created, otherwise only one is stored: the upper if it
++exists, else the lower.
++
++Only the lists of names from directories are merged. Other content
++such as metadata and extended attributes are reported for the upper
++directory only. These attributes of the lower directory are hidden.
++
++whiteouts and opaque directories
++--------------------------------
++
++In order to support rm and rmdir without changing the lower
++filesystem, an overlay filesystem needs to record in the upper filesystem
++that files have been removed. This is done using whiteouts and opaque
++directories (non-directories are always opaque).
++
++The overlay filesystem uses extended attributes with a
++"trusted.overlay." prefix to record these details.
++
++A whiteout is created as a symbolic link with target
++"(overlay-whiteout)" and with xattr "trusted.overlay.whiteout" set to "y".
++When a whiteout is found in the upper level of a merged directory, any
++matching name in the lower level is ignored, and the whiteout itself
++is also hidden.
++
++A directory is made opaque by setting the xattr "trusted.overlay.opaque"
++to "y". Where the upper filesystem contains an opaque directory, any
++directory in the lower filesystem with the same name is ignored.
++
++readdir
++-------
++
++When a 'readdir' request is made on a merged directory, the upper and
++lower directories are each read and the name lists merged in the
++obvious way (upper is read first, then lower - entries that already
++exist are not re-added). This merged name list is cached in the
++'struct file' and so remains as long as the file is kept open. If the
++directory is opened and read by two processes at the same time, they
++will each have separate caches. A seekdir to the start of the
++directory (offset 0) followed by a readdir will cause the cache to be
++discarded and rebuilt.
++
++This means that changes to the merged directory do not appear while a
++directory is being read. This is unlikely to be noticed by many
++programs.
++
++seek offsets are assigned sequentially when the directories are read.
++Thus if
++ - read part of a directory
++ - remember an offset, and close the directory
++ - re-open the directory some time later
++ - seek to the remembered offset
++
++there may be little correlation between the old and new locations in
++the list of filenames, particularly if anything has changed in the
++directory.
++
++Readdir on directories that are not merged is simply handled by the
++underlying directory (upper or lower).
++
++
++Non-directories
++---------------
++
++Objects that are not directories (files, symlinks, device-special
++files etc.) are presented either from the upper or lower filesystem as
++appropriate. When a file in the lower filesystem is accessed in a way
++the requires write-access, such as opening for write access, changing
++some metadata etc., the file is first copied from the lower filesystem
++to the upper filesystem (copy_up). Note that creating a hard-link
++also requires copy_up, though of course creation of a symlink does
++not.
++
++The copy_up may turn out to be unnecessary, for example if the file is
++opened for read-write but the data is not modified.
++
++The copy_up process first makes sure that the containing directory
++exists in the upper filesystem - creating it and any parents as
++necessary. It then creates the object with the same metadata (owner,
++mode, mtime, symlink-target etc.) and then if the object is a file, the
++data is copied from the lower to the upper filesystem. Finally any
++extended attributes are copied up.
++
++Once the copy_up is complete, the overlay filesystem simply
++provides direct access to the newly created file in the upper
++filesystem - future operations on the file are barely noticed by the
++overlay filesystem (though an operation on the name of the file such as
++rename or unlink will of course be noticed and handled).
++
++
++Non-standard behavior
++---------------------
++
++The copy_up operation essentially creates a new, identical file and
++moves it over to the old name. The new file may be on a different
++filesystem, so both st_dev and st_ino of the file may change.
++
++Any open files referring to this inode will access the old data and
++metadata. Similarly any file locks obtained before copy_up will not
++apply to the copied up file.
++
++On a file is opened with O_RDONLY fchmod(2), fchown(2), futimesat(2)
++and fsetxattr(2) will fail with EROFS.
++
++If a file with multiple hard links is copied up, then this will
++"break" the link. Changes will not be propagated to other names
++referring to the same inode.
++
++Symlinks in /proc/PID/ and /proc/PID/fd which point to a non-directory
++object in overlayfs will not contain vaid absolute paths, only
++relative paths leading up to the filesystem's root. This will be
++fixed in the future.
++
++Some operations are not atomic, for example a crash during copy_up or
++rename will leave the filesystem in an inconsitent state. This will
++be addressed in the future.
++
++Changes to underlying filesystems
++---------------------------------
++
++Offline changes, when the overlay is not mounted, are allowed to either
++the upper or the lower trees.
++
++Changes to the underlying filesystems while part of a mounted overlay
++filesystem are not allowed. If the underlying filesystem is changed,
++the behavior of the overlay is undefined, though it will not result in
++a crash or deadlock.
+diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
+index 404a097..d0b7a48 100644
+--- a/Documentation/filesystems/proc.txt
++++ b/Documentation/filesystems/proc.txt
+@@ -41,6 +41,8 @@ Table of Contents
+ 3.5 /proc//mountinfo - Information about mounts
+ 3.6 /proc//comm & /proc//task//comm
+
++ 4 Configuring procfs
++ 4.1 Mount options
+
+ ------------------------------------------------------------------------------
+ Preface
+@@ -1542,3 +1544,40 @@ a task to set its own or one of its thread siblings comm value. The comm value
+ is limited in size compared to the cmdline value, so writing anything longer
+ then the kernel's TASK_COMM_LEN (currently 16 chars) will result in a truncated
+ comm value.
++
++
++------------------------------------------------------------------------------
++Configuring procfs
++------------------------------------------------------------------------------
++
++4.1 Mount options
++---------------------
++
++The following mount options are supported:
++
++ hidepid= Set /proc// access mode.
++ gid= Set the group authorized to learn processes information.
++
++hidepid=0 means classic mode - everybody may access all /proc// directories
++(default).
++
++hidepid=1 means users may not access any /proc// directories but their
++own. Sensitive files like cmdline, sched*, status are now protected against
++other users. This makes it impossible to learn whether any user runs
++specific program (given the program doesn't reveal itself by its behaviour).
++As an additional bonus, as /proc//cmdline is unaccessible for other users,
++poorly written programs passing sensitive information via program arguments are
++now protected against local eavesdroppers.
++
++hidepid=2 means hidepid=1 plus all /proc// will be fully invisible to other
++users. It doesn't mean that it hides a fact whether a process with a specific
++pid value exists (it can be learned by other means, e.g. by "kill -0 $PID"),
++but it hides process' uid and gid, which may be learned by stat()'ing
++/proc// otherwise. It greatly complicates an intruder's task of gathering
++information about running processes, whether some daemon runs with elevated
++privileges, whether other user runs some sensitive program, whether other users
++run any program at all, etc.
++
++gid= defines a group authorized to learn processes information otherwise
++prohibited by hidepid=. If you use some daemon like identd which needs to learn
++information about processes information, just add identd to this group.
+diff --git a/Documentation/hwmon/emc2305 b/Documentation/hwmon/emc2305
+new file mode 100644
+index 0000000..4de033b
+--- /dev/null
++++ b/Documentation/hwmon/emc2305
+@@ -0,0 +1,33 @@
++Kernel driver emc2305
++=====================
++
++Supported chips:
++ * SMSC EMC2305, EMC2303, EMC2302, EMC2301
++ Adresses scanned: I2C 0x2c, 0x2d, 0x2e, 0x2f, 0x4c, 0x4d
++ Prefixes: 'emc2305', 'emc2303', 'emc2302', 'emc2301'
++ Datasheet: Publicly available at the SMSC website :
++ http://www.smsc.com/Products/Thermal_and_Power_Management/Fan_Controllers
++
++Authors:
++ Reinhard Pfau, Guntermann & Drunck GmbH
++
++Description
++-----------
++
++The SMSC EMC2305 is a fan controller for up to 5 fans.
++The EMC2303 has the same functionality but supports only up to 3 fans.
++
++The EMC2302 supports 2 fans and the EMC2301 1 fan. These chips support less
++possible I2C addresses.
++
++Fan rotation speeds are reported in RPM.
++The driver supports the RPM based PWM control to keep a fan at a desired speed.
++To enable this function for a fan, write 3 to pwm_enable and the desired
++fan speed to fan_target.
++
++
++Devicetree
++----------
++
++Configuration is also possible via devicetree:
++Documentation/devicetree/bindings/hwmon/emc2305.txt
+diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87
+index 6f496a5..23b7def 100644
+--- a/Documentation/hwmon/it87
++++ b/Documentation/hwmon/it87
+@@ -26,6 +26,10 @@ Supported chips:
+ Prefix: 'it8721'
+ Addresses scanned: from Super I/O config space (8 I/O ports)
+ Datasheet: Not publicly available
++ * IT8728F
++ Prefix: 'it8728'
++ Addresses scanned: from Super I/O config space (8 I/O ports)
++ Datasheet: Not publicly available
+ * SiS950 [clone of IT8705F]
+ Prefix: 'it87'
+ Addresses scanned: from Super I/O config space (8 I/O ports)
+@@ -71,7 +75,7 @@ Description
+ -----------
+
+ This driver implements support for the IT8705F, IT8712F, IT8716F,
+-IT8718F, IT8720F, IT8721F, IT8726F, IT8758E and SiS950 chips.
++IT8718F, IT8720F, IT8721F, IT8726F, IT8728F, IT8758E and SiS950 chips.
+
+ These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
+ joysticks and other miscellaneous stuff. For hardware monitoring, they
+@@ -105,6 +109,9 @@ The IT8726F is just bit enhanced IT8716F with additional hardware
+ for AMD power sequencing. Therefore the chip will appear as IT8716F
+ to userspace applications.
+
++The IT8728F is considered compatible with the IT8721F, until a datasheet
++becomes available (hopefully.)
++
+ Temperatures are measured in degrees Celsius. An alarm is triggered once
+ when the Overtemperature Shutdown limit is crossed.
+
+@@ -121,8 +128,8 @@ alarm is triggered if the voltage has crossed a programmable minimum or
+ maximum limit. Note that minimum in this case always means 'closest to
+ zero'; this is important for negative voltage measurements. All voltage
+ inputs can measure voltages between 0 and 4.08 volts, with a resolution of
+-0.016 volt (except IT8721F/IT8758E: 0.012 volt.) The battery voltage in8 does
+-not have limit registers.
++0.016 volt (except IT8721F/IT8758E and IT8728F: 0.012 volt.) The battery
++voltage in8 does not have limit registers.
+
+ On the IT8721F/IT8758E, some voltage inputs are internal and scaled inside
+ the chip (in7, in8 and optionally in3). The driver handles this transparently
+diff --git a/Documentation/input/alps.txt b/Documentation/input/alps.txt
+new file mode 100644
+index 0000000..ab5478f
+--- /dev/null
++++ b/Documentation/input/alps.txt
+@@ -0,0 +1,75 @@
++ALPS Touchpad Protocol
++----------------------
++
++Introduction
++------------
++
++Currently the ALPS touchpad driver supports two protocol versions in use by
++ALPS touchpads, the "old" and "new" protocol versions. Fundamentally these
++differ only in the format of their event packets (in reality many features may
++be found on new protocol devices that aren't found on the old protocol
++devices, but these are handled transparently as feature differences rather
++than protocol differences).
++
++Detection
++---------
++
++All ALPS touchpads should respond to the "E6 report" command sequence:
++E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
++00-00-64.
++
++If the E6 report is successful, the touchpad model is identified using the "E7
++report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
++matched against known models in the alps_model_data_array.
++
++Packet Format
++-------------
++
++In the following tables, the following notation us used.
++
++ CAPITALS = stick, miniscules = touchpad
++
++?'s can have different meanings on different models, such as wheel rotation,
++extra buttons, stick buttons on a dualpoint, etc.
++
++PS/2 packet format
++------------------
++
++ byte 0: 0 0 YSGN XSGN 1 M R L
++ byte 1: X7 X6 X5 X4 X3 X2 X1 X0
++ byte 2: Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
++
++Note that the device never signals overflow condition.
++
++ALPS Absolute Mode - Old Format
++-------------------------------
++
++ byte 0: 1 0 0 0 1 x9 x8 x7
++ byte 1: 0 x6 x5 x4 x3 x2 x1 x0
++ byte 2: 0 ? ? l r ? fin ges
++ byte 3: 0 ? ? ? ? y9 y8 y7
++ byte 4: 0 y6 y5 y4 y3 y2 y1 y0
++ byte 5: 0 z6 z5 z4 z3 z2 z1 z0
++
++ALPS Absolute Mode - New Format
++-------------------------------
++
++ byte 0: 1 ? ? ? 1 ? ? ?
++ byte 1: 0 x6 x5 x4 x3 x2 x1 x0
++ byte 2: 0 x10 x9 x8 x7 ? fin ges
++ byte 3: 0 y9 y8 y7 1 M R L
++ byte 4: 0 y6 y5 y4 y3 y2 y1 y0
++ byte 5: 0 z6 z5 z4 z3 z2 z1 z0
++
++Dualpoint device -- interleaved packet format
++---------------------------------------------
++
++ byte 0: 1 1 0 0 1 1 1 1
++ byte 1: 0 x6 x5 x4 x3 x2 x1 x0
++ byte 2: 0 x10 x9 x8 x7 0 fin ges
++ byte 3: 0 0 YSGN XSGN 1 1 1 1
++ byte 4: X7 X6 X5 X4 X3 X2 X1 X0
++ byte 5: Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
++ byte 6: 0 y9 y8 y7 1 m r l
++ byte 7: 0 y6 y5 y4 y3 y2 y1 y0
++ byte 8: 0 z6 z5 z4 z3 z2 z1 z0
+diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
+index f0001eb..5455bd4 100644
+--- a/Documentation/kernel-parameters.txt
++++ b/Documentation/kernel-parameters.txt
+@@ -446,8 +446,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
+ ccw_timeout_log [S390]
+ See Documentation/s390/CommonIO for details.
+
+- cgroup_disable= [KNL] Disable a particular controller
+- Format: {name of the controller(s) to disable}
++ cgroup_disable= [KNL] Disable/enable a particular controller
++ cgroup_enable= Format: {name of the controller(s) to disable/enable}
+ {Currently supported controllers - "memory"}
+
+ checkreqprot [SELINUX] Set initial checkreqprot flag value.
+@@ -2197,6 +2197,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
+
+ default: off.
+
++ printk.always_kmsg_dump=
++ Trigger kmsg_dump for cases other than kernel oops or
++ panics
++ Format: (1/Y/y=enable, 0/N/n=disable)
++ default: disabled
++
+ printk.time= Show timing data prefixed to each printk message line
+ Format: (1/Y/y=enable, 0/N/n=disable)
+
+diff --git a/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt b/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt
+deleted file mode 100644
+index 256c2c9..0000000
+--- a/Documentation/netlabel/draft-ietf-cipso-ipsecurity-01.txt
++++ /dev/null
+@@ -1,791 +0,0 @@
+-IETF CIPSO Working Group
+-16 July, 1992
+-
+-
+-
+- COMMERCIAL IP SECURITY OPTION (CIPSO 2.2)
+-
+-
+-
+-1. Status
+-
+-This Internet Draft provides the high level specification for a Commercial
+-IP Security Option (CIPSO). This draft reflects the version as approved by
+-the CIPSO IETF Working Group. Distribution of this memo is unlimited.
+-
+-This document is an Internet Draft. Internet Drafts are working documents
+-of the Internet Engineering Task Force (IETF), its Areas, and its Working
+-Groups. Note that other groups may also distribute working documents as
+-Internet Drafts.
+-
+-Internet Drafts are draft documents valid for a maximum of six months.
+-Internet Drafts may be updated, replaced, or obsoleted by other documents
+-at any time. It is not appropriate to use Internet Drafts as reference
+-material or to cite them other than as a "working draft" or "work in
+-progress."
+-
+-Please check the I-D abstract listing contained in each Internet Draft
+-directory to learn the current status of this or any other Internet Draft.
+-
+-
+-
+-
+-2. Background
+-
+-Currently the Internet Protocol includes two security options. One of
+-these options is the DoD Basic Security Option (BSO) (Type 130) which allows
+-IP datagrams to be labeled with security classifications. This option
+-provides sixteen security classifications and a variable number of handling
+-restrictions. To handle additional security information, such as security
+-categories or compartments, another security option (Type 133) exists and
+-is referred to as the DoD Extended Security Option (ESO). The values for
+-the fixed fields within these two options are administered by the Defense
+-Information Systems Agency (DISA).
+-
+-Computer vendors are now building commercial operating systems with
+-mandatory access controls and multi-level security. These systems are
+-no longer built specifically for a particular group in the defense or
+-intelligence communities. They are generally available commercial systems
+-for use in a variety of government and civil sector environments.
+-
+-The small number of ESO format codes can not support all the possible
+-applications of a commercial security option. The BSO and ESO were
+-designed to only support the United States DoD. CIPSO has been designed
+-to support multiple security policies. This Internet Draft provides the
+-format and procedures required to support a Mandatory Access Control
+-security policy. Support for additional security policies shall be
+-defined in future RFCs.
+-
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 1]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-
+-3. CIPSO Format
+-
+-Option type: 134 (Class 0, Number 6, Copy on Fragmentation)
+-Option length: Variable
+-
+-This option permits security related information to be passed between
+-systems within a single Domain of Interpretation (DOI). A DOI is a
+-collection of systems which agree on the meaning of particular values
+-in the security option. An authority that has been assigned a DOI
+-identifier will define a mapping between appropriate CIPSO field values
+-and their human readable equivalent. This authority will distribute that
+-mapping to hosts within the authority's domain. These mappings may be
+-sensitive, therefore a DOI authority is not required to make these
+-mappings available to anyone other than the systems that are included in
+-the DOI.
+-
+-This option MUST be copied on fragmentation. This option appears at most
+-once in a datagram. All multi-octet fields in the option are defined to be
+-transmitted in network byte order. The format of this option is as follows:
+-
+-+----------+----------+------//------+-----------//---------+
+-| 10000110 | LLLLLLLL | DDDDDDDDDDDD | TTTTTTTTTTTTTTTTTTTT |
+-+----------+----------+------//------+-----------//---------+
+-
+- TYPE=134 OPTION DOMAIN OF TAGS
+- LENGTH INTERPRETATION
+-
+-
+- Figure 1. CIPSO Format
+-
+-
+-3.1 Type
+-
+-This field is 1 octet in length. Its value is 134.
+-
+-
+-3.2 Length
+-
+-This field is 1 octet in length. It is the total length of the option
+-including the type and length fields. With the current IP header length
+-restriction of 40 octets the value of this field MUST not exceed 40.
+-
+-
+-3.3 Domain of Interpretation Identifier
+-
+-This field is an unsigned 32 bit integer. The value 0 is reserved and MUST
+-not appear as the DOI identifier in any CIPSO option. Implementations
+-should assume that the DOI identifier field is not aligned on any particular
+-byte boundary.
+-
+-To conserve space in the protocol, security levels and categories are
+-represented by numbers rather than their ASCII equivalent. This requires
+-a mapping table within CIPSO hosts to map these numbers to their
+-corresponding ASCII representations. Non-related groups of systems may
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 2]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-have their own unique mappings. For example, one group of systems may
+-use the number 5 to represent Unclassified while another group may use the
+-number 1 to represent that same security level. The DOI identifier is used
+-to identify which mapping was used for the values within the option.
+-
+-
+-3.4 Tag Types
+-
+-A common format for passing security related information is necessary
+-for interoperability. CIPSO uses sets of "tags" to contain the security
+-information relevant to the data in the IP packet. Each tag begins with
+-a tag type identifier followed by the length of the tag and ends with the
+-actual security information to be passed. All multi-octet fields in a tag
+-are defined to be transmitted in network byte order. Like the DOI
+-identifier field in the CIPSO header, implementations should assume that
+-all tags, as well as fields within a tag, are not aligned on any particular
+-octet boundary. The tag types defined in this document contain alignment
+-bytes to assist alignment of some information, however alignment can not
+-be guaranteed if CIPSO is not the first IP option.
+-
+-CIPSO tag types 0 through 127 are reserved for defining standard tag
+-formats. Their definitions will be published in RFCs. Tag types whose
+-identifiers are greater than 127 are defined by the DOI authority and may
+-only be meaningful in certain Domains of Interpretation. For these tag
+-types, implementations will require the DOI identifier as well as the tag
+-number to determine the security policy and the format associated with the
+-tag. Use of tag types above 127 are restricted to closed networks where
+-interoperability with other networks will not be an issue. Implementations
+-that support a tag type greater than 127 MUST support at least one DOI that
+-requires only tag types 1 to 127.
+-
+-Tag type 0 is reserved. Tag types 1, 2, and 5 are defined in this
+-Internet Draft. Types 3 and 4 are reserved for work in progress.
+-The standard format for all current and future CIPSO tags is shown below:
+-
+-+----------+----------+--------//--------+
+-| TTTTTTTT | LLLLLLLL | IIIIIIIIIIIIIIII |
+-+----------+----------+--------//--------+
+- TAG TAG TAG
+- TYPE LENGTH INFORMATION
+-
+- Figure 2: Standard Tag Format
+-
+-In the three tag types described in this document, the length and count
+-restrictions are based on the current IP limitation of 40 octets for all
+-IP options. If the IP header is later expanded, then the length and count
+-restrictions specified in this document may increase to use the full area
+-provided for IP options.
+-
+-
+-3.4.1 Tag Type Classes
+-
+-Tag classes consist of tag types that have common processing requirements
+-and support the same security policy. The three tags defined in this
+-Internet Draft belong to the Mandatory Access Control (MAC) Sensitivity
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 3]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-class and support the MAC Sensitivity security policy.
+-
+-
+-3.4.2 Tag Type 1
+-
+-This is referred to as the "bit-mapped" tag type. Tag type 1 is included
+-in the MAC Sensitivity tag type class. The format of this tag type is as
+-follows:
+-
+-+----------+----------+----------+----------+--------//---------+
+-| 00000001 | LLLLLLLL | 00000000 | LLLLLLLL | CCCCCCCCCCCCCCCCC |
+-+----------+----------+----------+----------+--------//---------+
+-
+- TAG TAG ALIGNMENT SENSITIVITY BIT MAP OF
+- TYPE LENGTH OCTET LEVEL CATEGORIES
+-
+- Figure 3. Tag Type 1 Format
+-
+-
+-3.4.2.1 Tag Type
+-
+-This field is 1 octet in length and has a value of 1.
+-
+-
+-3.4.2.2 Tag Length
+-
+-This field is 1 octet in length. It is the total length of the tag type
+-including the type and length fields. With the current IP header length
+-restriction of 40 bytes the value within this field is between 4 and 34.
+-
+-
+-3.4.2.3 Alignment Octet
+-
+-This field is 1 octet in length and always has the value of 0. Its purpose
+-is to align the category bitmap field on an even octet boundary. This will
+-speed many implementations including router implementations.
+-
+-
+-3.4.2.4 Sensitivity Level
+-
+-This field is 1 octet in length. Its value is from 0 to 255. The values
+-are ordered with 0 being the minimum value and 255 representing the maximum
+-value.
+-
+-
+-3.4.2.5 Bit Map of Categories
+-
+-The length of this field is variable and ranges from 0 to 30 octets. This
+-provides representation of categories 0 to 239. The ordering of the bits
+-is left to right or MSB to LSB. For example category 0 is represented by
+-the most significant bit of the first byte and category 15 is represented
+-by the least significant bit of the second byte. Figure 4 graphically
+-shows this ordering. Bit N is binary 1 if category N is part of the label
+-for the datagram, and bit N is binary 0 if category N is not part of the
+-label. Except for the optimized tag 1 format described in the next section,
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 4]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-minimal encoding SHOULD be used resulting in no trailing zero octets in the
+-category bitmap.
+-
+- octet 0 octet 1 octet 2 octet 3 octet 4 octet 5
+- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX . . .
+-bit 01234567 89111111 11112222 22222233 33333333 44444444
+-number 012345 67890123 45678901 23456789 01234567
+-
+- Figure 4. Ordering of Bits in Tag 1 Bit Map
+-
+-
+-3.4.2.6 Optimized Tag 1 Format
+-
+-Routers work most efficiently when processing fixed length fields. To
+-support these routers there is an optimized form of tag type 1. The format
+-does not change. The only change is to the category bitmap which is set to
+-a constant length of 10 octets. Trailing octets required to fill out the 10
+-octets are zero filled. Ten octets, allowing for 80 categories, was chosen
+-because it makes the total length of the CIPSO option 20 octets. If CIPSO
+-is the only option then the option will be full word aligned and additional
+-filler octets will not be required.
+-
+-
+-3.4.3 Tag Type 2
+-
+-This is referred to as the "enumerated" tag type. It is used to describe
+-large but sparsely populated sets of categories. Tag type 2 is in the MAC
+-Sensitivity tag type class. The format of this tag type is as follows:
+-
+-+----------+----------+----------+----------+-------------//-------------+
+-| 00000010 | LLLLLLLL | 00000000 | LLLLLLLL | CCCCCCCCCCCCCCCCCCCCCCCCCC |
+-+----------+----------+----------+----------+-------------//-------------+
+-
+- TAG TAG ALIGNMENT SENSITIVITY ENUMERATED
+- TYPE LENGTH OCTET LEVEL CATEGORIES
+-
+- Figure 5. Tag Type 2 Format
+-
+-
+-3.4.3.1 Tag Type
+-
+-This field is one octet in length and has a value of 2.
+-
+-
+-3.4.3.2 Tag Length
+-
+-This field is 1 octet in length. It is the total length of the tag type
+-including the type and length fields. With the current IP header length
+-restriction of 40 bytes the value within this field is between 4 and 34.
+-
+-
+-3.4.3.3 Alignment Octet
+-
+-This field is 1 octet in length and always has the value of 0. Its purpose
+-is to align the category field on an even octet boundary. This will
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 5]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-speed many implementations including router implementations.
+-
+-
+-3.4.3.4 Sensitivity Level
+-
+-This field is 1 octet in length. Its value is from 0 to 255. The values
+-are ordered with 0 being the minimum value and 255 representing the
+-maximum value.
+-
+-
+-3.4.3.5 Enumerated Categories
+-
+-In this tag, categories are represented by their actual value rather than
+-by their position within a bit field. The length of each category is 2
+-octets. Up to 15 categories may be represented by this tag. Valid values
+-for categories are 0 to 65534. Category 65535 is not a valid category
+-value. The categories MUST be listed in ascending order within the tag.
+-
+-
+-3.4.4 Tag Type 5
+-
+-This is referred to as the "range" tag type. It is used to represent
+-labels where all categories in a range, or set of ranges, are included
+-in the sensitivity label. Tag type 5 is in the MAC Sensitivity tag type
+-class. The format of this tag type is as follows:
+-
+-+----------+----------+----------+----------+------------//-------------+
+-| 00000101 | LLLLLLLL | 00000000 | LLLLLLLL | Top/Bottom | Top/Bottom |
+-+----------+----------+----------+----------+------------//-------------+
+-
+- TAG TAG ALIGNMENT SENSITIVITY CATEGORY RANGES
+- TYPE LENGTH OCTET LEVEL
+-
+- Figure 6. Tag Type 5 Format
+-
+-
+-3.4.4.1 Tag Type
+-
+-This field is one octet in length and has a value of 5.
+-
+-
+-3.4.4.2 Tag Length
+-
+-This field is 1 octet in length. It is the total length of the tag type
+-including the type and length fields. With the current IP header length
+-restriction of 40 bytes the value within this field is between 4 and 34.
+-
+-
+-3.4.4.3 Alignment Octet
+-
+-This field is 1 octet in length and always has the value of 0. Its purpose
+-is to align the category range field on an even octet boundary. This will
+-speed many implementations including router implementations.
+-
+-
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 6]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-3.4.4.4 Sensitivity Level
+-
+-This field is 1 octet in length. Its value is from 0 to 255. The values
+-are ordered with 0 being the minimum value and 255 representing the maximum
+-value.
+-
+-
+-3.4.4.5 Category Ranges
+-
+-A category range is a 4 octet field comprised of the 2 octet index of the
+-highest numbered category followed by the 2 octet index of the lowest
+-numbered category. These range endpoints are inclusive within the range of
+-categories. All categories within a range are included in the sensitivity
+-label. This tag may contain a maximum of 7 category pairs. The bottom
+-category endpoint for the last pair in the tag MAY be omitted and SHOULD be
+-assumed to be 0. The ranges MUST be non-overlapping and be listed in
+-descending order. Valid values for categories are 0 to 65534. Category
+-65535 is not a valid category value.
+-
+-
+-3.4.5 Minimum Requirements
+-
+-A CIPSO implementation MUST be capable of generating at least tag type 1 in
+-the non-optimized form. In addition, a CIPSO implementation MUST be able
+-to receive any valid tag type 1 even those using the optimized tag type 1
+-format.
+-
+-
+-4. Configuration Parameters
+-
+-The configuration parameters defined below are required for all CIPSO hosts,
+-gateways, and routers that support multiple sensitivity labels. A CIPSO
+-host is defined to be the origination or destination system for an IP
+-datagram. A CIPSO gateway provides IP routing services between two or more
+-IP networks and may be required to perform label translations between
+-networks. A CIPSO gateway may be an enhanced CIPSO host or it may just
+-provide gateway services with no end system CIPSO capabilities. A CIPSO
+-router is a dedicated IP router that routes IP datagrams between two or more
+-IP networks.
+-
+-An implementation of CIPSO on a host MUST have the capability to reject a
+-datagram for reasons that the information contained can not be adequately
+-protected by the receiving host or if acceptance may result in violation of
+-the host or network security policy. In addition, a CIPSO gateway or router
+-MUST be able to reject datagrams going to networks that can not provide
+-adequate protection or may violate the network's security policy. To
+-provide this capability the following minimal set of configuration
+-parameters are required for CIPSO implementations:
+-
+-HOST_LABEL_MAX - This parameter contains the maximum sensitivity label that
+-a CIPSO host is authorized to handle. All datagrams that have a label
+-greater than this maximum MUST be rejected by the CIPSO host. This
+-parameter does not apply to CIPSO gateways or routers. This parameter need
+-not be defined explicitly as it can be implicitly derived from the
+-PORT_LABEL_MAX parameters for the associated interfaces.
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 7]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-
+-HOST_LABEL_MIN - This parameter contains the minimum sensitivity label that
+-a CIPSO host is authorized to handle. All datagrams that have a label less
+-than this minimum MUST be rejected by the CIPSO host. This parameter does
+-not apply to CIPSO gateways or routers. This parameter need not be defined
+-explicitly as it can be implicitly derived from the PORT_LABEL_MIN
+-parameters for the associated interfaces.
+-
+-PORT_LABEL_MAX - This parameter contains the maximum sensitivity label for
+-all datagrams that may exit a particular network interface port. All
+-outgoing datagrams that have a label greater than this maximum MUST be
+-rejected by the CIPSO system. The label within this parameter MUST be
+-less than or equal to the label within the HOST_LABEL_MAX parameter. This
+-parameter does not apply to CIPSO hosts that support only one network port.
+-
+-PORT_LABEL_MIN - This parameter contains the minimum sensitivity label for
+-all datagrams that may exit a particular network interface port. All
+-outgoing datagrams that have a label less than this minimum MUST be
+-rejected by the CIPSO system. The label within this parameter MUST be
+-greater than or equal to the label within the HOST_LABEL_MIN parameter.
+-This parameter does not apply to CIPSO hosts that support only one network
+-port.
+-
+-PORT_DOI - This parameter is used to assign a DOI identifier value to a
+-particular network interface port. All CIPSO labels within datagrams
+-going out this port MUST use the specified DOI identifier. All CIPSO
+-hosts and gateways MUST support either this parameter, the NET_DOI
+-parameter, or the HOST_DOI parameter.
+-
+-NET_DOI - This parameter is used to assign a DOI identifier value to a
+-particular IP network address. All CIPSO labels within datagrams destined
+-for the particular IP network MUST use the specified DOI identifier. All
+-CIPSO hosts and gateways MUST support either this parameter, the PORT_DOI
+-parameter, or the HOST_DOI parameter.
+-
+-HOST_DOI - This parameter is used to assign a DOI identifier value to a
+-particular IP host address. All CIPSO labels within datagrams destined for
+-the particular IP host will use the specified DOI identifier. All CIPSO
+-hosts and gateways MUST support either this parameter, the PORT_DOI
+-parameter, or the NET_DOI parameter.
+-
+-This list represents the minimal set of configuration parameters required
+-to be compliant. Implementors are encouraged to add to this list to
+-provide enhanced functionality and control. For example, many security
+-policies may require both incoming and outgoing datagrams be checked against
+-the port and host label ranges.
+-
+-
+-4.1 Port Range Parameters
+-
+-The labels represented by the PORT_LABEL_MAX and PORT_LABEL_MIN parameters
+-MAY be in CIPSO or local format. Some CIPSO systems, such as routers, may
+-want to have the range parameters expressed in CIPSO format so that incoming
+-labels do not have to be converted to a local format before being compared
+-against the range. If multiple DOIs are supported by one of these CIPSO
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 8]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-systems then multiple port range parameters would be needed, one set for
+-each DOI supported on a particular port.
+-
+-The port range will usually represent the total set of labels that may
+-exist on the logical network accessed through the corresponding network
+-interface. It may, however, represent a subset of these labels that are
+-allowed to enter the CIPSO system.
+-
+-
+-4.2 Single Label CIPSO Hosts
+-
+-CIPSO implementations that support only one label are not required to
+-support the parameters described above. These limited implementations are
+-only required to support a NET_LABEL parameter. This parameter contains
+-the CIPSO label that may be inserted in datagrams that exit the host. In
+-addition, the host MUST reject any incoming datagram that has a label which
+-is not equivalent to the NET_LABEL parameter.
+-
+-
+-5. Handling Procedures
+-
+-This section describes the processing requirements for incoming and
+-outgoing IP datagrams. Just providing the correct CIPSO label format
+-is not enough. Assumptions will be made by one system on how a
+-receiving system will handle the CIPSO label. Wrong assumptions may
+-lead to non-interoperability or even a security incident. The
+-requirements described below represent the minimal set needed for
+-interoperability and that provide users some level of confidence.
+-Many other requirements could be added to increase user confidence,
+-however at the risk of restricting creativity and limiting vendor
+-participation.
+-
+-
+-5.1 Input Procedures
+-
+-All datagrams received through a network port MUST have a security label
+-associated with them, either contained in the datagram or assigned to the
+-receiving port. Without this label the host, gateway, or router will not
+-have the information it needs to make security decisions. This security
+-label will be obtained from the CIPSO if the option is present in the
+-datagram. See section 4.1.2 for handling procedures for unlabeled
+-datagrams. This label will be compared against the PORT (if appropriate)
+-and HOST configuration parameters defined in section 3.
+-
+-If any field within the CIPSO option, such as the DOI identifier, is not
+-recognized the IP datagram is discarded and an ICMP "parameter problem"
+-(type 12) is generated and returned. The ICMP code field is set to "bad
+-parameter" (code 0) and the pointer is set to the start of the CIPSO field
+-that is unrecognized.
+-
+-If the contents of the CIPSO are valid but the security label is
+-outside of the configured host or port label range, the datagram is
+-discarded and an ICMP "destination unreachable" (type 3) is generated
+-and returned. The code field of the ICMP is set to "communication with
+-destination network administratively prohibited" (code 9) or to
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 9]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-"communication with destination host administratively prohibited"
+-(code 10). The value of the code field used is dependent upon whether
+-the originator of the ICMP message is acting as a CIPSO host or a CIPSO
+-gateway. The recipient of the ICMP message MUST be able to handle either
+-value. The same procedure is performed if a CIPSO can not be added to an
+-IP packet because it is too large to fit in the IP options area.
+-
+-If the error is triggered by receipt of an ICMP message, the message
+-is discarded and no response is permitted (consistent with general ICMP
+-processing rules).
+-
+-
+-5.1.1 Unrecognized tag types
+-
+-The default condition for any CIPSO implementation is that an
+-unrecognized tag type MUST be treated as a "parameter problem" and
+-handled as described in section 4.1. A CIPSO implementation MAY allow
+-the system administrator to identify tag types that may safely be
+-ignored. This capability is an allowable enhancement, not a
+-requirement.
+-
+-
+-5.1.2 Unlabeled Packets
+-
+-A network port may be configured to not require a CIPSO label for all
+-incoming datagrams. For this configuration a CIPSO label must be
+-assigned to that network port and associated with all unlabeled IP
+-datagrams. This capability might be used for single level networks or
+-networks that have CIPSO and non-CIPSO hosts and the non-CIPSO hosts
+-all operate at the same label.
+-
+-If a CIPSO option is required and none is found, the datagram is
+-discarded and an ICMP "parameter problem" (type 12) is generated and
+-returned to the originator of the datagram. The code field of the ICMP
+-is set to "option missing" (code 1) and the ICMP pointer is set to 134
+-(the value of the option type for the missing CIPSO option).
+-
+-
+-5.2 Output Procedures
+-
+-A CIPSO option MUST appear only once in a datagram. Only one tag type
+-from the MAC Sensitivity class MAY be included in a CIPSO option. Given
+-the current set of defined tag types, this means that CIPSO labels at
+-first will contain only one tag.
+-
+-All datagrams leaving a CIPSO system MUST meet the following condition:
+-
+- PORT_LABEL_MIN <= CIPSO label <= PORT_LABEL_MAX
+-
+-If this condition is not satisfied the datagram MUST be discarded.
+-If the CIPSO system only supports one port, the HOST_LABEL_MIN and the
+-HOST_LABEL_MAX parameters MAY be substituted for the PORT parameters in
+-the above condition.
+-
+-The DOI identifier to be used for all outgoing datagrams is configured by
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 10]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-the administrator. If port level DOI identifier assignment is used, then
+-the PORT_DOI configuration parameter MUST contain the DOI identifier to
+-use. If network level DOI assignment is used, then the NET_DOI parameter
+-MUST contain the DOI identifier to use. And if host level DOI assignment
+-is employed, then the HOST_DOI parameter MUST contain the DOI identifier
+-to use. A CIPSO implementation need only support one level of DOI
+-assignment.
+-
+-
+-5.3 DOI Processing Requirements
+-
+-A CIPSO implementation MUST support at least one DOI and SHOULD support
+-multiple DOIs. System and network administrators are cautioned to
+-ensure that at least one DOI is common within an IP network to allow for
+-broadcasting of IP datagrams.
+-
+-CIPSO gateways MUST be capable of translating a CIPSO option from one
+-DOI to another when forwarding datagrams between networks. For
+-efficiency purposes this capability is only a desired feature for CIPSO
+-routers.
+-
+-
+-5.4 Label of ICMP Messages
+-
+-The CIPSO label to be used on all outgoing ICMP messages MUST be equivalent
+-to the label of the datagram that caused the ICMP message. If the ICMP was
+-generated due to a problem associated with the original CIPSO label then the
+-following responses are allowed:
+-
+- a. Use the CIPSO label of the original IP datagram
+- b. Drop the original datagram with no return message generated
+-
+-In most cases these options will have the same effect. If you can not
+-interpret the label or if it is outside the label range of your host or
+-interface then an ICMP message with the same label will probably not be
+-able to exit the system.
+-
+-
+-6. Assignment of DOI Identifier Numbers =
+-
+-Requests for assignment of a DOI identifier number should be addressed to
+-the Internet Assigned Numbers Authority (IANA).
+-
+-
+-7. Acknowledgements
+-
+-Much of the material in this RFC is based on (and copied from) work
+-done by Gary Winiger of Sun Microsystems and published as Commercial
+-IP Security Option at the INTEROP 89, Commercial IPSO Workshop.
+-
+-
+-8. Author's Address
+-
+-To submit mail for distribution to members of the IETF CIPSO Working
+-Group, send mail to: cipso@wdl1.wdl.loral.com.
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 11]
+-
+-
+-
+-CIPSO INTERNET DRAFT 16 July, 1992
+-
+-
+-
+-
+-To be added to or deleted from this distribution, send mail to:
+-cipso-request@wdl1.wdl.loral.com.
+-
+-
+-9. References
+-
+-RFC 1038, "Draft Revised IP Security Option", M. St. Johns, IETF, January
+-1988.
+-
+-RFC 1108, "U.S. Department of Defense Security Options
+-for the Internet Protocol", Stephen Kent, IAB, 1 March, 1991.
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-Internet Draft, Expires 15 Jan 93 [PAGE 12]
+-
+-
+-
+diff --git a/Documentation/sysctl/fs.txt b/Documentation/sysctl/fs.txt
+index 88fd7f5..171c65a 100644
+--- a/Documentation/sysctl/fs.txt
++++ b/Documentation/sysctl/fs.txt
+@@ -32,6 +32,8 @@ Currently, these files are in /proc/sys/fs:
+ - nr_open
+ - overflowuid
+ - overflowgid
++- protected_hardlinks
++- protected_symlinks
+ - suid_dumpable
+ - super-max
+ - super-nr
+@@ -157,22 +159,68 @@ The default is 65534.
+
+ ==============================================================
+
++protected_hardlinks:
++
++A long-standing class of security issues is the hardlink-based
++time-of-check-time-of-use race, most commonly seen in world-writable
++directories like /tmp. The common method of exploitation of this flaw
++is to cross privilege boundaries when following a given hardlink (i.e. a
++root process follows a hardlink created by another user). Additionally,
++on systems without separated partitions, this stops unauthorized users
++from "pinning" vulnerable setuid/setgid files against being upgraded by
++the administrator, or linking to special files.
++
++When set to "0", hardlink creation behavior is unrestricted.
++
++When set to "1" hardlinks cannot be created by users if they do not
++already own the source file, or do not have read/write access to it.
++
++This protection is based on the restrictions in Openwall and grsecurity.
++
++==============================================================
++
++protected_symlinks:
++
++A long-standing class of security issues is the symlink-based
++time-of-check-time-of-use race, most commonly seen in world-writable
++directories like /tmp. The common method of exploitation of this flaw
++is to cross privilege boundaries when following a given symlink (i.e. a
++root process follows a symlink belonging to another user). For a likely
++incomplete list of hundreds of examples across the years, please see:
++http://cve.mitre.org/cgi-bin/cvekey.cgi?keyword=/tmp
++
++When set to "0", symlink following behavior is unrestricted.
++
++When set to "1" symlinks are permitted to be followed only when outside
++a sticky world-writable directory, or when the uid of the symlink and
++follower match, or when the directory owner matches the symlink's owner.
++
++This protection is based on the restrictions in Openwall and grsecurity.
++
++==============================================================
++
+ suid_dumpable:
+
+ This value can be used to query and set the core dump mode for setuid
+ or otherwise protected/tainted binaries. The modes are
+
+ 0 - (default) - traditional behaviour. Any process which has changed
+- privilege levels or is execute only will not be dumped
++ privilege levels or is execute only will not be dumped.
+ 1 - (debug) - all processes dump core when possible. The core dump is
+ owned by the current user and no security is applied. This is
+ intended for system debugging situations only. Ptrace is unchecked.
++ This is insecure as it allows regular users to examine the memory
++ contents of privileged processes.
+ 2 - (suidsafe) - any binary which normally would not be dumped is dumped
+- readable by root only. This allows the end user to remove
+- such a dump but not access it directly. For security reasons
+- core dumps in this mode will not overwrite one another or
+- other files. This mode is appropriate when administrators are
+- attempting to debug problems in a normal environment.
++ anyway, but only if the "core_pattern" kernel sysctl is set to
++ either a pipe handler or a fully qualified path. (For more details
++ on this limitation, see CVE-2006-2451.) This mode is appropriate
++ when administrators are attempting to debug problems in a normal
++ environment, and either have a core dump pipe handler that knows
++ to treat privileged core dumps with care, or specific directory
++ defined for catching core dumps. If a core dump happens without
++ a pipe handler or fully qualifid path, a message will be emitted
++ to syslog warning about the lack of a correct setting.
+
+ ==============================================================
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 8659eba..4ea868c 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1321,6 +1321,15 @@ W: http://atl1.sourceforge.net
+ S: Maintained
+ F: drivers/net/ethernet/atheros/
+
++ALX ETHERNET DRIVERS
++M: Cloud Ren
++M: Stevent Li
++M: Wu Ken
++M: David Liu
++L: nic-devel@qualcomm.com
++W: http://wireless.kernel.org/en/users/Drivers/ethernet/alx
++F: drivers/net/ethernet/atheros/alx/
++
+ ATM
+ M: Chas Williams
+ L: linux-atm-general@lists.sourceforge.net (moderated for non-subscribers)
+@@ -4901,6 +4910,13 @@ F: drivers/scsi/osd/
+ F: include/scsi/osd_*
+ F: fs/exofs/
+
++OVERLAYFS FILESYSTEM
++M: Miklos Szeredi
++L: linux-fsdevel@vger.kernel.org
++S: Supported
++F: fs/overlayfs/*
++F: Documentation/filesystems/overlayfs.txt
++
+ P54 WIRELESS DRIVER
+ M: Christian Lamparter
+ L: linux-wireless@vger.kernel.org
+@@ -6026,6 +6042,14 @@ S: Supported
+ F: Documentation/hwmon/emc2103
+ F: drivers/hwmon/emc2103.c
+
++SMSC EMC2305 HARDWARE MONITOR DRIVER
++M: Reinhard Pfau
++L: lm-sensors@lm-sensors.org
++S: Maintained
++F: Documentation/hwmon/emc2305
++F: Documentation/devicetree/bindings/hwmon/emc2305.txt
++F: drivers/hwmon/emc2305.c
++
+ SMSC SCH5627 HARDWARE MONITOR DRIVER
+ M: Hans de Goede
+ L: lm-sensors@lm-sensors.org
+diff --git a/Makefile b/Makefile
+index 9d5fea7..6013f6e 100644
+--- a/Makefile
++++ b/Makefile
+@@ -195,46 +195,6 @@ export KBUILD_BUILDHOST := $(SUBARCH)
+ ARCH ?= $(SUBARCH)
+ CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
+
+-# Architecture as present in compile.h
+-UTS_MACHINE := $(ARCH)
+-SRCARCH := $(ARCH)
+-
+-# Additional ARCH settings for x86
+-ifeq ($(ARCH),i386)
+- SRCARCH := x86
+-endif
+-ifeq ($(ARCH),x86_64)
+- SRCARCH := x86
+-endif
+-
+-# Additional ARCH settings for sparc
+-ifeq ($(ARCH),sparc32)
+- SRCARCH := sparc
+-endif
+-ifeq ($(ARCH),sparc64)
+- SRCARCH := sparc
+-endif
+-
+-# Additional ARCH settings for sh
+-ifeq ($(ARCH),sh64)
+- SRCARCH := sh
+-endif
+-
+-# Additional ARCH settings for tile
+-ifeq ($(ARCH),tilepro)
+- SRCARCH := tile
+-endif
+-ifeq ($(ARCH),tilegx)
+- SRCARCH := tile
+-endif
+-
+-# Where to locate arch specific headers
+-hdr-arch := $(SRCARCH)
+-
+-ifeq ($(ARCH),m68knommu)
+- hdr-arch := m68k
+-endif
+-
+ KCONFIG_CONFIG ?= .config
+ export KCONFIG_CONFIG
+
+@@ -354,6 +314,44 @@ CFLAGS_KERNEL =
+ AFLAGS_KERNEL =
+ CFLAGS_GCOV = -fprofile-arcs -ftest-coverage
+
++-include $(obj)/.kernelvariables
++
++# Architecture as present in compile.h
++UTS_MACHINE := $(ARCH)
++SRCARCH := $(ARCH)
++
++# Additional ARCH settings for x86
++ifeq ($(ARCH),i386)
++ SRCARCH := x86
++endif
++ifeq ($(ARCH),x86_64)
++ SRCARCH := x86
++endif
++
++# Additional ARCH settings for sparc
++ifeq ($(ARCH),sparc64)
++ SRCARCH := sparc
++endif
++
++# Additional ARCH settings for sh
++ifeq ($(ARCH),sh64)
++ SRCARCH := sh
++endif
++
++# Additional ARCH settings for tile
++ifeq ($(ARCH),tilepro)
++ SRCARCH := tile
++endif
++ifeq ($(ARCH),tilegx)
++ SRCARCH := tile
++endif
++
++# Where to locate arch specific headers
++hdr-arch := $(SRCARCH)
++
++ifeq ($(ARCH),m68knommu)
++ hdr-arch := m68k
++endif
+
+ # Use LINUXINCLUDE when you must reference the include/ directory.
+ # Needed to be compatible with the O= option
+@@ -978,7 +976,7 @@ endif
+ prepare2: prepare3 outputmakefile asm-generic
+
+ prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \
+- include/config/auto.conf
++ include/config/auto.conf include/generated/package.h
+ $(cmd_crmodverdir)
+
+ archprepare: archscripts prepare1 scripts_basic
+@@ -1010,12 +1008,25 @@ define filechk_version.h
+ echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))';)
+ endef
+
++ifneq ($(DISTRIBUTION_OFFICIAL_BUILD),)
++define filechk_package.h
++ echo \#define LINUX_PACKAGE_ID \" $(DISTRIBUTOR) $(DISTRIBUTION_VERSION)\"
++endef
++else
++define filechk_package.h
++ echo \#define LINUX_PACKAGE_ID \"\"
++endef
++endif
++
+ include/linux/version.h: $(srctree)/Makefile FORCE
+ $(call filechk,version.h)
+
+ include/generated/utsrelease.h: include/config/kernel.release FORCE
+ $(call filechk,utsrelease.h)
+
++include/generated/package.h: $(srctree)/Makefile FORCE
++ $(call filechk,package.h)
++
+ PHONY += headerdep
+ headerdep:
+ $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 082bd36..7a06e22 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -30,6 +30,7 @@ config ARM
+ select HAVE_SPARSE_IRQ
+ select GENERIC_IRQ_SHOW
+ select CPU_PM if (SUSPEND || CPU_IDLE)
++ select HAVE_BPF_JIT
+ help
+ The ARM series is a line of low-power-consumption RISC chip designs
+ licensed by ARM Ltd and targeted at embedded applications and
+@@ -161,6 +162,13 @@ config ARCH_HAS_CPUFREQ
+ config ARCH_HAS_CPU_IDLE_WAIT
+ def_bool y
+
++-config ARCH_SUPPORTS_BIG_ENDIAN
++ bool
++ default y if ARCH_IXP4XX
++ help
++ Internal node to specify the architecture can run in Big Endian
++ mode.
++
+ config GENERIC_HWEIGHT
+ bool
+ default y
+@@ -978,6 +986,30 @@ config ARCH_ZYNQ
+ select USE_OF
+ help
+ Support for Xilinx Zynq ARM Cortex A9 Platform
++
++config ARCH_IPROC
++ bool "Broadcom ARMv7 iProc boards"
++ depends on MMU
++ select CPU_V7
++ select HAVE_CLK
++ select HAVE_SMP
++ select HAVE_MACH_CLKDEV
++ select COMMON_CLKDEV
++ select CLKDEV_LOOKUP
++ select ARM_GIC
++ select HAVE_ARM_SCU
++ select GENERIC_CLOCKEVENTS_BUILD
++ select GENERIC_CLOCKEVENTS
++ select PCI
++ select GENERIC_GPIO
++ select ARCH_REQUIRE_GPIOLIB
++ select CACHE_L2X0
++ select ARM_AMBA
++ select ARCH_HAS_CPUFREQ
++ select MULTI_IRQ_HANDLER
++ help
++ This is a common family of Broadcom Cortex A9 based boards
++
+ endchoice
+
+ #
+@@ -1013,6 +1045,8 @@ source "arch/arm/mach-iop33x/Kconfig"
+
+ source "arch/arm/mach-iop13xx/Kconfig"
+
++source "arch/arm/plat-iproc/Kconfig"
++
+ source "arch/arm/mach-ixp4xx/Kconfig"
+
+ source "arch/arm/mach-ixp2000/Kconfig"
+@@ -1023,6 +1057,8 @@ source "arch/arm/mach-kirkwood/Kconfig"
+
+ source "arch/arm/mach-ks8695/Kconfig"
+
++source "arch/arm/mach-iproc/Kconfig"
++
+ source "arch/arm/mach-lpc32xx/Kconfig"
+
+ source "arch/arm/mach-msm/Kconfig"
+@@ -1452,7 +1488,8 @@ config SMP
+ depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
++ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q || \
++ ARCH_IPROC
+ depends on MMU
+ select USE_GENERIC_SMP_HELPERS
+ select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index 362c7ca..e11f8ee 100644
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -198,6 +198,7 @@ machine-$(CONFIG_MACH_SPEAR310) := spear3xx
+ machine-$(CONFIG_MACH_SPEAR320) := spear3xx
+ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
+ machine-$(CONFIG_ARCH_ZYNQ) := zynq
++machine-$(CONFIG_MACH_IPROC) := iproc
+
+ # Platform directory name. This list is sorted alphanumerically
+ # by CONFIG_* macro name.
+@@ -214,6 +215,7 @@ plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
+ plat-$(CONFIG_PLAT_S5P) := s5p samsung
+ plat-$(CONFIG_PLAT_SPEAR) := spear
+ plat-$(CONFIG_PLAT_VERSATILE) := versatile
++plat-$(CONFIG_ARCH_IPROC) := iproc
+
+ ifeq ($(CONFIG_ARCH_EBSA110),y)
+ # This is what happens if you forget the IOCS16 line.
+@@ -255,6 +257,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
+
+ # If we have a machine-specific directory, then include it in the build.
+ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
++core-y += arch/arm/net/
+ core-y += $(machdirs) $(platdirs)
+
+ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 8c57359..6bfca86 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -18,6 +18,7 @@
+ * 100% relocatable. Any attempt to do so will result in a crash.
+ * Please select one of the following when turning on debugging.
+ */
++#define DEBUG 1
+ #ifdef DEBUG
+
+ #if defined(CONFIG_DEBUG_ICEDCC)
+diff --git a/arch/arm/boot/dts/accton_as4610_54.dts b/arch/arm/boot/dts/accton_as4610_54.dts
+new file mode 100644
+index 0000000..9276c0a
+--- /dev/null
++++ b/arch/arm/boot/dts/accton_as4610_54.dts
+@@ -0,0 +1,250 @@
++/*
++ * Accton AS4610 54 Device Tree Source
++ *
++ * Copyright 2015, Cumulus Networks, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++/dts-v1/;
++/include/ "helix4.dtsi"
++
++/ {
++ model = "accton,as4610_54";
++ compatible = "accton,as4610_54";
++
++ aliases {
++ serial0 = &uart0;
++ i2c-controller0 = &i2c0;
++ i2c-controller1 = &i2c1;
++ };
++
++ memory {
++ reg = <0x61000000 0x7f000000>;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x00>;
++ };
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x01>;
++ };
++ };
++
++ localbus@1c000000 {
++ #address-cells = <0x2>;
++ #size-cells = <0x1>;
++ /* NAND Flash */
++ ranges = <
++ 0x0 0x0 0x0 0x1c000000 0x00120000
++ 0x1 0x0 0x0 0x1c120000 0x00040000
++ >;
++
++ flash@0,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "cfi-flash";
++ reg = <0x0 0x0 0x02000000>;
++ byteswap;
++
++ partition@0 {
++ /* uboot */
++ reg = <0x00000000 0x00100000>;
++ label = "uboot";
++ };
++ partition@1 {
++ /* uboot-env */
++ reg = <0x00100000 0x00100000>;
++ label = "uboot-env";
++ env_size = <0x2000>;
++ };
++ partition@2 {
++ /* board_eeprom */
++ reg = <0x00200000 0x00100000>;
++ label = "board_eeprom";
++ };
++ partition@3 {
++ /* shmoo */
++ reg = <0x00300000 0x00100000>;
++ label = "shmoo";
++ };
++ partition@4 {
++ /* onie */
++ reg = <0x00400000 0x00800000>;
++ label = "onie";
++ };
++ partition@5 {
++ /* open */
++ reg = <0x00c00000 0x03c00000>;
++ label = "open";
++ };
++ partition@6 {
++ /* open2 */
++ reg = <0x04800000 0x7d000000>;
++ label = "open2";
++ };
++ partition@7 {
++ /* diag */
++ reg = <0xfec00000 0x01000000>;
++ label = "diag";
++ };
++ };
++ };
++
++ i2c0: i2c@18038000 {
++ compatible = "iproc-smb";
++ reg = <0x18038000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = < 127 >;
++ clock-frequency = <400000>;
++ cpld@1,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "accton,as4610-54-cpld";
++ label = "cpld";
++ reg = <0x30>;
++ };
++ };
++
++ i2c1: i2c@1803b000 {
++ compatible = "iproc-smb";
++ reg = <0x1803b000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = < 128 >;
++ clock-frequency = <100000>;
++ mux@70 {
++ compatible = "ti,pca9548";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ deselect-on-exit;
++
++ // SFP+ 1
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port49";
++ };
++ };
++
++ // SFP+ 2
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port50";
++ };
++ };
++
++ // SFP+ 3
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port51";
++ };
++ };
++
++ // SFP+ 4
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port52";
++ };
++ };
++
++ // QSFP+ STK1
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ };
++ };
++
++ // QSFP+ STK2
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ };
++ };
++
++ // PSU EEPROM
++ i2c@6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ psu_eeprom@50 {
++ compatible = "at,24c02";
++ reg = <0x50>;
++ label = "psu1_eeprom";
++ read-only;
++ };
++ psu_eeprom@51 {
++ compatible = "at,24c02";
++ reg = <0x51>;
++ label = "psu2_eeprom";
++ read-only;
++ };
++ };
++
++ i2c@7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++
++ temp@48 {
++ compatible = "nxp,lm77";
++ reg = <0x48>;
++ };
++
++ rtc@68 {
++ /* Actually M41T11 */
++ compatible = "dallas,ds1307";
++ reg = <0x68>;
++ };
++
++ board_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "board_eeprom";
++ };
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/dni_3448p.dts b/arch/arm/boot/dts/dni_3448p.dts
+new file mode 100644
+index 0000000..29ce09c
+--- /dev/null
++++ b/arch/arm/boot/dts/dni_3448p.dts
+@@ -0,0 +1,166 @@
++/*
++ * Delta Networks, Inc. 3448p Device Tree Source
++ *
++ * Copyright 2015, Cumulus Networks, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++/dts-v1/;
++/include/ "helix4.dtsi"
++
++/ {
++ model = "dni,3448p";
++ compatible = "dni,dni_3448p";
++
++ memory {
++ reg = <0x61000000 0x3f000000>;
++ };
++
++ aliases {
++ serial0 = &uart0;
++ i2c-controller0 = &i2c0;
++ i2c-controller1 = &i2c1;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x00>;
++ };
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x01>;
++ };
++ };
++
++ localbus@1c000000 {
++ #address-cells = <0x2>;
++ #size-cells = <0x1>;
++ /* NAND Flash */
++ ranges = <
++ 0x0 0x0 0x0 0x1c000000 0x00120000
++ 0x1 0x0 0x0 0x1c120000 0x00040000
++ >;
++
++ flash@0,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "cfi-flash";
++ reg = <0x0 0x0 0x02000000>;
++ byteswap;
++
++ partition@0 {
++ /* uboot */
++ reg = <0x00000000 0x00100000>;
++ label = "uboot";
++ };
++ partition@1 {
++ /* uboot-env */
++ reg = <0x00100000 0x00400000>;
++ label = "uboot-env";
++ env_size = <0x10000>;
++ };
++ partition@2 {
++ /* vpd */
++ reg = <0x00500000 0x00200000>;
++ label = "vpd";
++ };
++ partition@3 {
++ /* shmoo */
++ reg = <0x00700000 0x00200000>;
++ label = "shmoo";
++ };
++ partition@4 {
++ /* open */
++ reg = <0x00900000 0xf9500000>;
++ label = "open";
++ };
++ partition@5 {
++ /* onie */
++ reg = <0xf9e00000 0x00c00000>;
++ label = "onie";
++ };
++ partition@6 {
++ /* onie2 */
++ reg = <0xfaa00000 0x00c00000>;
++ label = "onie2";
++ };
++ partition@7 {
++ /* board_eeprom */
++ reg = <0xfb600000 0x00600000>;
++ label = "board_eeprom";
++ };
++ partition@8 {
++ /* diags */
++ reg = <0xfbc00000 0x02000000>;
++ label = "diag";
++ };
++ partition@9 {
++ /* diags2 */
++ reg = <0xfdc00000 0x02000000>;
++ label = "diag2";
++ };
++ };
++ cpld@1,0 {
++ compatible = "dni,3448p-cpld";
++ reg = <0x1 0x0 0x00040000>;
++ };
++ };
++
++ i2c0: i2c@18038000 {
++ compatible = "iproc-smb";
++ reg = <0x18038000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <0x0 127 0x0>;
++ clock-frequency = <100000>;
++ rtc@68 {
++ compatible = "stm,m41st85";
++ reg = <0x68>;
++ };
++ tmon@49 {
++ compatible = "ti,tmp75";
++ reg = <0x49>;
++ };
++ tmon@4a {
++ compatible = "ti,tmp75";
++ reg = <0x4a>;
++ };
++ CPLD1@1,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "dni,3448p-cpld";
++ label = "cpld";
++ reg = <0x28>;
++ };
++ };
++
++ i2c1: i2c@1803b000 {
++ compatible = "iproc-smb";
++ reg = <0x1803b000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <0x0 128 0x0>;
++ clock-frequency = <100000>;
++
++ fan@2c {
++ compatible = "maxim,max6639";
++ reg = <0x2c>;
++ };
++ psumux@01 {
++ compatible = "3448p-psu-mux";
++ reg = <0x01>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/helix4.dtsi b/arch/arm/boot/dts/helix4.dtsi
+new file mode 100644
+index 0000000..1a7ce9e
+--- /dev/null
++++ b/arch/arm/boot/dts/helix4.dtsi
+@@ -0,0 +1,59 @@
++/include/ "skeleton.dtsi"
++
++/ {
++ interrupt-parent = <&gic>;
++
++ chipcommonA {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x18000000 0x00001000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ uart0: serial@0300 {
++ compatible = "ns16550";
++ reg = <0x0300 0x100>;
++ interrupts = <123>;
++ clock-frequency = <100000000>;
++ status = "enabled";
++ };
++ };
++
++ mpcore {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x19020000 0x00003000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ scu@0000 {
++ compatible = "arm,cortex-a9-scu";
++ reg = <0x0000 0x100>;
++ };
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x0100 0x100>;
++ };
++
++ L2: cache-controller@2000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x2000 0x1000>;
++ cache-unified;
++ cache-level = <2>;
++ };
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ clk_periph: periph {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
+new file mode 100644
+index 0000000..a5376b8
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
+@@ -0,0 +1,24 @@
++/dts-v1/;
++
++/include/ "kirkwood.dtsi"
++
++/ {
++ model = "Globalscale Technologies Dreamplug";
++ compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
++
++ memory {
++ device_type = "memory";
++ reg = <0x00000000 0x20000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 earlyprintk";
++ };
++
++ ocp@f1000000 {
++ serial@12000 {
++ clock-frequency = <200000000>;
++ status = "ok";
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
+new file mode 100644
+index 0000000..1ba75d4
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
+@@ -0,0 +1,26 @@
++/dts-v1/;
++
++/include/ "kirkwood.dtsi"
++
++/ {
++ model = "Iomega Iconnect";
++ compatible = "iom,iconnect-1.1", "iom,iconnect", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
++
++ memory {
++ device_type = "memory";
++ reg = <0x00000000 0x10000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
++ linux,initrd-start = <0x4500040>;
++ linux,initrd-end = <0x4800000>;
++ };
++
++ ocp@f1000000 {
++ serial@12000 {
++ clock-frequency = <200000000>;
++ status = "ok";
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
+new file mode 100644
+index 0000000..3474ef8
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood.dtsi
+@@ -0,0 +1,36 @@
++/include/ "skeleton.dtsi"
++
++/ {
++ compatible = "mrvl,kirkwood";
++
++ ocp@f1000000 {
++ compatible = "simple-bus";
++ ranges = <0 0xf1000000 0x1000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ serial@12000 {
++ compatible = "ns16550a";
++ reg = <0x12000 0x100>;
++ reg-shift = <2>;
++ interrupts = <33>;
++ /* set clock-frequency in board dts */
++ status = "disabled";
++ };
++
++ serial@12100 {
++ compatible = "ns16550a";
++ reg = <0x12100 0x100>;
++ reg-shift = <2>;
++ interrupts = <34>;
++ /* set clock-frequency in board dts */
++ status = "disabled";
++ };
++
++ rtc@10300 {
++ compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
++ reg = <0x10300 0x20>;
++ interrupts = <53>;
++ };
++ };
++};
+diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
+index 410a546..46d9ae8 100644
+--- a/arch/arm/common/gic.c
++++ b/arch/arm/common/gic.c
+@@ -40,6 +40,8 @@
+ #include
+
+ #include
++#include
++#include
+ #include
+ #include
+
+@@ -215,6 +217,29 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
+ #define gic_set_wake NULL
+ #endif
+
++asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
++{
++ u32 irqstat, irqnr;
++
++ do {
++ irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
++ irqnr = irqstat & ~0x1c00;
++
++ if (likely(irqnr > 15 && irqnr < 1021)) {
++ handle_IRQ(irqnr, regs);
++ continue;
++ }
++ if (irqnr < 16) {
++ writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
++#ifdef CONFIG_SMP
++ do_IPI(irqnr, regs);
++#endif
++ continue;
++ }
++ break;
++ } while (1);
++}
++
+ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+ {
+ struct gic_chip_data *chip_data = irq_get_handler_data(irq);
+diff --git a/arch/arm/configs/iproc_defconfig b/arch/arm/configs/iproc_defconfig
+new file mode 100644
+index 0000000..c401047
+--- /dev/null
++++ b/arch/arm/configs/iproc_defconfig
+@@ -0,0 +1,2425 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 3.6.5 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_HAVE_IRQ_WORK=y
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_FHANDLE is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_GENERIC_HARDIRQS=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_KTIME_SCALAR=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_PREEMPT_RCU is not set
++CONFIG_RCU_FANOUT=32
++CONFIG_RCU_FANOUT_LEAF=16
++# CONFIG_RCU_FANOUT_EXACT is not set
++# CONFIG_RCU_FAST_NO_HZ is not set
++# CONFIG_TREE_RCU_TRACE is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CHECKPOINT_RESTORE is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_ROOT_UID=0
++CONFIG_INITRAMFS_ROOT_GID=0
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_INITRAMFS_COMPRESSION_NONE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++# CONFIG_ELF_CORE is not set
++# CONFIG_BASE_FULL is not set
++CONFIG_FUTEX=y
++# CONFIG_EPOLL is not set
++# CONFIG_SIGNALFD is not set
++# CONFIG_TIMERFD is not set
++# CONFIG_EVENTFD is not set
++# CONFIG_SHMEM is not set
++# CONFIG_AIO is not set
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_PCI_QUIRKS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_ATTRS=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_USE_GENERIC_SMP_HELPERS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=1
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_STOP_MACHINE=y
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++# CONFIG_INLINE_SPIN_TRYLOCK is not set
++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK is not set
++# CONFIG_INLINE_SPIN_LOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_READ_TRYLOCK is not set
++# CONFIG_INLINE_READ_LOCK is not set
++# CONFIG_INLINE_READ_LOCK_BH is not set
++# CONFIG_INLINE_READ_LOCK_IRQ is not set
++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
++CONFIG_INLINE_READ_UNLOCK=y
++# CONFIG_INLINE_READ_UNLOCK_BH is not set
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_WRITE_TRYLOCK is not set
++# CONFIG_INLINE_WRITE_LOCK is not set
++# CONFIG_INLINE_WRITE_LOCK_BH is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
++CONFIG_INLINE_WRITE_UNLOCK=y
++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCMRING is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CNS3XXX is not set
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_PRIMA2 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MXS is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_PICOXCELL is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_SHMOBILE is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_S5P64X0 is not set
++# CONFIG_ARCH_S5PC100 is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_U300 is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_NOMADIK is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_VT8500 is not set
++# CONFIG_ARCH_ZYNQ is not set
++CONFIG_ARCH_IPROC=y
++CONFIG_BCM_ZRELADDR=0x61008000
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++
++#
++# Broadcom IPROC architecture based implementations
++#
++# CONFIG_ARCH_NORTHSTAR is not set
++CONFIG_MACH_IPROC=y
++CONFIG_GP_TIMER_COMPARATOR_LOAD_DELAY=y
++CONFIG_IPROC_DCACHE_INVALIDATION=y
++# CONFIG_IPROC_TIMER_UNIT_TESTS is not set
++# CONFIG_IPROC_SW_RESET_RECORD is not set
++# CONFIG_BRCM_PROP_MODULES is not set
++# CONFIG_BCM_STM is not set
++CONFIG_BCM_PARAMS_PHYS=0x61000000
++CONFIG_BCM_RAM_BASE=0x60000000
++CONFIG_BCM_RAM_START_RESERVED_SIZE=0x200000
++
++#
++# Broadcom iProc Drivers
++#
++# CONFIG_IPROC_CCB_TIMER is not set
++# CONFIG_IPROC_RNG is not set
++CONFIG_IPROC_MDIO=y
++# CONFIG_IPROC_GSIO_SPI is not set
++# CONFIG_IPROC_SD is not set
++# CONFIG_IPROC_DMA is not set
++CONFIG_IPROC_GPIO=y
++CONFIG_IPROC_QSPI=y
++CONFIG_IPROC_QSPI_SINGLE_MODE=y
++# CONFIG_IPROC_QSPI_DUAL_MODE is not set
++# CONFIG_IPROC_QSPI_QUAD_MODE is not set
++CONFIG_IPROC_QSPI_MAX_HZ=62500000
++CONFIG_IPROC_MTD_NAND=y
++# CONFIG_IPROC_MTD_NAND_USE_JFFS2 is not set
++# CONFIG_IPROC_MTD_NOR is not set
++# CONFIG_IPROC_PMU is not set
++# CONFIG_IPROC_PWM is not set
++CONFIG_IPROC_USB2H=y
++CONFIG_USB_EHCI_BCM=y
++CONFIG_USB_OHCI_BCM=y
++# CONFIG_IPROC_USB3H is not set
++CONFIG_IPROC_USB2D=m
++CONFIG_IPROC_PCIE=y
++# CONFIG_IPROC_PCIE_AER is not set
++CONFIG_IPROC_GMAC=y
++
++#
++# Broadcom HND network devices
++#
++CONFIG_HND=y
++CONFIG_ET=y
++CONFIG_ET_47XX=y
++CONFIG_ET_ALL_PASSIVE_ON=y
++# CONFIG_ET_ALL_PASSIVE_RUNTIME is not set
++# CONFIG_BCM_CTF is not set
++# CONFIG_BCM_IPROC_GMAC_ACP is not set
++# CONFIG_WL_EMULATOR is not set
++# CONFIG_BCM57XX is not set
++# CONFIG_WL is not set
++# CONFIG_WL_USBAP is not set
++CONFIG_WL_AP="wlconfig_lx_router_ap"
++CONFIG_WL_AP_SDSTD="wlconfig_lx_router_ap_sdstd"
++CONFIG_WL_STA="wlconfig_lx_router_sta"
++CONFIG_WL_APSTA="wlconfig_lx_router_apsta"
++CONFIG_WL_AP_ONCHIP_G="wlconfig_lx_router_ap_1chipG"
++CONFIG_WL_STA_ONCHIP_G="wlconfig_lx_router_sta_1chipG"
++CONFIG_WL_HIGH="wlconfig_lx_router_high"
++# CONFIG_EMF is not set
++# CONFIG_IPROC_SND is not set
++CONFIG_IPROC_I2C=y
++# CONFIG_IPROC_SRA is not set
++# CONFIG_IPROC_TDM is not set
++
++#
++# Broadcom iProc GPL Drivers
++#
++# CONFIG_IPROC_SND_CODEC_WM8955 is not set
++# CONFIG_IPROC_SND_CODEC_WM8750 is not set
++CONFIG_IPROC_CCB_WDT=y
++
++#
++# iProc SoC based Machine types
++#
++# CONFIG_MACH_NS is not set
++# CONFIG_MACH_HX4 is not set
++# CONFIG_MACH_HR2 is not set
++# CONFIG_MACH_NSP is not set
++# CONFIG_MACH_KT2 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_SWP_EMULATE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_OUTER_CACHE=y
++CONFIG_OUTER_CACHE_SYNC=y
++CONFIG_CACHE_L2X0=y
++CONFIG_CACHE_PL310=y
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_ARM_NR_BANKS=8
++CONFIG_CPU_HAS_PMU=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_458693 is not set
++# CONFIG_ARM_ERRATA_460075 is not set
++# CONFIG_ARM_ERRATA_742230 is not set
++# CONFIG_ARM_ERRATA_742231 is not set
++# CONFIG_PL310_ERRATA_588369 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_PL310_ERRATA_727915 is not set
++# CONFIG_ARM_ERRATA_743622 is not set
++# CONFIG_ARM_ERRATA_751472 is not set
++# CONFIG_PL310_ERRATA_753970 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_PL310_ERRATA_769419 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++CONFIG_ARM_GIC=y
++
++#
++# Bus support
++#
++CONFIG_ARM_AMBA=y
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_ARCH_SUPPORTS_MSI=y
++CONFIG_PCI_MSI=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_SCU=y
++# CONFIG_ARM_ARCH_TIMER is not set
++CONFIG_HAVE_ARM_TWD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=4
++CONFIG_HOTPLUG_CPU=y
++CONFIG_LOCAL_TIMERS=y
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=100
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++# CONFIG_HIGHMEM is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_COMPACTION is not set
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_CLEANCACHE is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++# CONFIG_CC_STACKPROTECTOR is not set
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++
++#
++# Boot options
++#
++# CONFIG_USE_OF is not set
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttyS0,115200n8 maxcpus=2 mem=512M"
++CONFIG_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_CMDLINE_EXTEND is not set
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++# CONFIG_PM_RUNTIME is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++# CONFIG_XFRM_USER is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++# CONFIG_IP_FIB_TRIE_STATS is not set
++CONFIG_IP_MULTIPLE_TABLES=y
++# CONFIG_IP_ROUTE_MULTIPATH is not set
++# CONFIG_IP_ROUTE_VERBOSE is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_IP_MROUTE is not set
++CONFIG_ARPD=y
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_INET_DIAG is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_DEBUG=y
++CONFIG_NETFILTER_ADVANCED=y
++CONFIG_BRIDGE_NETFILTER=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_NETLINK=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_PROCFS=y
++# CONFIG_NF_CONNTRACK_EVENTS is not set
++# CONFIG_NF_CONNTRACK_TIMEOUT is not set
++# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++# CONFIG_NF_CONNTRACK_AMANDA is not set
++CONFIG_NF_CONNTRACK_FTP=y
++# CONFIG_NF_CONNTRACK_H323 is not set
++# CONFIG_NF_CONNTRACK_IRC is not set
++# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
++# CONFIG_NF_CONNTRACK_SNMP is not set
++# CONFIG_NF_CONNTRACK_PPTP is not set
++# CONFIG_NF_CONNTRACK_SANE is not set
++# CONFIG_NF_CONNTRACK_SIP is not set
++CONFIG_NF_CONNTRACK_TFTP=y
++# CONFIG_NF_CT_NETLINK is not set
++# CONFIG_NF_CT_NETLINK_TIMEOUT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set
++CONFIG_NETFILTER_TPROXY=y
++CONFIG_NETFILTER_XTABLES=y
++
++#
++# Xtables combined modules
++#
++CONFIG_NETFILTER_XT_MARK=y
++CONFIG_NETFILTER_XT_CONNMARK=y
++
++#
++# Xtables targets
++#
++# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
++# CONFIG_NETFILTER_XT_TARGET_CT is not set
++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
++CONFIG_NETFILTER_XT_TARGET_HL=y
++# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
++# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
++# CONFIG_NETFILTER_XT_TARGET_LOG is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
++# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
++# CONFIG_NETFILTER_XT_TARGET_TEE is not set
++# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
++# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
++# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
++
++#
++# Xtables matches
++#
++# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
++# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
++# CONFIG_NETFILTER_XT_MATCH_CPU is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
++CONFIG_NETFILTER_XT_MATCH_ECN=y
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
++CONFIG_NETFILTER_XT_MATCH_HL=y
++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
++# CONFIG_NETFILTER_XT_MATCH_OSF is not set
++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
++# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
++CONFIG_NETFILTER_XT_MATCH_STATE=y
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
++# CONFIG_NETFILTER_XT_MATCH_TIME is not set
++# CONFIG_NETFILTER_XT_MATCH_U32 is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++CONFIG_NF_DEFRAG_IPV4=y
++CONFIG_NF_CONNTRACK_IPV4=y
++CONFIG_NF_CONNTRACK_PROC_COMPAT=y
++CONFIG_IP_NF_QUEUE=y
++CONFIG_IP_NF_IPTABLES=y
++CONFIG_IP_NF_MATCH_AH=y
++CONFIG_IP_NF_MATCH_ECN=y
++# CONFIG_IP_NF_MATCH_RPFILTER is not set
++CONFIG_IP_NF_MATCH_TTL=y
++CONFIG_IP_NF_FILTER=y
++CONFIG_IP_NF_TARGET_REJECT=y
++CONFIG_IP_NF_TARGET_ULOG=y
++CONFIG_NF_NAT=y
++CONFIG_NF_NAT_NEEDED=y
++CONFIG_IP_NF_TARGET_MASQUERADE=y
++CONFIG_IP_NF_TARGET_NETMAP=y
++CONFIG_IP_NF_TARGET_REDIRECT=y
++CONFIG_NF_NAT_FTP=y
++# CONFIG_NF_NAT_IRC is not set
++CONFIG_NF_NAT_TFTP=y
++# CONFIG_NF_NAT_AMANDA is not set
++# CONFIG_NF_NAT_PPTP is not set
++# CONFIG_NF_NAT_H323 is not set
++# CONFIG_NF_NAT_SIP is not set
++CONFIG_IP_NF_MANGLE=y
++# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
++CONFIG_IP_NF_TARGET_ECN=y
++CONFIG_IP_NF_TARGET_TTL=y
++CONFIG_IP_NF_RAW=y
++CONFIG_IP_NF_ARPTABLES=y
++CONFIG_IP_NF_ARPFILTER=y
++CONFIG_IP_NF_ARP_MANGLE=y
++# CONFIG_BRIDGE_NF_EBTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++CONFIG_STP=y
++CONFIG_GARP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_IGMP_SNOOPING=y
++# CONFIG_NET_DSA is not set
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++# CONFIG_DECNET is not set
++CONFIG_LLC=y
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++CONFIG_FIB_RULES=y
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++CONFIG_HAVE_BPF_JIT=y
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++# CONFIG_DMA_SHARED_BUFFER is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++CONFIG_CMA_AREAS=7
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++CONFIG_MTD_M25P80=y
++CONFIG_M25PXX_USE_FAST_READ=y
++CONFIG_M25PXX_STAY_IN_3BYTE_MODE=y
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_DENALI is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_RESERVE=2
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_DA is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++
++#
++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
++#
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_BLK_DEV_SX8 is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_XIP=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_ATMEL_PWM is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1780 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_BMP085_I2C is not set
++# CONFIG_BMP085_SPI is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++CONFIG_SCSI_TGT=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_ST=y
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_SCSI_BNX2X_FCOE is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_DPT_I2O is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_LIBFCOE is not set
++# CONFIG_FCOE is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_FC is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_LPFC is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_DC390T is not set
++# CONFIG_SCSI_NSP32 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_SRP is not set
++# CONFIG_SCSI_BFA_FC is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++# CONFIG_I2O is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_MII is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++CONFIG_NET_VENDOR_AMD=y
++# CONFIG_AMD8111_ETH is not set
++# CONFIG_PCNET32 is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++CONFIG_NET_VENDOR_BROADCOM=y
++# CONFIG_B44 is not set
++# CONFIG_BNX2 is not set
++# CONFIG_CNIC is not set
++CONFIG_TIGON3=y
++# CONFIG_BNX2X is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CIRRUS=y
++# CONFIG_CS89x0 is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_FARADAY=y
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++CONFIG_NET_VENDOR_INTEL=y
++# CONFIG_E100 is not set
++# CONFIG_E1000 is not set
++CONFIG_E1000E=y
++# CONFIG_IGB is not set
++# CONFIG_IGBVF is not set
++# CONFIG_IXGB is not set
++# CONFIG_IXGBE is not set
++CONFIG_NET_VENDOR_I825XX=y
++# CONFIG_IP1000 is not set
++# CONFIG_JME is not set
++CONFIG_NET_VENDOR_MARVELL=y
++# CONFIG_SKGE is not set
++# CONFIG_SKY2 is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++CONFIG_NET_VENDOR_MICREL=y
++# CONFIG_KS8851 is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_KSZ884X_PCI is not set
++CONFIG_NET_VENDOR_MICROCHIP=y
++# CONFIG_ENC28J60 is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++CONFIG_NET_VENDOR_NATSEMI=y
++# CONFIG_NATSEMI is not set
++# CONFIG_NS83820 is not set
++CONFIG_NET_VENDOR_8390=y
++# CONFIG_AX88796 is not set
++# CONFIG_NE2K_PCI is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++CONFIG_NET_VENDOR_SEEQ=y
++# CONFIG_SEEQ8005 is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++CONFIG_NET_VENDOR_SMSC=y
++# CONFIG_SMC91X is not set
++# CONFIG_EPIC100 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_SMSC9420 is not set
++CONFIG_NET_VENDOR_STMICRO=y
++# CONFIG_STMMAC_ETH is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TLAN is not set
++CONFIG_NET_VENDOR_VIA=y
++# CONFIG_VIA_RHINE is not set
++# CONFIG_VIA_VELOCITY is not set
++CONFIG_NET_VENDOR_WIZNET=y
++# CONFIG_WIZNET_W5100 is not set
++# CONFIG_WIZNET_W5300 is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_ATMEL is not set
++# CONFIG_PRISM54 is not set
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_HOSTAP is not set
++# CONFIG_WL_TI is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_PCI=y
++CONFIG_SERIAL_8250_NR_UARTS=2
++CONFIG_SERIAL_8250_RUNTIME_UARTS=2
++CONFIG_SERIAL_8250_EXTENDED=y
++# CONFIG_SERIAL_8250_MANY_PORTS is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++# CONFIG_SERIAL_8250_EM is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++# CONFIG_SERIAL_AMBA_PL011 is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX3107 is not set
++# CONFIG_SERIAL_MFD_HSU is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_TIMERIOMEM is not set
++# CONFIG_HW_RANDOM_ATMEL is not set
++# CONFIG_HW_RANDOM_EXYNOS is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_MUX is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_INTEL_MID is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_PL022 is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_DESIGNWARE is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++
++#
++# Enable Device Drivers -> PPS to see the PTP clock options.
++#
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO drivers:
++#
++# CONFIG_GPIO_GENERIC_PLATFORM is not set
++# CONFIG_GPIO_EM is not set
++# CONFIG_GPIO_PL061 is not set
++# CONFIG_GPIO_VX855 is not set
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_ADP5588 is not set
++
++#
++# PCI GPIO expanders:
++#
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_74X164 is not set
++
++#
++# AC97 GPIO expanders:
++#
++
++#
++# MODULbus GPIO expanders:
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_POWER_AVS is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++# CONFIG_ARM_SP805_WATCHDOG is not set
++# CONFIG_DW_WATCHDOG is not set
++# CONFIG_MPCORE_WATCHDOG is not set
++# CONFIG_MAX63XX_WATCHDOG is not set
++# CONFIG_ALIM7101_WDT is not set
++# CONFIG_I6300ESB_WDT is not set
++
++#
++# PCI-based Watchdog Cards
++#
++# CONFIG_PCIPCWATCHDOG is not set
++# CONFIG_WDTPCI is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_STMPE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_MEDIA_SUPPORT is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGA_ARB is not set
++# CONFIG_DRM is not set
++# CONFIG_STUB_POULSBO is not set
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++# CONFIG_FB is not set
++# CONFIG_EXYNOS_VIDEO is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++CONFIG_HIDRAW=y
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_AUREAL is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_TWINHAN is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO_TPKBD is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SONY is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB_ARCH_HAS_XHCI=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++CONFIG_USB_DEBUG=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DYNAMIC_MINORS=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_XHCI_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_EHCI_HCD_PLATFORM is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_CHIPIDEA is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++CONFIG_USB_UAS=y
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_ISP1301 is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_DUMMY_HCD is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++
++#
++# OTG and related infrastructure
++#
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ULPI is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_UWB is not set
++# CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMADEVICES_DEBUG=y
++CONFIG_DMADEVICES_VDEBUG=y
++
++#
++# DMA Devices
++#
++# CONFIG_AMBA_PL08X is not set
++# CONFIG_DW_DMAC is not set
++# CONFIG_TIMB_DMA is not set
++# CONFIG_PL330_DMA is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_BALLOON is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_MACH_CLKDEV=y
++
++#
++# Hardware Spinlock drivers
++#
++CONFIG_IOMMU_SUPPORT=y
++
++#
++# Remoteproc drivers (EXPERIMENTAL)
++#
++
++#
++# Rpmsg drivers (EXPERIMENTAL)
++#
++# CONFIG_VIRT_DRIVERS is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_XATTR=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_NILFS2_FS=y
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_FSNOTIFY is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_INOTIFY_USER is not set
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=y
++# CONFIG_FUSE_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++CONFIG_NTFS_FS=y
++# CONFIG_NTFS_DEBUG is not set
++# CONFIG_NTFS_RW is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++# CONFIG_PROC_PAGE_MONITOR is not set
++CONFIG_SYSFS=y
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
++# CONFIG_ENABLE_WARN_DEPRECATED is not set
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_HARDLOCKUP_DETECTOR is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_STATS is not set
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_INFO_REDUCED is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_CPU_STALL_INFO is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_LKDTM is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_ARM_UNWIND is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_LL=y
++CONFIG_DEBUG_LL_UART_NONE=y
++# CONFIG_DEBUG_ICEDCC is not set
++# CONFIG_DEBUG_SEMIHOSTING is not set
++# CONFIG_EARLY_PRINTK is not set
++# CONFIG_OC_ETM is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_PCOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=m
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++# CONFIG_CRYPTO_ZLIB is not set
++CONFIG_CRYPTO_LZO=y
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HIFN_795X is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++# CONFIG_CRC8 is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
++# CONFIG_AVERAGE is not set
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
+diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
+index 9abe7a0..fac79dc 100644
+--- a/arch/arm/include/asm/bug.h
++++ b/arch/arm/include/asm/bug.h
+@@ -32,7 +32,6 @@
+
+ #define __BUG(__file, __line, __value) \
+ do { \
+- BUILD_BUG_ON(sizeof(struct bug_entry) != 12); \
+ asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \
+ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \
+ "2:\t.asciz " #__file "\n" \
+diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
+index 3e91f22..b7641d6 100644
+--- a/arch/arm/include/asm/hardware/gic.h
++++ b/arch/arm/include/asm/hardware/gic.h
+@@ -42,6 +42,7 @@ extern struct irq_chip gic_arch_extn;
+ void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+ int gic_of_init(struct device_node *node, struct device_node *parent);
+ void gic_secondary_init(unsigned int);
++void gic_handle_irq(struct pt_regs *regs);
+ void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
+ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
+
+diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
+index fcbac3c..f2a1a30 100644
+--- a/arch/arm/include/asm/pgtable.h
++++ b/arch/arm/include/asm/pgtable.h
+@@ -21,7 +21,6 @@
+ #else
+
+ #include
+-#include
+ #include
+
+ #include
+@@ -33,14 +32,13 @@
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+- *
+- * Note that platforms may override VMALLOC_START, but they must provide
+- * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
+- * which may not overlap IO space.
+ */
+-#ifndef VMALLOC_START
+ #define VMALLOC_OFFSET (8*1024*1024)
+ #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
++#ifdef __ASSEMBLY__
++#define VMALLOC_END 0xff000000
++#else
++#define VMALLOC_END 0xff000000UL
+ #endif
+
+ #define LIBRARY_TEXT_START 0x0c000000
+@@ -338,6 +336,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+ * We provide our own arch_get_unmapped_area to cope with VIPT caches.
+ */
+ #define HAVE_ARCH_UNMAPPED_AREA
++#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+ /*
+ * remap a physical page `pfn' of size `size' with page protection `prot'
+diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
+index 3352451..da9f0d9 100644
+--- a/arch/arm/include/asm/processor.h
++++ b/arch/arm/include/asm/processor.h
+@@ -119,6 +119,8 @@ static inline void prefetch(const void *ptr)
+
+ #endif
+
++#define HAVE_ARCH_PICK_MMAP_LAYOUT
++
+ #endif
+
+ #endif /* __ASM_ARM_PROCESSOR_H */
+diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
+index ece0996..5ad6b59 100644
+--- a/arch/arm/kernel/entry-armv.S
++++ b/arch/arm/kernel/entry-armv.S
+@@ -27,25 +27,28 @@
+ #include
+
+ #include "entry-header.S"
++
+ #include
+
++
+ /*
+ * Interrupt handling.
+ */
+ .macro irq_handler
++
+ #ifdef CONFIG_MULTI_IRQ_HANDLER
+- ldr r1, =handle_arch_irq
++
++ ldr r1, =handle_arch_irq
+ mov r0, sp
+- ldr r1, [r1]
+ adr lr, BSYM(9997f)
+- teq r1, #0
+- movne pc, r1
+-#endif
++ ldr pc, [r1]
++#else
+ arch_irq_handler_default
++#endif
+ 9997:
+ .endm
+
+- .macro pabt_helper
++ .macro pabt_helper
+ @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
+ #ifdef MULTI_PABORT
+ ldr ip, .LCprocfns
+diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
+index 9d95a46..9dd0881 100644
+--- a/arch/arm/kernel/entry-header.S
++++ b/arch/arm/kernel/entry-header.S
+@@ -13,8 +13,10 @@
+ #define BAD_DATA 1
+ #define BAD_ADDREXCPTN 2
+ #define BAD_IRQ 3
++
+ #define BAD_UNDEFINSTR 4
+
++
+ @
+ @ Most of the stack format comes from struct pt_regs, but with
+ @ the addition of 8 bytes for storing syscall args 5 and 6.
+diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
+index 3606e85..f364802 100644
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -87,7 +87,26 @@ ENTRY(stext)
+
+ setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
+ @ and irqs disabled
+- mrc p15, 0, r9, c0, c0 @ get processor id
++#ifdef CONFIG_ARCH_IPROC
++
++#ifndef CONFIG_MACH_IPROC_P7
++#ifndef CONFIG_MACH_CYGNUS
++ /*
++ * fixup the vector table so that the secondary CPU does
++ * not start executing kernel instructions until we've
++ * patched its jump address during wakeup_secondary()
++ */
++ ldr r3,=0xffff002c
++ ldr r4,=0xffff0000
++ str r3, [r4, #0x400]
++#endif
++#endif
++
++ /* Make sure the cache is invalidated and MMU is disabled */
++ bl __iproc_head_fixup
++#endif /* CONFIG_ARCH_IPROC */
++
++ mrc p15, 0, r9, c0, c0 @ get processor id
+ bl __lookup_processor_type @ r5=procinfo r9=cpuid
+ movs r10, r5 @ invalid processor (r5=0)?
+ THUMB( it eq ) @ force fixup-able long branch encoding
+diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
+index 1e9be5d..7ab2fa7 100644
+--- a/arch/arm/kernel/module.c
++++ b/arch/arm/kernel/module.c
+@@ -111,19 +111,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ }
+
+ offset >>= 2;
++ offset &= 0x00ffffff;
+
+ *(u32 *)loc &= 0xff000000;
+ *(u32 *)loc |= offset & 0x00ffffff;
+ break;
+
+- case R_ARM_V4BX:
+- /* Preserve Rm and the condition code. Alter
++ case R_ARM_V4BX:
++ /* Preserve Rm and the condition code. Alter
+ * other bits to re-code instruction as
+ * MOV PC,Rm.
+ */
+- *(u32 *)loc &= 0xf000000f;
+- *(u32 *)loc |= 0x01a0f000;
+- break;
++ *(u32 *)loc &= 0xf000000f;
++ *(u32 *)loc |= 0x01a0f000;
++ break;
+
+ case R_ARM_PREL31:
+ offset = *(u32 *)loc + sym->st_value - loc;
+@@ -142,7 +143,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+
+ *(u32 *)loc &= 0xfff0f000;
+ *(u32 *)loc |= ((offset & 0xf000) << 4) |
+- (offset & 0x0fff);
++ (offset & 0x0fff);
++
+ break;
+
+ #ifdef CONFIG_THUMB2_KERNEL
+@@ -203,12 +205,13 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
+ (j1 << 13) | (j2 << 11) |
+ ((offset >> 1) & 0x07ff));
++
+ break;
+
+ case R_ARM_THM_MOVW_ABS_NC:
+ case R_ARM_THM_MOVT_ABS:
+- upper = *(u16 *)loc;
+- lower = *(u16 *)(loc + 2);
++ upper = __mem_to_opcode_thumb16(*(u16 *)loc);
++ lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
+
+ /*
+ * MOVT/MOVW instructions encoding in Thumb-2:
+@@ -229,12 +232,15 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+ offset >>= 16;
+
+- *(u16 *)loc = (u16)((upper & 0xfbf0) |
++ upper = (u16)((upper & 0xfbf0) |
+ ((offset & 0xf000) >> 12) |
+ ((offset & 0x0800) >> 1));
+- *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
++ lower = (u16)((lower & 0x8f00) |
+ ((offset & 0x0700) << 4) |
+ (offset & 0x00ff));
++
++ *(u16 *)loc = __opcode_to_mem_thumb16(upper);
++ *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
+ break;
+ #endif
+
+diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
+index d9e3c61..2dc26fd 100644
+--- a/arch/arm/kernel/process.c
++++ b/arch/arm/kernel/process.c
+@@ -31,6 +31,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #include
+ #include
+@@ -263,11 +264,12 @@ void __show_regs(struct pt_regs *regs)
+ unsigned long flags;
+ char buf[64];
+
+- printk("CPU: %d %s (%s %.*s)\n",
++ printk("CPU: %d %s (%s %.*s%s)\n",
+ raw_smp_processor_id(), print_tainted(),
+ init_utsname()->release,
+ (int)strcspn(init_utsname()->version, " "),
+- init_utsname()->version);
++ init_utsname()->version,
++ LINUX_PACKAGE_ID);
+ print_symbol("PC is at %s\n", instruction_pointer(regs));
+ print_symbol("LR is at %s\n", regs->ARM_lr);
+ printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n"
+diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
+index 8f5dd79..1edbb3d 100644
+--- a/arch/arm/kernel/smp_scu.c
++++ b/arch/arm/kernel/smp_scu.c
+@@ -27,7 +27,7 @@
+ */
+ unsigned int __init scu_get_core_count(void __iomem *scu_base)
+ {
+- unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
++ unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
+ return (ncores & 0x03) + 1;
+ }
+
+@@ -41,19 +41,19 @@ void scu_enable(void __iomem *scu_base)
+ #ifdef CONFIG_ARM_ERRATA_764369
+ /* Cortex-A9 only */
+ if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+- scu_ctrl = __raw_readl(scu_base + 0x30);
++ scu_ctrl = readl_relaxed(scu_base + 0x30);
+ if (!(scu_ctrl & 1))
+- __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
++ writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
+ }
+ #endif
+
+- scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
++ scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
+ /* already enabled? */
+ if (scu_ctrl & 1)
+ return;
+
+ scu_ctrl |= 1;
+- __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
++ writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
+
+ /*
+ * Ensure that the data accessed by CPU0 before the SCU was
+@@ -79,9 +79,9 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+ if (mode > 3 || mode == 1 || cpu > 3)
+ return -EINVAL;
+
+- val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
++ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+ val |= mode;
+- __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
++ writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
+
+ return 0;
+ }
+diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
+index a8a6682..0647dfa 100644
+--- a/arch/arm/kernel/smp_twd.c
++++ b/arch/arm/kernel/smp_twd.c
+@@ -39,7 +39,7 @@ static void twd_set_mode(enum clock_event_mode mode,
+ /* timer load already set up */
+ ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
+ | TWD_TIMER_CONTROL_PERIODIC;
+- __raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
++ writel_relaxed(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* period set, and timer enabled in 'next_event' hook */
+@@ -51,18 +51,18 @@ static void twd_set_mode(enum clock_event_mode mode,
+ ctrl = 0;
+ }
+
+- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
++ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
+ }
+
+ static int twd_set_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+ {
+- unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
++ unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
+
+ ctrl |= TWD_TIMER_CONTROL_ENABLE;
+
+- __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
+- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
++ writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER);
++ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
+
+ return 0;
+ }
+@@ -75,8 +75,8 @@ static int twd_set_next_event(unsigned long evt,
+ */
+ int twd_timer_ack(void)
+ {
+- if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
+- __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
++ if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) {
++ writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
+ return 1;
+ }
+
+@@ -110,16 +110,16 @@ static void __cpuinit twd_calibrate_rate(void)
+ /* OK, now the tick has started, let's get the timer going */
+ waitjiffies += 5;
+
+- /* enable, no interrupt or reload */
+- __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
++ /* enable, no interrupt or reload */
++ writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL);
+
+- /* maximum value */
+- __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
++ /* maximum value */
++ writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
+
+ while (get_jiffies_64() < waitjiffies)
+ udelay(10);
+
+- count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
++ count = readl_relaxed(twd_base + TWD_TIMER_COUNTER);
+
+ twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
+
+diff --git a/arch/arm/mach-iproc/Kconfig b/arch/arm/mach-iproc/Kconfig
+new file mode 100644
+index 0000000..c77208d
+--- /dev/null
++++ b/arch/arm/mach-iproc/Kconfig
+@@ -0,0 +1,107 @@
++menu "iProc SoC based Machine types"
++ depends on MACH_IPROC
++
++config MACH_CYGNUS
++ bool "Cygnus bring-up board"
++ help
++ Support for the Broadcom Cygnus bring-up board.
++
++config MACH_NS
++ bool "Support Broadcom Northstar bring-up board"
++ help
++ Support for the Broadcom Northstar bring-up board.
++
++config MACH_HX4
++ bool "Support Broadcom Helix4 bring-up board"
++ help
++ Support for the Broadcom Helix4 bring-up board.
++
++config MACH_HR2
++ bool "Support Broadcom Hurricane2 bring-up board"
++ help
++ Support for the Broadcom Hurricane2 bring-up board.
++
++config MACH_NSP
++ bool "Support Broadcom Northstar Plus bring-up board"
++ help
++ Support for the Broadcom Northstar Plus bring-up board.
++
++config MACH_KT2
++ bool "Support Broadcom Katana2 bring-up board"
++ help
++ Support for the Broadcom Katana2 bring-up board.
++
++config MACH_GH
++ bool "Support Broadcom Greyhound bring-up board"
++ select MACH_IPROC_P7
++ help
++ Support for the Broadcom Greyhound bring-up board.
++
++config MACH_DNI_3448P
++ select ARM_L1_CACHE_SHIFT_6
++ bool "Support Delta Networks Inc. 3448P board"
++ help
++ Support for the Broadcom Greyhound bring-up board.
++
++config MACH_ACCTON_AS4610_54
++ select ARM_L1_CACHE_SHIFT_6
++ bool "Support Accton AS4610 54 POE and non-POE board"
++ help
++ Support for Accton AS4610-54 POE and non -POE board.
++
++config MACH_IPROC_P7
++ bool "Support iProc Profile 7 architecture"
++ depends on MACH_GH
++ help
++ Support for iProc Profile 7 architecture.
++
++config MACH_IPROC_EMULATION
++ bool "Support iProc emulation"
++ help
++ Support for the iProc emulation.
++
++if MACH_CYGNUS
++
++config MACH_CYGNUS_EMULATION
++ bool "Is it Cygnus emulation ?"
++ default y
++ help
++ Support for the Broadcom Cygnus emulation
++
++if MACH_CYGNUS_EMULATION
++
++config CYGNUS_EMULATION_RTL_VER
++ string "specify RTL version"
++ default "Cygnus RTL-5.1"
++ help
++ running rtl version used for emulation build
++
++config CYGNUS_EMULATION_ARM_CLK
++ int "Hz - iHost clk don't change"
++ default 250000000
++ help
++ iHost clock in emulator
++
++config CYGNUS_EMULATION_PCLK
++ int "Hz - axi81 (pclk) in xls"
++ default 62500000
++ help
++ pheripheral clock in emulator
++
++config CYGNUS_EMULATION_SCLK
++ int "Hz - sclk in xls"
++ default 154380
++ help
++ uart clock in emulator
++
++config CYGNUS_EMULATION_CLK_125
++ int "Hz - axi41 clock in xls"
++ default 154380
++ help
++ 125Mhz equialent clock in emulator
++
++endif #MACH_CYGNUS_EMULATION
++
++endif #MACH_CYGNUS
++
++endmenu
+diff --git a/arch/arm/mach-iproc/Makefile b/arch/arm/mach-iproc/Makefile
+new file mode 100644
+index 0000000..b4a7ff3
+--- /dev/null
++++ b/arch/arm/mach-iproc/Makefile
+@@ -0,0 +1,15 @@
++ifdef CONFIG_MACH_CYGNUS
++obj-y := io_map.o northstar.o common.o northstar_dmu.o board_bu.o localtimer.o
++else
++obj-y := io_map.o northstar.o common.o northstar_dmu.o board_bu.o idm.o localtimer.o
++endif
++
++ifdef CONFIG_BCM_CTF2
++EXTRA_CFLAGS += -I$(srctree)/../../bcmdrivers/gmac/src/include/
++endif
++
++obj-$(CONFIG_PM) += pm.o
++
++#obj-$(CONFIG_MACH_NS) += board_bu.o
++
++obj-$(CONFIG_MTD) += flash.o
+diff --git a/arch/arm/mach-iproc/Makefile.boot b/arch/arm/mach-iproc/Makefile.boot
+new file mode 100644
+index 0000000..2de985c
+--- /dev/null
++++ b/arch/arm/mach-iproc/Makefile.boot
+@@ -0,0 +1,2 @@
++zreladdr-y := $(CONFIG_BCM_ZRELADDR)
++params_phys-y := $(CONFIG_BCM_PARAMS_PHYS)
+diff --git a/arch/arm/mach-iproc/board_bu.c b/arch/arm/mach-iproc/board_bu.c
+new file mode 100644
+index 0000000..7e07ed1
+--- /dev/null
++++ b/arch/arm/mach-iproc/board_bu.c
+@@ -0,0 +1,1097 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#ifdef CONFIG_EARLY_DMA_ALLOC
++#include
++#endif
++
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "northstar.h"
++#include "common.h"
++#ifdef HNDCTF
++#include
++#include
++#endif /* HNDCTF */
++
++#include
++#include
++#include
++
++#include
++
++/* Fast device at 0x6000 offset */
++static AMBA_APB_DEVICE(pl020, "pl020", 0, 0x18028000,
++ { 111 }, NULL);
++static AMBA_APB_DEVICE(pl021, "pl021", 0, 0x18029000,
++ { 111 }, NULL);
++
++struct pl022_config_chip spi_chip_info = {
++ /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
++ .com_mode = DMA_TRANSFER,
++ .iface = SSP_INTERFACE_MOTOROLA_SPI,
++ /* We can only act as master but SSP_SLAVE is possible in theory */
++ .hierarchy = SSP_MASTER,
++ /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
++ .slave_tx_disable = 0,
++ .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
++ .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
++ .ctrl_len = SSP_BITS_12,
++ .wait_state = SSP_MWIRE_WAIT_ZERO,
++ .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
++};
++
++static struct pl022_ssp_controller ssp_platform_data[] = {
++ {
++ /* If you have several SPI buses this varies, we have only bus 0 */
++ .bus_id = 0,
++ /*
++ * On the APP CPU GPIO 4, 5 and 6 are connected as generic
++ * chip selects for SPI. (Same on U330, U335 and U365.)
++ * TODO: make sure the GPIO driver can select these properly
++ * and do padmuxing accordingly too.
++ */
++ .num_chipselect = 1,
++ .enable_dma = 1,
++ },
++ {
++ /* If you have several SPI buses this varies, we have only bus 0 */
++ .bus_id = 1,
++ /*
++ * On the APP CPU GPIO 4, 5 and 6 are connected as generic
++ * chip selects for SPI. (Same on U330, U335 and U365.)
++ * TODO: make sure the GPIO driver can select these properly
++ * and do padmuxing accordingly too.
++ */
++ .num_chipselect = 1,
++ .enable_dma = 1,
++ },
++};
++
++static struct spi_board_info iproc_spi_devices[] = {
++ {
++ /* A dummy chip used for loopback tests */
++ .modalias = "spidev0",
++ /* Really dummy, pass in additional chip config here */
++ .platform_data = NULL,
++ /* This defines how the controller shall handle the device */
++ .controller_data = &spi_chip_info,
++ /* .irq - no external IRQ routed from this device */
++ .max_speed_hz = 1000000,
++ .bus_num = 0, /* Only one bus on this chip */
++ .chip_select = 0,
++ /* Means SPI_CS_HIGH, change if e.g low CS */
++ .mode = SPI_MODE_2 | SPI_NO_CS,
++ },
++ {
++ /* A dummy chip used for loopback tests */
++ .modalias = "spidev1",
++ /* Really dummy, pass in additional chip config here */
++ .platform_data = NULL,
++ /* This defines how the controller shall handle the device */
++ .controller_data = &spi_chip_info,
++ /* .irq - no external IRQ routed from this device */
++ .max_speed_hz = 1000000,
++ .bus_num = 1, /* Only one bus on this chip */
++ .chip_select = 0,
++ /* Means SPI_CS_HIGH, change if e.g low CS */
++ .mode = SPI_MODE_2 | SPI_NO_CS,
++ },
++};
++
++/*
++ * The order of device declaration may be important, since some devices
++ * have dependencies on other devices being initialized first.
++ */
++static struct amba_device *amba_pl_devs[] __initdata = {
++ &pl020_device,
++ &pl021_device,
++
++};
++
++void __init iproc_spi_init(struct amba_device *adev, int i)
++{
++ adev->dev.platform_data = &ssp_platform_data[i];
++}
++
++void __init iproc_spi_register_board_devices(void)
++{
++ /* Register any SPI devices */
++ spi_register_board_info(iproc_spi_devices, ARRAY_SIZE(iproc_spi_devices));
++}
++
++void __init iproc_init_devics(void)
++{
++ int i;
++
++ /* Register the AMBA devices in the AMBA bus abstraction layer */
++ for (i = 0; i < ARRAY_SIZE(amba_pl_devs); i++) {
++ struct amba_device *d = amba_pl_devs[i];
++ iproc_spi_init(d, i);
++ amba_device_register(d, &iomem_resource);
++ }
++
++ /* Register SPI bus */
++ iproc_spi_register_board_devices();
++}
++
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++#define IPROC_SDIO_PA IPROC_SDIO3_REG_BASE
++#define SDIO_CORE_REG_SIZE 0x10000
++#define BSC_CORE_REG_SIZE 0x1000
++#define SDIO_IDM_IDM_RESET_CONTROL (0x16800)
++#define IPROC_SDIO_IRQ (177)
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++#define SATA_M0_IDM_IO_CONTROL_DIRECT_VA HW_IO_PHYS_TO_VIRT(SATA_M0_IDM_IO_CONTROL_DIRECT)
++#define SATA_M0_IDM_IDM_RESET_CONTROL_VA HW_IO_PHYS_TO_VIRT(SATA_M0_IDM_IDM_RESET_CONTROL)
++#define SATA_TOP_CTRL_BUS_CTRL_VA HW_IO_PHYS_TO_VIRT(SATA_TOP_CTRL_BUS_CTRL)
++#define SATA3_PCB_UPPER_REG15_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG15)
++#define SATA3_PCB_UPPER_REG0_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG0)
++#define SATA3_PCB_UPPER_REG1_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG1)
++#define SATA3_PCB_UPPER_REG11_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG11)
++#define SATA3_PCB_UPPER_REG5_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG5)
++#define AXIIC_sata_m0_fn_mod_VA HW_IO_PHYS_TO_VIRT(AXIIC_sata_m0_fn_mod)
++#define BCM_INT_SATA 190
++#define NSP_CHIPID 0x3F00CF1E
++#endif
++
++#ifndef CONFIG_MACH_CYGNUS
++extern void request_idm_timeout_interrupts(void);
++#endif
++
++extern irqreturn_t idm_timeout_handler(int val, void *ptr);
++#if (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP))
++extern void* bcm5301x_otp_init(void);
++extern int bcm5301x_otp_exit(void);
++extern int bcm5301x_otp_read_dword(void *oh, uint wn, u32 *data);
++#endif /* (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP)) */
++
++#ifdef CONFIG_MACH_CYGNUS_EMULATION //cygnus:emulator:
++ /* This is the main reference clock 25MHz from external crystal */
++ static struct clk clk_ref = {
++ .name = "Refclk",
++ .rate = CONFIG_CYGNUS_EMULATION_SCLK, /* run-time override */
++ .fixed = 1,
++ .type = 0,
++ };
++#else
++/* This is the main reference clock 25MHz from external crystal */
++static struct clk clk_ref = {
++ .name = "Refclk",
++ .rate = 25 * 1000000, /* run-time override */
++ .fixed = 1,
++ .type = 0,
++};
++#endif /* END of CYGNUS */
++
++#ifdef HNDCTF
++ctf_t *kcih = NULL;
++EXPORT_SYMBOL(kcih);
++ctf_attach_t ctf_attach_fn = NULL;
++EXPORT_SYMBOL(ctf_attach_fn);
++#endif /* HNDCTF */
++
++static struct clk_lookup board_clk_lookups[] = {
++ {
++ .con_id = "refclk",
++ .clk = &clk_ref,
++ }
++};
++
++extern void __init northstar_timer_init(struct clk *clk_ref);
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++/* sdio */
++static struct sdio_platform_cfg sdio_platform_data = {
++ .devtype = SDIO_DEV_TYPE_SDMMC,
++};
++static struct resource sdio_resources[] = {
++ [0] = {
++ .start = IPROC_SDIO_PA,
++ .end = IPROC_SDIO_PA + BSC_CORE_REG_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_SDIO_IRQ,
++ .end = IPROC_SDIO_IRQ,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device board_sdio_device = {
++ .name = "iproc-sdio",
++ .id = 0,
++ .dev = {
++ .platform_data = &sdio_platform_data,
++ },
++ .num_resources = ARRAY_SIZE(sdio_resources),
++ .resource = sdio_resources,
++};
++
++static void setup_sdio(void)
++{
++ void __iomem *idm_base;
++ struct platform_device *sdio_plat_dev[1];
++ idm_base = (void __iomem *)IPROC_IDM_REGISTER_VA;
++ printk("%s: %d %p\n", __FUNCTION__, __LINE__, idm_base + SDIO_IDM_IDM_RESET_CONTROL);
++ writel_relaxed(0, idm_base + SDIO_IDM_IDM_RESET_CONTROL);
++ sdio_plat_dev[0] = &board_sdio_device;
++ platform_add_devices(sdio_plat_dev, 1);
++
++}
++#endif /* CONFIG_IPROC_SD || CONFIG_IPROC_SD_MODULE */
++
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++static struct resource iproc_pwm_resources = {
++ .start = IPROC_CCB_PWM_CTL,
++ .end = IPROC_CCB_PWM_CTL + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device board_pwm_device = {
++ .name = "iproc_pwmc",
++ .id = -1,
++ .resource = &iproc_pwm_resources,
++ .num_resources = 1,
++};
++static struct pwm_lookup board_pwm_lookup[] = {
++ PWM_LOOKUP("iproc_pwmc", 0,"iproc_pwmc","pwm-0"),
++ PWM_LOOKUP("iproc_pwmc", 1,"iproc_pwmc","pwm-1"),
++ PWM_LOOKUP("iproc_pwmc", 2,"iproc_pwmc","pwm-2"),
++ PWM_LOOKUP("iproc_pwmc", 3,"iproc_pwmc","pwm-3"),
++
++};
++
++#endif /* CONFIG_IPROC_PWM || CONFIG_IPROC_PWM_MODULE */
++
++#if defined(CONFIG_IPROC_WDT) || defined(CONFIG_IPROC_WDT_MODULE)
++/* watchdog */
++static struct resource wdt_resources[] = {
++ [0] = {
++ .start = IPROC_CCA_REG_BASE,
++ .end = IPROC_CCA_REG_BASE + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device board_wdt_device = {
++ .name = "iproc_wdt",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(wdt_resources),
++ .resource = wdt_resources,
++};
++#endif /* CONFIG_IPROC_WDT || CONFIG_IPROC_WDT_MODULE */
++
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++static AMBA_APB_DEVICE(sp805_wdt, "sp805-wdt", 0x00141805,
++ IPROC_SP805_WDT_REG_BASE, { }, NULL);
++#endif
++
++#if defined(CONFIG_IPROC_CCB_TIMER) || defined(CONFIG_IPROC_CCB_TIMER_MODULE)
++static struct resource ccb_timer_resources[] = {
++ [0] = {
++ .start = IPROC_CCB_TIMER_INT_START,
++ .end = IPROC_CCB_TIMER_INT_START + IPROC_CCB_TIMER_INT_COUNT - 1,
++ .flags = IORESOURCE_IRQ,
++ },
++ [1] = {
++ .start = IPROC_CCB_TIMER0_REGS_VA,
++ .end = IPROC_CCB_TIMER0_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IPROC_CCB_TIMER1_REGS_VA,
++ .end = IPROC_CCB_TIMER1_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [3] = {
++ .start = IPROC_CCB_TIMER2_REGS_VA,
++ .end = IPROC_CCB_TIMER2_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [4] = {
++ .start = IPROC_CCB_TIMER3_REGS_VA,
++ .end = IPROC_CCB_TIMER3_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device board_timer_device = {
++ .name = "iproc_ccb_timer",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(ccb_timer_resources),
++ .resource = ccb_timer_resources,
++};
++#endif /* CONFIG_IPROC_CCB_TIMER || CONFIG_IPROC_CCB_TIMER_MODULE */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++static struct resource fa2_resources[] = {
++ [0] = {
++ .start = CTF_CONTROL_REG, /* Macro is in socregs_nsp.h */
++ .end = CTF_CONTROL_REG + SZ_1K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 178,
++ .end = 178,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#endif
++#endif /* CONFIG_IPROC_FA2 */
++
++#if !(defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++/* Helix4 */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 127,
++ .end = 127,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource smbus_resources1[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus1_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus1_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM
++ },
++ [1] = {
++ .start = 128, /* macro in irqs.h (plat-iproc) */
++ .end = 128,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#elif defined(CONFIG_MACH_NSP)
++/* Northstar plus */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 121,
++ .end = 121,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#else
++/* Northstar */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = CCB_SMBUS_START, /* Define this macro is socregs.h, or
++ in iproc_regs.h */
++ .end = CCB_SMBUS_START + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_CCB_SMBUS, /* macro in irqs.h (plat-iproc) */
++ .end = BCM_INT_ID_CCB_SMBUS,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#endif
++
++/* Common to Northstar, Helix4 */
++static struct platform_device board_smbus_device = {
++ .name= "iproc-smb",
++ .id = 0,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(smbus_resources),
++ .resource = smbus_resources,
++};
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++static struct platform_device board_smbus_device1 = {
++ .name= "iproc-smb",
++ .id = 1,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(smbus_resources1),
++ .resource = smbus_resources1,
++};
++
++#endif /* CONFIG_MACH_HX4 */
++#endif /* Not ACCTON-AS4610-54, dni-3448p */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++static struct platform_device board_fa2_device = {
++ .name= "fa2",
++ .id = 0,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(fa2_resources),
++ .resource = fa2_resources,
++};
++#endif
++#endif /* CONFIG_IPROC_FA2 */
++
++#ifdef CONFIG_IPROC_USB3H
++static struct resource bcm_xhci_resources[] = {
++ [0] = {
++ .start = USB30_BASE,
++ .end = USB30_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_USB3H2CORE_USB2_INT0,
++ .end = BCM_INT_ID_USB3H2CORE_USB2_INT0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 xhci_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device bcm_xhci_device = {
++ .name = "bcm-xhci",
++ .id = 0,
++ .dev = {
++// .platform_data = &xhci_platform_data,
++ .dma_mask = &xhci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .resource = bcm_xhci_resources,
++ .num_resources = ARRAY_SIZE(bcm_xhci_resources),
++};
++#endif /* CONFIG_IPROC_USB3 */
++
++#ifdef CONFIG_USB_EHCI_BCM
++
++static u64 ehci_dmamask = DMA_BIT_MASK(32);
++
++static struct resource usbh_ehci_resource[] = {
++ [0] = {
++ .start = IPROC_USB20_REG_BASE,
++ .end = IPROC_USB20_REG_BASE + 0x0FFF,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ // FIXME Cumulus: Helix4 IRQ value should be 117,
++ // some #define in plat-iproc irqgs.h is messed up
++ .start = 117,
++ .end = 117,
++ //.start = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ //.end = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device usbh_ehci_device =
++{
++ .name = "bcm-ehci",
++ .id = 0,
++ .resource = usbh_ehci_resource,
++ .num_resources = ARRAY_SIZE(usbh_ehci_resource),
++ .dev = {
++ .dma_mask = &ehci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++#endif
++
++#ifdef CONFIG_USB_OHCI_BCM
++
++static u64 ohci_dmamask = DMA_BIT_MASK(32);
++
++static struct resource usbh_ohci_resource[] = {
++ [0] = {
++ .start = IPROC_USB20_REG_BASE + 0x1000,
++ .end = IPROC_USB20_REG_BASE + 0x1000 + 0x0FFF,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ // FIXME Cumulus: Helix4 IRQ value should be 117,
++ // some #define in plat-iproc irqgs.h is messed up
++ .start = 117,
++ .end = 117,
++ //.start = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ //.end = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device usbh_ohci_device =
++{
++ .name = "bcm-ohci",
++ .id = 0,
++ .resource = usbh_ohci_resource,
++ .num_resources = ARRAY_SIZE(usbh_ohci_resource),
++ .dev = {
++ .dma_mask = &ohci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++#endif
++
++#ifdef CONFIG_SATA_AHCI_PLATFORM
++static struct resource bcm_sata_resources[] = {
++ [0] = {
++ .start = SATA_AHCI_GHC_HBA_CAP,
++ .end = SATA_AHCI_GHC_HBA_CAP + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_SATA,
++ .end = BCM_INT_SATA,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++static u64 sata_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device bcm_sata_device = {
++ .name = "strict-ahci",
++ .id = 0,
++ .dev = {
++ .dma_mask = &sata_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .resource = bcm_sata_resources,
++ .num_resources = ARRAY_SIZE(bcm_sata_resources),
++};
++#endif
++
++#ifdef CONFIG_DMAC_PL330
++#include "../../../../bcmdrivers/dma/pl330-pdata.h"
++static struct iproc_pl330_data iproc_pl330_pdata = {
++ /* Non Secure DMAC virtual base address */
++ .dmac_ns_base = IPROC_DMAC_REG_VA,
++ /* Secure DMAC virtual base address */
++ .dmac_s_base = IPROC_DMAC_REG_VA,
++ /* # of PL330 dmac channels 'configurable' */
++ .num_pl330_chans = 8,
++ /* irq number to use */
++ .irq_base = BCM_INT_ID_DMAC,
++ /* # of PL330 Interrupt lines connected to GIC */
++ .irq_line_count = 16,
++};
++
++static struct platform_device pl330_dmac_device = {
++ .name = "iproc-dmac-pl330",
++ .id = 0,
++ .dev = {
++ .platform_data = &iproc_pl330_pdata,
++ .coherent_dma_mask = DMA_BIT_MASK(64),
++ },
++};
++#endif
++
++
++#if defined(CONFIG_MACH_NSP)
++void config_AHCI( void )
++{
++ volatile unsigned int sata_clk_enable;
++ volatile unsigned int bustopcfg;
++
++ printk("\nConfigure AHCI ...\n");
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ sata_clk_enable |= 0x1;
++ writel_relaxed( sata_clk_enable, SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ udelay(1000);
++
++
++ /* Reset core */
++ writel_relaxed(0x0, SATA_M0_IDM_IDM_RESET_CONTROL_VA);
++ udelay(1000);
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IDM_RESET_CONTROL_VA);
++ bustopcfg = __raw_readl(SATA_TOP_CTRL_BUS_CTRL_VA); // JIRA:LINUXDEV-39
++ bustopcfg &= ~ (( 3 << 2) | ( 3 << 4 ));
++ bustopcfg |= (( 2 << 2) | ( 2 << 4 ));//| ( 2<< 6 ));
++ //bustopcfg |= ( ( 0x2 << 8 ) | ( 0x2 << 17 ) );
++ writel_relaxed(bustopcfg, SATA_TOP_CTRL_BUS_CTRL_VA);
++}
++void configure_SATA_PHY ( void )
++{
++ unsigned int i, tmp;
++ void __iomem *bs = ioremap(AXIIC_sata_m0_fn_mod, 4);
++
++ void __iomem *id = IOMEM(IPROC_CCA_CORE_REG_VA);
++
++ printk("\nConfigure PHY ...\n");
++
++ writel_relaxed(0x0150,SATA3_PCB_UPPER_REG15_VA);
++ writel_relaxed( 0xF6F6, SATA3_PCB_UPPER_REG0_VA);
++ writel_relaxed( 0x2e96, SATA3_PCB_UPPER_REG1_VA);
++
++ writel_relaxed(0x0160,SATA3_PCB_UPPER_REG15_VA);
++ writel_relaxed( 0xF6F6, SATA3_PCB_UPPER_REG0_VA);
++ writel_relaxed( 0x2e96, SATA3_PCB_UPPER_REG1_VA);
++
++ //access SATA PLL
++ writel_relaxed(0x0050,SATA3_PCB_UPPER_REG15_VA);
++ //Audio PLL 0x8B
++ i = readl_relaxed(SATA3_PCB_UPPER_REG11_VA);
++ i &= ~ (( 0x1f) << 9 );
++ i |= ( 0xC << 9);
++ writel_relaxed( i, SATA3_PCB_UPPER_REG11_VA);
++
++ //Sequence for restarting PLL. Please try after changing the divider.
++ //'PLL_CapCtrl[10] = 1, PLL_CapCtrl[7:0] = F0h
++ //SATA3_PLL: PLL Register Bank address 0x50
++
++ //set register SATA3_PLL_capControl ( 0x85 )
++ i = readl_relaxed(SATA3_PCB_UPPER_REG5_VA);
++ i = ( i | 0x4f0 ) & 0xFF0;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG5_VA);
++
++ //'PLL_Ctrl[13:12] = 11
++ //Set register SATA3_PLL_CONTROL ( 0x81 )
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i |= 0x3000;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++
++ //'PLL_ReStart
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i &= 0x7FFF;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++ mdelay(100);
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i |= 0x8000;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++ mdelay(1000);
++ writel_relaxed(0x0000,SATA3_PCB_UPPER_REG15_VA);
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ tmp = readl(id);
++ if (tmp == NSP_CHIPID)
++ {
++ tmp = readl(bs);
++ tmp |= 0x3;
++ writel(tmp, bs);
++ tmp = readl(bs);
++ }
++}
++#endif
++
++#ifdef CONFIG_MACH_CYGNUS
++#include "include/mach/iproc_regs.h"
++#ifdef CONFIG_IPROC_DS1WM
++#include "../../../../../bcmgpldrivers/d1w/ds1wm.h"
++
++
++static struct ds1wm_driver_data ds1wm_platform_data = {
++ .clock_rate = 80000000,
++ .reset_recover_delay = 1, /*ms*/
++};
++
++static struct resource ds1wm_resources[] = {
++ [0] = {
++ .start = IPROC_D1W_REG_BASE,
++ .end = IPROC_D1W_REG_BASE+0x0F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_D1W_CLK_GATE_CTRL,
++ .end = IPROC_D1W_CLK_GATE_CTRL+0x03
++ },
++ [2] = {
++ .start = IPROC_D1W_IO_MUX_REG,
++ .end = IPROC_D1W_IO_MUX_REG+0x03
++ },
++ [3] = {
++ .start = IPROC_D1W_INTR,
++ .end = IPROC_D1W_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ds1wm_device = {
++ .name = "ds1wm",
++ .id = -1,
++ .dev = {
++ .platform_data = &ds1wm_platform_data,
++ },
++ .num_resources = ARRAY_SIZE(ds1wm_resources),
++ .resource = ds1wm_resources,
++};
++#endif
++
++#ifdef CONFIG_IPROC_KEYPAD
++#include "../../../../../bcmdrivers/keypad/keypad.h"
++static iproc_keypad_t keypad_info = {
++ .max_rows = 4,
++ .max_cols = 4,
++ .StatFilEn = 1,
++ .StatFilType = 0x5,
++ .ColFilEn = 1,
++ .ColFilType = 0x05,
++ .IoMode = 0,
++ .SwapRc = 0,
++ .ScanMode = 0
++};
++
++static struct resource keypad_resources[] = {
++ [0] = {
++ .start = IPROC_KEYPAD_REG_BASE,
++ .end = IPROC_KEYPAD_REG_BASE+0x4B,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_CRMU_ASIU_KEYPAD_CLK_DIV,
++ .end = IPROC_CRMU_ASIU_KEYPAD_CLK_DIV+0x03,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IPROC_IO_MUX_REG_BASE,
++ .end = IPROC_IO_MUX_REG_BASE+0x07,
++ .flags = IORESOURCE_MEM,
++ },
++ [3] = {
++ .start = IPROC_CLK_GATING_CTRL,
++ .end = IPROC_CLK_GATING_CTRL + 0x03,
++ .flags = IORESOURCE_MEM,
++ },
++ [4] = {
++ .start = IPROC_KEYPAD_INTR,
++ .end = IPROC_KEYPAD_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device keypad_device = {
++ .name = "iproc-keypad",
++ .id = -1,
++ .dev = {
++ .platform_data = &keypad_info,
++ },
++ .num_resources = ARRAY_SIZE(keypad_resources),
++ .resource = keypad_resources,
++};
++#endif
++#ifdef CONFIG_IPROC_TOUCHSCREEN
++static struct resource tsc_resources[] = {
++ [0] = {
++ .start = IPROC_TSC_REG_BASE,
++ .end = IPROC_TSC_REG_BASE+0x3F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_TSC_INTR,
++ .end = IPROC_TSC_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device tsc_device = {
++ .name = "iproc-tsc",
++ .id = -1,
++ .dev = {
++ .platform_data = NULL,
++ },
++ .num_resources = ARRAY_SIZE(tsc_resources),
++ .resource = tsc_resources,
++};
++#endif
++
++#ifdef CONFIG_IPROC_ADC
++static struct resource adc_resources[] = {
++ [0] = {
++ .start = IPROC_ADC_REG_BASE,
++ .end = IPROC_ADC_REG_BASE+0x3F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_ADC_INTR,
++ .end = IPROC_ADC_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device adc_device = {
++ .name = "iproc-adc",
++ .id = -1,
++ .dev = {
++ .platform_data = NULL,
++ },
++ .num_resources = ARRAY_SIZE(adc_resources),
++ .resource = adc_resources,
++};
++#endif
++
++#endif
++
++void __init board_map_io(void)
++{
++
++ /*
++ * Install clock sources in the lookup table.
++ */
++ clkdev_add_table(board_clk_lookups,
++ ARRAY_SIZE(board_clk_lookups));
++
++ /* Map machine specific iodesc here */
++ northstar_map_io();
++}
++
++void __init iproc_init_early(void)
++{
++
++ /*
++ * SDK allocates coherent buffers from atomic
++ * context. Increase size of atomic coherent pool to make sure such
++ * the allocations won't fail.
++ */
++#ifdef CONFIG_CMA
++ init_dma_coherent_pool_size(SZ_1M * 16);
++#endif
++ /*
++ * Allocate contiguous himem block for SDK usage
++ */
++#ifdef CONFIG_EARLY_DMA_ALLOC
++ eda_init();
++#endif
++}
++
++static struct platform_device *board_sata_device[] __initdata = {
++#ifdef CONFIG_SATA_AHCI_PLATFORM
++ &bcm_sata_device,
++#endif
++};
++
++static struct of_dev_auxdata iproc_auxdata_lookup[] __initdata =
++{
++ { /* sentinel */ },
++};
++static struct platform_device *board_devices[] __initdata = {
++#if !(defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++ &board_smbus_device,
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++ &board_smbus_device1,
++#endif
++#endif /*Don't use for Accton */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++ &board_fa2_device,
++#endif
++#endif /* FA+ */
++
++#if defined(CONFIG_IPROC_CCB_TIMER) || defined(CONFIG_IPROC_CCB_TIMER_MODULE)
++ &board_timer_device,
++#endif /* CONFIG_IPROC_CCB_TIMER || CONFIG_IPROC_CCB_TIMER_MODULE */
++#if defined(CONFIG_IPROC_WDT) || defined(CONFIG_IPROC_WDT_MODULE)
++ &board_wdt_device,
++#endif /* CONFIG_IPROC_WDT || CONFIG_IPROC_WDT_MODULE */
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++ &board_pwm_device,
++#endif /* CONFIG_IPROC_PWM || CONFIG_IPROC_PWM_MODULE */
++#ifdef CONFIG_IPROC_USB3H
++ &bcm_xhci_device,
++#endif
++#ifdef CONFIG_USB_EHCI_BCM
++ &usbh_ehci_device,
++#endif
++#ifdef CONFIG_USB_OHCI_BCM
++ &usbh_ohci_device,
++#endif
++#ifdef CONFIG_DMAC_PL330
++ &pl330_dmac_device,
++#endif
++#ifdef CONFIG_MACH_CYGNUS
++#ifdef CONFIG_IPROC_DS1WM
++ &ds1wm_device,
++#endif
++#ifdef CONFIG_IPROC_KEYPAD
++ &keypad_device,
++#endif
++#endif
++};
++
++static struct amba_device *amba_devs[] __initdata = {
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++ &sp805_wdt_device,
++#endif
++};
++
++static void __init board_add_devices(void)
++{
++ int i;
++
++ platform_add_devices(board_devices, ARRAY_SIZE(board_devices));
++// if (iproc_get_chipid() == 53010) {
++// }
++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
++ amba_device_register(amba_devs[i], &iomem_resource);
++ }
++}
++
++static void __init board_add_sata_device(void)
++{
++ platform_add_devices(board_sata_device, sizeof(board_sata_device)/sizeof((board_sata_device)[0]));
++}
++
++
++/* SPI device info of GSIO(SPI) interface */
++static struct spi_board_info bcm5301x_spi_device[] = {
++ {
++ .modalias = "spidev",
++ .platform_data = NULL,
++ .controller_data = NULL,
++ .max_speed_hz = 2 * 1000 * 1000,
++ .bus_num = 0,
++ .chip_select = 0,
++ .mode = SPI_MODE_0,
++ },
++};
++
++void __init board_timer_init(void)
++{
++ northstar_timer_init(&clk_ref);
++}
++
++struct sys_timer board_timer = {
++ .init = board_timer_init,
++};
++
++
++void __init board_init(void)
++{
++ uint32_t sata_enable=0;
++
++#if (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP))
++ void *oh;
++#endif /* (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP)) */
++
++ /*
++ * Add common platform devices that do not have board dependent HW
++ * configurations
++ */
++ board_add_common_devices(&clk_ref);
++#ifndef CONFIG_MACH_CYGNUS
++#ifndef CONFIG_MACH_NS
++ /* register IDM timeout interrupt handler */
++ request_idm_timeout_interrupts();
++#endif
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++ #if defined(CONFIG_IPROC_OTP)
++ /* read otp row 0xd to figure if sata is enabled */
++ oh = bcm5301x_otp_init();
++ if (oh != NULL)
++ {
++ bcm5301x_otp_read_dword(oh, 0xd, &sata_enable);
++ printk("%s: %d %08x\n", __FUNCTION__, __LINE__, sata_enable);
++ if ((sata_enable & 0x40000000) == 0x40000000)
++ {
++ config_AHCI();
++ configure_SATA_PHY();
++ }
++ bcm5301x_otp_exit();
++ }
++ else
++ printk("%s: %d bcm5301x_otp_init failed\n", __FUNCTION__, __LINE__);
++ #else /* defined(CONFIG_IPROC_OTP) */
++ printk("%s(): IPROC OTP not configured, can not determine if SATA is enabled.\n", __FUNCTION__);
++ #endif /* defined(CONFIG_IPROC_OTP) */
++#endif
++
++ board_add_devices();
++ if ((sata_enable & 0x40000000) == 0x40000000)
++ board_add_sata_device();
++
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++ /* only bcm53012 support sdio */
++ if ((__REG32(IPROC_IDM_REGISTER_VA + 0xd500) & 0xc) == 0x0) {
++ setup_sdio();
++ }
++#endif
++
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++ writel_relaxed(0xf, IPROC_CCB_GPIO_REG_VA + IPROC_GPIO_CCB_AUX_SEL);
++ pwm_add_table(board_pwm_lookup, ARRAY_SIZE(board_pwm_lookup));
++#endif
++
++ /* Register SPI device info */
++ spi_register_board_info(bcm5301x_spi_device,
++ ARRAY_SIZE(bcm5301x_spi_device));
++
++ of_platform_populate(NULL, of_default_bus_match_table,
++ iproc_auxdata_lookup, NULL);
++ printk(KERN_DEBUG "board_init: Leave\n");
++}
++
++MACHINE_START(IPROC, "Broadcom iProc")
++
++// Used micro9 as a reference. Micro9 removed these two fields,
++// and replaced them with a call to ep93xx_map_io(), which in turn
++// calls iotable_init(). Northstar appears to have an equivalent
++// init (refer to northstar_io_desc[] array, in io_map.c
++ .map_io = board_map_io,
++ .init_early = iproc_init_early,
++ .init_irq = iproc_init_irq,
++ .handle_irq = gic_handle_irq,
++ .timer = &board_timer,
++ .init_machine = board_init,
++MACHINE_END
++
++static const char * helix4_dt_board_compat[] = {
++ "dni,dni_3448p",
++ "accton,as4610_54",
++ NULL
++};
++
++DT_MACHINE_START(HELIX4_DT, "Broadcom Helix4 (Flattened Device Tree)")
++ .map_io = board_map_io,
++ .init_early = iproc_init_early,
++ .init_irq = iproc_init_irq,
++ .handle_irq = gic_handle_irq,
++ .timer = &board_timer,
++ .init_machine = board_init,
++ .dt_compat = helix4_dt_board_compat,
++MACHINE_END
+diff --git a/arch/arm/mach-iproc/common.c b/arch/arm/mach-iproc/common.c
+new file mode 100644
+index 0000000..b116ffc
+--- /dev/null
++++ b/arch/arm/mach-iproc/common.c
+@@ -0,0 +1,347 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++//#include
++#include
++#include
++#include
++#include
++#include
++
++#define IPROC_UART0_PA IPROC_CCA_UART0_REG_BASE
++#define IPROC_UART1_PA IPROC_CCA_UART1_REG_BASE
++#define IPROC_UART2_PA IPROC_CCB_UART0_REG_BASE
++#define IPROC_UART3_PA IPROC_CCA_UART3_REG_BASE
++#define IPROC_CCA_UART_CLK_PA IPROC_CCA_UART_CLK_REG_BASE
++#define IPROC_CCA_CCAP_PA IPROC_CCA_CORE_CAP_REG_BASE
++#define IPROC_CCA_CCTL_PA IPROC_CCA_CORE_CTL_REG_BASE
++#define IPROC_CCA_INTMASK_PA IPROC_CCA_INTMASK_REG_BASE
++
++#define IPROC_UART0_VA HW_IO_PHYS_TO_VIRT(IPROC_UART0_PA)
++#define IPROC_UART1_VA HW_IO_PHYS_TO_VIRT(IPROC_UART1_PA)
++#define IPROC_UART2_VA HW_IO_PHYS_TO_VIRT(IPROC_UART2_PA)
++#define IPROC_UART3_VA HW_IO_PHYS_TO_VIRT(IPROC_UART3_PA)
++#define IPROC_CCA_UART_CLK_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_UART_CLK_PA)
++#define IPROC_CCA_CCAP_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_CCAP_PA)
++#define IPROC_CCA_CCTL_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_CCTL_PA)
++#define IPROC_CCA_INTMASK_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_INTMASK_PA)
++
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IRQ_IPROC_UART0 117
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P))
++#define IRQ_IPROC_UART0 123
++#elif defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IRQ_IPROC_UART0 123
++#define IRQ_IPROC_UART2 124
++#elif defined(CONFIG_MACH_HR2)
++#define IRQ_IPROC_UART0 123
++#elif defined(CONFIG_MACH_GH)
++#define IRQ_IPROC_UART0 105
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IRQ_IPROC_UART0 IPROC_INTERRUPTS__chipcommonG_uart0_intr
++ #define IRQ_IPROC_UART1 IPROC_INTERRUPTS__chipcommonG_uart1_intr//chandra:fix
++ #define IRQ_IPROC_UART2 IPROC_INTERRUPTS__chipcommonG_uart2_intr//chandra:fix
++ #define IRQ_IPROC_UART3 IPROC_INTERRUPTS__chipcommonG_uart3_intr//chandra:fix
++#else
++#error "No valid UART IRQ selected"
++#endif
++
++#if defined(CONFIG_MACH_HR2) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (76800)
++#elif defined(CONFIG_MACH_KT2) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (65800)
++#elif defined(CONFIG_MACH_IPROC_P7) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (56864)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_UART_CLK (100000000)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_UART_CLK CONFIG_CYGNUS_EMULATION_SCLK
++#else
++#define IPROC_UART_CLK (62500000)
++#endif
++
++#ifdef CONFIG_MACH_IPROC_P7
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_UART0, \
++ .uartclk = IPROC_UART_CLK, \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++#elif defined(CONFIG_MACH_CYGNUS) /* !CONFIG_MACH_IPROC_P7 */
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_##name, \
++ .uartclk = CONFIG_CYGNUS_EMULATION_SCLK, /*.uartclk = 62500000,*/ \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++#else /* ! CONFIG_MACH_CYGNUS */
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_UART0, \
++ .uartclk = IPROC_UART_CLK, \
++ .regshift = 0, \
++ .iotype = UPIO_MEM, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++
++
++#define IPROC_APB_CLK 125000000
++
++#define IPROC_8250PORT_UART2(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = 124, \
++ .uartclk = IPROC_APB_CLK, \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++
++#endif /* CONFIG_MACH_IPROC_P7 */
++
++static struct plat_serial8250_port uart_data[] = {
++#if (defined(CONFIG_MACH_HR2) && !defined(CONFIG_MACH_IPROC_EMULATION))
++ IPROC_8250PORT(UART1), /* Use UART2 as ttys0 */
++ IPROC_8250PORT(UART0),
++#elif defined(CONFIG_MACH_CYGNUS)
++ IPROC_8250PORT(UART3),
++ IPROC_8250PORT(UART0),
++#else
++ IPROC_8250PORT(UART0),
++ IPROC_8250PORT(UART1),
++#endif
++ { .flags = 0, },
++};
++
++static struct platform_device board_serial_device = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = uart_data,
++ },
++};
++
++#if defined(CONFIG_MPCORE_WATCHDOG)
++static struct resource wdt_device_resource[] = {
++ [0] = {
++ .start = IPROC_PERIPH_PVT_TIM_REG_BASE,
++ .end = IPROC_PERIPH_PVT_TIM_REG_BASE + 0x34,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_CCB_TIM1_INT2,
++ .end = BCM_INT_ID_CCB_TIM1_INT2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device wdt_device =
++{
++ .name = "mpcore_wdt",
++ .id = -1,
++ .resource = wdt_device_resource,
++ .num_resources = ARRAY_SIZE(wdt_device_resource),
++};
++#endif
++enum {
++ HX4_NONE = 0,
++ HX4_DNI_3448P,
++ HX4_ACCTON_AS4610_54
++};
++
++/*
++ * API to return the type of platform retrieved from device tree
++ * Note: This is hack until complete device tree is supported for
++ * for all broadcom iproc device drivers
++ */
++int brcm_get_hx4_model(void)
++{
++ const char *model = NULL;
++ unsigned long dt_root;
++
++ dt_root = of_get_flat_dt_root();
++ model = of_get_flat_dt_prop(dt_root, "model", NULL);
++ if (!model) {
++ model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
++ if (!model)
++ model = "";
++ }
++
++ if (!strcmp(model, "dni,3448p"))
++ return HX4_DNI_3448P;
++ else if (!strcmp(model, "accton,as4610_54"))
++ return HX4_ACCTON_AS4610_54;
++
++ printk( KERN_ERR "Unknown Model %s\n", model );
++ return HX4_NONE;
++}
++
++/* Common devices among all Northstar boards */
++//static struct platform_device *board_common_plat_devices[] __initdata = {
++// &board_serial_device,
++//#if defined(CONFIG_MPCORE_WATCHDOG)
++// &wdt_device,
++//#endif
++//};
++
++void __init iproc_config_boot_console(struct clk *ref_clk)
++{
++ u32 i;
++ u32 clk_rate = IPROC_UART_CLK;
++
++#ifndef CONFIG_MACH_IPROC_P7
++ u8 uart_clk_sel;
++ u8 uart_clk_ovr;
++ u16 uart_clk_div;
++ struct clk * clk = NULL ;
++ int modelnum;
++
++ /* Get Core Capabilities Register, and extract
++ UART Clock Select from bits 4..3 which show
++ the clock source. Values are:
++ 0 = 25Mhz clock input
++ 1 = Internal clock
++ 2 = reserved
++ 3 = reserved
++ */
++ uart_clk_sel = (readl(IPROC_CCA_CCAP_VA) >> 3) & 0x3;
++
++ /* Get UARTClkOvr from bit 0 of the Core Control Register
++ If set, this bit indicates that the UART clock is supplied
++ from the internal ALP (APB) clock. If clear then it indicates
++ that APBX_IDM_IO_CONTROL_DIRECT register bit UARTClkSel controls
++ the clock source
++ */
++ uart_clk_ovr = readl(IPROC_CCA_CCTL_VA) & 0x01;
++
++ /* uart_clk_div: ChipcommonA_ClkDiv bits 0..7 */
++ uart_clk_div = 0xff & readl(IPROC_CCA_UART_CLK_VA);
++ if( uart_clk_div == 0 )
++ uart_clk_div = 0x100 ;
++
++ if( uart_clk_sel == 0 ) {
++ /* uart_clk_sel = 0 -> external reference clock source */
++ clk = ref_clk ;
++ BUG_ON( !clk );
++ clk_rate = clk_get_rate(clk);
++ } else if( uart_clk_sel == 1 ) {
++ /* uart_clk_sel = 1 -> Internal clock optionally divided */
++ clk = clk_get_sys( "iproc_slow", "c_clk125" );
++ BUG_ON( !clk );
++#if defined(CONFIG_MACH_IPROC_EMULATION)
++ clk_rate = IPROC_UART_CLK ;
++#else
++ clk_rate = clk_get_rate(clk) ;
++#endif
++
++ if( ! uart_clk_ovr )
++ clk_rate /= uart_clk_div;
++ }
++
++ printk( KERN_INFO "Sel=%d Ovr=%d Div=%d\n", uart_clk_sel, uart_clk_ovr, uart_clk_div );
++ printk( KERN_INFO "UART clock rate %u\n", clk_rate );
++#endif /* !CONFIG_MACH_IPROC_P7 */
++
++ modelnum = brcm_get_hx4_model();
++ if (modelnum == HX4_ACCTON_AS4610_54) {
++ for(i = 0; i < ARRAY_SIZE(uart_data); i++ ) {
++ switch (i) {
++ case 0:
++ uart_data[i].membase = (void __iomem *)(IPROC_UART1_VA);
++ uart_data[i].mapbase = (resource_size_t)(IPROC_UART1_PA);
++ uart_data[i].irq = IRQ_IPROC_UART0;
++ uart_data[i].uartclk = IPROC_UART_CLK;
++ uart_data[i].regshift = 0;
++ uart_data[i].iotype = UPIO_MEM;
++ uart_data[i].type = PORT_16550A;
++ uart_data[i].flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ;
++ uart_data[i].private_data = (void __iomem *)((IPROC_UART1_VA) + 0x00);
++ break;
++ case 1:
++ uart_data[i].membase = (void __iomem *)(IPROC_UART2_VA);
++ uart_data[i].mapbase = (resource_size_t)(IPROC_UART2_PA);
++ uart_data[i].irq = 124;
++ uart_data[i].uartclk = IPROC_APB_CLK;
++ uart_data[i].regshift = 2;
++ uart_data[i].iotype = UPIO_MEM32;
++ uart_data[i].type = PORT_16550A;
++ uart_data[i].flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ;
++ uart_data[i].private_data = (void __iomem *)((IPROC_UART2_VA) + 0x00);
++ break;
++ }
++ }
++ }
++
++ /* fixup UART port structure */
++ for(i = 0; i < ARRAY_SIZE(uart_data); i++ ) {
++ if( uart_data[i].flags == 0 )
++ break;
++ if( uart_data[i].irq == 0 )
++ uart_data[i].flags |= UPF_AUTO_IRQ;
++
++ /* XXX TBD - UART input clock source and rate */
++ if(i != 1) {
++ uart_data[i].uartclk = clk_rate ;
++ }
++
++ }
++
++ /* Install SoC devices in the system: uarts */
++ platform_device_register(&board_serial_device);
++
++#ifndef CONFIG_MACH_IPROC_P7
++ /* Enable UART interrupt in ChipcommonA */
++ i = readl(IPROC_CCA_INTMASK_VA);
++ i |= 1 << 6;
++ writel(i, IPROC_CCA_INTMASK_VA);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++}
++
++void __init board_add_common_devices(struct clk *ref_clk)
++{
++ /*
++ * Configure boot console
++ */
++ iproc_config_boot_console(ref_clk);
++}
+diff --git a/arch/arm/mach-iproc/common.h b/arch/arm/mach-iproc/common.h
+new file mode 100644
+index 0000000..d49a6b9
+--- /dev/null
++++ b/arch/arm/mach-iproc/common.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __MACH_NORTHSTAR_COMMON_H
++#define __MACH_NORTHSTAR_COMMON_H
++#include
++#include
++#include
++#include
++
++#include
++
++void __init board_add_common_devices(struct clk *ref_clk);
++
++#endif /* __MACH_NORTHSTAR_COMMON_H */
+diff --git a/arch/arm/mach-iproc/flash.c b/arch/arm/mach-iproc/flash.c
+new file mode 100644
+index 0000000..8fd637b
+--- /dev/null
++++ b/arch/arm/mach-iproc/flash.c
+@@ -0,0 +1,375 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++
++#include
++
++#ifdef CONFIG_MTD
++
++#include
++#include
++#include
++
++/* Since GSIO uses bus number 0, QSPI uses bus number 1 */
++#define IPROC_QSPI_BUS_NUMBER (1)
++
++/* Currently NAND controller only supports 2 LUNs */
++#define IPROC_NAND_MAX_LUNS (2)
++
++int brcm_get_hx4_model(void);
++
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++static struct mtd_partition accton_as4610_sflash_partition_map[] = {
++ {
++ .name = "nboot",
++ .offset = 0x00000000,
++ .size = 0x000e0000,
++ },
++ {
++ .name = "shmoo",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x0010000,
++ },
++ {
++ .name = "uboot-env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00010000,
++ },
++ {
++ .name = "onie",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#if defined(CONFIG_MACH_HX4)
++static struct mtd_partition sflash_partition_map[] = {
++ {
++ .name = "boot",
++ .offset = 0x00000000,
++ .size = 640 * 1024,
++ },
++ {
++ .name = "env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 384 * 1024,
++ },
++ {
++ .name = "system",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 15 * 1024 * 1024,
++ },
++ {
++ .name = "rootfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#endif /* Unused code for Accton AS4610-54 and DNI-3448P */
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++static struct mtd_partition dni_3448p_nand_partition_map[] = {
++ {
++ .name = "uboot",
++ .offset = 0x00000000,
++ .size = 0x00100000,
++ },
++ {
++ .name = "uboot-env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00400000,
++ },
++ {
++ .name = "vpd",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00200000,
++ },
++ {
++ .name = "shmoo",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00200000,
++ },
++ {
++ .name = "open",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0xf9500000,
++ },
++ {
++ .name = "onie",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00c00000,
++ },
++ {
++ .name = "onie2",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00c00000,
++ },
++ {
++ .name = "board_eeprom",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00600000,
++ },
++ {
++ .name = "diag",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x02000000,
++ },
++ {
++ .name = "diag2",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x02000000,
++ },
++};
++static struct mtd_partition accton_as4610_nand_partition_map[] = {
++};
++
++static struct mtd_partition nand_partition_map[] = {
++ {
++ .name = "nboot",
++ .offset = 0x00000000,
++ .size = 2 * 1024 * 1024,
++ },
++ {
++ .name = "nenv",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 4 * 1024 * 1024,
++ },
++ {
++ .name = "nsystem",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 10 * 1024 * 1024,
++ },
++ {
++ .name = "nrootfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 48 * 1024 * 1024,
++ },
++ {
++ .name = "ncustfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++enum {
++ HX4_NONE = 0,
++ HX4_DNI_3448P,
++ HX4_ACCTON_AS4610_54
++};
++
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++static int __init
++brcm_setup_spi_master(int cs, int bus_id)
++{
++ struct brcmspi_platform_data pdata;
++ struct platform_device *pdev;
++ const struct resource res[] = {
++ {
++ .start = IPROC_QSPI_IRQ_START,
++ .end = IPROC_QSPI_IRQ_END,
++ .flags = IORESOURCE_IRQ
++ },
++ {
++ .start = QSPI_MSPI_SPCR0_LSB,
++ .end = QSPI_MSPI_DISABLE_FLUSH_GEN + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_BSPI_REGS_REV_ID,
++ .end = QSPI_BSPI_REGS_BSPI_PIO_DATA + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_RAF_START_ADDR,
++ .end = QSPI_RAF_CURR_ADDR + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,
++ .end = QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IPROC_IDM_QSPI_REG_BASE,
++ .end = IPROC_IDM_QSPI_REG_BASE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IPROC_CRU_REG_BASE,
++ .end = IPROC_CRU_REG_BASE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ };
++
++ memset(&pdata, 0, sizeof(pdata));
++ pdata.flash_cs = cs;
++ pdev = platform_device_alloc("qspi_iproc", bus_id);
++ if (!pdev ||
++ platform_device_add_resources(pdev, res, sizeof(res)/sizeof(res[0])) ||
++ platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
++ platform_device_add(pdev)) {
++ platform_device_put(pdev);
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static int __init
++brcm_setup_spi_flash(int cs, int bus_num, int nr_parts, struct mtd_partition *parts)
++{
++ struct spi_board_info board_info;
++ struct flash_platform_data *pdata;
++ struct spi_master *master;
++
++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
++ if (!pdata)
++ return -ENOMEM;
++
++ pdata->nr_parts = nr_parts;
++ pdata->parts = parts;
++
++ memset(&board_info, 0, sizeof(board_info));
++
++ strcpy(board_info.modalias, "m25p80");
++ board_info.bus_num = bus_num;
++ board_info.chip_select = cs;
++ board_info.max_speed_hz = CONFIG_IPROC_QSPI_MAX_HZ;
++ board_info.mode = SPI_MODE_3;
++ board_info.platform_data = pdata;
++
++ master = spi_busnum_to_master(bus_num);
++ if (master) {
++ /* Master driver already loaded */
++ if (spi_new_device(master, &board_info) == NULL) {
++ printk(KERN_WARNING "%s: can't add SPI device\n", __func__);
++ kfree(pdata);
++ return -ENODEV;
++ }
++ } else {
++ /* Master driver not yet loaded, register the board first. */
++ if (spi_register_board_info(&board_info, 1) != 0) {
++ printk(KERN_WARNING "%s: can't register SPI device\n", __func__);
++ kfree(pdata);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++static void __init
++northstar_setup_nand_flash(void)
++{
++ u32 straps;
++ struct platform_device *pdev;
++ struct brcmnand_platform_data pdata;
++ int i, modelnum;
++
++ straps = __REG32(IPROC_DMU_BASE_VA + IPROC_DMU_STRAPS_OFFSET);
++ pdata.strap_boot = ((straps >> IPROC_STRAP_BOOT_DEV_SHIFT) & 3) == 1;
++ pdata.strap_type = (straps >> IPROC_STRAP_NAND_TYPE_SHIFT) & 0xf;
++ pdata.strap_page_size = (straps >> IPROC_STRAP_NAND_PAGE_SHIFT) & 0x3;
++ if (!pdata.strap_boot) {
++ pdata.strap_type &= 0x7;
++ }
++
++ modelnum = brcm_get_hx4_model();
++
++ if (modelnum == HX4_DNI_3448P) {
++ pdata.nr_parts = ARRAY_SIZE(dni_3448p_nand_partition_map);
++ pdata.parts = dni_3448p_nand_partition_map;
++ } else if (modelnum == HX4_ACCTON_AS4610_54) {
++ pdata.nr_parts = ARRAY_SIZE(accton_as4610_nand_partition_map);
++ pdata.parts = accton_as4610_nand_partition_map;
++ } else {
++ pdata.nr_parts = ARRAY_SIZE(nand_partition_map);
++ pdata.parts = nand_partition_map;
++ }
++
++ for(i=0; i 0) {
++ pdata.nr_parts = 0;
++ pdata.parts = NULL;
++ }
++
++ pdata.chip_select = i;
++ pdev = platform_device_alloc("nand_iproc", i);
++ if (!pdev ||
++ platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
++ platform_device_add(pdev)) {
++ platform_device_put(pdev);
++ }
++ }
++}
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++static int __init
++northstar_mtd_setup(void)
++{
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++ if (brcm_get_hx4_model() == HX4_ACCTON_AS4610_54) {
++ /* SPI flash (currently used for primary) */
++ brcm_setup_spi_master(
++ 0,
++ IPROC_QSPI_BUS_NUMBER
++ );
++ brcm_setup_spi_flash(
++ 0,
++ IPROC_QSPI_BUS_NUMBER,
++ ARRAY_SIZE(accton_as4610_sflash_partition_map),
++ accton_as4610_sflash_partition_map
++ );
++ } /* Required only for Accton AS4610 54*/
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++#ifdef CONFIG_MACH_NS
++ /* Don't bring up NAND driver if it's BCM53010 */
++ if ((__REG32(IPROC_IDM_REGISTER_VA + 0xd500) & 0xc) != 0x4)
++#endif /* CONFIG_MACH_NS */
++ northstar_setup_nand_flash();
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++ return 0;
++}
++
++/*
++ * late_initcall means the flash drivers are already loaded, so we control
++ * the order in which the /dev/mtd* devices get created.
++ */
++late_initcall(northstar_mtd_setup);
++
++#endif /* CONFIG_MTD */
+diff --git a/arch/arm/mach-iproc/idm.c b/arch/arm/mach-iproc/idm.c
+new file mode 100644
+index 0000000..444c3fe
+--- /dev/null
++++ b/arch/arm/mach-iproc/idm.c
+@@ -0,0 +1,723 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++
++#include
++#include
++#include
++#include
++
++#ifdef CONFIG_MACH_NSP
++/* this is actually AXI_PCIE_S2 but for HX4, HR2, and KT2 it has been hijacked by CMICD */
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL AXI_PCIE_S2_IDM_IDM_ERROR_LOG_CONTROL
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE AXI_PCIE_S2_IDM_IDM_ERROR_LOG_COMPLETE
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS AXI_PCIE_S2_IDM_IDM_ERROR_LOG_STATUS
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ADDR_LSB
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ID
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS AXI_PCIE_S2_IDM_IDM_ERROR_LOG_FLAGS
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS AXI_PCIE_S2_IDM_IDM_INTERRUPT_STATUS
++
++#endif
++
++#ifdef CONFIG_MACH_NS
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18106900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18106904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18106908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810690C
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18106914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810691C
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18106A00
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810790C
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810791C
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18107A00
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18108900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18108908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810890C
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18108914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810891C
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18108A00
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810990C
++#define DDR_S2_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810991C
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x18109A00
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810A900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810A904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810A908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810A90C
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810A914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810A91C
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810AA00
++
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810B900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810B904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810B908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810B90C
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810B914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810B91C
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810BA00
++
++/* this is actually AXI_PCIE_S2 but for HX4, HR2, and KT2 it has been hijacked by CMICD */
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810C900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810C904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810C908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810C90C
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810C914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810C91C
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810CA00
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1810D900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1810D904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1810D908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810D90C
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1810D914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1810D91C
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1810DA00
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811A900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811A904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811A908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811A90C
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811A914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811A91C
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811AA00
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811B900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811B904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811B908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811B90C
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811B914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811B91C
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811BA00
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811C900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811C904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811C908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811C90C
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811C914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811C91C
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811CA00
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190C
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1812191C
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x1812A900
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18132900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x181312908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18132910
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x18132904
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18132A00
++
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18133900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18133904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x181313908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1813390c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18133910
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x18133904
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18133A00
++
++#define AXIIC_DS_2_IDM_ERROR_LOG_CONTROL 0x18134900
++#define AXIIC_DS_2_IDM_ERROR_LOG_COMPLETE 0x18134904
++#define AXIIC_DS_2_IDM_ERROR_LOG_STATUS 0x181314908
++#define AXIIC_DS_2_IDM_ERROR_LOG_ADDR_LSB 0x1813490c
++#define AXIIC_DS_2_IDM_ERROR_LOG_ID 0x18134910
++#define AXIIC_DS_2_IDM_ERROR_LOG_FLAGS 0x18134904
++#define AXIIC_DS_2_IDM_INTERRUPT_STATUS 0x18134A00
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18135900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18135904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x181315908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1813590c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18135910
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x18135904
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18135A00
++
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18136900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18136904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x181316908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1813690c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18136910
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x18136904
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18136A00
++
++#define IHOST_L2C_INT_MASK 0x19022214
++#define IHOST_GICDIST_enable_set2 0x19021108
++
++#endif
++
++#define IHOST_L2C_INT_MASK_VA HW_IO_PHYS_TO_VIRT(IHOST_L2C_INT_MASK)
++#define IHOST_GICDIST_enable_set2_VA HW_IO_PHYS_TO_VIRT(IHOST_GICDIST_enable_set2)
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_CONTROL)
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_COMPLETE)
++#define IHOST_S1_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_STATUS)
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_ADDR_LSB)
++#define IHOST_S1_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_ID)
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_FLAGS)
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_CONTROL)
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_COMPLETE)
++#define IHOST_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_STATUS)
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define IHOST_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_ID)
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_FLAGS)
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_CONTROL)
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_COMPLETE)
++#define DDR_S1_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_STATUS)
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_ADDR_LSB)
++#define DDR_S1_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_ID)
++#define DDR_S1_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_FLAGS)
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_CONTROL)
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_COMPLETE)
++#define DDR_S2_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_STATUS)
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_ADDR_LSB)
++#define DDR_S2_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_ID)
++#define DDR_S2_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_FLAGS)
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_ID)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_ID)
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_CONTROL)
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_COMPLETE)
++#define ROM_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_STATUS)
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define ROM_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_ID)
++#define ROM_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_FLAGS)
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_CONTROL)
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_COMPLETE)
++#define NAND_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_STATUS)
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define NAND_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_ID)
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_CONTROL)
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_COMPLETE)
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_STATUS)
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define QSPI_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_ID)
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_ID)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_CONTROL)
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_COMPLETE)
++#define SRAM_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_STATUS)
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define SRAM_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_ID)
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_FLAGS)
++
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_ID)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_CONTROL)
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE)
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_STATUS)
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB)
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_ID)
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_FLAGS)
++
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBW_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_STATUS)
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBW_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_ID)
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBX_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_STATUS)
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBX_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_ID)
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_CONTROL)
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE)
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_STATUS)
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB)
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_ID)
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_FLAGS)
++
++#define IDM_ERROR_LOG_ENABLE 0x33A
++#define IDM_ERROR_LOG_CLEAR 0x3
++
++#ifdef CONFIG_MACH_IPROC_P7
++#define IHOST_S0_IDM_IRQ 52
++#define DDR_S1_IDM_IRQ 54
++#define DDR_S2_IDM_IRQ 55
++#define AXI_PCIE_S0_IDM_IRQ 56
++#define AXI_PCIE_S1_IDM_IRQ 57
++#define ROM_S0_IDM_IRQ 58
++#define NAND_IDM_IRQ 59
++#define QSPI_IDM_IRQ 60
++#define SRAM_S0_IDM_IRQ 62
++#define A9JTAG_S0_IDM_IRQ 64
++#define APX_IDM_IRQ 68
++#define CMICD_S0_IDM_IRQ 71
++#define AXIIC_DS_0_IDM_IRQ 78
++#define AXIIC_DS_1_IDM_IRQ 79
++#define AXIIC_DS_2_IDM_IRQ 80
++#define AXIIC_DS_3_IDM_IRQ 81
++#define AXIIC_DS_4_IDM_IRQ 83
++#else
++#define IHOST_S1_IDM_IRQ 62
++#define IHOST_S0_IDM_IRQ 63
++#define DDR_S1_IDM_IRQ 64
++#define DDR_S2_IDM_IRQ 65
++#define AXI_PCIE_S0_IDM_IRQ 66
++#define AXI_PCIE_S1_IDM_IRQ 67
++#define CMICD_S0_IDM_IRQ 68
++#define ROM_S0_IDM_IRQ 69
++#define NAND_IDM_IRQ 70
++#define QSPI_IDM_IRQ 71
++#define SATA_IDM_IRQ 72
++#define A9JTAG_S0_IDM_IRQ 73
++#define SRAM_S0_IDM_IRQ 74
++#define APW_IDM_IRQ 75
++#define APX_IDM_IRQ 76
++#define APBY_S0_IDM_IRQ 77
++#define APBZ_S0_IDM_IRQ 78
++#define AXIIC_DS_0_IDM_IRQ 79
++#define AXIIC_DS_1_IDM_IRQ 80
++#define AXIIC_DS_2_IDM_IRQ 81
++#define AXIIC_DS_3_IDM_IRQ 82
++#define AXIIC_DS_4_IDM_IRQ 83
++#endif
++
++static irqreturn_t idm_timeout_handler(int val, void *ptr)
++{
++ u32 errStat;
++// printk("%s: %d, %d entry\n", __FUNCTION__, __LINE__, val);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, IHOST_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, DDR_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, DDR_S2_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, ROM_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, NAND_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, QSPI_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, SRAM_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBW_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBX_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++// printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++ return IRQ_HANDLED;
++}
++
++int l2cc_interrupt_error_handler(int val, void *ptr)
++{
++ printk("%s: %d, %d entry\n", __FUNCTION__, __LINE__, val);
++ printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++ return 0;
++}
++
++void request_idm_timeout_interrupts(void)
++{
++ u32 l2cc_mask;
++ int ret = 0;
++
++// printk("%s: %d entry\n", __FUNCTION__, __LINE__);
++
++ /* clear all pending idm interrupts */
++ idm_timeout_handler(0, NULL);
++
++ /* enable idm error log for all slaves */
++
++ __raw_writel(IDM_ERROR_LOG_ENABLE, IHOST_S1_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, DDR_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, DDR_S2_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++
++#ifndef CONFIG_MACH_NS
++ __raw_writel(IDM_ERROR_LOG_ENABLE, SRAM_S0_IDM_ERROR_LOG_CONTROL_VA);
++#ifndef CONFIG_MACH_IPROC_P7
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBY_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBW_IDM_IDM_ERROR_LOG_CONTROL_VA);
++#endif
++#endif
++
++ __raw_writel(IDM_ERROR_LOG_ENABLE, ROM_S0_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, NAND_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, QSPI_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBX_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXIIC_DS_0_IDM_ERROR_LOG_CONTROL_VA);
++
++ /* now enable the idm interrupts */
++
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(IHOST_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(IHOST_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(DDR_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(DDR_S2_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXI_PCIE_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXI_PCIE_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(CMICD_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(ROM_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(NAND_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(QSPI_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(SATA_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(A9JTAG_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(SRAM_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APX_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(APW_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APBY_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APBZ_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(AXIIC_DS_0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_2_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_3_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(AXIIC_DS_4_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++// printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++}
+diff --git a/arch/arm/mach-iproc/include/mach/io_map.h b/arch/arm/mach-iproc/include/mach/io_map.h
+new file mode 100644
+index 0000000..01dd6fd
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/io_map.h
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __NORTHSTAR_IO_MAP_H
++#define __NORTHSTAR_IO_MAP_H
++
++#include
++#include
++#include
++
++#define IPROC_CCA_CORE_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_REG_BASE)
++#define IPROC_CCA_UART0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_UART0_REG_BASE)
++#define IPROC_CCB_GPIO_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_GPIO_REG_BASE)
++#define IPROC_CCB_PWM_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_PWM_REG_BASE)
++#define IPROC_CCB_MDIO_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_MDIO_REG_BASE)
++#define IPROC_CCB_RNG_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_RNG_REG_BASE)
++#define IPROC_CCB_TIM0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_TIM0_REG_BASE)
++#define IPROC_CCB_TIM1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_TIM1_REG_BASE)
++#define IPROC_CCB_SRAU_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_SRAU_REG_BASE)
++#define IPROC_CCB_UART0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_UART0_REG_BASE)
++
++#define IPROC_DDRC_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_DDRC_REG_BASE)
++#define IPROC_DMAC_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_DMAC_REG_BASE)
++#define IPROC_PCIE_AXIB0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB0_REG_BASE)
++#define IPROC_PCIE_AXIB1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB1_REG_BASE)
++#define IPROC_PCIE_AXIB2_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB2_REG_BASE)
++
++#define IPROC_SDIO3_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_SDIO3_REG_BASE)
++#define IPROC_USB20_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB20_REG_BASE)
++#define IPROC_USB30_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB30_REG_BASE)
++#define IPROC_USB20_PHY_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB20_PHY_REG_BASE)
++#define IPROC_GMAC0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC0_REG_BASE)
++#define IPROC_GMAC1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC1_REG_BASE)
++#define IPROC_GMAC2_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC2_REG_BASE)
++#define IPROC_GMAC3_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC3_REG_BASE)
++#define IPROC_DMU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_DMU_REG_BASE)
++#define IPROC_CRU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_CRU_REG_BASE)
++#define IPROC_IDM_REGISTER_VA HW_IO_PHYS_TO_VIRT(IPROC_IDM_REG_BASE)
++#define IPROC_USB2D_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB2D_REG_BASE)
++
++#define IPROC_CTF_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_CTF_REG_BASE)
++
++/* ARM9 Private memory region */
++#define PERIPH_BASE IPROC_PERIPH_BASE
++#define IPROC_PERIPH_VA HW_IO_PHYS_TO_VIRT(IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_SCU_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_INT_CTRL_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x100)
++#define IPROC_PERIPH_GLB_TIM_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x200)
++#define IPROC_PERIPH_PVT_TIM_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x600)
++#define IPROC_PERIPH_PVT_WDT_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x620)
++#define IPROC_PERIPH_INT_DISTR_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x1000)
++#define IPROC_L2CC_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x2000)
++
++#define IPROC_ROOT_CLK_VA HW_IO_PHYS_TO_VIRT(IPROC_CLK_WR_ACC_REG_BASE)
++#define IPROC_GICCPU_VA HW_IO_PHYS_TO_VIRT(IPROC_GICCPU_CTL_REG_BASE)
++
++#define CCU_PROF_REG_BASE IPROC_CCU_PROF_CTL_REG_BASE
++#define IPROC_CCU_PROF_CTL_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE)
++#define IPROC_CCU_PROF_SEL_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x004)
++#define IPROC_CCU_PROF_CNT_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x008)
++#define IPROC_CCU_PROF_DBG_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x00C)
++
++#ifdef CONFIG_MACH_CYGNUS
++ #define IPROC_UART_LLDEBUG_PA IPROC_CCA_UART3_REG_BASE
++ #define IPROC_UART_LLDEBUG_VA HW_IO_PHYS_TO_VIRT(IPROC_UART_LLDEBUG_PA)
++#else
++ #define IPROC_UART_LLDEBUG_PA IPROC_CCA_UART0_REG_BASE
++ #define IPROC_UART_LLDEBUG_VA IPROC_CCA_UART0_REG_VA
++#endif
++
++#define IPROC_I2S_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_I2S_REG_BASE)
++
++#endif /*__NORTHSTAR_IO_MAP_H */
+diff --git a/arch/arm/mach-iproc/include/mach/iproc_regs.h b/arch/arm/mach-iproc/include/mach/iproc_regs.h
+new file mode 100644
+index 0000000..460c436
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/iproc_regs.h
+@@ -0,0 +1,824 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __IPROC_REGS_H
++#define __IPROC_REGS_H __FILE__
++#include
++#ifdef CONFIG_MACH_CYGNUS
++#include "socregs-cygnus.h"
++#elif defined(CONFIG_MACH_NS)
++#include "socregs_ns_open.h"
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#include "socregs_ing_open.h"
++#elif defined(CONFIG_MACH_NSP)
++#include "socregs_nsp_open.h"
++#elif defined(CONFIG_MACH_IPROC_P7)
++#include "socregs_p7_open.h"
++#else
++#error "No valid iProc Machine type selected"
++#endif
++
++#if defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_IPROC_P7) || \
++ defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_CPUS (1)
++#else
++#define IPROC_NUM_CPUS (2)
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_IRQS (IPROC_INTERRUPTS_WIDTH)
++#else
++#define IPROC_NUM_IRQS (256)
++#endif /* end of CONFIG_MACH_CYGNUS) */
++
++#define IPROC_CPU0_MIN_INT_PRIORITY (0)
++#define IPROC_CPU1_MIN_INT_PRIORITY (0)
++
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_DDR_MEM_BASE1 (0x02000000)
++#else
++#define IPROC_DDR_MEM_BASE1 (0x0)
++#endif /* end of CONFIG_MACH_CYGNUS */
++
++#if defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_CYGNUS)
++#define IPROC_DDR_MEM_BASE2 (0x60000000)
++#else
++#define IPROC_DDR_MEM_BASE2 (0x80000000)
++#endif
++
++
++/* remap to newer reg file defs */
++#ifndef CONFIG_MACH_NS
++#ifdef CONFIG_MACH_CYGNUS //chandra: todo- has to check
++ #define CCA_CHIPID ICFG_CHIP_ID_REG
++#else
++ #define CCA_CHIPID ChipcommonA_ChipID
++#endif
++
++#define NAND_NAND_FLASH_REV NAND_nand_flash_REVISION
++#define NAND_DIRECT_READ_RD_MISS NAND_direct_read_rd_miss
++#define NAND_ECC_MIPS_CORR NAND_ecc_mips_corr
++#define NAND_NAND_FLASH_FLASH_CACHE127 NAND_nand_flash_FLASH_CACHE127
++#define QSPI_MSPI_SPCR0_LSB QSPI_mspi_SPCR0_LSB
++#define QSPI_MSPI_DISABLE_FLUSH_GEN QSPI_mspi_DISABLE_FLUSH_GEN
++#define QSPI_BSPI_REGS_REV_ID QSPI_bspi_registers_REVISION_ID
++#define QSPI_BSPI_REGS_BSPI_PIO_DATA QSPI_bspi_registers_BSPI_PIO_DATA
++#define QSPI_RAF_START_ADDR QSPI_raf_START_ADDR
++#define QSPI_RAF_CURR_ADDR QSPI_raf_CURR_ADDR
++#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED QSPI_raf_interrupt_LR_fullness_reached
++#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE QSPI_mspi_interrupt_MSPI_halt_set_transaction_done
++
++#define CCB_TIM0_TIM_TMR1_LOAD ChipcommonB_tim0_TIM_TIMER1Load
++#define CCB_TIM1_TIM_TMR1_LOAD ChipcommonB_tim1_TIM_TIMER1Load
++
++#define GMAC0_DEVCT GMAC0_DEVCONTROL
++
++#define CCA_GPIO_EVT_BASE ChipcommonA_GPIOEvent_BASE
++#define CCA_GPIO_INPUT_BASE ChipcommonA_GPIOInput_BASE
++#define CCB_GP_INT_CLR_BASE ChipcommonB_GP_INT_TYPE_BASE
++
++#define PAXB_0_PCIE_CTL (PAXB_0_CLK_CONTROL)
++
++#define CCB_MII_MGMT_CTL ChipcommonB_MII_Management_Control
++
++#endif
++
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_NSP) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define CCB_RNG_CTRL ChipcommonB_rng_CTRL
++#endif
++
++
++/* the below might be NS specific */
++#ifdef CONFIG_MACH_CYGNUS //chandra: todo- only timers are mapped correctly
++ #define IPROC_CCA_REG_BASE CCA_CHIPID
++ #define IPROC_CCB_GPIO_REG_BASE (CCB_GP_DATA_IN)
++ #define IPROC_CCB_PWM_REG_BASE (CCB_PWMCTL)
++ #define IPROC_CCB_MDIO_REG_BASE (CCB_MII_MGMT_CTL)
++ #define IPROC_CCB_RNG_REG_BASE (CCB_RNG_CTRL)
++ #define IPROC_CCB_TIM0_REG_BASE (ChipcommonG_tim0_TIM_TIMER1Load)
++ #define IPROC_CCB_TIM1_REG_BASE (ChipcommonG_tim1_TIM_TIMER1Load)
++ #define IPROC_CCB_SRAU_REG_BASE (CCB_SRAB_CMDSTAT)
++ #define IPROC_D1W_REG_BASE (ASIU_D1W_DIN)
++ #define IPROC_D1W_INTR (CHIP_INTR1__ASIU_D1W_INTR)
++ #define IPROC_D1W_CLK_GATE_CTRL (ASIU_TOP_CLK_GATING_CTRL)
++ #define IPROC_D1W_IO_MUX_REG (CRMU_IOMUX_CTRL4)
++
++ #define IPROC_KEYPAD_INTR (ASIU_INTR_STATUS__asiu_keypad_intr)
++ #define IPROC_KEYPAD_REG_BASE (KEYPAD_TOP_REGS_KPCR)
++ #define IPROC_KEYPAD_TOP_REGS_KPCR (KEYPAD_TOP_REGS_KPCR)
++ #define IPROC_KEYPAD_TOP_REGS_KPIOR (KEYPAD_TOP_REGS_KPIOR)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR0 (KEYPAD_TOP_REGS_KPEMR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR1 (KEYPAD_TOP_REGS_KPEMR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR2 (KEYPAD_TOP_REGS_KPEMR2)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR3 (KEYPAD_TOP_REGS_KPEMR3)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR0 (KEYPAD_TOP_REGS_KPSSR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR1 (KEYPAD_TOP_REGS_KPSSR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPIMR0 (KEYPAD_TOP_REGS_KPIMR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPIMR1 (KEYPAD_TOP_REGS_KPIMR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPICR0 (KEYPAD_TOP_REGS_KPICR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPICR1 (KEYPAD_TOP_REGS_KPICR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPISR0 (KEYPAD_TOP_REGS_KPISR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPISR1 (KEYPAD_TOP_REGS_KPISR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR0 (KEYPAD_TOP_REGS_KPSSR0)
++ #define IPROC_CRMU_ASIU_KEYPAD_CLK_DIV (CRMU_ASIU_KEYPAD_CLK_DIV)
++ #define IPROC_IO_MUX_REG_BASE (CRMU_IOMUX_CTRL1)
++ #define IPROC_CLK_GATING_CTRL (ASIU_TOP_CLK_GATING_CTRL)
++ #define IPROC_KEYPAD_CLK_GATE_EN_BIT (ASIU_TOP_CLK_GATING_CTRL__KEYPAD_CLK_GATE_EN)
++
++ #define IPROC_TSC_REG_BASE (TSCRegCtl1)
++ #define IPROC_TSC_INTR (ASIU_INTR_STATUS__asiu_touch_screen_intr)
++ #define IPROC_ADC_REG_BASE (TSCRegCtl1)
++ #define IPROC_ADC_INTR (ASIU_INTR_STATUS__asiu_touch_screen_intr)
++// #define IPROC_CCB_UART0_REG_BASE (CCB_UART0_RBR_THR_DLL)
++#else
++#define IPROC_CCA_REG_BASE CCA_CHIPID
++#define IPROC_CCB_GPIO_REG_BASE (IPROC_GPIO_CCB_BASE)
++#define IPROC_CCB_PWM_REG_BASE (CCB_PWMCTL)
++#define IPROC_CCB_MDIO_REG_BASE (CCB_MII_MGMT_CTL)
++#define IPROC_CCB_RNG_REG_BASE (CCB_RNG_CTRL)
++#define IPROC_CCB_TIM0_REG_BASE (CCB_TIM0_TIM_TMR1_LOAD)
++#define IPROC_CCB_TIM1_REG_BASE (CCB_TIM1_TIM_TMR1_LOAD)
++#define IPROC_CCB_SRAU_REG_BASE (CCB_SRAB_CMDSTAT)
++#define CCB_UART0_RBR_THR_DLL (0x18037000)
++#define IPROC_CCB_UART0_REG_BASE (CCB_UART0_RBR_THR_DLL)
++#endif /* end of CONFIG_MACH_CYGNUS */
++
++/* iProc Profile 7 specific remapping */
++#if defined(CONFIG_MACH_IPROC_P7)
++
++#define ChipcommonA_ChipID (ICFG_CHIP_ID_REG)
++#define IPROC_CCA_UART0_REG_BASE (ChipcommonG_UART0_UART_RBR_THR_DLL)
++#define IPROC_CCA_UART1_REG_BASE (ChipcommonG_UART1_UART_RBR_THR_DLL)
++#define IPROC_CCS_RNG_REG_BASE (ChipcommonS_RNG_CTRL)
++
++#else /* !CONFIG_MACH_IPROC_P7 */
++
++#define IPROC_CCA_BASE IPROC_CCA_REG_BASE
++#define IPROC_CCA_CORE_CAP_REG_BASE (IPROC_CCA_BASE + 0x04)
++#define IPROC_CCA_CORE_CTL_REG_BASE (IPROC_CCA_BASE + 0x08)
++
++#if defined(CONFIG_MACH_CYGNUS)
++ #define IPROC_CCA_UART0_REG_BASE (ChipcommonG_UART0_UART_RBR_THR_DLL) //(IPROC_CCA_BASE + 0x300) //chandra:
++ #define IPROC_CCA_UART1_REG_BASE (ChipcommonG_UART1_UART_RBR_THR_DLL) //(IPROC_CCA_BASE + 0x400)
++ #define IPROC_CCA_UART2_REG_BASE (ChipcommonG_UART2_UART_RBR_THR_DLL)
++ #define IPROC_CCA_UART3_REG_BASE (ChipcommonG_UART3_UART_RBR_THR_DLL)
++ #define IPROC_CCA_UART4_REG_BASE (ChipcommonG_UART4_UART_RBR_THR_DLL)
++#else
++#define IPROC_CCA_UART0_REG_BASE (IPROC_CCA_BASE + 0x300)
++#define IPROC_CCA_UART1_REG_BASE (IPROC_CCA_BASE + 0x400)
++#endif /*end of CYGNUS */
++#define IPROC_CCA_INTMASK_REG_BASE (IPROC_CCA_BASE + 0x24)
++#define IPROC_CCA_UART_CLK_REG_BASE (IPROC_CCA_BASE + 0xa4)
++
++#endif /* CONFIG_MACH_IPROC_P7 */
++
++#define IPROC_CLK_WR_ACC_REG_BASE (0x19000000)
++#define IPROC_CLK_WR_ACC_REG_OFFSET (0x000)
++#define IPROC_CLK_POLICY_FREQ_REG (0x19000008)
++#define IPROC_CLK_POLICY_FREQ_OFFSET (0x008)
++#define IPROC_CLK_POLICY_CTL_REG (0x1900000C)
++#define IPROC_CLK_POLICY_CTL_OFFSET (0x00C)
++#define IPROC_CLK_POLICY0_MSK_REG (0x19000010)
++#define IPROC_CLK_POLICY0_MSK_OFFSET (0x010)
++#define IPROC_CLK_POLICY1_MSK_REG (0x19000014)
++#define IPROC_CLK_POLICY1_MSK_OFFSET (0x014)
++#define IPROC_CLK_POLICY2_MSK_REG (0x19000018)
++#define IPROC_CLK_POLICY2_MSK_OFFSET (0x018)
++#define IPROC_CLK_POLICY3_MSK_REG (0x1900001C)
++#define IPROC_CLK_POLICY3_MSK_OFFSET (0x01C)
++#define IPROC_CLK_INT_EN_REG (0x19000020)
++#define IPROC_CLK_INT_EN_OFFSET (0x020)
++#define IPROC_CLK_INT_STAT_REG (0x19000024)
++#define IPROC_CLK_INT_STAT_OFFSET (0x024)
++#define IPROC_CLK_LVM_EN_REG (0x19000034)
++#define IPROC_CLK_LVM_EN_OFFSET (0x034)
++#define IPROC_CLK_LVM0_3_REG (0x19000038)
++#define IPROC_CLK_LVM0_3_OFFSET (0x038)
++#define IPROC_CLK_LVM4_7_REG (0x1900003C)
++#define IPROC_CLK_LVM4_7_OFFSET (0x03C)
++#define IPROC_CLK_VLT0_3_REG (0x19000040)
++#define IPROC_CLK_VLT0_3_OFFSET (0x040)
++#define IPROC_CLK_VLT4_7_REG (0x19000044)
++#define IPROC_CLK_VLT4_7_OFFSET (0x044)
++#define IPROC_CLK_BUS_QUIESC_REG (0x19000100)
++#define IPROC_CLK_BUS_QUIESC_OFFSET (0x100)
++#define IPROC_CLK_CORE0_GATE_REG (0x19000200)
++#define IPROC_CLK_CORE0_GATE_OFFSET (0x200)
++#define IPROC_CLK_CORE1_GATE_REG (0x19000204)
++#define IPROC_CLK_CORE1_GATE_OFFSET (0x204)
++#define IPROC_CLK_ARM_SW_GATE_REG (0x19000210)
++#define IPROC_CLK_ARM_SW_GATE_OFFSET (0x210)
++#define IPROC_CLK_ARM_PERIPH_GATE_REG (0x19000300)
++#define IPROC_CLK_ARM_PERIPH_GATE_OFFSET (0x300)
++#define IPROC_CLK_APB0_CLKGATE_REG (0x19000400)
++#define IPROC_CLK_APB0_CLKGATE_OFFSET (0x400)
++#define IPROC_CLK_PL310_DIV_REG (0x19000A00)
++#define IPROC_CLK_PL310_DIV_OFFSET (0xA00)
++#define IPROC_CLK_PL310_TRG_REG (0x19000A04)
++#define IPROC_CLK_PL310_TRG_OFFSET (0xA04)
++#define IPROC_CLK_ARM_SW_DIV_REG (0x19000A08)
++#define IPROC_CLK_ARM_SW_DIV_OFFSET (0xA08)
++#define IPROC_CLK_ARM_SW_TRG_REG (0x19000A0C)
++#define IPROC_CLK_ARM_SW_TRG_OFFSET (0xA0C)
++#define IPROC_CLK_APB_SW_DIV_REG (0x19000A10)
++#define IPROC_CLK_APB_SW_DIV_OFFSET (0xA10)
++#define IPROC_CLK_APB_SW_TRG_REG (0x19000A14)
++#define IPROC_CLK_APB_SW_TRG_OFFSET (0xA14)
++#define IPROC_CLK_PLL_ARMA_REG (0x19000C00)
++#define IPROC_CLK_PLL_ARMA_OFFSET (0xC00)
++#define IPROC_CLK_PLL_ARMB_REG (0x19000C04)
++#define IPROC_CLK_PLL_ARMB_OFFSET (0xC04)
++#define IPROC_CLK_PLL_ARMC_REG (0x19000C08)
++#define IPROC_CLK_PLL_ARMC_OFFSET (0xC08)
++#define IPROC_CLK_PLL_ARMCTL0_REG (0x19000C0C)
++#define IPROC_CLK_PLL_ARMCTL0_OFFSET (0xC0C)
++#define IPROC_CLK_PLL_ARMCTL1_REG (0x19000C10)
++#define IPROC_CLK_PLL_ARMCTL1_OFFSET (0xC10)
++#define IPROC_CLK_PLL_ARMCTL2_REG (0x19000C14)
++#define IPROC_CLK_PLL_ARMCTL2_OFFSET (0xC14)
++#define IPROC_CLK_PLL_ARMCTL3_REG (0x19000C18)
++#define IPROC_CLK_PLL_ARMCTL3_OFFSET (0xC18)
++#define IPROC_CLK_PLL_ARMCTL4_REG (0x19000C1C)
++#define IPROC_CLK_PLL_ARMCTL4_OFFSET (0xC1C)
++#define IPROC_CLK_PLL_ARMCTL5_REG (0x19000C20)
++#define IPROC_CLK_PLL_ARMCTL5_OFFSET (0xC20)
++#define IPROC_CLK_PLL_ARM_OFFSET_REG (0x19000C24)
++#define IPROC_CLK_PLL_ARM_OFFSET_OFFSET (0xC24)
++#define IPROC_CLK_ARM_DIV_REG (0x19000E00)
++#define IPROC_CLK_ARM_DIV_OFFSET (0xE00)
++#define IPROC_CLK_ARM_SEG_TRG_REG (0x19000E04)
++#define IPROC_CLK_ARM_SEG_TRG_OFFSET (0xE04)
++#define IPROC_CLK_ARM_SEG_TRG_OVRD_REG (0x19000E08)
++#define IPROC_CLK_ARM_SEG_TRG_OVRD_OFFSET (0xE08)
++#define IPROC_CLK_PLL_DEBUG_REG (0x19000E10)
++#define IPROC_CLK_PLL_DEBUG_OFFSET (0xE10)
++#define IPROC_CLK_ACTIVITY_MON1_REG (0x19000E20)
++#define IPROC_CLK_ACTIVITY_MON1_OFFSET (0xE20)
++#define IPROC_CLK_ACTIVITY_MON2_REG (0x19000E24)
++#define IPROC_CLK_ACTIVITY_MON2_OFFSET (0xE24)
++#define IPROC_CLK_GATE_DBG_REG (0x19000E40)
++#define IPROC_CLK_GATE_DBG_OFFSET (0xE40)
++#define IPROC_CLK_APB_CLKGATE_DBG1_REG (0x19000E48)
++#define IPROC_CLK_APB_CLKGATE_DBG1_OFFSET (0xE48)
++#define IPROC_CLK_CLKMON_REG (0x19000E64)
++#define IPROC_CLK_CLKMON_OFFSET (0xE64)
++#define IPROC_CLK_KPROC_CCU_PROF_CTL_REG (0x19000E90)
++#define IPROC_CLK_KPROC_CCU_PROF_CTL_OFFSET (0xE90)
++#define IPROC_CLK_KPROC_CCU_PROF_SEL_REG (0x19000E94)
++#define IPROC_CLK_KPROC_CCU_PROF_SEL_OFFSET (0xE94)
++#define IPROC_CLK_KPROC_CCU_PROF_CNT_REG (0x19000E98)
++#define IPROC_CLK_KPROC_CCU_PROF_CNT_OFFSET (0xE98)
++#define IPROC_CLK_KPROC_CCU_PROF_DBG_REG (0x19000E9C)
++#define IPROC_CLK_KPROC_CCU_PROF_DBG_OFFSET (0xE9C)
++#define IPROC_CLK_POLICY_DBG_REG (0x19000EC0)
++#define IPROC_CLK_POLICY_DBG_OFFSET (0xEC0)
++#define IPROC_CLK_TGTMASK_DBG1_REG (0x19000EC4)
++#define IPROC_CLK_TGTMASK_DBG1_OFFSET (0xEC4)
++#define IPROC_RST_WR_ACCESS_REG (0x19000F00)
++#define IPROC_RST_WR_ACCESS_OFFSET (0xF00)
++#define IPROC_RST_SOFT_RSTN_REG (0x19000F04)
++#define IPROC_RST_SOFT_RSTN_OFFSET (0xF04)
++#define IPROC_RST_A9C_SOFT_RSTN_REG (0x19000F08)
++#define IPROC_RST_A9C_SOFT_RSTN_OFFSET (0xF08)
++#define IPROC_RST_A9CORE_SOFT_RSTN_REG (0x19000F08)
++#define IPROC_RST_A9CORE_SOFT_RSTN_OFFSET (0xF08)
++
++#define PLLARMC_PLLARM_MDIV_SHIFT 0
++#define PLLARMC_PLLARM_LOAD_EN_MASK (0x00000800)
++#define PLLARMA_PLLARM_NDIV_INT_MASK (0x0003FF00)
++#define PLLARMA_PLLARM_NDIV_INT_SHIFT 8
++#define PLLARMB_PLLARM_NDIV_FRAC_MASK (0x000FFFFF)
++#define PLLARMB_PLLARM_NDIV_FRAC_SHIFT 0
++#define ARMCTL5_PLLARM_H_MDIV_MASK (0x000000FF)
++#define ARMCTL5_PLLARM_H_MDIV_SHIFT 0
++
++#define IPROC_CLK_CTL_REG (IPROC_CCA_CLK_CTL_REG_BASE + 0x000)
++#define IPROC_CCA_CLK_HW_REQ_OFF 0x00000020
++
++#define IPROC_DDRC_REG_BASE (DDR_DENALI_CTL_00) //(0x18010000)
++#define IPROC_DMAC_REG_BASE (DMAC_P1330_NON_DS) //(0x1802C000)
++#define IPROC_PCIE_AXIB0_REG_BASE (PAXB_0_PCIE_CTL) //(0x18012000)
++#define IPROC_PCIE_AXIB1_REG_BASE (PAXB_1_PCIE_CTL) //(0x18013000)
++#define IPROC_PCIE_AXIB2_REG_BASE (PAXB_2_PCIE_CTL) //(0x18014000)
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_SDIO3_REG_BASE (SDIO_EMMC_SDXC_SYSADDR) //(0x18020000)
++#define IPROC_SDIO_IDM_RESET_CONTROL (0x16800)
++#define IPROC_SDIO_IRQ (177)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT (0x18116408)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE (22)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_SDIO3_REG_BASE (SDIO_eMMCSDXC_SYSADDR)
++#define IPROC_SDIO_IDM_RESET_CONTROL (0x17800)
++#define IPROC_SDIO_IRQ (177)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT (SDIO_IDM_IO_CONTROL_DIRECT)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE (SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE)
++
++#endif
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_USB20_REG_BASE (0x18021000)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_NSP) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_USB20_REG_BASE (0x1802A000)
++#define IPROC_UDC_IRQ (238)
++#endif
++#define IPROC_USB30_REG_BASE (0x18023000)
++//#define IPROC_USB30_REG_BASE (0x18022000)
++#define IPROC_USB20_PHY_REG_BASE (0x18023000) /* ??*/
++
++#if (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_USB2D_REG_BASE USB2D_ENDPNT_IN_CTRL_0
++#define IPROC_USB2D_REG_SIZE (0x2000) /* 8KB */
++#endif
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_NUM_GMACS 4
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCTL) //(0x18024000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCTL) //(0x18025000)
++#define IPROC_GMAC2_REG_BASE (GMAC2_DEVCTL) //(0x18026000)
++#define IPROC_GMAC3_REG_BASE (GMAC3_DEVCTL) //(0x18027000)
++#define IPROC_GMAC0_INT 179
++#define IPROC_GMAC1_INT 180
++#define IPROC_GMAC2_INT 181
++#define IPROC_GMAC3_INT 182
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_NUM_GMACS 2
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCONTROL) //(0x18023000)
++#define IPROC_GMAC2_REG_BASE (0) // n/a
++#define IPROC_GMAC3_REG_BASE (0) // n/a
++#define IPROC_GMAC0_INT 234
++#define IPROC_GMAC1_INT 235
++#define IPROC_GMAC2_INT 0 // n/a
++#define IPROC_GMAC3_INT 0 // n/a
++#elif defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_GMACS 1
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (0) // n/a
++#define IPROC_GMAC2_REG_BASE (0) // n/a
++#define IPROC_GMAC3_REG_BASE (0) // n/a
++#define IPROC_GMAC0_INT 234
++#define IPROC_GMAC1_INT 0 // n/a
++#define IPROC_GMAC2_INT 0 // n/a
++#define IPROC_GMAC3_INT 0 // n/a
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_NUM_GMACS 4
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCONTROL) //(0x18023000)
++#define IPROC_GMAC2_REG_BASE (FA_GMAC0_DEVCONTROL) //(0x18024000)
++#define IPROC_GMAC3_REG_BASE (FA_GMAC1_DEVCONTROL) //(0x18025000)
++#define IPROC_GMAC0_INT 179
++#define IPROC_GMAC1_INT 180
++#define IPROC_GMAC2_INT 181
++#define IPROC_GMAC3_INT 182
++#endif
++
++#define IPROC_CTF_REG_BASE (0x18027C00)
++
++#define IPROC_I2S_REG_BASE (0x1802A000)
++#define IPROC_CCU_PROF_CTL_REG_BASE (0x19000E90)
++
++/* IDM / CRU / DMU */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CRU_REG_BASE (0x1800b000)
++#define IPROC_DMU_REG_BASE (0x1800c000)
++#define IPROC_IDM_REG_BASE (0x18100000)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined (CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_CRU_REG_BASE CRU_control
++#define IPROC_DMU_REG_BASE DMU_PCU_IPROC_CONTROL
++#define IPROC_IDM_REG_BASE (IHOST_M0_IO_CONTROL_DIRECT - 0x408)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_CRU_REG_BASE CRU_control
++#define IPROC_DMU_REG_BASE PCU_MDIO_MGT
++
++#define IPROC_IDM_REG_BASE (IHOST_M0_IO_CONTROL_DIRECT - 0x408)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_CRU_REG_BASE (CRU_control)
++#define IPROC_DMU_REG_BASE DMU_S0_IDM_IDM_RESET_CONTROL
++#endif
++#ifndef CONFIG_MACH_GH
++#define DMU_PCU_IPROC_CONTROL 0x1803f000
++#endif
++
++/* Straps */
++#if defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP)
++#define IPROC_DMU_STRAPS_OFFSET (0x2a0)
++#define IPROC_STRAP_BOOT_DEV_SHIFT (16)
++#define IPROC_STRAP_NAND_TYPE_SHIFT (12)
++#define IPROC_STRAP_NAND_PAGE_SHIFT (10)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_DMU_STRAPS_OFFSET DMU_PCU_IPROC_STRAPS_CAPTURED_BASE
++#define IPROC_STRAP_BOOT_DEV_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R
++#define IPROC_STRAP_NAND_TYPE_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R
++#define IPROC_STRAP_NAND_PAGE_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R
++#endif
++#define IPROC_STRAP_BOOT_DEV_QSPI (0)
++#define IPROC_STRAP_BOOT_DEV_NAND (1)
++#define IPROC_STRAP_BOOT_DEV_PNOR (4)
++
++/* NAND and QSPI */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_IDM_NAND_REG_BASE (0x1811a408)
++#define IPROC_NAND_IRQ_START (100)
++#define IPROC_IDM_QSPI_REG_BASE (0x1811b408)
++#define IPROC_QSPI_IRQ_START (104)
++#define IPROC_QSPI_IRQ_END (109)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (100)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (104)
++#define IPROC_QSPI_IRQ_END (109)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (106)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (110)
++#define IPROC_QSPI_IRQ_END (116)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (IPROC_INTERRUPTS__chipcommonG_spi0_intr)
++#define IPROC_QSPI_IRQ_END (IPROC_INTERRUPTS__chipcommonG_spi5_intr)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (101)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (102)
++#define IPROC_QSPI_IRQ_END (102)
++#endif
++
++/* PNOR */
++#ifdef CONFIG_MACH_IPROC_P7
++#define S29GL_FLASH_SIZE 0x04000000
++#define S29GL_FLASH_PHYS 0xe8000000
++#define PNOR_NAND_SEL_REG ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL
++#define PNOR_NAND_SEL_REG_OVERRIDE ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel_sw_ovwr
++#define PNOR_NAND_SEL_REG_PNOR_SEL ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel
++#elif defined(CONFIG_MACH_HR2)
++#define S29GL_FLASH_SIZE 0x04000000
++#define S29GL_FLASH_PHYS 0x20000000
++#define PNOR_NAND_SEL_REG 0x1803fc3c
++#define PNOR_NAND_SEL_REG_OVERRIDE 2
++#define PNOR_NAND_SEL_REG_PNOR_SEL 3
++#endif
++
++/* ARM9 Private memory region */
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_PERIPH_BASE (IHOST_SCU_CONTROL)//chandra:
++#else
++#define IPROC_PERIPH_BASE (0x19020000) //(IHOST_A9MP_scu_CONTROL)
++#endif
++#define IPROC_PERIPH_SCU_REG_BASE (IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100)
++#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
++#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600)
++#define IPROC_PERIPH_PVT_WDT_REG_BASE (IPROC_PERIPH_BASE + 0x620)
++#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000)
++#define IPROC_L2CC_REG_BASE (IPROC_PERIPH_BASE + 0x2000)
++#define IPROC_GTIM_GLB_LO (0x00000000)
++#define IPROC_GTIM_GLB_HI (0x00000004)
++#define IPROC_GTIM_GLB_CTL (0x00000008)
++#define IPROC_GTIM_GLB_STS (0x0000000C)
++#define IPROC_GTIM_GLB_CMP_LO (0x00000010)
++#define IPROC_GTIM_GLB_CMP_HI (0x00000014)
++#define IPROC_GTIM_GLB_INCR (0x00000018)
++
++/* Structures and bit definitions */
++/* SCU Control register */
++#define IPROC_SCU_CTRL_SCU_EN (0x00000001)
++#define IPROC_SCU_CTRL_ADRFLT_EN (0x00000002)
++#define IPROC_SCU_CTRL_PARITY_EN (0x00000004)
++#define IPROC_SCU_CTRL_SPEC_LNFL_EN (0x00000008)
++#define IPROC_SCU_CTRL_FRC2P0_EN (0x00000010)
++#define IPROC_SCU_CTRL_SCU_STNDBY_EN (0x00000020)
++#define IPROC_SCU_CTRL_IC_STNDBY_EN (0x00000040)
++
++/* ARM A9 Private Timer */
++#define IPROC_PVT_TIM_CTRL_TIM_EN (0x00000001)
++#define IPROC_PVT_TIM_CTRL_AUTO_RELD (0x00000002)
++#define IPROC_PVT_TIM_CTRL_INT_EN (0x00000004)
++#define IPROC_PVT_TIM_CTRL_PRESC_MASK (0x0000FF00)
++#define IPROC_PVT_TIM_INT_STATUS_SET (0x00000001)
++
++/* Global timer */
++#define IPROC_GLB_TIM_CTRL_STCS_EN (0x00000000)
++#define IPROC_GLB_TIM_CTRL_TIM_EN (0x00000001)
++#define IPROC_GLB_TIM_CTRL_COMP_EN (0x00000002)
++#define IPROC_GLB_TIM_CTRL_INT_EN (0x00000004)
++#define IPROC_GLB_TIM_CTRL_AUTO_INC (0x00000008)
++#define IPROC_GLB_TIM_CTRL_STCM_SET (0x0000000C)
++#define IPROC_GLB_TIM_CTRL_PRESC_MASK (0x0000FF00)
++#define IPROC_GLB_TIM_INT_STATUS_SET (0x00000001)
++
++#define GLBTMR_GLOB_STATUS_EVENT_G_SHIFT (0x00000000)
++#define GLBTMR_GLOB_CTRL_TIMER_EN_G_SHIFT (0x00000000)
++
++/* GIC(Generic Interrupt controller) CPU interface registers */
++#if defined(CONFIG_MACH_CYGNUS)
++ #define IPROC_GICCPU_CTL_REG_BASE (IHOST_GICCPU_CONTROL)
++#else
++ #define IPROC_GICCPU_CTL_REG_BASE (0x19020100)
++#endif
++#define IPROC_GICCPU_PRI_MASK_OFFSET (0x04)
++#define IPROC_GICCPU_BIN_PT_OFFSET (0x08)
++#define IPROC_GICCPU_INT_ACK_OFFSET (0x0C)
++#define IPROC_GICCPU_EOI_OFFSET (0x10)
++#define IPROC_GICCPU_RUN_PRI_OFFSET (0x14)
++#define IPROC_GICCPU_HI_PEND_OFFSET (0x18)
++#define IPROC_GICCPU_ALIAS_BIN_PT_NS_OFFSET (0x1C)
++#define IPROC_GICCPU_INT_GFC_OFFSET (0x40)
++#define IPROC_GICCPU_INT_FIQ_SET_OFFSET (0x44)
++#define IPROC_GICCPU_INTEG_MATCH_OFFSET (0x50)
++#define IPROC_GICCPU_INTEG_ENABLE_OFFSET (0x54)
++#define IPROC_GICCPU_CPU_IDENT_OFFSET (0xFC)
++
++#define IPROC_GIC_CI_CTRL_EN (0x00000001)
++#define IPROC_GIC_CI_PMR_PRIO_MASK (0x000000FF)
++#define IPROC_GIC_CI_BPR_BP_MASK (0x00000003)
++#define IPROC_GIC_CI_IAR_INTID_MASK (0x000003FF)
++#define IPROC_GIC_CI_IAR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_IAR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_EOIR_INTID_MASK (0x000003FF)
++#define IPROC_GIC_CI_EOIR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_EOIR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_RPR_PRIO_MASK (0x000000FF)
++#define IPROC_GIC_CI_HPIR_PENDID_MASK (0x000003FF)
++#define IPROC_GIC_CI_HPIR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_HPIR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_ABPR_BP_MASK (0x00000003)
++
++#define IPROC_GIC_DIST_CTRL_S_EN_S (0x00000001)
++#define IPROC_GIC_DIST_CTRL_S_EN_NS (0x00000002)
++#define IPROC_GIC_DIST_CTRL_NS_EN_NS (0x00000001)
++
++#define IPROC_GIC_DIST_ISR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISER_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ICER_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISPR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISPR_SECURE (1)
++#define IPROC_GIC_DIST_ISPR_NON_SECURE (0)
++#define IPROC_GIC_DIST_ICPR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_IPR_BIT_SIZE (8)
++#define IPROC_GIC_DIST_IPTR_BIT_SIZE (8)
++#define IPROC_GIC_DIST_IPTR_CPU0 (0x01)
++#define IPROC_GIC_DIST_IPTR_CPU1 (0x02)
++#define IPROC_GIC_DIST_SGIR_ID_MASK (0xF)
++#define IPROC_GIC_DIST_SGIR_TR_LIST_MASK (0x00FF0000)
++#define IPROC_GIC_DIST_SGIR_TR_LIST_BOFFSET (16)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_MASK (0x03000000)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_BOFFSET (24)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_LIST (0)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_ALL_EX_ME (0x01)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_ME_ONLY (0x02)
++
++#define IPROC_INTR_LEVEL_SENSITIVE (1)
++#define IPROC_INTR_EDGE_TRIGGERED (2)
++
++/* GPIO Driver */
++#if defined(CONFIG_IPROC_GPIO) || defined(CONFIG_IPROC_GPIO_MODULE) || \
++ defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++
++/* Chipcommon A GPIO */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CCA_INT_STS (CCA_INT_STS_BASE)
++#define IPROC_CCA_INT_MASK (CCA_INT_MASK_BASE)
++#define IPROC_GPIO_CCA_BASE (CCA_GPIO_INPUT)
++#define IPROC_GPIO_CCA_DIN (CCA_GPIO_INPUT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_DOUT (CCA_GPIO_OUT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_EN (CCA_GPIO_OUT_EN_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL (CCA_GPIO_INT_POLARITY_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL_MASK (CCA_GPIOINT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT (CCA_GPIO_EVT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT_MASK (CCA_GPIO_EVTINT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_WATCHDOG_COUNTER (CCA_WDOG_CTR_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EDGE (CCA_GPIO_EVT_INT_POLARITY_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_TIMER_VAL (CCA_GPIO_TMR_VAL_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_TIMEOUT_MASK (CCA_GPIO_TMR_OUT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_CLK_DIV (CCA_CLK_DIV_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_DEBUG (CCA_GPIODBG_SEL_BASE - CCA_GPIO_INPUT_BASE)
++
++#define IPROC_DMU_BASE (0x1800c000)
++
++#define IPROC_GPIO_CCA_PULL_UP (0x01dc)
++#define IPROC_GPIO_CCA_PULL_DOWN (0x01e0)
++#define IPROC_GPIO_CCA_CTRL0 (0x01c0)
++
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_NSP, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_CCA_INT_STS (ChipcommonA_IntStatus_BASE)
++#define IPROC_CCA_INT_MASK (ChipcommonA_IntMask_BASE)
++#define IPROC_GPIO_CCA_BASE (ChipcommonA_GPIOInput)
++#define IPROC_GPIO_CCA_DIN (ChipcommonA_GPIOInput_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_DOUT (ChipcommonA_GPIOOut_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_EN (ChipcommonA_GPIOOutEn_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL (ChipcommonA_GPIOIntPolarity_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL_MASK (ChipcommonA_GPIOIntMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT (ChipcommonA_GPIOEvent_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT_MASK (ChipcommonA_GPIOEventIntMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_WATCHDOG_COUNTER (ChipcommonA_WatchdogCounter_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EDGE (ChipcommonA_GPIOEventIntPolarity_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_TIMER_VAL (ChipcommonA_GPIOTimerVal_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_TIMEOUT_MASK (ChipcommonA_GPIOTimerOutMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_CLK_DIV (ChipcommonA_ClkDiv_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_DEBUG (ChipcommonA_GPIODebugSel_BASE - ChipcommonA_GPIOInput_BASE)
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++#define IPROC_DMU_BASE (DMAC_pl330_DS)
++#define IPROC_GPIO_CCA_PULL_UP (CRU_GPIO_CONTROL7_BASE)
++#define IPROC_GPIO_CCA_PULL_DOWN (CRU_GPIO_CONTROL8_BASE)
++#define IPROC_GPIO_CCA_CTRL0 (CRU_GPIO_CONTROL0_BASE)
++#endif
++
++/* Chipcommon B GPIO */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_GPIO_CCB_BASE (CCB_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (CCB_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (CCB_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (CCB_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (CCB_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (CCB_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (CCB_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (CCB_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (CCB_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (CCB_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (CCB_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (CCB_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (CCB_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (CCB_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (CCB_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (CCB_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (CCB_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (CCB_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (CCB_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (CCB_GP_PRB_OE_BASE)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_GPIO_CCG_BASE (ChipcommonG_GP_DATA_IN)
++#define IPROC_GPIO_CCB_BASE (ChipcommonG_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (ChipcommonG_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (ChipcommonG_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (ChipcommonG_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (ChipcommonG_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (ChipcommonG_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (ChipcommonG_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (ChipcommonG_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (ChipcommonG_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (ChipcommonG_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (ChipcommonG_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (ChipcommonG_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (ChipcommonG_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (ChipcommonG_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (ChipcommonG_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (ChipcommonG_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (ChipcommonG_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (ChipcommonG_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (ChipcommonG_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (ChipcommonG_GP_PRB_OE_BASE)
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_NSP, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_GPIO_CCB_BASE (ChipcommonB_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (ChipcommonB_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (ChipcommonB_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (ChipcommonB_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (ChipcommonB_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (ChipcommonB_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (ChipcommonB_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (ChipcommonB_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (ChipcommonB_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (ChipcommonB_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (ChipcommonB_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (ChipcommonB_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (ChipcommonB_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (ChipcommonB_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (ChipcommonB_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (ChipcommonB_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (ChipcommonB_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (ChipcommonB_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (ChipcommonB_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (ChipcommonB_GP_PRB_OE_BASE)
++#endif
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IPROC_GPIO_CCA_INT (117)
++#define IPROC_GPIO_CCB_INT (119)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_GPIO_CCG_INT (116)
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_GPIO_CCA_INT (123)
++#define IPROC_GPIO_CCB_INT (125)
++#endif
++#endif /* CONFIG_IPROC_GPIO || CONFIG_IPROC_GPIO_MODULE */
++
++/* PWM Driver */
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CCB_PWM_CTL (CCB_PWM_CTL)
++#define IPROC_CCB_PWM_CTL_BASE (CCB_PWM_CTL_BASE)
++#define IPROC_CCB_PWM_PRESCALE_BASE (CCB_PWM_PRESCALE_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT0_BASE (CCB_PWM_PERIOD_COUNT0_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT1_BASE (CCB_PWM_PERIOD_COUNT1_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT2_BASE (CCB_PWM_PERIOD_COUNT2_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT3_BASE (CCB_PWM_PERIOD_COUNT3_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT0_BASE (CCB_PWM_DUTY_HI_COUNT0_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT1_BASE (CCB_PWM_DUTY_HI_COUNT1_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT2_BASE (CCB_PWM_DUTY_HI_COUNT2_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT3_BASE (CCB_PWM_DUTY_HI_COUNT3_BASE)
++#endif /* CONFIG_MACH_NS */
++
++#if defined(CONFIG_MACH_NSP)
++#define IPROC_CCB_PWM_CTL (ChipcommonB_PWMCTL)
++#define IPROC_CCB_PWM_CTL_BASE (ChipcommonB_PWMCTL_BASE)
++#define IPROC_CCB_PWM_PRESCALE_BASE (ChipcommonB_PWM_PRESCALE_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT0_BASE (ChipcommonB_PWM_PERIOD_COUNT0_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT1_BASE (ChipcommonB_PWM_PERIOD_COUNT1_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT2_BASE (ChipcommonB_PWM_PERIOD_COUNT2_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT3_BASE (ChipcommonB_PWM_PERIOD_COUNT3_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT0_BASE (ChipcommonB_PWM_DUTYHI_COUNT0_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT1_BASE (ChipcommonB_PWM_DUTYHI_COUNT1_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT2_BASE (ChipcommonB_PWM_DUTYHI_COUNT2_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT3_BASE (ChipcommonB_PWM_DUTYHI_COUNT3_BASE)
++#endif /* CONFIG_MACH_NSP */
++
++#endif /* CONFIG_IPROC_PWM */
++
++/* ChipCommonB Timer */
++#if defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_CCB_TIMER0_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim0_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER1_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim1_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER2_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim2_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER3_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim3_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER_INT_START (119)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#elif (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IPROC_CCB_TIMER0_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x00)
++#define IPROC_CCB_TIMER1_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x20)
++#define IPROC_CCB_TIMER2_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x00)
++#define IPROC_CCB_TIMER3_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x20)
++#define IPROC_CCB_TIMER_INT_START (122)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#else /* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_CCB_TIMER0_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x00)
++#define IPROC_CCB_TIMER1_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x20)
++#define IPROC_CCB_TIMER2_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x00)
++#define IPROC_CCB_TIMER3_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x20)
++#define IPROC_CCB_TIMER_INT_START (129)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#endif
++
++/* ChipCommonB Watchdog */
++/*
++ * CCB WDT could be set only when CONFIG_MACH_HR2, CONFIG_MACH_HX4,
++ * CONFIG_MACH_DNI_3448P or CONFIG_MACH_NSP is set
++ */
++#define IPROC_CCB_WDT_WDOGLOAD ChipcommonB_WDT_WDOGLOAD
++#define IPROC_CCB_WDT_REG_BASE IPROC_CCB_WDT_WDOGLOAD
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_CCB_WDT_BOOTSTATUS DMU_PCU_CRU_RESET_REASON
++#define IPROC_CCB_WDT_BOOTSTATUS_BIT DMU_PCU_CRU_RESET_REASON__watchdog_reset
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_CCB_WDT_BOOTSTATUS CRU_WATCHDOG_PCIE_RESET_STATUS
++#define IPROC_CCB_WDT_BOOTSTATUS_BIT CRU_WATCHDOG_PCIE_RESET_STATUS__CCB_WATCHDOG_RESET_EVENT
++#endif
++
++/* ChipCommonG Watchdog */
++#if defined(CONFIG_IPROC_CCG_WDT) || defined(CONFIG_IPROC_CCG_WDT_MODULE)
++#define IPROC_CCG_WDT_REG_BASE ChipcommonG_WDT_WDOGLOAD
++#define IPROC_CCG_WDT_BOOTSTATUS DMU_PCU_CRU_RESET_REASON
++#define IPROC_CCG_WDT_BOOTSTATUS_BIT DMU_PCU_CRU_RESET_REASON__watchdog_reset
++#endif /* CONFIG_IPROC_CCG_WDT || CONFIG_IPROC_CCG_WDT_MODULE */
++
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++#define IPROC_SP805_WDT_REG_BASE IPROC_CCB_WDT_REG_BASE
++#define IPROC_SP805_WDT_BOOTSTATUS IPROC_CCB_WDT_BOOTSTATUS
++#define IPROC_SP805_WDT_BOOTSTATUS_BIT IPROC_CCB_WDT_BOOTSTATUS_BIT
++#endif /* CONFIG_IPROC_SP805_WDT */
++
++#endif /*__IPROC_REGS_H */
+diff --git a/arch/arm/mach-iproc/include/mach/nand_iproc.h b/arch/arm/mach-iproc/include/mach/nand_iproc.h
+new file mode 100644
+index 0000000..9c4d4fc
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/nand_iproc.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _NAND_IPROC_H_
++#define _NAND_IPROC_H_
++
++/*
++ * Registers used directly in driver
++ */
++
++/*
++ * Shared Structure
++ */
++struct mtd_partition;
++struct brcmnand_platform_data {
++ int chip_select;
++ int strap_boot;
++ int strap_type;
++ int strap_page_size;
++ int nr_parts;
++ struct mtd_partition *parts;
++};
++
++#endif /* _NAND_IPROC_H_ */
+diff --git a/arch/arm/mach-iproc/include/mach/qspi_iproc.h b/arch/arm/mach-iproc/include/mach/qspi_iproc.h
+new file mode 100644
+index 0000000..14fcac8
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/qspi_iproc.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _QSPI_IPROC_H_
++#define _QSPI_IPROC_H_
++
++/*
++ * Shared Structure
++ */
++struct brcmspi_platform_data {
++ int flash_cs;
++};
++
++#endif /* _SPI_IPROC_H_ */
+diff --git a/arch/arm/mach-iproc/include/mach/reg_utils.h b/arch/arm/mach-iproc/include/mach/reg_utils.h
+new file mode 100644
+index 0000000..6cc36bf
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/reg_utils.h
+@@ -0,0 +1,160 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef REG_UTILS
++#define REG_UTILS
++
++/* ---- Include Files ---------------------------------------------------- */
++
++#include
++
++/* ---- Public Constants and Types --------------------------------------- */
++
++#define __REG32(x) (*((volatile uint32_t *)(x)))
++#define __REG16(x) (*((volatile uint16_t *)(x)))
++#define __REG8(x) (*((volatile uint8_t *) (x)))
++
++/* ---- Public Variable Externs ------------------------------------------ */
++/* ---- Public Function Prototypes --------------------------------------- */
++
++/****************************************************************************/
++/*
++ * 32-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg32_set_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg32_write_masked(volatile uint32_t *reg, uint32_t mask,
++ uint32_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg32_write(volatile uint32_t *reg, uint32_t value)
++{
++ *reg = value;
++}
++
++static inline uint32_t
++reg32_read(volatile uint32_t *reg)
++{
++ return *reg;
++}
++
++/****************************************************************************/
++/*
++ * 16-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg16_set_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg16_write(volatile uint16_t *reg, uint16_t value)
++{
++ *reg = value;
++}
++
++static inline uint16_t
++reg16_read(volatile uint16_t *reg)
++{
++ return *reg;
++}
++
++/****************************************************************************/
++/*
++ * 8-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg8_set_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg8_write(volatile uint8_t *reg, uint8_t value)
++{
++ *reg = value;
++}
++
++static inline uint8_t
++reg8_read(volatile uint8_t *reg)
++{
++ return *reg;
++}
++#endif /* REG_UTILS */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_ing_open.h b/arch/arm/mach-iproc/include/mach/socregs_ing_open.h
+new file mode 100644
+index 0000000..2431b98
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_ing_open.h
+@@ -0,0 +1,775 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_ING_OPEN_H
++#define __SOCREGS_ING_OPEN_H
++
++#define ChipcommonA_ChipID 0x18000000
++#define ChipcommonB_PWMCTL 0x18031000
++#define ChipcommonB_WDT_WDOGLOAD 0x18039000
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_SMBus_Config 0x18038000
++#define ChipcommonA_OTPProg 0x18000018
++#define ChipcommonA_OTPLayout 0x1800001c
++#define ChipcommonA_CoreCapabilities 0x18000004
++#define ChipcommonA_OTPStatus 0x18000010
++#define ChipcommonB_rng_CTRL 0x18033000
++#define QSPI_mspi_SPCR0_LSB 0x18027200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
++#define QSPI_bspi_registers_REVISION_ID 0x18027000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
++#define QSPI_raf_START_ADDR 0x18027100
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define QSPI_raf_CURR_ADDR 0x18027120
++#define CRU_control 0x1803e000
++#define GMAC0_DEVCONTROL 0x18022000
++#define GMAC1_DEVCONTROL 0x18023000
++#define ChipcommonA_GPIOEvent_BASE 0x078
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_CLR_BASE 0x024
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOIntMask_BASE 0x074
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonB_GP_INT_DE_BASE 0x010
++#define ChipcommonB_GP_INT_EDGE_BASE 0x014
++#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_GP_PAD_RES_BASE 0x034
++#define ChipcommonB_GP_RES_EN_BASE 0x038
++#define ChipcommonA_ChipID 0x18000000
++#define DMAC_pl330_DS 0x18020000
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define PAXB_0_CLK_CONTROL 0x18012000
++#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
++#define ChipcommonB_MII_Management_Control 0x18032000
++#define ChipcommonB_MII_Management_Command_Data 0x18032004
++#define NAND_nand_flash_REVISION 0x18026000
++#define NAND_direct_read_rd_miss 0x18026f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
++#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
++#define ChipcommonB_PWM_PRESCALE_BASE 0x024
++#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
++#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
++#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
++#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
++#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
++#define ChipcommonB_PWMCTL_BASE 0x000
++#define ChipcommonB_rng_CTRL 0x18033000
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define USB2_IDM_IDM_IO_CONTROL_DIRECT 0x18115408
++#define USB2D_IDM_IDM_IO_CONTROL_DIRECT 0x18116408
++#define USB2D_IDM_IDM_IO_CONTROL_DIRECT__clk_enable 0
++#define USB2D_IDM_IDM_RESET_CONTROL 0x18116800
++#define USB2D_IDM_IDM_RESET_CONTROL__RESET 0
++#endif
++#define DMU_CRU_RESET_BASE 0x200
++#define ChipcommonB_SMBus1_SMBus_Config 0x1803b000
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define USB2D_ENDPNT_IN_CTRL_0 0x18042000
++#endif
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810c900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810c904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810c908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810c90c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810c914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810c91c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810ca00
++#endif
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810d914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810da00
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
++#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define APBV_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18122900
++#define APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18122904
++#define APBV_S0_IDM_IDM_ERROR_LOG_STATUS 0x18122908
++#define APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812290c
++#define APBV_S0_IDM_IDM_ERROR_LOG_ID 0x18122914
++#define APBV_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812291c
++#define APBV_S0_IDM_IDM_INTERRUPT_STATUS 0x18122a00
++#endif
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18124900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18124904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x18124908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1812490c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18124914
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x1812491c
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18124a00
++#endif
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18142900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18142904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18142908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1814290c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18142914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1814291c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18142a00
++#endif
++#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
++#define ChipcommonA_IntMask_BASE 0x024
++#define DMU_PCU_CRU_RESET_REASON 0x1803f014
++#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonA_GPIOOut 0x18000064
++#define ChipcommonA_GPIOOutEn 0x18000068
++#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
++#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM0_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
++#define AMAC_IDM0_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
++#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
++#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM1_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
++#define AMAC_IDM1_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
++#if defined(CONFIG_MACH_KT2)
++#define IPROC_WRAP_USBPHY_CTRL 0x1803fc20
++#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_CTRL_SEL 1
++#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 3
++#define IPROC_WRAP_MISC_CONTROL 0x1803fc24
++#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_MDIO_SEL 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0 0x1803fc00
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_BASE 0xc00
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2 26
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_L 25
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_R 24
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_L 23
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_R 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_L 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_R 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL 19
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT 18
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE 17
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_L 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_R 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_L 11
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_WIDTH 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_RESETVALUE 0x000
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1 0x1803fc04
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_BASE 0xc04
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_RESETVALUE 0x2
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_L 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_R 26
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_RESETVALUE 0x3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_L 25
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_R 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_WIDTH 4
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_RESETVALUE 0x7
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_L 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_WIDTH 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_RESETVALUE 0x4dc00000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2 0x1803fc08
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_BASE 0xc08
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_L 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_R 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_WIDTH 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_RESETVALUE 0x000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_L 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_WIDTH 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_RESETVALUE 0x0000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_RESETVALUE 0x20000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3 0x1803fc0c
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_BASE 0xc0c
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN 30
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_L 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_R 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_WIDTH 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_RESETVALUE 0x00000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_L 9
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_WIDTH 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_RESETVALUE 0x80
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_RESETVALUE 0x80
++#define IPROC_DDR_PLL_CTRL_REGISTER_4 0x1803fc10
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_BASE 0xc10
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_L 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_R 24
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_WIDTH 4
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN 23
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_L 19
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_R 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_WIDTH 6
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_L 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_R 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_WIDTH 6
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_L 7
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_WIDTH 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_RESETVALUE 0x08
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_RESETVALUE 0x8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5 0x1803fc14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_BASE 0xc14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_R 17
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_WIDTH 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB 11
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_L 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_R 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_L 7
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_WIDTH 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_RESETVALUE 0x64
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_RESETVALUE 0xd864
++#define IPROC_DDR_PLL_STATUS 0x1803fc18
++#define IPROC_DDR_PLL_STATUS_BASE 0xc18
++#define IPROC_DDR_PLL_STATUS__RESERVED_L 31
++#define IPROC_DDR_PLL_STATUS__RESERVED_R 14
++#define IPROC_DDR_PLL_STATUS__RESERVED_WIDTH 18
++#define IPROC_DDR_PLL_STATUS__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST 13
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_WIDTH 1
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK 12
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_WIDTH 1
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_L 11
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_R 0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_WIDTH 12
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_RESETVALUE 0x000
++#define IPROC_DDR_PLL_STATUS_WIDTH 32
++#define IPROC_DDR_PLL_STATUS__WIDTH 32
++#define IPROC_DDR_PLL_STATUS_ALL_L 31
++#define IPROC_DDR_PLL_STATUS_ALL_R 0
++#define IPROC_DDR_PLL_STATUS__ALL_L 31
++#define IPROC_DDR_PLL_STATUS__ALL_R 0
++#define IPROC_DDR_PLL_STATUS_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_STATUS_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_STATUS_RESETVALUE 0x0
++#endif
++#if (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_WRAP_USBPHY_CTRL 0x1803fc34
++#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 3
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 13
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 21
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0 0x1803fc1c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_BASE 0xc1c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_R 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_RESETVALUE 0x18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_L 23
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_R 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_RESETVALUE 0x0f
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_L 15
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_RESETVALUE 0x64
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_RESETVALUE 0x1e
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RESETVALUE 0x180f641e
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1 0x1803fc20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_BASE 0xc20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB 26
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB 25
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_L 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_R 22
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_L 21
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_R 18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_RESETVALUE 0x8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_L 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_R 15
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_L 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_R 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_RESETVALUE 0x4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_L 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_R 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_WIDTH 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_L 5
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_WIDTH 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RESETVALUE 0x660c000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2 0x1803fc24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_BASE 0xc24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_R 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_RESETVALUE 0x00
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_L 19
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_R 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_L 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_R 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_L 13
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_R 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_L 10
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_RESETVALUE 0x0f
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RESETVALUE 0xf
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3 0x1803fc28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_BASE 0xc28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_R 30
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN 29
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_R 26
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_L 25
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_R 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN 23
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN 22
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN 21
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL 19
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT 18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_L 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_R 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET 13
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_L 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_WIDTH 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_RESETVALUE 0x000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RESETVALUE 0x15400000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4 0x1803fc2c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_BASE 0xc2c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_WIDTH 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_RESETVALUE 0x00000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_RESETVALUE 0x78
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RESETVALUE 0x78
++#define IPROC_WRAP_IPROC_XGPLL_STATUS 0x1803fc30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_BASE 0xc30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_L 30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_WIDTH 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_RESETVALUE 0x0
++#if defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_MDIO_SEL 3
++#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_CTRL_SEL 2
++#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 4
++#endif
++#define IPROC_WRAP_MISC_CONTROL 0x1803fc3c
++#endif
++
++#endif /* __SOCREGS_ING_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_ns_open.h b/arch/arm/mach-iproc/include/mach/socregs_ns_open.h
+new file mode 100644
+index 0000000..8f3d2eb
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_ns_open.h
+@@ -0,0 +1,81 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_NS_OPEN_H
++#define __SOCREGS_NS_OPEN_H
++
++
++#define CCA_CHIPID 0x18000000
++#define CCA_CHIPID_BASE 0x000
++#define CCB_GP_DATA_IN 0x18001000
++#define USB30_BASE 0x18023000
++#define SDIO_EMMC_SDXC_SYSADDR 0x18020000
++#define CCB_PWM_CTL 0x18002000
++#define CCB_TIM0_TIM_TMR1_LOAD 0x18005000
++#define CCB_TIM1_TIM_TMR1_LOAD 0x18006000
++#define CCB_SMBUS_START 0x18009000
++#define CCB_GP_AUX_SEL_BASE 0x028
++#define QSPI_MSPI_SPCR0_LSB 0x18029200
++#define QSPI_MSPI_DISABLE_FLUSH_GEN 0x18029384
++#define QSPI_BSPI_REGS_REV_ID 0x18029000
++#define QSPI_BSPI_REGS_BSPI_PIO_DATA 0x1802904c
++#define QSPI_RAF_START_ADDR 0x18029100
++#define QSPI_RAF_CURR_ADDR 0x18029120
++#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED 0x180293a0
++#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE 0x180293b8
++#define GMAC0_DEVCTL 0x18024000
++#define GMAC1_DEVCTL 0x18025000
++#define GMAC2_DEVCTL 0x18026000
++#define GMAC3_DEVCTL 0x18027000
++#define CCA_GPIO_EVT_BASE 0x078
++#define CCA_GPIO_INPUT 0x18000060
++#define CCA_GPIO_INPUT_BASE 0x060
++#define CCB_GP_INT_CLR_BASE 0x024
++#define CCA_GPIO_EVTINT_MASK_BASE 0x07c
++#define CCB_GP_INT_MSK_BASE 0x018
++#define CCA_GPIOINT_MASK_BASE 0x074
++#define CCA_GPIO_EVT_INT_POLARITY_BASE 0x084
++#define CCA_GPIO_INT_POLARITY_BASE 0x070
++#define CCA_INT_MASK_BASE 0x024
++#define CCB_GP_INT_TYPE_BASE 0x00c
++#define CCB_GP_INT_DE_BASE 0x010
++#define CCB_GP_INT_EDGE_BASE 0x014
++#define CCA_INT_STS_BASE 0x020
++#define CCB_GP_INT_MSTAT_BASE 0x020
++#define CCB_GP_PAD_RES_BASE 0x034
++#define CCB_GP_RES_EN_BASE 0x038
++#define CCB_MII_MGMT_CTL 0x18003000
++#define CCB_MII_MGMT_DATA 0x18003004
++#define NAND_NAND_FLASH_REV 0x18028000
++#define ChipcommonB_MII_Management_Control CCB_MII_MGMT_CTL
++#define ChipcommonB_MII_Management_Command_Data CCB_MII_MGMT_DATA
++#define NAND_DIRECT_READ_RD_MISS 0x18028f00
++#define CCB_PWM_PRESCALE_BASE 0x024
++#define CCB_PWM_PERIOD_COUNT0_BASE 0x004
++#define CCB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define CCB_PWM_DUTY_HI_COUNT2_BASE 0x018
++#define CCB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define CCB_PWM_DUTY_HI_COUNT0_BASE 0x008
++#define CCB_PWM_DUTY_HI_COUNT1_BASE 0x010
++#define CCB_PWM_DUTY_HI_COUNT2_BASE 0x018
++#define CCB_PWM_DUTY_HI_COUNT3_BASE 0x020
++#define CCB_PWM_CTL_BASE 0x000
++#define CCB_PWM_PERIOD_COUNT2_BASE 0x014
++#define CCB_RNG_CTRL 0x18004000
++
++
++#endif /* __SOCREGS_NS_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h b/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h
+new file mode 100644
+index 0000000..e98c003
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h
+@@ -0,0 +1,398 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_NSP_OPEN_H
++#define __SOCREGS_NSP_OPEN_H
++
++#define ChipcommonA_ChipID 0x18000000
++#define PCU_MDIO_MGT 0x1803f000
++#define ChipcommonB_PWMCTL 0x18031000
++#define ChipcommonB_WDT_WDOGLOAD 0x18039000
++#define USB3_CAPLENGTH 0x18029000
++#define USB30_BASE USB3_CAPLENGTH
++#define SATA_AHCI_GHC_HBA_CAP 0x18041000
++#define SATA_M0_IDM_IO_CONTROL_DIRECT 0x1811e408
++#define SATA_M0_IDM_IDM_RESET_CONTROL 0x1811e800
++#define SATA3_PCB_UPPER_REG1 0x18040304
++#define SATA3_PCB_UPPER_REG0 0x18040300
++#define SATA3_PCB_UPPER_REG1 0x18040304
++#define SATA3_PCB_UPPER_REG11 0x1804032c
++#define SATA3_PCB_UPPER_REG5 0x18040314
++#define SATA3_PCB_UPPER_REG15 0x1804033c
++#define SATA_TOP_CTRL_BUS_CTRL 0x18040024
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_SMBus_Config 0x18038000
++#define ChipcommonB_tim0_TIM_TIMER1Load 0x18034000
++#define ChipcommonB_tim1_TIM_TIMER1Load 0x18035000
++#define QSPI_mspi_SPCR0_LSB 0x18027200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
++#define QSPI_bspi_registers_REVISION_ID 0x18027000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
++#define QSPI_raf_START_ADDR 0x18027100
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define QSPI_raf_CURR_ADDR 0x18027120
++#define CRU_control 0x1803e000
++#define GMAC0_DEVCONTROL 0x18022000
++#define GMAC1_DEVCONTROL 0x18023000
++#define FA_GMAC0_DEVCONTROL 0x18024000
++#define FA_GMAC1_DEVCONTROL 0x18025000
++#define CRU_CLKSET_KEY_OFFSET 0x1803f180
++#define CRU_LCPLL2_CONTROL0 0x1803f548
++#define CRU_LCPLL2_CONTROL0__PWRDWN 12
++#define CRU_LCPLL2_CONTROL0__RESETB 11
++#define CRU_LCPLL2_STATUS__LOCK 12
++#define CRU_LCPLL2_CONTROL0__PWRDWN 12
++#define CRU_LCPLL2_CONTROL0__RESETB 11
++#define CRU_RESET__SGMII_RESET_N 8
++#define CRU_RESET 0x1803f184
++#define SGMII_CONFIG 0x1803f410
++#define SGMII_CONFIG__RSTB_PLL 17
++#define SGMII_CONFIG__RSTB_MDIOREGS 16
++#define SGMII_CONFIG__TXD1G_FIFO_RSTB_WIDTH 4
++#define SGMII_CONFIG__TXD1G_FIFO_RSTB_R 11
++#define P5_MUX_CONFIG__P5_MODE_WIDTH 3
++#define CRU_LCPLL2_CONTROL0__POST_RESETB 10
++#define P5_MUX_CONFIG 0x1803f308
++#define P5_MUX_CONFIG__P5_MODE_R 0
++#define P5_MUX_CONFIG__P5_MODE_SGMII 0x0
++#define P5_MUX_CONFIG__P5_MODE_GPHY3 0x4
++#define P4_MUX_CONFIG 0x1803f30c
++#define P4_MUX_CONFIG__P4_MODE_R 0
++#define P4_MUX_CONFIG__P4_MODE_WIDTH 3
++#define P4_MUX_CONFIG__P4_MODE_SGMII 0x0
++#define ChipcommonA_GPIOEvent_BASE 0x078
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_CLR_BASE 0x024
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOIntMask_BASE 0x074
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonB_GP_INT_DE_BASE 0x010
++#define ChipcommonB_GP_INT_EDGE_BASE 0x014
++#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define CRU_GPIO_CONTROL0_BASE 0x1f1c0
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define CRU_GPIO_CONTROL7_BASE 0x1f1dc
++#define CRU_GPIO_CONTROL8_BASE 0x1f1e0
++#define ChipcommonB_GP_PAD_RES_BASE 0x034
++#define ChipcommonB_GP_RES_EN_BASE 0x038
++#define ChipcommonA_ChipID 0x18000000
++#define DMAC_pl330_DS 0x18020000
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define PAXB_0_CLK_CONTROL 0x18012000
++#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
++#define ChipcommonB_MII_Management_Control 0x18032000
++#define ChipcommonB_MII_Management_Command_Data 0x18032004
++#define NAND_nand_flash_REVISION 0x18026000
++#define NAND_direct_read_rd_miss 0x18026f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
++#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
++#define ChipcommonB_PWM_PRESCALE_BASE 0x024
++#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
++#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
++#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
++#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
++#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
++#define ChipcommonB_PWMCTL_BASE 0x000
++#define ChipcommonB_rng_CTRL 0x18033000
++#define USB2_IDM_IDM_IO_CONTROL_DIRECT 0x18115408
++#define USB3_IDM_IDM_RESET_CONTROL 0x18104800
++#define CRU_WATCHDOG_PCIE_RESET_STATUS 0x1803f564
++#define CRU_WATCHDOG_PCIE_RESET_STATUS__CCB_WATCHDOG_RESET_EVENT 0
++#define SDIO_eMMCSDXC_SYSADDR 0x18021000
++#define IHOST_M0_IO_CONTROL_DIRECT 0x18100408
++#define ChipcommonA_IntMask_BASE 0x024
++#define ChipcommonA_OTPProg 0x18000018
++#define ChipcommonA_OTPLayout 0x1800001c
++#define ChipcommonA_CoreCapabilities 0x18000004
++#define ChipcommonA_OTPStatus 0x18000010
++#define SDIO_IDM_IO_CONTROL_DIRECT 0x18117408
++#define SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE 22
++
++
++/* IDM registers */
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810c900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810c904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810c908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810c90c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810c914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810c91c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810ca00
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ID 0x1810d914
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
++#define AXI_PCIE_S2_IDM_IDM_INTERRUPT_STATUS 0x1810da00
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
++#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
++#define APBV_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18122900
++#define APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18122904
++#define APBV_S0_IDM_IDM_ERROR_LOG_STATUS 0x18122908
++#define APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812290c
++#define APBV_S0_IDM_IDM_ERROR_LOG_ID 0x18122914
++#define APBV_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812291c
++#define APBV_S0_IDM_IDM_INTERRUPT_STATUS 0x18122a00
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18124900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18124904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x18124908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1812490c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18124914
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x1812491c
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18124a00
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18142900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18142904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18142908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1814290c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18142914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1814291c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18142a00
++#define CTF_CONTROL_REG 0x18025c00
++#define CTF_CONTROL_BASE 0x5c00
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP37 0x0
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP26 0x2
++#define CTF_FLOW_TIMER_CONFIG0__TCP_ESTABLISHED_TIMEBASE_R 2
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_R 0
++#define CTF_FLOW_TIMER_CONFIG1__TCP_ESTABLISHED_TIMEOUT_R 8
++#define CTF_FLOW_TIMER_CONFIG1__UDP_ESTABLISHED_TIMEOUT_R 16
++#define CTF_FLOW_TIMER_CONFIG1__TCP_FINISHED_TIMEOUT_R 0
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_R 4
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_R 4
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMER_CONFIG0__TCP_ESTABLISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMEOUT_CONTROL__FLOW_ENTRY_POINTER_R 5
++
++#define CTF_DRR_CONFIG__MAC_WEIGHT_R 7
++#define CTF_MEM_ACC_CONTROL__RD_WR_N 15
++#define CTF_MEM_ACC_CONTROL__TABLE_SELECT_R 12
++#define CTF_MEM_ACC_CONTROL__ALL_R 0
++
++#define PAE_M0_IDM_IDM_RESET_CONTROL 0x1811f800
++#define PAE_S0_IDM_IDM_RESET_CONTROL 0x18125800
++#define CTF_CONTROL__MEM_INIT 1
++#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
++#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
++#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define CTF_CONTROL__CTF_MODE 0
++#define CTF_CONTROL__FRAGMENTATION_ENABLE 2
++#define CTF_CONTROL__DISABLE_MAC_DA_CHECK 3
++#define CTF_CONTROL__PAE_ENABLED 5
++#define CTF_CONTROL__SPU_ENABLE 6
++#define CTF_BRCM_HDR_CONTROL 0x18025c08
++#define CTF_BRCM_HDR_CONTROL__BRCM_HDR_REASON_CODE_MASK_WIDTH 8
++#define CTF_BRCM_HDR_CONTROL__BRCM_HDR_REASON_CODE_MASK_R 0
++#define SPU_CONTROL 0x1802f000
++#define SPU_CONTROL__OUT_ENDIAN 12
++#define SPU_CONTROL__IN_ENDIAN 11
++#define SPU_CONTROL__SOFT_RST 1
++#define R5_CONFIG0 0x180490d8
++#define R5_CONFIG0__TE_INIT 31
++#define R5_CONFIG0__SYS_PORESET 30
++#define R5_CONFIG0__RESET_N 29
++#define R5_CONFIG0__PARITY_ODD 28
++#define R5_CONFIG0__PADDR_DEBUG31 27
++#define R5_CONFIG0__LOC_ZERO_RAMA 26
++#define R5_CONFIG0__INTERRUPT_ASYNC 25
++#define R5_CONFIG0__INITRAMB 24
++#define R5_CONFIG0__INITRAMA 23
++#define R5_CONFIG0__DEBUG_RESTART 22
++#define R5_CONFIG0__DEBUG_RESET_N 21
++#define R5_CONFIG0__DEBUG_RESET 20
++#define R5_CONFIG0__DEBUG_RESET 20
++#define R5_CONFIG0__DEBUG_NO_CLK_STOP 19
++#define R5_CONFIG0__DEBUG_NIDEN 18
++#define R5_CONFIG0__DEBUG_ENTCM1IF 17
++#define R5_CONFIG0__DEBUG_EN 16
++#define R5_CONFIG0__DEBUG_EDBGRQ 15
++#define R5_CONFIG0__DAP_DAP_TO_DEBUG_APB_EN 14
++#define R5_CONFIG0__CPU_HALT 13
++#define R5_CONFIG0__CFG_ENDIAN 12
++#define R5_CONFIG0__CFG_EE 11
++#define R5_CONFIG0__BTCM_SPLIT 10
++#define R5_CONFIG0__BTCM_SIZE_R 6
++#define R5_CONFIG0__BTCM_SIZE_WIDTH 4
++#define R5_CONFIG0__ATCM_SIZE_R 2
++#define R5_CONFIG0__ATCM_SIZE_WIDTH 4
++#define R5_CONFIG0__RMW_RAM_R 0
++#define R5_CONFIG0__RMW_RAM_WIDTH 2
++
++#define PAE_ECC_DEBUG 0x180490cc
++#define PAE_ECC_DEBUG__ECC_DISABLE 10
++#define PAE_BUFFER_CONFIG 0x18049010
++#define PAE_BUFFER_CONFIG__PAE_MEM_INIT 1
++#define PAE_BUFFER_CONFIG__PAE_SYS_INIT 0
++#define PAE_BUFFER_CONFIG__PAE_MEM_INIT_DONE 2
++#define PAE_BUFFER_ALLOCATION0 0x18049018
++#define PAE_BUFFER_ALLOCATION0 0x18049018
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_END_ADDR_R 16
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_END_ADDR_WIDTH 12
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_START_ADDR_R 0
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_START_ADDR_WIDTH 12
++
++#define PAE_BUFFER_ALLOCATION1 0x1804901c
++#define PAE_BUFFER_BACKPRESSURE_CONFIG0 0x18049020
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XOFF_R 16
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XOFF_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XON_R 0
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XON_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_CONFIG1 0x18049024
++#define PAE_BUFFER_CONGESTION_CONFIG 0x18049028
++#define PAE_BUFFER_CONGESTION_CONFIG__ENQ0_STOP_LEVEL_R 0
++#define PAE_BUFFER_CONGESTION_CONFIG__ENQ0_STOP_LEVEL_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_MAP0 0x1804902c
++#define PAE_BUFFER_BACKPRESSURE_MAP__INTERCEPT_PT_BACKPRESSURE_CONTRIBUTOR_MASK_R 0
++#define PAE_BUFFER_BACKPRESSURE_MAP__INTERCEPT_PT_BACKPRESSURE_CONTRIBUTOR_MASK_WIDTH 2
++#define PAE_BUFFER_BACKPRESSURE_MAP1 0x18049030
++#define PAE_SCRATCHPAD_ALLOCATION 0x18049014
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_END_ADDR_R 16
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_END_ADDR_WIDTH 12
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_START_ADDR_R 0
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_START_ADDR_WIDTH 12
++#define CTF_DEBUG_CONTROL 0x18025ca0
++#define CTF_DEBUG_CONTROL__DM_FIFO_BP_LEVEL_R 10
++#define CTF_DEBUG_CONTROL__DM_FIFO_BP_LEVEL_WIDTH 8
++#define AXIIC_sata_m0_fn_mod 0x1a051108
++
++#endif /* __SOCREGS_NSP_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_p7_open.h b/arch/arm/mach-iproc/include/mach/socregs_p7_open.h
+new file mode 100644
+index 0000000..4ffeeba
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_p7_open.h
+@@ -0,0 +1,261 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_P7_OPEN_H
++#define __SOCREGS_P7_OPEN_H
++
++#ifdef CONFIG_MACH_GH
++/*
++ * Greyhound only registers
++ */
++#define DMU_PCU_IPROC_CONTROL 0x1800f000
++#define DMU_CRU_RESET_BASE 0x200
++
++#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
++
++#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 4
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 14
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 22
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
++
++#endif /* End of Greyhound only registers */
++
++#define ICFG_CHIP_ID_REG 0x18000000
++#define ChipcommonG_UART0_UART_RBR_THR_DLL 0x18020000
++#define ChipcommonG_UART1_UART_RBR_THR_DLL 0x18021000
++
++#define QSPI_mspi_SPCR0_LSB 0x18047200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18047384
++#define QSPI_bspi_registers_REVISION_ID 0x18047000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1804704c
++#define QSPI_raf_START_ADDR 0x18047100
++#define QSPI_raf_CURR_ADDR 0x18047120
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180473a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180473b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define CRU_control 0x1800e000
++
++#define NAND_nand_flash_REVISION 0x18046000
++#define NAND_direct_read_rd_miss 0x18046f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0xf8105408
++
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL 0x18000c8c
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel 1
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel_sw_ovwr 0
++#define ICFG_PNOR_STRAPS 0x18000a5c
++#define ICFG_PNOR_STRAPS__PNOR_SRAM_MW_R 0
++#define PNOR_set_opmode 0x18045018
++#define PNOR_set_opmode__set_mw_R 0
++#define PNOR_direct_cmd 0x18045010
++#define PNOR_direct_cmd__cmd_type_R 21
++
++#define ChipcommonG_tim0_TIM_TIMER1Load 0x18003000
++#define ChipcommonG_tim1_TIM_TIMER1Load 0x18004000
++#define ChipcommonG_tim2_TIM_TIMER1Load 0x18005000
++#define ChipcommonG_tim3_TIM_TIMER1Load 0x18006000
++
++#define ChipcommonS_RNG_CTRL 0x18032000
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18107a00
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18106900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18106904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18106908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810690c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18106914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810691c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18106a00
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18108900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x18108908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x18108914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x18108a00
++
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x18109900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x18109908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x18109914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x18109a00
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810a908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810a914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810aa00
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18119900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18119904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x18119908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811990c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x18119914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811991c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x18119a00
++
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x1811b908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x1811b914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x1811ba00
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18130900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18130904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18130908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813090c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18130914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813091c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18130a00
++
++#define APBY_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBY_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBY_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBY_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBY_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBY_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBY_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++
++#define APBZ_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBZ_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBZ_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBZ_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBZ_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBZ_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBZ_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0xf8102900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0xf8102904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0xf8102908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0xf810290c
++#define DDR_S1_IDM_ERROR_LOG_ID 0xf8102914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0xf810291c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0xf8102a00
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0xf8103900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0xf8103904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0xf8103908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0xf810390c
++#define DDR_S2_IDM_ERROR_LOG_ID 0xf8103914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0xf810391c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0xf8103a00
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0xf8104900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0xf8104904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0xf8104908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0xf810490c
++#define ROM_S0_IDM_ERROR_LOG_ID 0xf8104914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0xf810491c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0xf8104a00
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0xf8105900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0xf8105904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0xf8105908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0xf810590c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0xf8105914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0xf810591c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0xf8105a00
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0xf8106900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0xf8106904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0xf8106908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0xf810690c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0xf8106914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0xf810691c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0xf8106a00
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18120908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18120914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18120a00
++
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18121900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18121908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18121914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18121a00
++
++#define AXIIC_DS_2_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define AXIIC_DS_2_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define AXIIC_DS_2_IDM_ERROR_LOG_STATUS 0x1811d908
++#define AXIIC_DS_2_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define AXIIC_DS_2_IDM_ERROR_LOG_ID 0x1811d914
++#define AXIIC_DS_2_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define AXIIC_DS_2_IDM_INTERRUPT_STATUS 0x1811da00
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x1811e900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x1811e904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x1811e908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1811e90c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x1811e914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1811e91c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x1811ea00
++
++/* GPIO */
++#define ChipcommonG_GP_DATA_IN 0x1800a000
++#define ChipcommonG_GP_DATA_IN_BASE 0x000
++#define ChipcommonG_GP_DATA_OUT_BASE 0x004
++#define ChipcommonG_GP_OUT_EN_BASE 0x008
++#define ChipcommonG_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonG_GP_INT_DE_BASE 0x010
++#define ChipcommonG_GP_INT_EDGE_BASE 0x014
++#define ChipcommonG_GP_INT_MSK_BASE 0x018
++#define ChipcommonG_GP_INT_STAT_BASE 0x01c
++#define ChipcommonG_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonG_GP_INT_CLR_BASE 0x024
++#define ChipcommonG_GP_AUX_SEL_BASE 0x028
++#define ChipcommonG_GP_INIT_VAL_BASE 0x030
++#define ChipcommonG_GP_PAD_RES_BASE 0x034
++#define ChipcommonG_GP_RES_EN_BASE 0x038
++#define ChipcommonG_GP_TEST_INPUT_BASE 0x03c
++#define ChipcommonG_GP_TEST_OUTPUT_BASE 0x040
++#define ChipcommonG_GP_TEST_ENABLE_BASE 0x044
++#define ChipcommonG_GP_PRB_ENABLE_BASE 0x048
++#define ChipcommonG_GP_PRB_OE_BASE 0x04c
++
++/* Watchdog */
++#define ChipcommonG_WDT_WDOGLOAD 0x18009000
++#define DMU_PCU_CRU_RESET_REASON 0x1800f014
++#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
++
++#endif /* __SOCREGS_P7_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/vmalloc.h b/arch/arm/mach-iproc/include/mach/vmalloc.h
+new file mode 100644
+index 0000000..0611b30
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/vmalloc.h
+@@ -0,0 +1,24 @@
++/*
++ * arch/arm/mach-iproc/include/mach/vmalloc.h
++ *
++ * Copyright (C) 2014
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifdef __ASSEMBLY__
++#define VMALLOC_END 0xff000000
++#else
++#define VMALLOC_END 0xff000000UL
++#endif
+diff --git a/arch/arm/mach-iproc/io_map.c b/arch/arm/mach-iproc/io_map.c
+new file mode 100644
+index 0000000..cbea0a2
+--- /dev/null
++++ b/arch/arm/mach-iproc/io_map.c
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++#include
++
++#define IO_DESC(va, sz) { .virtual = va, \
++ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
++ .length = sz, \
++ .type = MT_DEVICE }
++
++
++static struct map_desc northstar_io_desc[] __initdata =
++{
++ IO_DESC(IO_CORE_IDM_VA,IO_CORE_IDM_SIZE),
++ IO_DESC(IO_ARMCORE_VA, IO_ARMCORE_SIZE),
++#ifdef CONFIG_MACH_IPROC_P7
++ IO_DESC(IO_SMAU_IDM_VA, IO_SMAU_IDM_SIZE),
++#endif /* !CONFIG_MACH_IPROC_P7 */
++};
++
++extern void __init iproc_map_io(void);
++
++void __init northstar_map_io(void)
++{
++ iotable_init(northstar_io_desc, ARRAY_SIZE(northstar_io_desc));
++}
+diff --git a/arch/arm/mach-iproc/localtimer.c b/arch/arm/mach-iproc/localtimer.c
+new file mode 100644
+index 0000000..b139cac
+--- /dev/null
++++ b/arch/arm/mach-iproc/localtimer.c
+@@ -0,0 +1,27 @@
++/*
++ * linux/arch/arm/mach-iproc/localtimer.c
++ *
++ * Copyright (C) 2002 ARM Ltd.
++ * All Rights Reserved
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include
++#include
++#include
++
++#include
++#include
++#include
++
++/*
++ * Setup the local clock events for a CPU.
++ */
++int __cpuinit local_timer_setup(struct clock_event_device *evt)
++{
++ evt->irq = IRQ_LOCALTIMER;
++ twd_timer_setup(evt);
++ return 0;
++}
+diff --git a/arch/arm/mach-iproc/northstar.c b/arch/arm/mach-iproc/northstar.c
+new file mode 100644
+index 0000000..dc23a34
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar.c
+@@ -0,0 +1,166 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++
++
++
++
++#define TIMER_LOAD 0x00
++#define TIMER_VALUE 0x04
++#define TIMER_CTRL 0x08
++#define TIMER_CTRL_PRESC_SHFT (8)
++#define TIMER_CTRL_IE (1 << 2)
++#define TIMER_CTRL_PERIODIC (1 << 1)
++#define TIMER_CTRL_ENABLE (1 << 0)
++
++#define TIMER_INTCLR 0x0c
++#define IPROC_L2CC_REG_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_L2CC_REG_BASE)
++
++extern void __iomem *twd_base;
++extern void iproc_clocksource_init(void __iomem *);
++extern void iproc_clockevents_init(void __iomem *, unsigned int);
++extern void __init northstar_dmu_init(struct clk *clk_ref);
++extern void __init iproc_cru_init(struct clk *clk_ref);
++extern void iproc_enable_data_prefetch_aborts(void);
++extern void northstar_restart(char mode, const char *cmd);
++
++static void
++northstar_poweroff(void)
++{
++ while(1)
++ ;
++}
++
++
++#ifdef CONFIG_CACHE_L2X0
++static void __init northstar_l2x0_init(void)
++{
++ void __iomem *l2cache_base = IOMEM(IPROC_L2CC_REG_VA);
++ void __iomem *cca = IOMEM(IPROC_CCA_CORE_REG_VA);
++ unsigned int chipid = (readl(cca) & 0x0000ffff);
++
++ /*
++ * 16KB way size, 16-way associativity
++ */
++#if defined(CONFIG_MACH_NS)
++ if (chipid >= 0xcf19 /* costar */) {
++#ifdef CONFIG_BCM_IPROC_CA9_PREFETCH
++ /* inst/data prefetch & Early BRESP & Fill line zero (also need A9) */
++ l2x0_init(l2cache_base, (0x0A150000 | 0x3 << 28 | 0x1 << 30 | 0x1 << 0), ~(0x000F0000));
++#else
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#endif /* CONFIG_BCM_IPROC_CA9_PREFETCH */
++ } else { /* northstar */
++ l2x0_init(l2cache_base, 0x0A130000, ~(0x000F0000));
++ }
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#elif defined(CONFIG_MACH_HR2)
++ l2x0_init(l2cache_base, 0x0A120000, ~(0x000F0000));
++#elif defined(CONFIG_MACH_NSP)
++#ifdef CONFIG_BCM_IPROC_CA9_PREFETCH
++ /* inst/data prefetch & Early BRESP & Fill line zero (also need A9) */
++ l2x0_init(l2cache_base, (0x0A150000 | 0x3 << 28 | 0x1 << 30 | 0x1 << 0), ~(0x000F0000));
++#else
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#endif /* CONFIG_BCM_IPROC_CA9_PREFETCH */
++#elif defined(CONFIG_MACH_IPROC_P7)
++ l2x0_init(l2cache_base, 0x0A130000, ~(0x000F0000));
++#endif
++}
++#endif
++
++static int __init northstar_init(void)
++{
++#ifdef CONFIG_PM
++ pm_power_off = northstar_poweroff;
++#endif
++ arm_pm_restart = northstar_restart;
++
++#ifdef CONFIG_MACH_CYGNUS
++#else
++#ifdef CONFIG_CACHE_L2X0
++ northstar_l2x0_init();
++#endif
++#endif /* END of CYGNUS */
++
++ return 0;
++}
++early_initcall(northstar_init);
++
++/*
++ * CPU global and MPCORE Per CPU local timer
++ */
++#define GLB_TIMER IOMEM(IPROC_PERIPH_GLB_TIM_REG_VA);
++#define PVT_TIMER IOMEM(IPROC_PERIPH_PVT_TIM_REG_VA);
++
++void __iomem *gtimer_va_base = GLB_TIMER;
++void __iomem *ptimer_va_base = PVT_TIMER;
++
++/*
++ * Set up the clock source and clock events devices
++ */
++void __init northstar_timer_init(struct clk *clk_ref)
++{
++ int err;
++
++ /*
++ * Setup DMU and CRU early
++ */
++ northstar_dmu_init(clk_ref);
++ iproc_cru_init(clk_ref);
++
++ /*
++ * Initialise to a known state (all timers off)
++ */
++ writel(0, ptimer_va_base + TIMER_CTRL);
++ writel(0, gtimer_va_base + TIMER_CTRL);
++
++#ifdef CONFIG_HAVE_ARM_TWD
++ /*
++ * Setup the local clock events for a CPU.
++ */
++ twd_base = IO_ADDRESS(IPROC_PERIPH_PVT_TIM_REG_VA);
++#endif
++
++ iproc_clocksource_init(gtimer_va_base);
++ iproc_clockevents_init(gtimer_va_base, BCM_INT_ID_PPI11);
++
++ iproc_enable_data_prefetch_aborts();
++}
+diff --git a/arch/arm/mach-iproc/northstar.h b/arch/arm/mach-iproc/northstar.h
+new file mode 100644
+index 0000000..09b3ccc
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __NORTHSTAR_H
++#define __NORTHSTAR_H
++
++#include
++#include
++
++extern struct platform_device northstar_ipc_device;
++
++void __init northstar_map_io(void);
++
++#endif /* __NORTHSTAR_H */
+diff --git a/arch/arm/mach-iproc/northstar_dmu.c b/arch/arm/mach-iproc/northstar_dmu.c
+new file mode 100644
+index 0000000..f95b0e3
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar_dmu.c
+@@ -0,0 +1,802 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++#include
++#include
++
++#define IPROC_DMU_BASE_PA IPROC_DMU_BASE_REG
++//#define IPROC_DMU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_DMU_BASE_PA)
++
++static struct resource dmu_regs = {
++ .name = "dmu_regs",
++ .start = (resource_size_t) IOMEM(IPROC_DMU_BASE_VA),
++ .end = (resource_size_t) (IOMEM(IPROC_DMU_BASE_VA) + SZ_4K - 1),
++ .flags = IORESOURCE_MEM,
++};
++
++/*
++ * Clock management scheme is a provisional implementation
++ * only intended to retreive the pre-set frequencies for each
++ * of the clocks.
++ * Better handling of post-dividers and fractional part of
++ * feedbeck dividers need to be added.
++ * Need to understand what diagnostics from CRU registers could
++ * be handy, and export that via a sysfs interface.
++ */
++
++/*
++ * The CRU contains two similar PLLs: LCPLL and GENPLL,
++ * both with several output channels divided from the PLL
++ * output
++ */
++
++/*
++ * Get PLL running status and update output frequency
++ */
++static int lcpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv, ndiv_int, ndiv_frac;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* read status register */
++ reg = readl(clk->regs_base + 0x10);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if ((reg & (1 << 12)) == 0) {
++ clk->rate = 0;
++ }
++
++ /* Update PLL frequency */
++
++ /* control1 register */
++ reg = readl(clk->regs_base + 0x04);
++
++ /* feedback divider integer and fraction parts */
++ pdiv = (reg >> 28) & 7 ;
++ ndiv_int = (reg >> 20) & 0xff;
++ ndiv_frac = reg & ((1<<20)-1);
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv ;
++
++ x = x * ((u64) ndiv_int << 20 | ndiv_frac) ;
++
++ clk->rate = x >> 20 ;
++
++ return 0;
++}
++
++static const struct clk_ops lcpll_ops = {
++ .status = lcpll_status,
++};
++
++static int lcpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++ BUG_ON(base == NULL);
++
++ /* enable bit is in enableb_ch[] inversed */
++ enable = ((readl(base + 0) >> 6) & 7) ^ 7;
++
++ if (0 == (enable & (1 << clk->chan))) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* get divider */
++ reg = readl(base + 0x08);
++
++ mdiv = 0xff & (reg >> ((0x3^clk->chan) << 3));
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("LCPLL[%d] mdiv=%u rate=%lu\n", clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = (clk->parent->rate / mdiv);
++ return 0;
++}
++
++
++static const struct clk_ops lcpll_chan_ops = {
++ .status = lcpll_chan_status,
++};
++
++/*
++ * LCPLL has 4 output channels
++ */
++static struct clk clk_lcpll = {
++ .ops = &lcpll_ops,
++ .name = "LCPLL",
++ .type = CLK_PLL,
++ .chan = 4,
++};
++
++/*
++ * LCPLL output clocks -
++ * chan 0 - PCIe ref clock, should be 1 GHz,
++ * chan 1 - SDIO clock, e.g. 200 MHz,
++ * chan 2 - DDR clock, typical 166.667 MHz for DDR667,
++ * chan 3 - Unknown
++ */
++
++static struct clk clk_lcpll_ch[4] = {
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch3",
++ .chan = 3,
++ },
++};
++
++/*
++ * Get PLL running status and update output frequency
++ */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++static int genpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv;
++ unsigned ndiv_int;
++ unsigned ndiv_frac;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* Offset of the PLL status register */
++ reg = readl(clk->regs_base + 0x20);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if((reg & (1 << 12)) == 0) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* Update PLL frequency */
++
++ /* get PLL feedback divider values from control5 */
++ reg = readl(clk->regs_base + 0x14);
++
++ /* feedback divider integer and fraction parts */
++ ndiv_int = reg >> 20;
++ ndiv_frac = reg & ((1 << 20) - 1);
++
++ /* get pdiv */
++ reg = readl(clk->regs_base + 0x18);
++ pdiv = (reg >> 24) & 7;
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv;
++
++ x = x * ((u64) ndiv_int << 20 | ndiv_frac);
++
++ clk->rate = x >> 20;
++
++ return 0;
++}
++#endif
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++static int genpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv;
++ unsigned ndiv_int;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* Offset of the PLL status register */
++ reg = readl(clk->regs_base + 0x18);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if((reg & (1 << IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK)) == 0) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* Update PLL frequency */
++
++ /* get PLL feedback divider values from control5 */
++ reg = readl(clk->regs_base + 0x04);
++
++ /* feedback divider integer and fraction parts */
++ ndiv_int = (reg >> IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R) & ((1 << IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH) -1);
++
++ /* get pdiv */
++ pdiv = (reg >> IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R) & ((1 << IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH) -1);
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv;
++
++ x = x * ((u64) ndiv_int);
++
++ clk->rate = x;
++
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_KT2)
++static int genpll_status(struct clk * clk)
++{
++ clk->rate = 2475000000;
++
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS) //chandra: todo
++static int genpll_status(struct clk * clk)
++{
++
++}
++#endif
++static const struct clk_ops genpll_ops = {
++ .status = genpll_status,
++};
++
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++static int genpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv;
++ unsigned off, shift;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++
++ BUG_ON (base == NULL);
++
++ /* enable bit is in enableb_ch[0..5] inversed */
++ enable = ((readl(base + 0x04) >> 12) & 0x3f) ^ 0x3f ;
++
++ if (0 == (enable & (1 << clk->chan))) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ off = 0x18; shift = 16;
++ break;
++
++ case 1:
++ off = 0x18; shift = 8;
++ break;
++
++ case 2:
++ off = 0x18; shift = 0;
++ break;
++
++ case 3:
++ off = 0x1c; shift = 16;
++ break;
++
++ case 4:
++ off = 0x1c; shift = 8;
++ break;
++
++ case 5:
++ off = 0x1c; shift = 16; /* Set to AXI clock */
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ off = shift = 0; /* fend off warnings */
++ }
++
++ reg = readl(base + off);
++
++ mdiv = 0xff & (reg >> shift);
++ /* APB clock is always AXIclock/4 */
++ if(clk->chan == 5)
++ mdiv = mdiv * 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++static int genpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv = 0;
++ unsigned off, shift;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++
++ BUG_ON (base == NULL);
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ off = 0x04; shift = IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R;
++ break;
++
++ case 1:
++ off = 0x04; shift = IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R;
++ break;
++
++ case 2:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R;
++ break;
++
++ case 3:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R;
++ break;
++
++ case 4:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R;
++ break;
++
++ case 5:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R;
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ off = shift = 0; /* fend off warnings */
++ }
++
++ reg = readl(base + off);
++
++ mdiv = 0xff & (reg >> shift);
++ if(clk->chan == 5)
++ mdiv *= 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_KT2)
++static int genpll_chan_status(struct clk * clk)
++{
++ unsigned mdiv = 0;
++
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ mdiv = 10;
++ break;
++
++ case 3:
++ mdiv = 5;
++ break;
++
++ case 4:
++ mdiv = 10;
++ break;
++
++ case 5:
++ mdiv = 5;
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ }
++
++ if(clk->chan == 5)
++ mdiv *= 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS) //chandra: todo
++static int genpll_chan_status(struct clk * clk)
++{
++
++}
++#endif
++
++static const struct clk_ops genpll_chan_ops = {
++ .status = genpll_chan_status,
++};
++
++
++/*
++ * GENPLL has 6 output channels
++ */
++static struct clk clk_genpll = {
++ .ops = &genpll_ops,
++ .name = "GENPLL",
++ .type = CLK_PLL,
++ .chan = 6,
++};
++
++/*
++ * chan 0 - Ethernet switch and MAC, RGMII, need 250 MHz
++ * chan 1 - Ethernet switch slow clock, 150 Mhz
++ * chan 2 - USB PHY clock, need 30 MHz
++ * chan 3 - iProc N MHz clock, set from OTP
++ * chan 4 - iProc N/2 MHz clock, set from OTP
++ * chan 5 - iProc N/4 MHz clock, set from OTP
++ *
++ * To Do: which clock goes to MPCORE PERIPHCLOCK?
++ */
++#ifdef CONFIG_MACH_CYGNUS_EMULATION //chandra:emul
++ static struct clk clk_genpll_ch[6] = {
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = 992000,
++ .type = CLK_DIV,
++ .name = "genpll_ch3",
++ .chan = 3,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = 644800,
++ .type = CLK_DIV,
++ .name = "genpll_ch4",
++ .chan = 4,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = CONFIG_CYGNUS_EMULATION_CLK_125,//25000000,
++ .type = CLK_DIV,
++ .name = "genpll_ch5",
++ .chan = 5,
++ },
++ };
++
++#else
++static struct clk clk_genpll_ch[6] = {
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch3",
++ .chan = 3,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch4",
++ .chan = 4,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch5",
++ .chan = 5,
++ },
++};
++#endif
++
++/*
++ * This table is used to locate clock sources
++ * from device drivers
++ */
++
++static struct clk_lookup ns_clk_lookups[] = {
++ {
++ .dev_id = "pcie",
++ .con_id = "c_clk100",
++ .clk = &clk_lcpll_ch[0],
++ },{
++ .dev_id = "sdio",
++ .con_id = "c_clk200",
++ .clk = &clk_lcpll_ch[1],
++ },{
++ .dev_id = "ddr",
++ .con_id = "c_clk400",
++ .clk = &clk_lcpll_ch[2],
++ },{
++ .dev_id = "tbd",
++ .con_id = "c_clk120",
++ .clk = &clk_lcpll_ch[3],
++ },{
++ .dev_id = "en_phy",
++ .con_id = "c_clk250",
++ .clk = &clk_genpll_ch[0],
++ },{
++ .dev_id = "en",
++ .con_id = "c_clk150",
++ .clk = &clk_genpll_ch[1],
++ },{
++ .dev_id = "usb_phy",
++ .con_id = "c_clk30",
++ .clk = &clk_genpll_ch[2],
++ },{
++ .dev_id = "iproc_fast",
++ .con_id = "c_clk500",
++ .clk = &clk_genpll_ch[3],
++ },{
++ .dev_id = "iproc_med",
++ .con_id = "c_clk250",
++ .clk = &clk_genpll_ch[4],
++ },{
++ .dev_id = "iproc_slow",
++ .con_id = "c_clk125",
++ .clk = &clk_genpll_ch[5],
++ }
++#ifdef CONFIG_ARM_AMBA
++ ,{
++ .con_id = "apb_pclk",
++ .clk = &clk_genpll_ch[5],
++ }
++#if defined (CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++ ,{
++ .dev_id = "sp805-wdt",
++ .clk = &clk_genpll_ch[5],
++ }
++#endif
++#endif
++};
++
++/*
++ * Install above clocks into clock lookup table
++ * and initialize the register base address for each
++*/
++static void __init northstar_clocks_init(void *__iomem cru_regs_base,
++ struct clk * clk_ref)
++{
++ /*
++ * Registers are already mapped with the rest of DMU block
++ * Update register base address
++ */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ clk_lcpll.regs_base = cru_regs_base + 0x00 ;
++ clk_genpll.regs_base = cru_regs_base + 0x40 ;
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++ clk_lcpll.regs_base = cru_regs_base + 0x1c ;
++ clk_genpll.regs_base = cru_regs_base + 0x00 ;
++#endif
++
++ /* Set parent as reference ckock */
++ clk_lcpll.parent = clk_ref;
++ clk_genpll.parent = clk_ref;
++
++ /* Install clock sources into the lookup table */
++ clkdev_add_table(ns_clk_lookups,
++ ARRAY_SIZE(ns_clk_lookups));
++}
++
++void __init northstar_dmu_init(struct clk *clk_ref)
++{
++ void * __iomem reg_base;
++
++ if (IS_ERR_OR_NULL(clk_ref )) {
++ printk(KERN_ERR "CRU no clock source - skip init\n");
++ return;
++ }
++
++ BUG_ON (request_resource(&iomem_resource, &dmu_regs));
++
++ /* DMU regs are mapped as part of the fixed mapping with CCA+CCB */
++ reg_base = (void * __iomem) dmu_regs.start;
++
++ BUG_ON (IS_ERR_OR_NULL(reg_base));
++
++ /* Initialize clocks */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ northstar_clocks_init(reg_base + 0x100, clk_ref); /* CRU LCPLL control0 */
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++ northstar_clocks_init(reg_base + 0xc00, clk_ref); /* IPROC_WRAP_GEN_PLL_CTRL0 */
++#elif defined(CONFIG_MACH_KT2)
++ northstar_clocks_init(NULL, clk_ref); /* IPROC_WRAP_GEN_PLL_CTRL0 */
++#endif
++}
++
++void (*cpld_system_reset)(void);
++EXPORT_SYMBOL(cpld_system_reset); /* used in dni_3448p_cpld.c module */
++
++/*
++ * Reset the system
++ */
++void northstar_restart(char mode, const char *cmd)
++{
++ void * __iomem reg_addr;
++ u32 reg;
++
++ if (cpld_system_reset) {
++ printk( KERN_INFO "Using CPLD reset\n");
++ cpld_system_reset();
++ }
++
++ /* CRU_RESET register */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ reg_addr = (void * __iomem) dmu_regs.start + 0x184 ;
++ /* set iproc_reset_n to 0, it may come back or not ... TBD */
++ reg = readl_relaxed(reg_addr);
++ reg &= ~((u32) 1 << 1);
++ writel_relaxed(reg, reg_addr);
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++ reg_addr = (void * __iomem) dmu_regs.start + DMU_CRU_RESET_BASE ;
++ /* Reset iproc and cmicd/switch */
++ writel_relaxed(0, reg_addr);
++#endif
++
++
++}
++
++
++
++
++
++
++
++void northstar_clocks_show( void )
++{
++ unsigned i;
++// struct clk * clk ;
++
++ printk("=========== CLOCKS =================\n");
++
++ printk( "DMU Clocks:\n" );
++ for (i = 0; i < ARRAY_SIZE( ns_clk_lookups); i++) {
++ printk("%s, %s: (%s) %lu\n",
++ ns_clk_lookups[i].con_id,
++ ns_clk_lookups[i].dev_id,
++ ns_clk_lookups[i].clk->name,
++ clk_get_rate( ns_clk_lookups[i].clk));
++ }
++ printk( "DMU Clocks# %u\n", i );
++}
+diff --git a/arch/arm/mach-iproc/pm.c b/arch/arm/mach-iproc/pm.c
+new file mode 100644
+index 0000000..ca2eef4
+--- /dev/null
++++ b/arch/arm/mach-iproc/pm.c
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++
++int iproc_arm_cpu_do_idle(void)
++{
++ return cpu_do_idle();
++}
++EXPORT_SYMBOL(iproc_arm_cpu_do_idle);
++
++inline void iproc_arm_cpu_resume(void)
++{
++ cpu_resume();
++}
++EXPORT_SYMBOL(iproc_arm_cpu_resume);
++
++int iproc_arm_cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
++{
++ return cpu_suspend(arg, fn);
++}
++EXPORT_SYMBOL(iproc_arm_cpu_suspend);
+diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
+index ffb9d6a..6ec5258 100644
+--- a/arch/arm/mach-ixp4xx/include/mach/io.h
++++ b/arch/arm/mach-ixp4xx/include/mach/io.h
+@@ -385,6 +385,20 @@ static inline unsigned int ioread16(const void __iomem *addr)
+ #endif
+ }
+
++#define ioread16be(p) ioread16be(p)
++static inline unsigned int ioread16be(const void __iomem *addr)
++{
++ unsigned long port = (unsigned long __force)addr;
++ if (__is_io_address(port))
++ return (unsigned int)inw(port & PIO_MASK);
++ else
++#ifndef CONFIG_IXP4XX_INDIRECT_PCI
++ return be16_to_cpu((__force __be16)__raw_readw(addr));
++#else
++ return be16_to_cpu((__force __le16)(unsigned int)__indirect_readw(addr));
++#endif
++}
++
+ #define ioread16_rep(p, v, c) ioread16_rep(p, v, c)
+ static inline void ioread16_rep(const void __iomem *addr, void *vaddr,
+ u32 count)
+@@ -415,6 +429,21 @@ static inline unsigned int ioread32(const void __iomem *addr)
+ }
+ }
+
++#define ioread32be(p) ioread32be(p)
++static inline unsigned int ioread32be(const void __iomem *addr)
++{
++ unsigned long port = (unsigned long __force)addr;
++ if (__is_io_address(port))
++ return (unsigned int)inl(port & PIO_MASK);
++ else {
++#ifndef CONFIG_IXP4XX_INDIRECT_PCI
++ return be32_to_cpu((__force __be32)__raw_readl(addr));
++#else
++ return be32_to_cpu((__force __be32)(unsigned int)__indirect_readl(addr));
++#endif
++ }
++}
++
+ #define ioread32_rep(p, v, c) ioread32_rep(p, v, c)
+ static inline void ioread32_rep(const void __iomem *addr, void *vaddr,
+ u32 count)
+@@ -473,6 +502,20 @@ static inline void iowrite16(u16 value, void __iomem *addr)
+ #endif
+ }
+
++#define iowrite16be(v, p) iowrite16be(v, p)
++static inline void iowrite16be(u16 value, void __iomem *addr)
++{
++ unsigned long port = (unsigned long __force)addr;
++ if (__is_io_address(port))
++ outw(value, port & PIO_MASK);
++ else
++#ifndef CONFIG_IXP4XX_INDIRECT_PCI
++ __raw_writew(cpu_to_be16(value), addr);
++#else
++ __indirect_writew(cpu_to_be16(value), addr);
++#endif
++}
++
+ #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c)
+ static inline void iowrite16_rep(void __iomem *addr, const void *vaddr,
+ u32 count)
+@@ -502,6 +545,20 @@ static inline void iowrite32(u32 value, void __iomem *addr)
+ #endif
+ }
+
++#define iowrite32be(v, p) iowrite32be(v, p)
++static inline void iowrite32be(u32 value, void __iomem *addr)
++{
++ unsigned long port = (unsigned long __force)addr;
++ if (__is_io_address(port))
++ outl(value, port & PIO_MASK);
++ else
++#ifndef CONFIG_IXP4XX_INDIRECT_PCI
++ __raw_writel((u32 __force)cpu_to_be32(value), addr);
++#else
++ __indirect_writel((u32 __force)cpu_to_be32(value), addr);
++#endif
++}
++
+ #define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c)
+ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
+ u32 count)
+diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
+index 7fc603b..a41a90c 100644
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -44,6 +44,26 @@ config MACH_GURUPLUG
+ Say 'Y' here if you want your kernel to support the
+ Marvell GuruPlug Reference Board.
+
++config ARCH_KIRKWOOD_DT
++ bool "Marvell Kirkwood Flattened Device Tree"
++ select USE_OF
++ help
++ Say 'Y' here if you want your kernel to support the
++ Marvell Kirkwood using flattened device tree.
++
++config MACH_DREAMPLUG_DT
++ bool "Marvell DreamPlug (Flattened Device Tree)"
++ select ARCH_KIRKWOOD_DT
++ help
++ Say 'Y' here if you want your kernel to support the
++ Marvell DreamPlug (Flattened Device Tree).
++
++config MACH_ICONNECT_DT
++ bool "Iomega Iconnect (Flattened Device Tree)"
++ select ARCH_KIRKWOOD_DT
++ help
++ Say 'Y' here to enable Iomega Iconnect support.
++
+ config MACH_TS219
+ bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
+ help
+diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
+index 5dcaa81..7858070 100644
+--- a/arch/arm/mach-kirkwood/Makefile
++++ b/arch/arm/mach-kirkwood/Makefile
+@@ -20,3 +20,6 @@ obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
+ obj-$(CONFIG_MACH_T5325) += t5325-setup.o
+
+ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
++obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
++obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
++obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
+diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
+index 760a0ef..81244fb 100644
+--- a/arch/arm/mach-kirkwood/Makefile.boot
++++ b/arch/arm/mach-kirkwood/Makefile.boot
+@@ -1,3 +1,6 @@
+ zreladdr-y += 0x00008000
+ params_phys-y := 0x00000100
+ initrd_phys-y := 0x00800000
++
++dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
++dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
+diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
+new file mode 100644
+index 0000000..9854539
+--- /dev/null
++++ b/arch/arm/mach-kirkwood/board-dreamplug.c
+@@ -0,0 +1,152 @@
++/*
++ * Copyright 2012 (C), Jason Cooper
++ *
++ * arch/arm/mach-kirkwood/board-dreamplug.c
++ *
++ * Marvell DreamPlug Reference Board Init for drivers not converted to
++ * flattened device tree yet.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include