From 87cd765b8ce809e50b1fc9b3471c27b8d72cf939 Mon Sep 17 00:00:00 2001 From: Jonathan Tsai Date: Mon, 10 Jul 2017 15:42:38 +0800 Subject: [PATCH] [Quanta-IX1,LY4R] Update ONLP: 1. Add sfp functions of onlp_sfpi_control_set() and onlp_sfpi_control_get() --- .../module/src/sfpi.c | 190 ++++++++++++++---- .../x86_64_quanta_ly4r_gpio_table.h | 15 ++ .../src/x86_64_quanta_ly4r/module/src/sfpi.c | 101 +++++++++- 3 files changed, 261 insertions(+), 45 deletions(-) diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sfpi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sfpi.c index ffcfde0b..d5ea1b29 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sfpi.c +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ix1-rangeley/onlp/builds/src/x86_64_quanta_ix1_rangeley/module/src/sfpi.c @@ -28,7 +28,7 @@ #include #include #include "x86_64_quanta_ix1_rangeley_log.h" - +#include #include #include @@ -46,40 +46,54 @@ typedef struct sfpmap_s { static sfpmap_t sfpmap__[] = { - { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-1/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, - { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-2/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, - { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-3/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, - { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-4/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, - { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-5/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, - { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-6/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, - { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-7/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, - { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-8/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, - { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-9/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, - { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-10/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, - { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-11/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, - { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-12/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, - { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-13/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, - { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-14/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, - { 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-15/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL }, - { 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-16/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL }, - { 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-17/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL }, - { 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-18/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL }, - { 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-19/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL }, - { 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-20/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL }, - { 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-21/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL }, - { 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-22/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL }, - { 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-23/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, - { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-24/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, - { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-25/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, - { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-26/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, - { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-27/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, - { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-28/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, - { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-29/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, - { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-30/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, - { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-31/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, - { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-32/module_present", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, + { 1, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-1/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-32/32-0050/eeprom", NULL }, + { 2, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-2/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-33/33-0050/eeprom", NULL }, + { 3, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-3/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-34/34-0050/eeprom", NULL }, + { 4, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-4/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-35/35-0050/eeprom", NULL }, + { 5, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-5/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-36/36-0050/eeprom", NULL }, + { 6, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-6/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-37/37-0050/eeprom", NULL }, + { 7, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-7/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-38/38-0050/eeprom", NULL }, + { 8, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-8/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-39/39-0050/eeprom", NULL }, + { 9, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-9/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-40/40-0050/eeprom", NULL }, + { 10, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-10/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-41/41-0050/eeprom", NULL }, + { 11, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-11/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-42/42-0050/eeprom", NULL }, + { 12, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-12/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-43/43-0050/eeprom", NULL }, + { 13, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-13/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-44/44-0050/eeprom", NULL }, + { 14, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-14/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-45/45-0050/eeprom", NULL }, + { 15, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-15/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-46/46-0050/eeprom", NULL }, + { 16, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0038/cpld-qsfp28/port-16/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-47/47-0050/eeprom", NULL }, + { 17, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-17/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-48/48-0050/eeprom", NULL }, + { 18, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-18/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-49/49-0050/eeprom", NULL }, + { 19, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-19/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-50/50-0050/eeprom", NULL }, + { 20, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-20/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-51/51-0050/eeprom", NULL }, + { 21, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-21/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-52/52-0050/eeprom", NULL }, + { 22, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-22/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-53/53-0050/eeprom", NULL }, + { 23, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-23/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-54/54-0050/eeprom", NULL }, + { 24, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-24/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/i2c-55/55-0050/eeprom", NULL }, + { 25, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-25/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-56/56-0050/eeprom", NULL }, + { 26, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-26/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-57/57-0050/eeprom", NULL }, + { 27, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-27/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-58/58-0050/eeprom", NULL }, + { 28, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-28/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-59/59-0050/eeprom", NULL }, + { 29, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-29/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-60/60-0050/eeprom", NULL }, + { 30, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-30/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-61/61-0050/eeprom", NULL }, + { 31, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-31/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-62/62-0050/eeprom", NULL }, + { 32, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-16/16-0039/cpld-qsfp28/port-32/%s", NULL, "/sys/devices/pci0000:00/0000:00:1f.3/i2c-0/i2c-17/i2c-63/63-0050/eeprom", NULL }, }; +#define SFP_GET(_port) (sfpmap__ + _port - 1) +#define MAX_SFP_PATH 128 +static char sfp_node_path[MAX_SFP_PATH] = {0}; + +static char* +sfp_get_port_path(int port, char *node_name) +{ + sfpmap_t* sfp = SFP_GET(port); + + sprintf(sfp_node_path, sfp->present_cpld, + node_name); + return sfp_node_path; +} + int onlp_sfpi_init(void) { @@ -104,14 +118,10 @@ onlp_sfpi_bitmap_get(onlp_sfp_bitmap_t* bmap) return ONLP_STATUS_OK; } -#define SFP_GET(_port) (sfpmap__ + _port - 1) - int onlp_sfpi_is_present(int port) { - sfpmap_t* sfp = SFP_GET(port); - - return onlplib_sfp_is_present_file(sfp->present_cpld, /* Present */ "1\n", /* Absent */ "0\n"); + return onlplib_sfp_is_present_file(sfp_get_port_path(port, "module_present"), /* Present */ "1\n", /* Absent */ "0\n"); } int @@ -128,3 +138,107 @@ onlp_sfpi_dom_read(int port, uint8_t data[256]) return onlplib_sfp_eeprom_read_file(sfp->dom, data); } +int +onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value) +{ + int rv; + char* path = NULL; + + switch(control){ + case ONLP_SFP_CONTROL_RESET_STATE: + { + path = sfp_get_port_path(port, "reset"); + + if (onlp_file_write_int(value, path) != 0) { + AIM_LOG_ERROR("Unable to set reset status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + case ONLP_SFP_CONTROL_LP_MODE: + { + path = sfp_get_port_path(port, "lpmode"); + + if (onlp_file_write_int(value, path) != 0) { + AIM_LOG_ERROR("Unable to set lp_mode status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + + return rv; +} + +int +onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value) +{ + int rv; + char* path = NULL; + + switch(control){ + case ONLP_SFP_CONTROL_RESET_STATE: + { + path = sfp_get_port_path(port, "reset"); + + if (onlp_file_read_int(value, path) < 0) { + AIM_LOG_ERROR("Unable to read reset status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + if(*value == 0){ + *value = 1; + } + else{ + *value = 0; + } + rv = ONLP_STATUS_OK; + } + break; + } + + case ONLP_SFP_CONTROL_LP_MODE: + { + path = sfp_get_port_path(port, "lpmode"); + + if (onlp_file_read_int(value, path) < 0) { + AIM_LOG_ERROR("Unable to read lpmode status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + else { + rv = ONLP_STATUS_OK; + } + break; + } + + case ONLP_SFP_CONTROL_RX_LOS: + { + *value = 0; + rv = ONLP_STATUS_OK; + break; + } + + case ONLP_SFP_CONTROL_TX_DISABLE: + { + *value = 0; + rv = ONLP_STATUS_OK; + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + + return rv; +} + diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/inc/x86_64_quanta_ly4r/x86_64_quanta_ly4r_gpio_table.h b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/inc/x86_64_quanta_ly4r/x86_64_quanta_ly4r_gpio_table.h index 1794e95f..030c4b7c 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/inc/x86_64_quanta_ly4r/x86_64_quanta_ly4r_gpio_table.h +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/inc/x86_64_quanta_ly4r/x86_64_quanta_ly4r_gpio_table.h @@ -12,11 +12,26 @@ #define QUANTA_LY4R_I2C_GPIO_BASE 0x10 #define QUANTA_LY4R_PCA9698_GPIO_BASE (QUANTA_LY4R_I2C_GPIO_BASE) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_1_TX_FAULT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,0)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_1_TX_DIS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,1)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_1_PRSNT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,2)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_1_RX_LOS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,3)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_2_TX_FAULT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,4)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_2_TX_DIS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,5)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_2_PRSNT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,6)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_2_RX_LOS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(0,7)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_3_TX_FAULT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,0)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_3_TX_DIS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,1)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_3_PRSNT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,2)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_3_RX_LOS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,3)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_4_TX_FAULT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,4)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_4_TX_DIS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,5)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_4_PRSNT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,6)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_4_RX_LOS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(1,7)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_5_TX_FAULT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,0)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_5_TX_DIS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,1)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_5_PRSNT_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,2)) +#define QUANTA_LY4R_PCA9698_GPIO_SFP_5_RX_LOS_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,3)) #define QUANTA_LY4R_PCA9698_BOOT_STSLED_N (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,4)) #define QUANTA_LY4R_PCA9698_SYS_STSLED (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,5)) #define QUANTA_LY4R_PCA9698_GPIO_SFP_P3V3_PW_EN (QUANTA_LY4R_PCA9698_GPIO_BASE + QUANTA_LY4R_PCA953x_GPIO(2,6)) diff --git a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/src/sfpi.c b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/src/sfpi.c index 7e1f6861..ceba9fe4 100755 --- a/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/src/sfpi.c +++ b/packages/platforms/quanta/x86-64/x86-64-quanta-ly4r/onlp/builds/src/x86_64_quanta_ly4r/module/src/sfpi.c @@ -28,7 +28,7 @@ #include #include #include "x86_64_quanta_ly4r_log.h" - +#include #include #include @@ -39,18 +39,20 @@ typedef struct sfpmap_s { int port; int present_gpio; - const char* reset_gpio; + int tx_fault_gpio; + int tx_dis_gpio; + int rx_los_gpio; const char* eeprom; const char* dom; } sfpmap_t; static sfpmap_t sfpmap__[] = { - { 49, QUANTA_LY4R_PCA9698_GPIO_SFP_1_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-32/32-0050/eeprom", NULL }, - { 50, QUANTA_LY4R_PCA9698_GPIO_SFP_2_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-33/33-0050/eeprom", NULL }, - { 51, QUANTA_LY4R_PCA9698_GPIO_SFP_3_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-34/34-0050/eeprom", NULL }, - { 52, QUANTA_LY4R_PCA9698_GPIO_SFP_4_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-35/35-0050/eeprom", NULL }, - { 53, QUANTA_LY4R_PCA9698_GPIO_SFP_5_PRSNT_N, NULL, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-36/36-0050/eeprom", NULL }, + { 49, QUANTA_LY4R_PCA9698_GPIO_SFP_1_PRSNT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_1_TX_FAULT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_1_TX_DIS_N, QUANTA_LY4R_PCA9698_GPIO_SFP_1_RX_LOS_N, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-32/32-0050/eeprom", NULL }, + { 50, QUANTA_LY4R_PCA9698_GPIO_SFP_2_PRSNT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_2_TX_FAULT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_2_TX_DIS_N, QUANTA_LY4R_PCA9698_GPIO_SFP_2_RX_LOS_N, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-33/33-0050/eeprom", NULL }, + { 51, QUANTA_LY4R_PCA9698_GPIO_SFP_3_PRSNT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_3_TX_FAULT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_3_TX_DIS_N, QUANTA_LY4R_PCA9698_GPIO_SFP_3_RX_LOS_N, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-34/34-0050/eeprom", NULL }, + { 52, QUANTA_LY4R_PCA9698_GPIO_SFP_4_PRSNT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_4_TX_FAULT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_4_TX_DIS_N, QUANTA_LY4R_PCA9698_GPIO_SFP_4_RX_LOS_N, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-35/35-0050/eeprom", NULL }, + { 53, QUANTA_LY4R_PCA9698_GPIO_SFP_5_PRSNT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_5_TX_FAULT_N, QUANTA_LY4R_PCA9698_GPIO_SFP_5_TX_DIS_N, QUANTA_LY4R_PCA9698_GPIO_SFP_5_RX_LOS_N, "/sys/devices/pci0000:00/0000:00:13.0/i2c-1/i2c-36/36-0050/eeprom", NULL }, }; #define SFP_GET(_port) (sfpmap__ + _port - 49) @@ -72,6 +74,10 @@ onlp_sfpi_init(void) for(i = 49; i < 54; i++) { sfp = SFP_GET(i); onlp_gpio_export(sfp->present_gpio, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(sfp->tx_fault_gpio, ONLP_GPIO_DIRECTION_IN); + onlp_gpio_export(sfp->tx_dis_gpio, ONLP_GPIO_DIRECTION_OUT); + onlp_gpio_set(sfp->tx_dis_gpio, 1); + onlp_gpio_export(sfp->rx_los_gpio, ONLP_GPIO_DIRECTION_IN); } return ret; @@ -140,3 +146,84 @@ onlp_sfpi_dom_read(int port, uint8_t data[256]) return onlplib_sfp_eeprom_read_file(sfp->dom, data); } +int +onlp_sfpi_control_set(int port, onlp_sfp_control_t control, int value) +{ + int rv; + sfpmap_t* sfp = SFP_GET(port); + + switch(control){ + case ONLP_SFP_CONTROL_TX_DISABLE: + { + if(onlp_gpio_set(sfp->tx_dis_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to set tx_disable status to port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + + return rv; +} + +int +onlp_sfpi_control_get(int port, onlp_sfp_control_t control, int* value) +{ + int rv; + sfpmap_t* sfp = SFP_GET(port); + + switch(control){ + case ONLP_SFP_CONTROL_TX_FAULT: + { + if(onlp_gpio_get(sfp->tx_fault_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to read tx_fault status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + case ONLP_SFP_CONTROL_TX_DISABLE: + { + if(onlp_gpio_get(sfp->tx_dis_gpio, value) == ONLP_STATUS_OK){ + if(*value == 0){ + *value = 1; + } + else{ + *value = 0; + } + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to read tx_disable status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + case ONLP_SFP_CONTROL_RX_LOS: + { + if(onlp_gpio_get(sfp->rx_los_gpio, value) == ONLP_STATUS_OK){ + rv = ONLP_STATUS_OK; + } + else{ + AIM_LOG_ERROR("Unable to read rx_los status from port(%d)\r\n", port); + rv = ONLP_STATUS_E_INTERNAL; + } + break; + } + + default: + rv = ONLP_STATUS_E_UNSUPPORTED; + } + + return rv; +}