diff --git a/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/.gitignore b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/.gitignore
new file mode 100644
index 00000000..3898a1cf
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/.gitignore
@@ -0,0 +1,2 @@
+linux-3.2*
+kernel-3.2*
diff --git a/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/Makefile b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/Makefile
new file mode 100644
index 00000000..06577e25
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/Makefile
@@ -0,0 +1,41 @@
+############################################################
+#
+#
+# Copyright 2015 Big Switch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+#
+############################################################
+
+THIS_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+include $(ONL)/make/config.mk
+
+ifndef K_TARGET_DIR
+K_TARGET_DIR := $(THIS_DIR)
+endif
+
+include ../../kconfig.mk
+K_CONFIG := arm-iproc-all.config
+K_BUILD_TARGET := Image
+K_COPY_SRC := arch/arm/boot/Image
+K_COPY_GZIP := 1
+ifndef K_COPY_DST
+K_COPY_DST := kernel-3.2-deb7-arm-iproc-all.bin.gz
+endif
+
+export ARCH=arm
+DTS_LIST := accton_as4610_54
+
+include $(ONL)/make/kbuild.mk
diff --git a/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/arm-iproc-all.config b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/arm-iproc-all.config
new file mode 100644
index 00000000..8aa366c4
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/configs/arm-iproc-all/arm-iproc-all.config
@@ -0,0 +1,2432 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.2.84 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
+CONFIG_LOCALVERSION="-OpenNetworkLinux"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="onl"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_RD_XZ=y
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_ZYNQ is not set
+CONFIG_ARCH_IPROC=y
+CONFIG_BCM_ZRELADDR=0x61008000
+CONFIG_GPIO_PCA953X=y
+
+#
+# Broadcom IPROC architecture based implementations
+#
+# CONFIG_ARCH_NORTHSTAR is not set
+CONFIG_MACH_IPROC=y
+# CONFIG_IPROC_64K_PAGE is not set
+CONFIG_GP_TIMER_COMPARATOR_LOAD_DELAY=y
+CONFIG_IPROC_DCACHE_INVALIDATION=y
+# CONFIG_IPROC_TIMER_UNIT_TESTS is not set
+# CONFIG_IPROC_SW_RESET_RECORD is not set
+# CONFIG_BRCM_PROP_MODULES is not set
+# CONFIG_BCM_STM is not set
+CONFIG_BCM_PARAMS_PHYS=0x61000000
+CONFIG_BCM_RAM_BASE=0x60000000
+CONFIG_BCM_RAM_START_RESERVED_SIZE=0x200000
+
+#
+# iProc SoC based Machine types
+#
+# CONFIG_MACH_CYGNUS is not set
+# CONFIG_MACH_NS is not set
+# CONFIG_MACH_HX4 is not set
+# CONFIG_MACH_HR2 is not set
+# CONFIG_MACH_NSP is not set
+# CONFIG_MACH_KT2 is not set
+# CONFIG_MACH_GH is not set
+# CONFIG_MACH_DNI_3448P is not set
+CONFIG_MACH_ACCTON_AS4610_54=y
+# CONFIG_MACH_IPROC_EMULATION is not set
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_CPU_HAS_PMU=y
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_742230 is not set
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_PL310_ERRATA_588369 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_PL310_ERRATA_727915 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_PL310_ERRATA_753970 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_ERRATA_754327 is not set
+# CONFIG_ARM_ERRATA_764369 is not set
+# CONFIG_PL310_ERRATA_769419 is not set
+CONFIG_ARM_GIC=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_LOAD_CIS is not set
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+# CONFIG_YENTA is not set
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=4
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_LOCAL_TIMERS=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+# CONFIG_IP_PIMSM_V1 is not set
+CONFIG_IP_PIMSM_V2=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=y
+CONFIG_TCP_CONG_HTCP=y
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFB is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+# CONFIG_NET_SCH_QFQ is not set
+
+#
+# Classification
+#
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+CONFIG_HAVE_BPF_JIT=y
+# CONFIG_BPF_JIT is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_OF_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_M25PXX_STAY_IN_3BYTE_MODE is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_VIRTIO_BLK=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+CONFIG_EARLY_DMA_ALLOC=y
+CONFIG_EDA_DEF_SIZE=0x04000000
+CONFIG_EDA_DEF_ALIGN=0x00100000
+# CONFIG_RETIMER_CLASS is not set
+# CONFIG_DS100DF410 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_CLASS=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_SFF_8436 is not set
+CONFIG_EEPROM_ACCTON_AS4610_SFP=y
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_SATA_PMP is not set
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_ATA_BMDMA is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+CONFIG_PATA_PCMCIA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_LINEAR=y
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID10=y
+CONFIG_MD_RAID456=y
+# CONFIG_MULTICORE_RAID456 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_MD_FAULTY is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+# CONFIG_DM_THIN_PROVISIONING is not set
+CONFIG_DM_MIRROR=y
+CONFIG_DM_RAID=y
+# CONFIG_DM_LOG_USERSPACE is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+CONFIG_DUMMY=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_MACVLAN is not set
+CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_VIRTIO_NET=y
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+CONFIG_NET_VENDOR_FUJITSU=y
+# CONFIG_PCMCIA_FMVJ18X is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_NET_VENDOR_INTEL=y
+# CONFIG_E100 is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_IXGB is not set
+# CONFIG_IXGBE is not set
+CONFIG_NET_VENDOR_I825XX=y
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_SFC is not set
+CONFIG_NET_VENDOR_SMSC=y
+# CONFIG_SMC91X is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_XIRCOM is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_TR is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_CS=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+# CONFIG_SERIAL_8250_DW is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_HVC_DCC is not set
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_I2C_MUX_PCA9541=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_I2C_MUX_DNI_6448 is not set
+# CONFIG_I2C_MUX_QUANTA is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_EG20T is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_PL061 is not set
+# CONFIG_GPIO_VX855 is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+CONFIG_SENSORS_ADM1021=y
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CY8CXX is not set
+# CONFIG_SENSORS_CY8C3245R1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+CONFIG_SENSORS_LM75=y
+CONFIG_SENSORS_LM77=y
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+CONFIG_SENSORS_LM85=y
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+CONFIG_SENSORS_LTC4215=y
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+CONFIG_SENSORS_MAX6650=y
+CONFIG_SENSORS_MAX6620=y
+CONFIG_SENSORS_MAX6697=y
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+CONFIG_SENSORS_EMC2305=y
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+CONFIG_SENSORS_W83781D=y
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_SENSORS_ACCTON_I2C_CPLD=y
+CONFIG_SENSORS_ACCTON_AS4610_FAN=y
+CONFIG_SENSORS_ACCTON_AS4610_PSU=y
+CONFIG_SENSORS_YM2651Y=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+# CONFIG_HID_PID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_SDRICOH_CS is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_RENESAS_TPU is not set
+CONFIG_LEDS_ACCTON_AS4610=y
+# CONFIG_LEDS_TRIGGERS is not set
+
+#
+# LED Triggers
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1374=y
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_RING=y
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_MACH_CLKDEV=y
+
+#
+# Hardware Spinlock drivers
+#
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# Broadcom iProc Drivers
+#
+# CONFIG_IPROC_CCB_TIMER is not set
+CONFIG_IPROC_MDIO=y
+# CONFIG_IPROC_DMA is not set
+CONFIG_IPROC_GPIO=y
+CONFIG_IPROC_QSPI=y
+CONFIG_IPROC_QSPI_SINGLE_MODE=y
+# CONFIG_IPROC_QSPI_DUAL_MODE is not set
+# CONFIG_IPROC_QSPI_QUAD_MODE is not set
+CONFIG_IPROC_QSPI_MAX_HZ=62500000
+# CONFIG_IPROC_MTD_NAND is not set
+# CONFIG_IPROC_PWM is not set
+CONFIG_IPROC_USB2H=y
+CONFIG_USB_EHCI_BCM=y
+CONFIG_IPROC_GMAC=y
+
+#
+# Broadcom HND network devices
+#
+CONFIG_HND=y
+CONFIG_ET=y
+CONFIG_ET_47XX=y
+# CONFIG_ET_NAPI2_POLL is not set
+# CONFIG_BCM_CTF is not set
+# CONFIG_BCM_CTF2 is not set
+# CONFIG_BCM_IPROC_GMAC_ACP is not set
+# CONFIG_BCM_IPROC_GMAC_PREFETCH is not set
+# CONFIG_BCM_IPROC_GMAC_SKB_RECYCLING is not set
+# CONFIG_BCM_IPROC_GMAC_LOCK_OPT is not set
+# CONFIG_BCM_IPROC_GMAC_RWREG_OPT is not set
+# CONFIG_BCM_IPROC_GMAC_SG is not set
+# CONFIG_WL_EMULATOR is not set
+# CONFIG_BCM57XX is not set
+# CONFIG_WL is not set
+# CONFIG_WL_USBAP is not set
+CONFIG_WL_AP=""
+CONFIG_WL_AP_SDSTD=""
+CONFIG_WL_STA=""
+CONFIG_WL_APSTA=""
+CONFIG_WL_AP_ONCHIP_G=""
+CONFIG_WL_STA_ONCHIP_G=""
+CONFIG_WL_HIGH=""
+CONFIG_IPROC_SDK_MGT_PORT_HANDOFF=y
+# CONFIG_IPROC_2STAGE_RX is not set
+CONFIG_IPROC_I2C=y
+# CONFIG_IPROC_PMU is not set
+# CONFIG_BCM_IPROC_CA9_PREFETCH is not set
+# CONFIG_BCM_BARRIER_PERFORMANCE is not set
+# CONFIG_BCM_MEM_OPTIMIZATION is not set
+# CONFIG_BROADCOM_CUSTOM_SENDFILE is not set
+# CONFIG_BCM_CUSTOM_RECVFILE is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_INOTIFY_STACKFS=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_OVERLAYFS_FS=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_MASK=0x1
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_ASYNC_RAID6_TEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=y
+CONFIG_ASYNC_CORE=y
+CONFIG_ASYNC_MEMCPY=y
+CONFIG_ASYNC_XOR=y
+CONFIG_ASYNC_PQ=y
+CONFIG_ASYNC_RAID6_RECOV=y
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=y
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+# CONFIG_CORDIC is not set
diff --git a/packages/base/any/kernels/3.2-lts/kconfig.mk b/packages/base/any/kernels/3.2-lts/kconfig.mk
new file mode 100644
index 00000000..bbaa91cb
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/kconfig.mk
@@ -0,0 +1,27 @@
+############################################################
+#
+#
+# Copyright 2015 Big Switch Networks, Inc.
+#
+# Licensed under the Eclipse Public License, Version 1.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied. See the License for the specific
+# language governing permissions and limitations under the
+# License.
+#
+#
+############################################################
+
+THIS_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+K_MAJOR_VERSION := 3
+K_PATCH_LEVEL := 2
+K_SUB_LEVEL := 84
+K_SUFFIX :=
+K_PATCH_DIR := $(THIS_DIR)/patches
diff --git a/packages/base/any/kernels/3.2-lts/patches/Makefile.patch b/packages/base/any/kernels/3.2-lts/patches/Makefile.patch
new file mode 100644
index 00000000..fb3eefaf
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/Makefile.patch
@@ -0,0 +1,131 @@
+--- a/Makefile
++++ b/Makefile
+@@ -195,46 +195,6 @@ export KBUILD_BUILDHOST := $(SUBARCH)
+ ARCH ?= $(SUBARCH)
+ CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
+
+-# Architecture as present in compile.h
+-UTS_MACHINE := $(ARCH)
+-SRCARCH := $(ARCH)
+-
+-# Additional ARCH settings for x86
+-ifeq ($(ARCH),i386)
+- SRCARCH := x86
+-endif
+-ifeq ($(ARCH),x86_64)
+- SRCARCH := x86
+-endif
+-
+-# Additional ARCH settings for sparc
+-ifeq ($(ARCH),sparc32)
+- SRCARCH := sparc
+-endif
+-ifeq ($(ARCH),sparc64)
+- SRCARCH := sparc
+-endif
+-
+-# Additional ARCH settings for sh
+-ifeq ($(ARCH),sh64)
+- SRCARCH := sh
+-endif
+-
+-# Additional ARCH settings for tile
+-ifeq ($(ARCH),tilepro)
+- SRCARCH := tile
+-endif
+-ifeq ($(ARCH),tilegx)
+- SRCARCH := tile
+-endif
+-
+-# Where to locate arch specific headers
+-hdr-arch := $(SRCARCH)
+-
+-ifeq ($(ARCH),m68knommu)
+- hdr-arch := m68k
+-endif
+-
+ KCONFIG_CONFIG ?= .config
+ export KCONFIG_CONFIG
+
+@@ -354,6 +314,44 @@ CFLAGS_KERNEL =
+ AFLAGS_KERNEL =
+ CFLAGS_GCOV = -fprofile-arcs -ftest-coverage
+
++-include $(obj)/.kernelvariables
++
++# Architecture as present in compile.h
++UTS_MACHINE := $(ARCH)
++SRCARCH := $(ARCH)
++
++# Additional ARCH settings for x86
++ifeq ($(ARCH),i386)
++ SRCARCH := x86
++endif
++ifeq ($(ARCH),x86_64)
++ SRCARCH := x86
++endif
++
++# Additional ARCH settings for sparc
++ifeq ($(ARCH),sparc64)
++ SRCARCH := sparc
++endif
++
++# Additional ARCH settings for sh
++ifeq ($(ARCH),sh64)
++ SRCARCH := sh
++endif
++
++# Additional ARCH settings for tile
++ifeq ($(ARCH),tilepro)
++ SRCARCH := tile
++endif
++ifeq ($(ARCH),tilegx)
++ SRCARCH := tile
++endif
++
++# Where to locate arch specific headers
++hdr-arch := $(SRCARCH)
++
++ifeq ($(ARCH),m68knommu)
++ hdr-arch := m68k
++endif
+
+ # Use LINUXINCLUDE when you must reference the include/ directory.
+ # Needed to be compatible with the O= option
+@@ -978,7 +976,7 @@ endif
+ prepare2: prepare3 outputmakefile asm-generic
+
+ prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \
+- include/config/auto.conf
++ include/config/auto.conf include/generated/package.h
+ $(cmd_crmodverdir)
+
+ archprepare: archscripts prepare1 scripts_basic
+@@ -1010,12 +1008,25 @@ define filechk_version.h
+ echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))';)
+ endef
+
++ifneq ($(DISTRIBUTION_OFFICIAL_BUILD),)
++define filechk_package.h
++ echo \#define LINUX_PACKAGE_ID \" $(DISTRIBUTOR) $(DISTRIBUTION_VERSION)\"
++endef
++else
++define filechk_package.h
++ echo \#define LINUX_PACKAGE_ID \"\"
++endef
++endif
++
+ include/linux/version.h: $(srctree)/Makefile FORCE
+ $(call filechk,version.h)
+
+ include/generated/utsrelease.h: include/config/kernel.release FORCE
+ $(call filechk,utsrelease.h)
+
++include/generated/package.h: $(srctree)/Makefile FORCE
++ $(call filechk,package.h)
++
+ PHONY += headerdep
+ headerdep:
+ $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 082bd36..7a06e22 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_Kconfig.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_Kconfig.patch
new file mode 100644
index 00000000..47cb8e3e
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_Kconfig.patch
@@ -0,0 +1,85 @@
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -30,6 +30,7 @@ config ARM
+ select HAVE_SPARSE_IRQ
+ select GENERIC_IRQ_SHOW
+ select CPU_PM if (SUSPEND || CPU_IDLE)
++ select HAVE_BPF_JIT
+ help
+ The ARM series is a line of low-power-consumption RISC chip designs
+ licensed by ARM Ltd and targeted at embedded applications and
+@@ -161,6 +162,13 @@ config ARCH_HAS_CPUFREQ
+ config ARCH_HAS_CPU_IDLE_WAIT
+ def_bool y
+
++-config ARCH_SUPPORTS_BIG_ENDIAN
++ bool
++ default y if ARCH_IXP4XX
++ help
++ Internal node to specify the architecture can run in Big Endian
++ mode.
++
+ config GENERIC_HWEIGHT
+ bool
+ default y
+@@ -978,6 +986,30 @@ config ARCH_ZYNQ
+ select USE_OF
+ help
+ Support for Xilinx Zynq ARM Cortex A9 Platform
++
++config ARCH_IPROC
++ bool "Broadcom ARMv7 iProc boards"
++ depends on MMU
++ select CPU_V7
++ select HAVE_CLK
++ select HAVE_SMP
++ select HAVE_MACH_CLKDEV
++ select COMMON_CLKDEV
++ select CLKDEV_LOOKUP
++ select ARM_GIC
++ select HAVE_ARM_SCU
++ select GENERIC_CLOCKEVENTS_BUILD
++ select GENERIC_CLOCKEVENTS
++ select PCI
++ select GENERIC_GPIO
++ select ARCH_REQUIRE_GPIOLIB
++ select CACHE_L2X0
++ select ARM_AMBA
++ select ARCH_HAS_CPUFREQ
++ select MULTI_IRQ_HANDLER
++ help
++ This is a common family of Broadcom Cortex A9 based boards
++
+ endchoice
+
+ #
+@@ -1013,6 +1045,8 @@ source "arch/arm/mach-iop33x/Kconfig"
+
+ source "arch/arm/mach-iop13xx/Kconfig"
+
++source "arch/arm/plat-iproc/Kconfig"
++
+ source "arch/arm/mach-ixp4xx/Kconfig"
+
+ source "arch/arm/mach-ixp2000/Kconfig"
+@@ -1023,6 +1057,8 @@ source "arch/arm/mach-kirkwood/Kconfig"
+
+ source "arch/arm/mach-ks8695/Kconfig"
+
++source "arch/arm/mach-iproc/Kconfig"
++
+ source "arch/arm/mach-lpc32xx/Kconfig"
+
+ source "arch/arm/mach-msm/Kconfig"
+@@ -1452,7 +1488,8 @@ config SMP
+ depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+ ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+- ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
++ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q || \
++ ARCH_IPROC
+ depends on MMU
+ select USE_GENERIC_SMP_HELPERS
+ select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index 362c7ca..e11f8ee 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_Makefile.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_Makefile.patch
new file mode 100644
index 00000000..937a0d51
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_Makefile.patch
@@ -0,0 +1,28 @@
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -198,6 +198,7 @@ machine-$(CONFIG_MACH_SPEAR310) := spear3xx
+ machine-$(CONFIG_MACH_SPEAR320) := spear3xx
+ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
+ machine-$(CONFIG_ARCH_ZYNQ) := zynq
++machine-$(CONFIG_MACH_IPROC) := iproc
+
+ # Platform directory name. This list is sorted alphanumerically
+ # by CONFIG_* macro name.
+@@ -214,6 +215,7 @@ plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
+ plat-$(CONFIG_PLAT_S5P) := s5p samsung
+ plat-$(CONFIG_PLAT_SPEAR) := spear
+ plat-$(CONFIG_PLAT_VERSATILE) := versatile
++plat-$(CONFIG_ARCH_IPROC) := iproc
+
+ ifeq ($(CONFIG_ARCH_EBSA110),y)
+ # This is what happens if you forget the IOCS16 line.
+@@ -255,6 +257,7 @@ core-$(CONFIG_VFP) += arch/arm/vfp/
+
+ # If we have a machine-specific directory, then include it in the build.
+ core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
++core-y += arch/arm/net/
+ core-y += $(machdirs) $(platdirs)
+
+ drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 8c57359..6bfca86 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_compressed_head.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_compressed_head.S.patch
new file mode 100644
index 00000000..f09f0cb3
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_compressed_head.S.patch
@@ -0,0 +1,13 @@
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -18,6 +18,7 @@
+ * 100% relocatable. Any attempt to do so will result in a crash.
+ * Please select one of the following when turning on debugging.
+ */
++#define DEBUG 1
+ #ifdef DEBUG
+
+ #if defined(CONFIG_DEBUG_ICEDCC)
+diff --git a/arch/arm/boot/dts/accton_as4610_54.dts b/arch/arm/boot/dts/accton_as4610_54.dts
+new file mode 100644
+index 0000000..9276c0a
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_accton_as4610_54.dts.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_accton_as4610_54.dts.patch
new file mode 100644
index 00000000..7737f9ef
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_accton_as4610_54.dts.patch
@@ -0,0 +1,256 @@
+--- /dev/null
++++ b/arch/arm/boot/dts/accton_as4610_54.dts
+@@ -0,0 +1,250 @@
++/*
++ * Accton AS4610 54 Device Tree Source
++ *
++ * Copyright 2015, Cumulus Networks, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++/dts-v1/;
++/include/ "helix4.dtsi"
++
++/ {
++ model = "accton,as4610_54";
++ compatible = "accton,as4610_54";
++
++ aliases {
++ serial0 = &uart0;
++ i2c-controller0 = &i2c0;
++ i2c-controller1 = &i2c1;
++ };
++
++ memory {
++ reg = <0x61000000 0x7f000000>;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x00>;
++ };
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x01>;
++ };
++ };
++
++ localbus@1c000000 {
++ #address-cells = <0x2>;
++ #size-cells = <0x1>;
++ /* NAND Flash */
++ ranges = <
++ 0x0 0x0 0x0 0x1c000000 0x00120000
++ 0x1 0x0 0x0 0x1c120000 0x00040000
++ >;
++
++ flash@0,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "cfi-flash";
++ reg = <0x0 0x0 0x02000000>;
++ byteswap;
++
++ partition@0 {
++ /* uboot */
++ reg = <0x00000000 0x00100000>;
++ label = "uboot";
++ };
++ partition@1 {
++ /* uboot-env */
++ reg = <0x00100000 0x00100000>;
++ label = "uboot-env";
++ env_size = <0x2000>;
++ };
++ partition@2 {
++ /* board_eeprom */
++ reg = <0x00200000 0x00100000>;
++ label = "board_eeprom";
++ };
++ partition@3 {
++ /* shmoo */
++ reg = <0x00300000 0x00100000>;
++ label = "shmoo";
++ };
++ partition@4 {
++ /* onie */
++ reg = <0x00400000 0x00800000>;
++ label = "onie";
++ };
++ partition@5 {
++ /* open */
++ reg = <0x00c00000 0x03c00000>;
++ label = "open";
++ };
++ partition@6 {
++ /* open2 */
++ reg = <0x04800000 0x7d000000>;
++ label = "open2";
++ };
++ partition@7 {
++ /* diag */
++ reg = <0xfec00000 0x01000000>;
++ label = "diag";
++ };
++ };
++ };
++
++ i2c0: i2c@18038000 {
++ compatible = "iproc-smb";
++ reg = <0x18038000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = < 127 >;
++ clock-frequency = <400000>;
++ cpld@1,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "accton,as4610-54-cpld";
++ label = "cpld";
++ reg = <0x30>;
++ };
++ };
++
++ i2c1: i2c@1803b000 {
++ compatible = "iproc-smb";
++ reg = <0x1803b000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = < 128 >;
++ clock-frequency = <100000>;
++ mux@70 {
++ compatible = "ti,pca9548";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ deselect-on-exit;
++
++ // SFP+ 1
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port49";
++ };
++ };
++
++ // SFP+ 2
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port50";
++ };
++ };
++
++ // SFP+ 3
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port51";
++ };
++ };
++
++ // SFP+ 4
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "port52";
++ };
++ };
++
++ // QSFP+ STK1
++ i2c@4 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <4>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ };
++ };
++
++ // QSFP+ STK2
++ i2c@5 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <5>;
++ sfp_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ };
++ };
++
++ // PSU EEPROM
++ i2c@6 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <6>;
++ psu_eeprom@50 {
++ compatible = "at,24c02";
++ reg = <0x50>;
++ label = "psu1_eeprom";
++ read-only;
++ };
++ psu_eeprom@51 {
++ compatible = "at,24c02";
++ reg = <0x51>;
++ label = "psu2_eeprom";
++ read-only;
++ };
++ };
++
++ i2c@7 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <7>;
++
++ temp@48 {
++ compatible = "nxp,lm77";
++ reg = <0x48>;
++ };
++
++ rtc@68 {
++ /* Actually M41T11 */
++ compatible = "dallas,ds1307";
++ reg = <0x68>;
++ };
++
++ board_eeprom@50 {
++ compatible = "at,24c04";
++ reg = <0x50>;
++ label = "board_eeprom";
++ };
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/dni_3448p.dts b/arch/arm/boot/dts/dni_3448p.dts
+new file mode 100644
+index 0000000..29ce09c
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_dni_3448p.dts.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_dni_3448p.dts.patch
new file mode 100644
index 00000000..61a1af5f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_dni_3448p.dts.patch
@@ -0,0 +1,172 @@
+--- /dev/null
++++ b/arch/arm/boot/dts/dni_3448p.dts
+@@ -0,0 +1,166 @@
++/*
++ * Delta Networks, Inc. 3448p Device Tree Source
++ *
++ * Copyright 2015, Cumulus Networks, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ */
++/dts-v1/;
++/include/ "helix4.dtsi"
++
++/ {
++ model = "dni,3448p";
++ compatible = "dni,dni_3448p";
++
++ memory {
++ reg = <0x61000000 0x3f000000>;
++ };
++
++ aliases {
++ serial0 = &uart0;
++ i2c-controller0 = &i2c0;
++ i2c-controller1 = &i2c1;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x00>;
++ };
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ next-level-cache = <&L2>;
++ reg = <0x01>;
++ };
++ };
++
++ localbus@1c000000 {
++ #address-cells = <0x2>;
++ #size-cells = <0x1>;
++ /* NAND Flash */
++ ranges = <
++ 0x0 0x0 0x0 0x1c000000 0x00120000
++ 0x1 0x0 0x0 0x1c120000 0x00040000
++ >;
++
++ flash@0,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "cfi-flash";
++ reg = <0x0 0x0 0x02000000>;
++ byteswap;
++
++ partition@0 {
++ /* uboot */
++ reg = <0x00000000 0x00100000>;
++ label = "uboot";
++ };
++ partition@1 {
++ /* uboot-env */
++ reg = <0x00100000 0x00400000>;
++ label = "uboot-env";
++ env_size = <0x10000>;
++ };
++ partition@2 {
++ /* vpd */
++ reg = <0x00500000 0x00200000>;
++ label = "vpd";
++ };
++ partition@3 {
++ /* shmoo */
++ reg = <0x00700000 0x00200000>;
++ label = "shmoo";
++ };
++ partition@4 {
++ /* open */
++ reg = <0x00900000 0xf9500000>;
++ label = "open";
++ };
++ partition@5 {
++ /* onie */
++ reg = <0xf9e00000 0x00c00000>;
++ label = "onie";
++ };
++ partition@6 {
++ /* onie2 */
++ reg = <0xfaa00000 0x00c00000>;
++ label = "onie2";
++ };
++ partition@7 {
++ /* board_eeprom */
++ reg = <0xfb600000 0x00600000>;
++ label = "board_eeprom";
++ };
++ partition@8 {
++ /* diags */
++ reg = <0xfbc00000 0x02000000>;
++ label = "diag";
++ };
++ partition@9 {
++ /* diags2 */
++ reg = <0xfdc00000 0x02000000>;
++ label = "diag2";
++ };
++ };
++ cpld@1,0 {
++ compatible = "dni,3448p-cpld";
++ reg = <0x1 0x0 0x00040000>;
++ };
++ };
++
++ i2c0: i2c@18038000 {
++ compatible = "iproc-smb";
++ reg = <0x18038000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <0x0 127 0x0>;
++ clock-frequency = <100000>;
++ rtc@68 {
++ compatible = "stm,m41st85";
++ reg = <0x68>;
++ };
++ tmon@49 {
++ compatible = "ti,tmp75";
++ reg = <0x49>;
++ };
++ tmon@4a {
++ compatible = "ti,tmp75";
++ reg = <0x4a>;
++ };
++ CPLD1@1,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "dni,3448p-cpld";
++ label = "cpld";
++ reg = <0x28>;
++ };
++ };
++
++ i2c1: i2c@1803b000 {
++ compatible = "iproc-smb";
++ reg = <0x1803b000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <0x0 128 0x0>;
++ clock-frequency = <100000>;
++
++ fan@2c {
++ compatible = "maxim,max6639";
++ reg = <0x2c>;
++ };
++ psumux@01 {
++ compatible = "3448p-psu-mux";
++ reg = <0x01>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/helix4.dtsi b/arch/arm/boot/dts/helix4.dtsi
+new file mode 100644
+index 0000000..1a7ce9e
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_helix4.dtsi.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_helix4.dtsi.patch
new file mode 100644
index 00000000..0d5d3e20
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_boot_dts_helix4.dtsi.patch
@@ -0,0 +1,65 @@
+--- /dev/null
++++ b/arch/arm/boot/dts/helix4.dtsi
+@@ -0,0 +1,59 @@
++/include/ "skeleton.dtsi"
++
++/ {
++ interrupt-parent = <&gic>;
++
++ chipcommonA {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x18000000 0x00001000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ uart0: serial@0300 {
++ compatible = "ns16550";
++ reg = <0x0300 0x100>;
++ interrupts = <123>;
++ clock-frequency = <100000000>;
++ status = "enabled";
++ };
++ };
++
++ mpcore {
++ compatible = "simple-bus";
++ ranges = <0x00000000 0x19020000 0x00003000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ scu@0000 {
++ compatible = "arm,cortex-a9-scu";
++ reg = <0x0000 0x100>;
++ };
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x0100 0x100>;
++ };
++
++ L2: cache-controller@2000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x2000 0x1000>;
++ cache-unified;
++ cache-level = <2>;
++ };
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ clk_periph: periph {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <400000000>;
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
+new file mode 100644
+index 0000000..a5376b8
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_common_gic.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_common_gic.c.patch
new file mode 100644
index 00000000..5e544e90
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_common_gic.c.patch
@@ -0,0 +1,44 @@
+--- a/arch/arm/common/gic.c
++++ b/arch/arm/common/gic.c
+@@ -40,6 +40,8 @@
+ #include
+
+ #include
++#include
++#include
+ #include
+ #include
+
+@@ -215,6 +217,29 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
+ #define gic_set_wake NULL
+ #endif
+
++asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
++{
++ u32 irqstat, irqnr;
++
++ do {
++ irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
++ irqnr = irqstat & ~0x1c00;
++
++ if (likely(irqnr > 15 && irqnr < 1021)) {
++ handle_IRQ(irqnr, regs);
++ continue;
++ }
++ if (irqnr < 16) {
++ writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
++#ifdef CONFIG_SMP
++ do_IPI(irqnr, regs);
++#endif
++ continue;
++ }
++ break;
++ } while (1);
++}
++
+ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+ {
+ struct gic_chip_data *chip_data = irq_get_handler_data(irq);
+diff --git a/arch/arm/configs/iproc_defconfig b/arch/arm/configs/iproc_defconfig
+new file mode 100644
+index 0000000..c401047
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_configs_iproc_defconfig.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_configs_iproc_defconfig.patch
new file mode 100644
index 00000000..7757265a
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_configs_iproc_defconfig.patch
@@ -0,0 +1,2430 @@
+--- /dev/null
++++ b/arch/arm/configs/iproc_defconfig
+@@ -0,0 +1,2425 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/arm 3.6.5 Kernel Configuration
++#
++CONFIG_ARM=y
++CONFIG_SYS_SUPPORTS_APM_EMULATION=y
++CONFIG_GENERIC_GPIO=y
++CONFIG_HAVE_PROC_CPU=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_HWEIGHT=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_ARM_PATCH_PHYS_VIRT=y
++CONFIG_GENERIC_BUG=y
++CONFIG_HAVE_IRQ_WORK=y
++
++#
++# General setup
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_KERNEL_GZIP=y
++# CONFIG_KERNEL_LZMA is not set
++# CONFIG_KERNEL_XZ is not set
++# CONFIG_KERNEL_LZO is not set
++CONFIG_DEFAULT_HOSTNAME="(none)"
++# CONFIG_SWAP is not set
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_FHANDLE is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
++CONFIG_HAVE_GENERIC_HARDIRQS=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++# CONFIG_IRQ_DOMAIN_DEBUG is not set
++CONFIG_KTIME_SCALAR=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++
++#
++# Timers subsystem
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++# CONFIG_HIGH_RES_TIMERS is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_PREEMPT_RCU is not set
++CONFIG_RCU_FANOUT=32
++CONFIG_RCU_FANOUT_LEAF=16
++# CONFIG_RCU_FANOUT_EXACT is not set
++# CONFIG_RCU_FAST_NO_HZ is not set
++# CONFIG_TREE_RCU_TRACE is not set
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_CHECKPOINT_RESTORE is not set
++# CONFIG_NAMESPACES is not set
++# CONFIG_SCHED_AUTOGROUP is not set
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_ROOT_UID=0
++CONFIG_INITRAMFS_ROOT_GID=0
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_INITRAMFS_COMPRESSION_NONE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_SYSCTL=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
++CONFIG_KALLSYMS=y
++# CONFIG_KALLSYMS_ALL is not set
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++# CONFIG_ELF_CORE is not set
++# CONFIG_BASE_FULL is not set
++CONFIG_FUTEX=y
++# CONFIG_EPOLL is not set
++# CONFIG_SIGNALFD is not set
++# CONFIG_TIMERFD is not set
++# CONFIG_EVENTFD is not set
++# CONFIG_SHMEM is not set
++# CONFIG_AIO is not set
++CONFIG_EMBEDDED=y
++CONFIG_HAVE_PERF_EVENTS=y
++CONFIG_PERF_USE_VMALLOC=y
++
++#
++# Kernel Performance Events And Counters
++#
++# CONFIG_PERF_EVENTS is not set
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_PCI_QUIRKS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++# CONFIG_PROFILING is not set
++CONFIG_HAVE_OPROFILE=y
++# CONFIG_KPROBES is not set
++# CONFIG_JUMP_LABEL is not set
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_ATTRS=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_USE_GENERIC_SMP_HELPERS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_DMA_API_DEBUG=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_HAVE_GENERIC_DMA_COHERENT=y
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=1
++CONFIG_MODULES=y
++# CONFIG_MODULE_FORCE_LOAD is not set
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_MODULE_FORCE_UNLOAD is not set
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_STOP_MACHINE=y
++CONFIG_BLOCK=y
++CONFIG_LBDAF=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++# CONFIG_BSD_DISKLABEL is not set
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_SYSV68_PARTITION is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++# CONFIG_INLINE_SPIN_TRYLOCK is not set
++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK is not set
++# CONFIG_INLINE_SPIN_LOCK_BH is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_READ_TRYLOCK is not set
++# CONFIG_INLINE_READ_LOCK is not set
++# CONFIG_INLINE_READ_LOCK_BH is not set
++# CONFIG_INLINE_READ_LOCK_IRQ is not set
++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
++CONFIG_INLINE_READ_UNLOCK=y
++# CONFIG_INLINE_READ_UNLOCK_BH is not set
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
++# CONFIG_INLINE_WRITE_TRYLOCK is not set
++# CONFIG_INLINE_WRITE_LOCK is not set
++# CONFIG_INLINE_WRITE_LOCK_BH is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
++CONFIG_INLINE_WRITE_UNLOCK=y
++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_FREEZER=y
++
++#
++# System Type
++#
++CONFIG_MMU=y
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_VEXPRESS is not set
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_BCMRING is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CNS3XXX is not set
++# CONFIG_ARCH_GEMINI is not set
++# CONFIG_ARCH_PRIMA2 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_MXC is not set
++# CONFIG_ARCH_MXS is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IOP13XX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_DOVE is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_MV78XX0 is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_ARCH_MMP is not set
++# CONFIG_ARCH_KS8695 is not set
++# CONFIG_ARCH_W90X900 is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_PICOXCELL is not set
++# CONFIG_ARCH_PNX4008 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_MSM is not set
++# CONFIG_ARCH_SHMOBILE is not set
++# CONFIG_ARCH_RPC is not set
++# CONFIG_ARCH_SA1100 is not set
++# CONFIG_ARCH_S3C24XX is not set
++# CONFIG_ARCH_S3C64XX is not set
++# CONFIG_ARCH_S5P64X0 is not set
++# CONFIG_ARCH_S5PC100 is not set
++# CONFIG_ARCH_S5PV210 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_U300 is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_NOMADIK is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_OMAP is not set
++# CONFIG_PLAT_SPEAR is not set
++# CONFIG_ARCH_VT8500 is not set
++# CONFIG_ARCH_ZYNQ is not set
++CONFIG_ARCH_IPROC=y
++CONFIG_BCM_ZRELADDR=0x61008000
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++
++#
++# Broadcom IPROC architecture based implementations
++#
++# CONFIG_ARCH_NORTHSTAR is not set
++CONFIG_MACH_IPROC=y
++CONFIG_GP_TIMER_COMPARATOR_LOAD_DELAY=y
++CONFIG_IPROC_DCACHE_INVALIDATION=y
++# CONFIG_IPROC_TIMER_UNIT_TESTS is not set
++# CONFIG_IPROC_SW_RESET_RECORD is not set
++# CONFIG_BRCM_PROP_MODULES is not set
++# CONFIG_BCM_STM is not set
++CONFIG_BCM_PARAMS_PHYS=0x61000000
++CONFIG_BCM_RAM_BASE=0x60000000
++CONFIG_BCM_RAM_START_RESERVED_SIZE=0x200000
++
++#
++# Broadcom iProc Drivers
++#
++# CONFIG_IPROC_CCB_TIMER is not set
++# CONFIG_IPROC_RNG is not set
++CONFIG_IPROC_MDIO=y
++# CONFIG_IPROC_GSIO_SPI is not set
++# CONFIG_IPROC_SD is not set
++# CONFIG_IPROC_DMA is not set
++CONFIG_IPROC_GPIO=y
++CONFIG_IPROC_QSPI=y
++CONFIG_IPROC_QSPI_SINGLE_MODE=y
++# CONFIG_IPROC_QSPI_DUAL_MODE is not set
++# CONFIG_IPROC_QSPI_QUAD_MODE is not set
++CONFIG_IPROC_QSPI_MAX_HZ=62500000
++CONFIG_IPROC_MTD_NAND=y
++# CONFIG_IPROC_MTD_NAND_USE_JFFS2 is not set
++# CONFIG_IPROC_MTD_NOR is not set
++# CONFIG_IPROC_PMU is not set
++# CONFIG_IPROC_PWM is not set
++CONFIG_IPROC_USB2H=y
++CONFIG_USB_EHCI_BCM=y
++CONFIG_USB_OHCI_BCM=y
++# CONFIG_IPROC_USB3H is not set
++CONFIG_IPROC_USB2D=m
++CONFIG_IPROC_PCIE=y
++# CONFIG_IPROC_PCIE_AER is not set
++CONFIG_IPROC_GMAC=y
++
++#
++# Broadcom HND network devices
++#
++CONFIG_HND=y
++CONFIG_ET=y
++CONFIG_ET_47XX=y
++CONFIG_ET_ALL_PASSIVE_ON=y
++# CONFIG_ET_ALL_PASSIVE_RUNTIME is not set
++# CONFIG_BCM_CTF is not set
++# CONFIG_BCM_IPROC_GMAC_ACP is not set
++# CONFIG_WL_EMULATOR is not set
++# CONFIG_BCM57XX is not set
++# CONFIG_WL is not set
++# CONFIG_WL_USBAP is not set
++CONFIG_WL_AP="wlconfig_lx_router_ap"
++CONFIG_WL_AP_SDSTD="wlconfig_lx_router_ap_sdstd"
++CONFIG_WL_STA="wlconfig_lx_router_sta"
++CONFIG_WL_APSTA="wlconfig_lx_router_apsta"
++CONFIG_WL_AP_ONCHIP_G="wlconfig_lx_router_ap_1chipG"
++CONFIG_WL_STA_ONCHIP_G="wlconfig_lx_router_sta_1chipG"
++CONFIG_WL_HIGH="wlconfig_lx_router_high"
++# CONFIG_EMF is not set
++# CONFIG_IPROC_SND is not set
++CONFIG_IPROC_I2C=y
++# CONFIG_IPROC_SRA is not set
++# CONFIG_IPROC_TDM is not set
++
++#
++# Broadcom iProc GPL Drivers
++#
++# CONFIG_IPROC_SND_CODEC_WM8955 is not set
++# CONFIG_IPROC_SND_CODEC_WM8750 is not set
++CONFIG_IPROC_CCB_WDT=y
++
++#
++# iProc SoC based Machine types
++#
++# CONFIG_MACH_NS is not set
++# CONFIG_MACH_HX4 is not set
++# CONFIG_MACH_HR2 is not set
++# CONFIG_MACH_NSP is not set
++# CONFIG_MACH_KT2 is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_V7=y
++CONFIG_CPU_32v6K=y
++CONFIG_CPU_32v7=y
++CONFIG_CPU_ABRT_EV7=y
++CONFIG_CPU_PABRT_V7=y
++CONFIG_CPU_CACHE_V7=y
++CONFIG_CPU_CACHE_VIPT=y
++CONFIG_CPU_COPY_V6=y
++CONFIG_CPU_TLB_V7=y
++CONFIG_CPU_HAS_ASID=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
++
++#
++# Processor Features
++#
++# CONFIG_ARM_LPAE is not set
++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
++CONFIG_ARM_THUMB=y
++# CONFIG_ARM_THUMBEE is not set
++# CONFIG_SWP_EMULATE is not set
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
++# CONFIG_CPU_BPREDICT_DISABLE is not set
++CONFIG_OUTER_CACHE=y
++CONFIG_OUTER_CACHE_SYNC=y
++CONFIG_CACHE_L2X0=y
++CONFIG_CACHE_PL310=y
++CONFIG_ARM_L1_CACHE_SHIFT_6=y
++CONFIG_ARM_L1_CACHE_SHIFT=6
++CONFIG_ARM_DMA_MEM_BUFFERABLE=y
++CONFIG_ARM_NR_BANKS=8
++CONFIG_CPU_HAS_PMU=y
++CONFIG_MULTI_IRQ_HANDLER=y
++# CONFIG_ARM_ERRATA_430973 is not set
++# CONFIG_ARM_ERRATA_458693 is not set
++# CONFIG_ARM_ERRATA_460075 is not set
++# CONFIG_ARM_ERRATA_742230 is not set
++# CONFIG_ARM_ERRATA_742231 is not set
++# CONFIG_PL310_ERRATA_588369 is not set
++# CONFIG_ARM_ERRATA_720789 is not set
++# CONFIG_PL310_ERRATA_727915 is not set
++# CONFIG_ARM_ERRATA_743622 is not set
++# CONFIG_ARM_ERRATA_751472 is not set
++# CONFIG_PL310_ERRATA_753970 is not set
++# CONFIG_ARM_ERRATA_754322 is not set
++# CONFIG_ARM_ERRATA_754327 is not set
++# CONFIG_ARM_ERRATA_764369 is not set
++# CONFIG_PL310_ERRATA_769419 is not set
++# CONFIG_ARM_ERRATA_775420 is not set
++CONFIG_ARM_GIC=y
++
++#
++# Bus support
++#
++CONFIG_ARM_AMBA=y
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCI_SYSCALL=y
++CONFIG_ARCH_SUPPORTS_MSI=y
++CONFIG_PCI_MSI=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++# CONFIG_PCI_STUB is not set
++# CONFIG_PCI_IOV is not set
++# CONFIG_PCI_PRI is not set
++# CONFIG_PCI_PASID is not set
++# CONFIG_PCCARD is not set
++
++#
++# Kernel Features
++#
++CONFIG_HAVE_SMP=y
++CONFIG_SMP=y
++CONFIG_SMP_ON_UP=y
++CONFIG_ARM_CPU_TOPOLOGY=y
++# CONFIG_SCHED_MC is not set
++# CONFIG_SCHED_SMT is not set
++CONFIG_HAVE_ARM_SCU=y
++# CONFIG_ARM_ARCH_TIMER is not set
++CONFIG_HAVE_ARM_TWD=y
++CONFIG_VMSPLIT_3G=y
++# CONFIG_VMSPLIT_2G is not set
++# CONFIG_VMSPLIT_1G is not set
++CONFIG_PAGE_OFFSET=0xC0000000
++CONFIG_NR_CPUS=4
++CONFIG_HOTPLUG_CPU=y
++CONFIG_LOCAL_TIMERS=y
++CONFIG_ARCH_NR_GPIO=0
++CONFIG_PREEMPT_NONE=y
++# CONFIG_PREEMPT_VOLUNTARY is not set
++# CONFIG_PREEMPT is not set
++CONFIG_HZ=100
++# CONFIG_THUMB2_KERNEL is not set
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
++CONFIG_HAVE_ARCH_PFN_VALID=y
++# CONFIG_HIGHMEM is not set
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_FLATMEM_MANUAL=y
++CONFIG_FLATMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_HAVE_MEMBLOCK=y
++CONFIG_PAGEFLAGS_EXTENDED=y
++CONFIG_SPLIT_PTLOCK_CPUS=4
++# CONFIG_COMPACTION is not set
++# CONFIG_PHYS_ADDR_T_64BIT is not set
++CONFIG_ZONE_DMA_FLAG=0
++CONFIG_VIRT_TO_BUS=y
++# CONFIG_KSM is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_CLEANCACHE is not set
++CONFIG_FORCE_MAX_ZONEORDER=11
++CONFIG_ALIGNMENT_TRAP=y
++# CONFIG_UACCESS_WITH_MEMCPY is not set
++# CONFIG_SECCOMP is not set
++# CONFIG_CC_STACKPROTECTOR is not set
++# CONFIG_DEPRECATED_PARAM_STRUCT is not set
++
++#
++# Boot options
++#
++# CONFIG_USE_OF is not set
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="console=ttyS0,115200n8 maxcpus=2 mem=512M"
++CONFIG_CMDLINE_FROM_BOOTLOADER=y
++# CONFIG_CMDLINE_EXTEND is not set
++# CONFIG_CMDLINE_FORCE is not set
++# CONFIG_XIP_KERNEL is not set
++# CONFIG_KEXEC is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_AUTO_ZRELADDR is not set
++
++#
++# CPU Power Management
++#
++# CONFIG_CPU_IDLE is not set
++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++# CONFIG_VFP is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
++CONFIG_HAVE_AOUT=y
++# CONFIG_BINFMT_AOUT is not set
++# CONFIG_BINFMT_MISC is not set
++
++#
++# Power management options
++#
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
++CONFIG_PM_SLEEP=y
++CONFIG_PM_SLEEP_SMP=y
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++# CONFIG_PM_RUNTIME is not set
++CONFIG_PM=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_APM_EMULATION is not set
++CONFIG_PM_CLK=y
++CONFIG_CPU_PM=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARM_CPU_SUSPEND=y
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++# CONFIG_UNIX_DIAG is not set
++# CONFIG_XFRM_USER is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++# CONFIG_IP_FIB_TRIE_STATS is not set
++CONFIG_IP_MULTIPLE_TABLES=y
++# CONFIG_IP_ROUTE_MULTIPATH is not set
++# CONFIG_IP_ROUTE_VERBOSE is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++# CONFIG_IP_MROUTE is not set
++CONFIG_ARPD=y
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_INET_DIAG is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_DEBUG=y
++CONFIG_NETFILTER_ADVANCED=y
++CONFIG_BRIDGE_NETFILTER=y
++
++#
++# Core Netfilter Configuration
++#
++CONFIG_NETFILTER_NETLINK=y
++# CONFIG_NETFILTER_NETLINK_ACCT is not set
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_PROCFS=y
++# CONFIG_NF_CONNTRACK_EVENTS is not set
++# CONFIG_NF_CONNTRACK_TIMEOUT is not set
++# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++# CONFIG_NF_CONNTRACK_AMANDA is not set
++CONFIG_NF_CONNTRACK_FTP=y
++# CONFIG_NF_CONNTRACK_H323 is not set
++# CONFIG_NF_CONNTRACK_IRC is not set
++# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
++# CONFIG_NF_CONNTRACK_SNMP is not set
++# CONFIG_NF_CONNTRACK_PPTP is not set
++# CONFIG_NF_CONNTRACK_SANE is not set
++# CONFIG_NF_CONNTRACK_SIP is not set
++CONFIG_NF_CONNTRACK_TFTP=y
++# CONFIG_NF_CT_NETLINK is not set
++# CONFIG_NF_CT_NETLINK_TIMEOUT is not set
++# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set
++CONFIG_NETFILTER_TPROXY=y
++CONFIG_NETFILTER_XTABLES=y
++
++#
++# Xtables combined modules
++#
++CONFIG_NETFILTER_XT_MARK=y
++CONFIG_NETFILTER_XT_CONNMARK=y
++
++#
++# Xtables targets
++#
++# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
++# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
++# CONFIG_NETFILTER_XT_TARGET_CT is not set
++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
++CONFIG_NETFILTER_XT_TARGET_HL=y
++# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
++# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
++# CONFIG_NETFILTER_XT_TARGET_LOG is not set
++# CONFIG_NETFILTER_XT_TARGET_MARK is not set
++# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
++# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
++# CONFIG_NETFILTER_XT_TARGET_TEE is not set
++# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set
++# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
++# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
++
++#
++# Xtables matches
++#
++# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
++# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
++# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
++# CONFIG_NETFILTER_XT_MATCH_CPU is not set
++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
++# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
++CONFIG_NETFILTER_XT_MATCH_ECN=y
++# CONFIG_NETFILTER_XT_MATCH_ESP is not set
++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
++CONFIG_NETFILTER_XT_MATCH_HL=y
++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
++# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
++# CONFIG_NETFILTER_XT_MATCH_MAC is not set
++# CONFIG_NETFILTER_XT_MATCH_MARK is not set
++# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
++# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set
++# CONFIG_NETFILTER_XT_MATCH_OSF is not set
++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
++# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
++# CONFIG_NETFILTER_XT_MATCH_REALM is not set
++# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set
++CONFIG_NETFILTER_XT_MATCH_STATE=y
++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
++# CONFIG_NETFILTER_XT_MATCH_STRING is not set
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
++# CONFIG_NETFILTER_XT_MATCH_TIME is not set
++# CONFIG_NETFILTER_XT_MATCH_U32 is not set
++# CONFIG_IP_SET is not set
++# CONFIG_IP_VS is not set
++
++#
++# IP: Netfilter Configuration
++#
++CONFIG_NF_DEFRAG_IPV4=y
++CONFIG_NF_CONNTRACK_IPV4=y
++CONFIG_NF_CONNTRACK_PROC_COMPAT=y
++CONFIG_IP_NF_QUEUE=y
++CONFIG_IP_NF_IPTABLES=y
++CONFIG_IP_NF_MATCH_AH=y
++CONFIG_IP_NF_MATCH_ECN=y
++# CONFIG_IP_NF_MATCH_RPFILTER is not set
++CONFIG_IP_NF_MATCH_TTL=y
++CONFIG_IP_NF_FILTER=y
++CONFIG_IP_NF_TARGET_REJECT=y
++CONFIG_IP_NF_TARGET_ULOG=y
++CONFIG_NF_NAT=y
++CONFIG_NF_NAT_NEEDED=y
++CONFIG_IP_NF_TARGET_MASQUERADE=y
++CONFIG_IP_NF_TARGET_NETMAP=y
++CONFIG_IP_NF_TARGET_REDIRECT=y
++CONFIG_NF_NAT_FTP=y
++# CONFIG_NF_NAT_IRC is not set
++CONFIG_NF_NAT_TFTP=y
++# CONFIG_NF_NAT_AMANDA is not set
++# CONFIG_NF_NAT_PPTP is not set
++# CONFIG_NF_NAT_H323 is not set
++# CONFIG_NF_NAT_SIP is not set
++CONFIG_IP_NF_MANGLE=y
++# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
++CONFIG_IP_NF_TARGET_ECN=y
++CONFIG_IP_NF_TARGET_TTL=y
++CONFIG_IP_NF_RAW=y
++CONFIG_IP_NF_ARPTABLES=y
++CONFIG_IP_NF_ARPFILTER=y
++CONFIG_IP_NF_ARP_MANGLE=y
++# CONFIG_BRIDGE_NF_EBTABLES is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++CONFIG_STP=y
++CONFIG_GARP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_IGMP_SNOOPING=y
++# CONFIG_NET_DSA is not set
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++# CONFIG_DECNET is not set
++CONFIG_LLC=y
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_WAN_ROUTER is not set
++# CONFIG_PHONET is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++CONFIG_DNS_RESOLVER=y
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_XPS=y
++CONFIG_BQL=y
++# CONFIG_BPF_JIT is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++# CONFIG_IRDA is not set
++# CONFIG_BT is not set
++# CONFIG_AF_RXRPC is not set
++CONFIG_FIB_RULES=y
++CONFIG_WIRELESS=y
++# CONFIG_CFG80211 is not set
++# CONFIG_LIB80211 is not set
++
++#
++# CFG80211 needs to be enabled for MAC80211
++#
++# CONFIG_WIMAX is not set
++# CONFIG_RFKILL is not set
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++CONFIG_HAVE_BPF_JIT=y
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=y
++CONFIG_FIRMWARE_IN_KERNEL=y
++CONFIG_EXTRA_FIRMWARE=""
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_SYS_HYPERVISOR is not set
++# CONFIG_GENERIC_CPU_DEVICES is not set
++# CONFIG_DMA_SHARED_BUFFER is not set
++CONFIG_CMA=y
++# CONFIG_CMA_DEBUG is not set
++
++#
++# Default contiguous memory area size:
++#
++CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_CMA_SIZE_SEL_MBYTES=y
++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
++# CONFIG_CMA_SIZE_SEL_MIN is not set
++# CONFIG_CMA_SIZE_SEL_MAX is not set
++CONFIG_CMA_ALIGNMENT=8
++CONFIG_CMA_AREAS=7
++# CONFIG_CONNECTOR is not set
++CONFIG_MTD=y
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLKDEVS=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_DATAFLASH is not set
++CONFIG_MTD_M25P80=y
++CONFIG_M25PXX_USE_FAST_READ=y
++CONFIG_M25PXX_STAY_IN_3BYTE_MODE=y
++# CONFIG_MTD_SST25L is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++# CONFIG_MTD_DOCG3 is not set
++CONFIG_MTD_NAND_ECC=y
++# CONFIG_MTD_NAND_ECC_SMC is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_SM_COMMON is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_DENALI is not set
++# CONFIG_MTD_NAND_GPIO is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_RICOH is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_NAND_DOCG4 is not set
++# CONFIG_MTD_NAND_CAFE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
++# CONFIG_MTD_ALAUDA is not set
++# CONFIG_MTD_ONENAND is not set
++
++#
++# LPDDR flash memory drivers
++#
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_RESERVE=2
++# CONFIG_MTD_UBI_GLUEBI is not set
++# CONFIG_PARPORT is not set
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++# CONFIG_BLK_CPQ_DA is not set
++# CONFIG_BLK_CPQ_CISS_DA is not set
++# CONFIG_BLK_DEV_DAC960 is not set
++# CONFIG_BLK_DEV_UMEM is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++# CONFIG_BLK_DEV_LOOP is not set
++
++#
++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
++#
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_BLK_DEV_SX8 is not set
++# CONFIG_BLK_DEV_UB is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=4096
++CONFIG_BLK_DEV_XIP=y
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_MG_DISK is not set
++# CONFIG_BLK_DEV_RBD is not set
++
++#
++# Misc devices
++#
++# CONFIG_SENSORS_LIS3LV02D is not set
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_ATMEL_PWM is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_INTEL_MID_PTI is not set
++# CONFIG_SGI_IOC4 is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1780 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_TI_DAC7512 is not set
++# CONFIG_BMP085_I2C is not set
++# CONFIG_BMP085_SPI is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++# CONFIG_EEPROM_AT24 is not set
++# CONFIG_EEPROM_AT25 is not set
++# CONFIG_EEPROM_LEGACY is not set
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_93XX46 is not set
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# CONFIG_TI_ST is not set
++# CONFIG_SENSORS_LIS3_SPI is not set
++# CONFIG_SENSORS_LIS3_I2C is not set
++
++#
++# Altera FPGA firmware download module
++#
++# CONFIG_ALTERA_STAPL is not set
++CONFIG_HAVE_IDE=y
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++CONFIG_SCSI_TGT=y
++# CONFIG_SCSI_NETLINK is not set
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_ST=y
++# CONFIG_CHR_DEV_OSST is not set
++# CONFIG_BLK_DEV_SR is not set
++CONFIG_CHR_DEV_SG=y
++# CONFIG_CHR_DEV_SCH is not set
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++CONFIG_SCSI_LOWLEVEL=y
++# CONFIG_ISCSI_TCP is not set
++# CONFIG_ISCSI_BOOT_SYSFS is not set
++# CONFIG_SCSI_CXGB3_ISCSI is not set
++# CONFIG_SCSI_CXGB4_ISCSI is not set
++# CONFIG_SCSI_BNX2_ISCSI is not set
++# CONFIG_SCSI_BNX2X_FCOE is not set
++# CONFIG_BE2ISCSI is not set
++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
++# CONFIG_SCSI_HPSA is not set
++# CONFIG_SCSI_3W_9XXX is not set
++# CONFIG_SCSI_3W_SAS is not set
++# CONFIG_SCSI_ACARD is not set
++# CONFIG_SCSI_AACRAID is not set
++# CONFIG_SCSI_AIC7XXX is not set
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++# CONFIG_SCSI_AIC79XX is not set
++# CONFIG_SCSI_AIC94XX is not set
++# CONFIG_SCSI_MVSAS is not set
++# CONFIG_SCSI_MVUMI is not set
++# CONFIG_SCSI_DPT_I2O is not set
++# CONFIG_SCSI_ADVANSYS is not set
++# CONFIG_SCSI_ARCMSR is not set
++# CONFIG_MEGARAID_NEWGEN is not set
++# CONFIG_MEGARAID_LEGACY is not set
++# CONFIG_MEGARAID_SAS is not set
++# CONFIG_SCSI_MPT2SAS is not set
++# CONFIG_SCSI_UFSHCD is not set
++# CONFIG_SCSI_HPTIOP is not set
++# CONFIG_LIBFC is not set
++# CONFIG_LIBFCOE is not set
++# CONFIG_FCOE is not set
++# CONFIG_SCSI_DMX3191D is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++# CONFIG_SCSI_IPS is not set
++# CONFIG_SCSI_INITIO is not set
++# CONFIG_SCSI_INIA100 is not set
++# CONFIG_SCSI_STEX is not set
++# CONFIG_SCSI_SYM53C8XX_2 is not set
++# CONFIG_SCSI_QLOGIC_1280 is not set
++# CONFIG_SCSI_QLA_FC is not set
++# CONFIG_SCSI_QLA_ISCSI is not set
++# CONFIG_SCSI_LPFC is not set
++# CONFIG_SCSI_DC395x is not set
++# CONFIG_SCSI_DC390T is not set
++# CONFIG_SCSI_NSP32 is not set
++# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_PMCRAID is not set
++# CONFIG_SCSI_PM8001 is not set
++# CONFIG_SCSI_SRP is not set
++# CONFIG_SCSI_BFA_FC is not set
++# CONFIG_SCSI_DH is not set
++# CONFIG_SCSI_OSD_INITIATOR is not set
++# CONFIG_ATA is not set
++# CONFIG_MD is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++# CONFIG_I2O is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_MII is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_TUN is not set
++# CONFIG_VETH is not set
++# CONFIG_ARCNET is not set
++
++#
++# CAIF transport drivers
++#
++CONFIG_ETHERNET=y
++CONFIG_NET_VENDOR_3COM=y
++# CONFIG_VORTEX is not set
++# CONFIG_TYPHOON is not set
++CONFIG_NET_VENDOR_ADAPTEC=y
++# CONFIG_ADAPTEC_STARFIRE is not set
++CONFIG_NET_VENDOR_ALTEON=y
++# CONFIG_ACENIC is not set
++CONFIG_NET_VENDOR_AMD=y
++# CONFIG_AMD8111_ETH is not set
++# CONFIG_PCNET32 is not set
++CONFIG_NET_VENDOR_ATHEROS=y
++# CONFIG_ATL2 is not set
++# CONFIG_ATL1 is not set
++# CONFIG_ATL1E is not set
++# CONFIG_ATL1C is not set
++CONFIG_NET_VENDOR_BROADCOM=y
++# CONFIG_B44 is not set
++# CONFIG_BNX2 is not set
++# CONFIG_CNIC is not set
++CONFIG_TIGON3=y
++# CONFIG_BNX2X is not set
++CONFIG_NET_VENDOR_BROCADE=y
++# CONFIG_BNA is not set
++# CONFIG_NET_CALXEDA_XGMAC is not set
++CONFIG_NET_VENDOR_CHELSIO=y
++# CONFIG_CHELSIO_T1 is not set
++# CONFIG_CHELSIO_T3 is not set
++# CONFIG_CHELSIO_T4 is not set
++# CONFIG_CHELSIO_T4VF is not set
++CONFIG_NET_VENDOR_CIRRUS=y
++# CONFIG_CS89x0 is not set
++CONFIG_NET_VENDOR_CISCO=y
++# CONFIG_ENIC is not set
++# CONFIG_DM9000 is not set
++# CONFIG_DNET is not set
++CONFIG_NET_VENDOR_DEC=y
++# CONFIG_NET_TULIP is not set
++CONFIG_NET_VENDOR_DLINK=y
++# CONFIG_DL2K is not set
++# CONFIG_SUNDANCE is not set
++CONFIG_NET_VENDOR_EMULEX=y
++# CONFIG_BE2NET is not set
++CONFIG_NET_VENDOR_EXAR=y
++# CONFIG_S2IO is not set
++# CONFIG_VXGE is not set
++CONFIG_NET_VENDOR_FARADAY=y
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++CONFIG_NET_VENDOR_HP=y
++# CONFIG_HP100 is not set
++CONFIG_NET_VENDOR_INTEL=y
++# CONFIG_E100 is not set
++# CONFIG_E1000 is not set
++CONFIG_E1000E=y
++# CONFIG_IGB is not set
++# CONFIG_IGBVF is not set
++# CONFIG_IXGB is not set
++# CONFIG_IXGBE is not set
++CONFIG_NET_VENDOR_I825XX=y
++# CONFIG_IP1000 is not set
++# CONFIG_JME is not set
++CONFIG_NET_VENDOR_MARVELL=y
++# CONFIG_SKGE is not set
++# CONFIG_SKY2 is not set
++CONFIG_NET_VENDOR_MELLANOX=y
++# CONFIG_MLX4_EN is not set
++# CONFIG_MLX4_CORE is not set
++CONFIG_NET_VENDOR_MICREL=y
++# CONFIG_KS8851 is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_KSZ884X_PCI is not set
++CONFIG_NET_VENDOR_MICROCHIP=y
++# CONFIG_ENC28J60 is not set
++CONFIG_NET_VENDOR_MYRI=y
++# CONFIG_MYRI10GE is not set
++# CONFIG_FEALNX is not set
++CONFIG_NET_VENDOR_NATSEMI=y
++# CONFIG_NATSEMI is not set
++# CONFIG_NS83820 is not set
++CONFIG_NET_VENDOR_8390=y
++# CONFIG_AX88796 is not set
++# CONFIG_NE2K_PCI is not set
++CONFIG_NET_VENDOR_NVIDIA=y
++# CONFIG_FORCEDETH is not set
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_ETHOC is not set
++CONFIG_NET_PACKET_ENGINE=y
++# CONFIG_HAMACHI is not set
++# CONFIG_YELLOWFIN is not set
++CONFIG_NET_VENDOR_QLOGIC=y
++# CONFIG_QLA3XXX is not set
++# CONFIG_QLCNIC is not set
++# CONFIG_QLGE is not set
++# CONFIG_NETXEN_NIC is not set
++CONFIG_NET_VENDOR_REALTEK=y
++# CONFIG_8139CP is not set
++# CONFIG_8139TOO is not set
++# CONFIG_R8169 is not set
++CONFIG_NET_VENDOR_RDC=y
++# CONFIG_R6040 is not set
++CONFIG_NET_VENDOR_SEEQ=y
++# CONFIG_SEEQ8005 is not set
++CONFIG_NET_VENDOR_SILAN=y
++# CONFIG_SC92031 is not set
++CONFIG_NET_VENDOR_SIS=y
++# CONFIG_SIS900 is not set
++# CONFIG_SIS190 is not set
++# CONFIG_SFC is not set
++CONFIG_NET_VENDOR_SMSC=y
++# CONFIG_SMC91X is not set
++# CONFIG_EPIC100 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_SMSC9420 is not set
++CONFIG_NET_VENDOR_STMICRO=y
++# CONFIG_STMMAC_ETH is not set
++CONFIG_NET_VENDOR_SUN=y
++# CONFIG_HAPPYMEAL is not set
++# CONFIG_SUNGEM is not set
++# CONFIG_CASSINI is not set
++# CONFIG_NIU is not set
++CONFIG_NET_VENDOR_TEHUTI=y
++# CONFIG_TEHUTI is not set
++CONFIG_NET_VENDOR_TI=y
++# CONFIG_TLAN is not set
++CONFIG_NET_VENDOR_VIA=y
++# CONFIG_VIA_RHINE is not set
++# CONFIG_VIA_VELOCITY is not set
++CONFIG_NET_VENDOR_WIZNET=y
++# CONFIG_WIZNET_W5100 is not set
++# CONFIG_WIZNET_W5300 is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MICREL_KS8995MA is not set
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++
++#
++# USB Network Adapters
++#
++# CONFIG_USB_CATC is not set
++# CONFIG_USB_KAWETH is not set
++# CONFIG_USB_PEGASUS is not set
++# CONFIG_USB_RTL8150 is not set
++# CONFIG_USB_USBNET is not set
++# CONFIG_USB_IPHETH is not set
++CONFIG_WLAN=y
++# CONFIG_ATMEL is not set
++# CONFIG_PRISM54 is not set
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_HOSTAP is not set
++# CONFIG_WL_TI is not set
++
++#
++# Enable WiMAX (Networking options) to see the WiMAX drivers
++#
++# CONFIG_WAN is not set
++# CONFIG_VMXNET3 is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
++# CONFIG_INPUT_POLLDEV is not set
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++# CONFIG_INPUT_JOYDEV is not set
++# CONFIG_INPUT_EVDEV is not set
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_GPIO is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++CONFIG_INPUT_MOUSE=y
++CONFIG_MOUSE_PS2=y
++CONFIG_MOUSE_PS2_ALPS=y
++CONFIG_MOUSE_PS2_LOGIPS2PP=y
++CONFIG_MOUSE_PS2_SYNAPTICS=y
++CONFIG_MOUSE_PS2_TRACKPOINT=y
++# CONFIG_MOUSE_PS2_ELANTECH is not set
++# CONFIG_MOUSE_PS2_SENTELIC is not set
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_AMBAKMI is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_GAMEPORT is not set
++
++#
++# Character devices
++#
++# CONFIG_VT is not set
++CONFIG_UNIX98_PTYS=y
++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_N_GSM is not set
++# CONFIG_TRACE_SINK is not set
++CONFIG_DEVKMEM=y
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_PCI=y
++CONFIG_SERIAL_8250_NR_UARTS=2
++CONFIG_SERIAL_8250_RUNTIME_UARTS=2
++CONFIG_SERIAL_8250_EXTENDED=y
++# CONFIG_SERIAL_8250_MANY_PORTS is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++# CONFIG_SERIAL_8250_EM is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_AMBA_PL010 is not set
++# CONFIG_SERIAL_AMBA_PL011 is not set
++# CONFIG_SERIAL_MAX3100 is not set
++# CONFIG_SERIAL_MAX3107 is not set
++# CONFIG_SERIAL_MFD_HSU is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_IFX6X60 is not set
++# CONFIG_SERIAL_PCH_UART is not set
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_HVC_DCC is not set
++# CONFIG_IPMI_HANDLER is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_TIMERIOMEM is not set
++# CONFIG_HW_RANDOM_ATMEL is not set
++# CONFIG_HW_RANDOM_EXYNOS is not set
++# CONFIG_R3964 is not set
++# CONFIG_APPLICOM is not set
++# CONFIG_RAW_DRIVER is not set
++# CONFIG_TCG_TPM is not set
++CONFIG_DEVPORT=y
++CONFIG_I2C=y
++CONFIG_I2C_BOARDINFO=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_MUX is not set
++# CONFIG_I2C_HELPER_AUTO is not set
++# CONFIG_I2C_SMBUS is not set
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_ALGOBIT is not set
++# CONFIG_I2C_ALGOPCF is not set
++# CONFIG_I2C_ALGOPCA is not set
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_I2C_INTEL_MID is not set
++# CONFIG_I2C_NOMADIK is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_PXA_PCI is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_PARPORT_LIGHT is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_STUB is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_ALGO is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++CONFIG_SPI=y
++# CONFIG_SPI_DEBUG is not set
++CONFIG_SPI_MASTER=y
++
++#
++# SPI Master Controller Drivers
++#
++# CONFIG_SPI_ALTERA is not set
++# CONFIG_SPI_BITBANG is not set
++# CONFIG_SPI_GPIO is not set
++# CONFIG_SPI_OC_TINY is not set
++# CONFIG_SPI_PL022 is not set
++# CONFIG_SPI_PXA2XX_PCI is not set
++# CONFIG_SPI_TOPCLIFF_PCH is not set
++# CONFIG_SPI_XCOMM is not set
++# CONFIG_SPI_XILINX is not set
++# CONFIG_SPI_DESIGNWARE is not set
++
++#
++# SPI Protocol Masters
++#
++# CONFIG_SPI_SPIDEV is not set
++# CONFIG_SPI_TLE62X0 is not set
++# CONFIG_HSI is not set
++
++#
++# PPS support
++#
++# CONFIG_PPS is not set
++
++#
++# PPS generators support
++#
++
++#
++# PTP clock support
++#
++
++#
++# Enable Device Drivers -> PPS to see the PTP clock options.
++#
++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
++CONFIG_ARCH_REQUIRE_GPIOLIB=y
++CONFIG_GPIOLIB=y
++# CONFIG_DEBUG_GPIO is not set
++CONFIG_GPIO_SYSFS=y
++
++#
++# Memory mapped GPIO drivers:
++#
++# CONFIG_GPIO_GENERIC_PLATFORM is not set
++# CONFIG_GPIO_EM is not set
++# CONFIG_GPIO_PL061 is not set
++# CONFIG_GPIO_VX855 is not set
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_MAX7300 is not set
++# CONFIG_GPIO_MAX732X is not set
++# CONFIG_GPIO_PCF857X is not set
++# CONFIG_GPIO_SX150X is not set
++# CONFIG_GPIO_ADP5588 is not set
++
++#
++# PCI GPIO expanders:
++#
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_RDC321X is not set
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MAX7301 is not set
++# CONFIG_GPIO_MCP23S08 is not set
++# CONFIG_GPIO_MC33880 is not set
++# CONFIG_GPIO_74X164 is not set
++
++#
++# AC97 GPIO expanders:
++#
++
++#
++# MODULbus GPIO expanders:
++#
++# CONFIG_W1 is not set
++# CONFIG_POWER_SUPPLY is not set
++# CONFIG_POWER_AVS is not set
++# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++
++#
++# Watchdog Device Drivers
++#
++# CONFIG_SOFT_WATCHDOG is not set
++# CONFIG_ARM_SP805_WATCHDOG is not set
++# CONFIG_DW_WATCHDOG is not set
++# CONFIG_MPCORE_WATCHDOG is not set
++# CONFIG_MAX63XX_WATCHDOG is not set
++# CONFIG_ALIM7101_WDT is not set
++# CONFIG_I6300ESB_WDT is not set
++
++#
++# PCI-based Watchdog Cards
++#
++# CONFIG_PCIPCWATCHDOG is not set
++# CONFIG_WDTPCI is not set
++
++#
++# USB-based Watchdog Cards
++#
++# CONFIG_USBPCWATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++
++#
++# Sonics Silicon Backplane
++#
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++
++#
++# Broadcom specific AMBA
++#
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_CORE is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS65010 is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_TPS65910 is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS65912_SPI is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_STMPE is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_TMIO is not set
++# CONFIG_MFD_T7L66XB is not set
++# CONFIG_MFD_TC6387XB is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_SPI is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_MAX77686 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_SEC_CORE is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_ARIZONA_SPI is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM831X_SPI is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_MC13XXX_SPI is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_EZX_PCAP is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_AAT2870_CORE is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_REGULATOR is not set
++# CONFIG_MEDIA_SUPPORT is not set
++
++#
++# Graphics support
++#
++# CONFIG_VGA_ARB is not set
++# CONFIG_DRM is not set
++# CONFIG_STUB_POULSBO is not set
++# CONFIG_VGASTATE is not set
++# CONFIG_VIDEO_OUTPUT_CONTROL is not set
++# CONFIG_FB is not set
++# CONFIG_EXYNOS_VIDEO is not set
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++# CONFIG_SOUND is not set
++
++#
++# HID support
++#
++CONFIG_HID=y
++CONFIG_HIDRAW=y
++# CONFIG_UHID is not set
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACRUX is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_AUREAL is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_TWINHAN is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LENOVO_TPKBD is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SONY is not set
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++# CONFIG_USB_HIDDEV is not set
++CONFIG_USB_ARCH_HAS_OHCI=y
++CONFIG_USB_ARCH_HAS_EHCI=y
++CONFIG_USB_ARCH_HAS_XHCI=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++CONFIG_USB_DEBUG=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DYNAMIC_MINORS=y
++# CONFIG_USB_OTG_WHITELIST is not set
++# CONFIG_USB_OTG_BLACKLIST_HUB is not set
++# CONFIG_USB_MON is not set
++# CONFIG_USB_WUSB_CBAF is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_XHCI_HCD is not set
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++# CONFIG_USB_EHCI_TT_NEWSCHED is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++# CONFIG_USB_ISP1362_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_EHCI_HCD_PLATFORM is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_CHIPIDEA is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++CONFIG_USB_STORAGE_DEBUG=y
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++CONFIG_USB_UAS=y
++# CONFIG_USB_LIBUSUAL is not set
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_RIO500 is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_LED is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_USB_SISUSBVGA is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_USB_ISP1301 is not set
++CONFIG_USB_GADGET=y
++# CONFIG_USB_GADGET_DEBUG is not set
++# CONFIG_USB_GADGET_DEBUG_FILES is not set
++# CONFIG_USB_GADGET_DEBUG_FS is not set
++CONFIG_USB_GADGET_VBUS_DRAW=2
++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
++
++#
++# USB Peripheral Controller
++#
++# CONFIG_USB_FUSB300 is not set
++# CONFIG_USB_R8A66597 is not set
++# CONFIG_USB_MV_UDC is not set
++# CONFIG_USB_M66592 is not set
++# CONFIG_USB_AMD5536UDC is not set
++# CONFIG_USB_NET2272 is not set
++# CONFIG_USB_NET2280 is not set
++# CONFIG_USB_GOKU is not set
++# CONFIG_USB_EG20T is not set
++# CONFIG_USB_DUMMY_HCD is not set
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++# CONFIG_USB_FILE_STORAGE is not set
++CONFIG_USB_MASS_STORAGE=m
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++
++#
++# OTG and related infrastructure
++#
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_USB_ULPI is not set
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_UWB is not set
++# CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
++# CONFIG_NEW_LEDS is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMADEVICES_DEBUG=y
++CONFIG_DMADEVICES_VDEBUG=y
++
++#
++# DMA Devices
++#
++# CONFIG_AMBA_PL08X is not set
++# CONFIG_DW_DMAC is not set
++# CONFIG_TIMB_DMA is not set
++# CONFIG_PL330_DMA is not set
++# CONFIG_AUXDISPLAY is not set
++# CONFIG_UIO is not set
++
++#
++# Virtio drivers
++#
++# CONFIG_VIRTIO_PCI is not set
++# CONFIG_VIRTIO_BALLOON is not set
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# CONFIG_STAGING is not set
++CONFIG_CLKDEV_LOOKUP=y
++CONFIG_HAVE_MACH_CLKDEV=y
++
++#
++# Hardware Spinlock drivers
++#
++CONFIG_IOMMU_SUPPORT=y
++
++#
++# Remoteproc drivers (EXPERIMENTAL)
++#
++
++#
++# Rpmsg drivers (EXPERIMENTAL)
++#
++# CONFIG_VIRT_DRIVERS is not set
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++CONFIG_EXT2_FS=y
++# CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
++CONFIG_EXT3_FS=y
++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_XATTR=y
++# CONFIG_EXT4_FS_POSIX_ACL is not set
++# CONFIG_EXT4_FS_SECURITY is not set
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD=y
++# CONFIG_JBD_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++CONFIG_NILFS2_FS=y
++# CONFIG_FS_POSIX_ACL is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_FSNOTIFY is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_INOTIFY_USER is not set
++# CONFIG_FANOTIFY is not set
++# CONFIG_QUOTA is not set
++# CONFIG_QUOTACTL is not set
++CONFIG_AUTOFS4_FS=y
++# CONFIG_FUSE_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++CONFIG_NTFS_FS=y
++# CONFIG_NTFS_DEBUG is not set
++# CONFIG_NTFS_RW is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
++# CONFIG_PROC_PAGE_MONITOR is not set
++CONFIG_SYSFS=y
++# CONFIG_HUGETLB_PAGE is not set
++# CONFIG_CONFIGFS_FS is not set
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++# CONFIG_JFFS2_LZO is not set
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_UBIFS_FS=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++CONFIG_UBIFS_FS_LZO=y
++CONFIG_UBIFS_FS_ZLIB=y
++# CONFIG_LOGFS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++CONFIG_NFS_V4=y
++# CONFIG_NFS_SWAP is not set
++# CONFIG_NFS_V4_1 is not set
++CONFIG_ROOT_NFS=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_NFS_USE_KERNEL_DNS=y
++# CONFIG_NFSD is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_GSS=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++# CONFIG_NLS_CODEPAGE_850 is not set
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++# CONFIG_NLS_ISO8859_15 is not set
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
++# CONFIG_ENABLE_WARN_DEPRECATED is not set
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_SHIRQ is not set
++# CONFIG_LOCKUP_DETECTOR is not set
++# CONFIG_HARDLOCKUP_DETECTOR is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_TIMER_STATS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_STATS is not set
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_SPARSE_RCU_POINTER is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++CONFIG_DEBUG_INFO=y
++# CONFIG_DEBUG_INFO_REDUCED is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_WRITECOUNT is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_TEST_LIST_SORT is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_DEBUG_CREDENTIALS is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_CPU_STALL_INFO is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++# CONFIG_LKDTM is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_ATOMIC64_SELFTEST is not set
++# CONFIG_SAMPLES is not set
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++# CONFIG_TEST_KSTRTOX is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_ARM_UNWIND is not set
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_LL=y
++CONFIG_DEBUG_LL_UART_NONE=y
++# CONFIG_DEBUG_ICEDCC is not set
++# CONFIG_DEBUG_SEMIHOSTING is not set
++# CONFIG_EARLY_PRINTK is not set
++# CONFIG_OC_ETM is not set
++# CONFIG_PID_IN_CONTEXTIDR is not set
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_DEFAULT_SECURITY=""
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_BLKCIPHER=y
++CONFIG_CRYPTO_BLKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=m
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_PCOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_WORKQUEUE=y
++# CONFIG_CRYPTO_CRYPTD is not set
++# CONFIG_CRYPTO_AUTHENC is not set
++# CONFIG_CRYPTO_TEST is not set
++
++#
++# Authenticated Encryption with Associated Data
++#
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_SEQIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_CTS is not set
++# CONFIG_CRYPTO_ECB is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_XTS is not set
++
++#
++# Hash modes
++#
++# CONFIG_CRYPTO_HMAC is not set
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++# CONFIG_CRYPTO_GHASH is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD128 is not set
++# CONFIG_CRYPTO_RMD160 is not set
++# CONFIG_CRYPTO_RMD256 is not set
++# CONFIG_CRYPTO_RMD320 is not set
++# CONFIG_CRYPTO_SHA1 is not set
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_WP512 is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=m
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++CONFIG_CRYPTO_DES=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++# CONFIG_CRYPTO_ZLIB is not set
++CONFIG_CRYPTO_LZO=y
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=m
++# CONFIG_CRYPTO_USER_API_HASH is not set
++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_HIFN_795X is not set
++# CONFIG_BINARY_PRINTF is not set
++
++#
++# Library routines
++#
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IO=y
++# CONFIG_CRC_CCITT is not set
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++# CONFIG_CRC_ITU_T is not set
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC7 is not set
++# CONFIG_LIBCRC32C is not set
++# CONFIG_CRC8 is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_COMPRESS=y
++CONFIG_LZO_DECOMPRESS=y
++# CONFIG_XZ_DEC is not set
++# CONFIG_XZ_DEC_BCJ is not set
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT=y
++CONFIG_HAS_DMA=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_NLATTR=y
++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
++# CONFIG_AVERAGE is not set
++# CONFIG_CORDIC is not set
++# CONFIG_DDR is not set
+diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
+index 9abe7a0..fac79dc 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_bug.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_bug.h.patch
new file mode 100644
index 00000000..b4db0dac
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_bug.h.patch
@@ -0,0 +1,12 @@
+--- a/arch/arm/include/asm/bug.h
++++ b/arch/arm/include/asm/bug.h
+@@ -32,7 +32,6 @@
+
+ #define __BUG(__file, __line, __value) \
+ do { \
+- BUILD_BUG_ON(sizeof(struct bug_entry) != 12); \
+ asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \
+ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \
+ "2:\t.asciz " #__file "\n" \
+diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
+index 3e91f22..b7641d6 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_hardware_gic.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_hardware_gic.h.patch
new file mode 100644
index 00000000..bc5fd627
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_hardware_gic.h.patch
@@ -0,0 +1,12 @@
+--- a/arch/arm/include/asm/hardware/gic.h
++++ b/arch/arm/include/asm/hardware/gic.h
+@@ -42,6 +42,7 @@ extern struct irq_chip gic_arch_extn;
+ void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+ int gic_of_init(struct device_node *node, struct device_node *parent);
+ void gic_secondary_init(unsigned int);
++void gic_handle_irq(struct pt_regs *regs);
+ void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
+ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
+
+diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
+index fcbac3c..f2a1a30 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_pgtable.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_pgtable.h.patch
new file mode 100644
index 00000000..e308b092
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_pgtable.h.patch
@@ -0,0 +1,39 @@
+--- a/arch/arm/include/asm/pgtable.h
++++ b/arch/arm/include/asm/pgtable.h
+@@ -21,7 +21,6 @@
+ #else
+
+ #include
+-#include
+ #include
+
+ #include
+@@ -33,14 +32,13 @@
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+- *
+- * Note that platforms may override VMALLOC_START, but they must provide
+- * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
+- * which may not overlap IO space.
+ */
+-#ifndef VMALLOC_START
+ #define VMALLOC_OFFSET (8*1024*1024)
+ #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
++#ifdef __ASSEMBLY__
++#define VMALLOC_END 0xff000000
++#else
++#define VMALLOC_END 0xff000000UL
+ #endif
+
+ #define LIBRARY_TEXT_START 0x0c000000
+@@ -338,6 +336,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+ * We provide our own arch_get_unmapped_area to cope with VIPT caches.
+ */
+ #define HAVE_ARCH_UNMAPPED_AREA
++#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+ /*
+ * remap a physical page `pfn' of size `size' with page protection `prot'
+diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
+index 3352451..da9f0d9 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_processor.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_processor.h.patch
new file mode 100644
index 00000000..ecf5bf4c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_include_asm_processor.h.patch
@@ -0,0 +1,13 @@
+--- a/arch/arm/include/asm/processor.h
++++ b/arch/arm/include/asm/processor.h
+@@ -119,6 +119,8 @@ static inline void prefetch(const void *ptr)
+
+ #endif
+
++#define HAVE_ARCH_PICK_MMAP_LAYOUT
++
+ #endif
+
+ #endif /* __ASM_ARM_PROCESSOR_H */
+diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
+index ece0996..5ad6b59 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-armv.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-armv.S.patch
new file mode 100644
index 00000000..6d188842
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-armv.S.patch
@@ -0,0 +1,39 @@
+--- a/arch/arm/kernel/entry-armv.S
++++ b/arch/arm/kernel/entry-armv.S
+@@ -27,25 +27,28 @@
+ #include
+
+ #include "entry-header.S"
++
+ #include
+
++
+ /*
+ * Interrupt handling.
+ */
+ .macro irq_handler
++
+ #ifdef CONFIG_MULTI_IRQ_HANDLER
+- ldr r1, =handle_arch_irq
++
++ ldr r1, =handle_arch_irq
+ mov r0, sp
+- ldr r1, [r1]
+ adr lr, BSYM(9997f)
+- teq r1, #0
+- movne pc, r1
+-#endif
++ ldr pc, [r1]
++#else
+ arch_irq_handler_default
++#endif
+ 9997:
+ .endm
+
+- .macro pabt_helper
++ .macro pabt_helper
+ @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
+ #ifdef MULTI_PABORT
+ ldr ip, .LCprocfns
+diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
+index 9d95a46..9dd0881 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-header.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-header.S.patch
new file mode 100644
index 00000000..b7f2c53d
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_entry-header.S.patch
@@ -0,0 +1,15 @@
+--- a/arch/arm/kernel/entry-header.S
++++ b/arch/arm/kernel/entry-header.S
+@@ -13,8 +13,10 @@
+ #define BAD_DATA 1
+ #define BAD_ADDREXCPTN 2
+ #define BAD_IRQ 3
++
+ #define BAD_UNDEFINSTR 4
+
++
+ @
+ @ Most of the stack format comes from struct pt_regs, but with
+ @ the addition of 8 bytes for storing syscall args 5 and 6.
+diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
+index 3606e85..f364802 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_head.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_head.S.patch
new file mode 100644
index 00000000..d9d3312b
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_head.S.patch
@@ -0,0 +1,32 @@
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -87,7 +87,26 @@ ENTRY(stext)
+
+ setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
+ @ and irqs disabled
+- mrc p15, 0, r9, c0, c0 @ get processor id
++#ifdef CONFIG_ARCH_IPROC
++
++#ifndef CONFIG_MACH_IPROC_P7
++#ifndef CONFIG_MACH_CYGNUS
++ /*
++ * fixup the vector table so that the secondary CPU does
++ * not start executing kernel instructions until we've
++ * patched its jump address during wakeup_secondary()
++ */
++ ldr r3,=0xffff002c
++ ldr r4,=0xffff0000
++ str r3, [r4, #0x400]
++#endif
++#endif
++
++ /* Make sure the cache is invalidated and MMU is disabled */
++ bl __iproc_head_fixup
++#endif /* CONFIG_ARCH_IPROC */
++
++ mrc p15, 0, r9, c0, c0 @ get processor id
+ bl __lookup_processor_type @ r5=procinfo r9=cpuid
+ movs r10, r5 @ invalid processor (r5=0)?
+ THUMB( it eq ) @ force fixup-able long branch encoding
+diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
+index 1e9be5d..7ab2fa7 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_module.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_module.c.patch
new file mode 100644
index 00000000..4c6c765c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_module.c.patch
@@ -0,0 +1,74 @@
+--- a/arch/arm/kernel/module.c
++++ b/arch/arm/kernel/module.c
+@@ -111,19 +111,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ }
+
+ offset >>= 2;
++ offset &= 0x00ffffff;
+
+ *(u32 *)loc &= 0xff000000;
+ *(u32 *)loc |= offset & 0x00ffffff;
+ break;
+
+- case R_ARM_V4BX:
+- /* Preserve Rm and the condition code. Alter
++ case R_ARM_V4BX:
++ /* Preserve Rm and the condition code. Alter
+ * other bits to re-code instruction as
+ * MOV PC,Rm.
+ */
+- *(u32 *)loc &= 0xf000000f;
+- *(u32 *)loc |= 0x01a0f000;
+- break;
++ *(u32 *)loc &= 0xf000000f;
++ *(u32 *)loc |= 0x01a0f000;
++ break;
+
+ case R_ARM_PREL31:
+ offset = *(u32 *)loc + sym->st_value - loc;
+@@ -142,7 +143,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+
+ *(u32 *)loc &= 0xfff0f000;
+ *(u32 *)loc |= ((offset & 0xf000) << 4) |
+- (offset & 0x0fff);
++ (offset & 0x0fff);
++
+ break;
+
+ #ifdef CONFIG_THUMB2_KERNEL
+@@ -203,12 +205,13 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
+ (j1 << 13) | (j2 << 11) |
+ ((offset >> 1) & 0x07ff));
++
+ break;
+
+ case R_ARM_THM_MOVW_ABS_NC:
+ case R_ARM_THM_MOVT_ABS:
+- upper = *(u16 *)loc;
+- lower = *(u16 *)(loc + 2);
++ upper = __mem_to_opcode_thumb16(*(u16 *)loc);
++ lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
+
+ /*
+ * MOVT/MOVW instructions encoding in Thumb-2:
+@@ -229,12 +232,15 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
+ if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+ offset >>= 16;
+
+- *(u16 *)loc = (u16)((upper & 0xfbf0) |
++ upper = (u16)((upper & 0xfbf0) |
+ ((offset & 0xf000) >> 12) |
+ ((offset & 0x0800) >> 1));
+- *(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
++ lower = (u16)((lower & 0x8f00) |
+ ((offset & 0x0700) << 4) |
+ (offset & 0x00ff));
++
++ *(u16 *)loc = __opcode_to_mem_thumb16(upper);
++ *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
+ break;
+ #endif
+
+diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
+index d9e3c61..2dc26fd 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_process.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_process.c.patch
new file mode 100644
index 00000000..48c61653
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_process.c.patch
@@ -0,0 +1,27 @@
+--- a/arch/arm/kernel/process.c
++++ b/arch/arm/kernel/process.c
+@@ -31,6 +31,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #include
+ #include
+@@ -263,11 +264,12 @@ void __show_regs(struct pt_regs *regs)
+ unsigned long flags;
+ char buf[64];
+
+- printk("CPU: %d %s (%s %.*s)\n",
++ printk("CPU: %d %s (%s %.*s%s)\n",
+ raw_smp_processor_id(), print_tainted(),
+ init_utsname()->release,
+ (int)strcspn(init_utsname()->version, " "),
+- init_utsname()->version);
++ init_utsname()->version,
++ LINUX_PACKAGE_ID);
+ print_symbol("PC is at %s\n", instruction_pointer(regs));
+ print_symbol("LR is at %s\n", regs->ARM_lr);
+ printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n"
+diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
+index 8f5dd79..1edbb3d 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_scu.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_scu.c.patch
new file mode 100644
index 00000000..1a88d2a2
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_scu.c.patch
@@ -0,0 +1,49 @@
+--- a/arch/arm/kernel/smp_scu.c
++++ b/arch/arm/kernel/smp_scu.c
+@@ -27,7 +27,7 @@
+ */
+ unsigned int __init scu_get_core_count(void __iomem *scu_base)
+ {
+- unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
++ unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
+ return (ncores & 0x03) + 1;
+ }
+
+@@ -41,19 +41,19 @@ void scu_enable(void __iomem *scu_base)
+ #ifdef CONFIG_ARM_ERRATA_764369
+ /* Cortex-A9 only */
+ if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+- scu_ctrl = __raw_readl(scu_base + 0x30);
++ scu_ctrl = readl_relaxed(scu_base + 0x30);
+ if (!(scu_ctrl & 1))
+- __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
++ writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
+ }
+ #endif
+
+- scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
++ scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
+ /* already enabled? */
+ if (scu_ctrl & 1)
+ return;
+
+ scu_ctrl |= 1;
+- __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
++ writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
+
+ /*
+ * Ensure that the data accessed by CPU0 before the SCU was
+@@ -79,9 +79,9 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode)
+ if (mode > 3 || mode == 1 || cpu > 3)
+ return -EINVAL;
+
+- val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
++ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
+ val |= mode;
+- __raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
++ writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
+
+ return 0;
+ }
+diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
+index a8a6682..0647dfa 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_twd.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_twd.c.patch
new file mode 100644
index 00000000..1634a4d4
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_kernel_smp_twd.c.patch
@@ -0,0 +1,70 @@
+--- a/arch/arm/kernel/smp_twd.c
++++ b/arch/arm/kernel/smp_twd.c
+@@ -39,7 +39,7 @@ static void twd_set_mode(enum clock_event_mode mode,
+ /* timer load already set up */
+ ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
+ | TWD_TIMER_CONTROL_PERIODIC;
+- __raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
++ writel_relaxed(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* period set, and timer enabled in 'next_event' hook */
+@@ -51,18 +51,18 @@ static void twd_set_mode(enum clock_event_mode mode,
+ ctrl = 0;
+ }
+
+- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
++ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
+ }
+
+ static int twd_set_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+ {
+- unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
++ unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
+
+ ctrl |= TWD_TIMER_CONTROL_ENABLE;
+
+- __raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
+- __raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
++ writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER);
++ writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL);
+
+ return 0;
+ }
+@@ -75,8 +75,8 @@ static int twd_set_next_event(unsigned long evt,
+ */
+ int twd_timer_ack(void)
+ {
+- if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
+- __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
++ if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) {
++ writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
+ return 1;
+ }
+
+@@ -110,16 +110,16 @@ static void __cpuinit twd_calibrate_rate(void)
+ /* OK, now the tick has started, let's get the timer going */
+ waitjiffies += 5;
+
+- /* enable, no interrupt or reload */
+- __raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
++ /* enable, no interrupt or reload */
++ writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL);
+
+- /* maximum value */
+- __raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
++ /* maximum value */
++ writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
+
+ while (get_jiffies_64() < waitjiffies)
+ udelay(10);
+
+- count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
++ count = readl_relaxed(twd_base + TWD_TIMER_COUNTER);
+
+ twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
+
+diff --git a/arch/arm/mach-iproc/Kconfig b/arch/arm/mach-iproc/Kconfig
+new file mode 100644
+index 0000000..c77208d
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Kconfig.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Kconfig.patch
new file mode 100644
index 00000000..d7548b4c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Kconfig.patch
@@ -0,0 +1,113 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/Kconfig
+@@ -0,0 +1,107 @@
++menu "iProc SoC based Machine types"
++ depends on MACH_IPROC
++
++config MACH_CYGNUS
++ bool "Cygnus bring-up board"
++ help
++ Support for the Broadcom Cygnus bring-up board.
++
++config MACH_NS
++ bool "Support Broadcom Northstar bring-up board"
++ help
++ Support for the Broadcom Northstar bring-up board.
++
++config MACH_HX4
++ bool "Support Broadcom Helix4 bring-up board"
++ help
++ Support for the Broadcom Helix4 bring-up board.
++
++config MACH_HR2
++ bool "Support Broadcom Hurricane2 bring-up board"
++ help
++ Support for the Broadcom Hurricane2 bring-up board.
++
++config MACH_NSP
++ bool "Support Broadcom Northstar Plus bring-up board"
++ help
++ Support for the Broadcom Northstar Plus bring-up board.
++
++config MACH_KT2
++ bool "Support Broadcom Katana2 bring-up board"
++ help
++ Support for the Broadcom Katana2 bring-up board.
++
++config MACH_GH
++ bool "Support Broadcom Greyhound bring-up board"
++ select MACH_IPROC_P7
++ help
++ Support for the Broadcom Greyhound bring-up board.
++
++config MACH_DNI_3448P
++ select ARM_L1_CACHE_SHIFT_6
++ bool "Support Delta Networks Inc. 3448P board"
++ help
++ Support for the Broadcom Greyhound bring-up board.
++
++config MACH_ACCTON_AS4610_54
++ select ARM_L1_CACHE_SHIFT_6
++ bool "Support Accton AS4610 54 POE and non-POE board"
++ help
++ Support for Accton AS4610-54 POE and non -POE board.
++
++config MACH_IPROC_P7
++ bool "Support iProc Profile 7 architecture"
++ depends on MACH_GH
++ help
++ Support for iProc Profile 7 architecture.
++
++config MACH_IPROC_EMULATION
++ bool "Support iProc emulation"
++ help
++ Support for the iProc emulation.
++
++if MACH_CYGNUS
++
++config MACH_CYGNUS_EMULATION
++ bool "Is it Cygnus emulation ?"
++ default y
++ help
++ Support for the Broadcom Cygnus emulation
++
++if MACH_CYGNUS_EMULATION
++
++config CYGNUS_EMULATION_RTL_VER
++ string "specify RTL version"
++ default "Cygnus RTL-5.1"
++ help
++ running rtl version used for emulation build
++
++config CYGNUS_EMULATION_ARM_CLK
++ int "Hz - iHost clk don't change"
++ default 250000000
++ help
++ iHost clock in emulator
++
++config CYGNUS_EMULATION_PCLK
++ int "Hz - axi81 (pclk) in xls"
++ default 62500000
++ help
++ pheripheral clock in emulator
++
++config CYGNUS_EMULATION_SCLK
++ int "Hz - sclk in xls"
++ default 154380
++ help
++ uart clock in emulator
++
++config CYGNUS_EMULATION_CLK_125
++ int "Hz - axi41 clock in xls"
++ default 154380
++ help
++ 125Mhz equialent clock in emulator
++
++endif #MACH_CYGNUS_EMULATION
++
++endif #MACH_CYGNUS
++
++endmenu
+diff --git a/arch/arm/mach-iproc/Makefile b/arch/arm/mach-iproc/Makefile
+new file mode 100644
+index 0000000..b4a7ff3
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.boot.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.boot.patch
new file mode 100644
index 00000000..21af44ed
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.boot.patch
@@ -0,0 +1,8 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/Makefile.boot
+@@ -0,0 +1,2 @@
++zreladdr-y := $(CONFIG_BCM_ZRELADDR)
++params_phys-y := $(CONFIG_BCM_PARAMS_PHYS)
+diff --git a/arch/arm/mach-iproc/board_bu.c b/arch/arm/mach-iproc/board_bu.c
+new file mode 100644
+index 0000000..7e07ed1
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.patch
new file mode 100644
index 00000000..60f3a4a0
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_Makefile.patch
@@ -0,0 +1,21 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/Makefile
+@@ -0,0 +1,15 @@
++ifdef CONFIG_MACH_CYGNUS
++obj-y := io_map.o northstar.o common.o northstar_dmu.o board_bu.o localtimer.o
++else
++obj-y := io_map.o northstar.o common.o northstar_dmu.o board_bu.o idm.o localtimer.o
++endif
++
++ifdef CONFIG_BCM_CTF2
++EXTRA_CFLAGS += -I$(srctree)/../../bcmdrivers/gmac/src/include/
++endif
++
++obj-$(CONFIG_PM) += pm.o
++
++#obj-$(CONFIG_MACH_NS) += board_bu.o
++
++obj-$(CONFIG_MTD) += flash.o
+diff --git a/arch/arm/mach-iproc/Makefile.boot b/arch/arm/mach-iproc/Makefile.boot
+new file mode 100644
+index 0000000..2de985c
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_board_bu.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_board_bu.c.patch
new file mode 100644
index 00000000..126a2d42
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_board_bu.c.patch
@@ -0,0 +1,1103 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/board_bu.c
+@@ -0,0 +1,1097 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#ifdef CONFIG_EARLY_DMA_ALLOC
++#include
++#endif
++
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "northstar.h"
++#include "common.h"
++#ifdef HNDCTF
++#include
++#include
++#endif /* HNDCTF */
++
++#include
++#include
++#include
++
++#include
++
++/* Fast device at 0x6000 offset */
++static AMBA_APB_DEVICE(pl020, "pl020", 0, 0x18028000,
++ { 111 }, NULL);
++static AMBA_APB_DEVICE(pl021, "pl021", 0, 0x18029000,
++ { 111 }, NULL);
++
++struct pl022_config_chip spi_chip_info = {
++ /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
++ .com_mode = DMA_TRANSFER,
++ .iface = SSP_INTERFACE_MOTOROLA_SPI,
++ /* We can only act as master but SSP_SLAVE is possible in theory */
++ .hierarchy = SSP_MASTER,
++ /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
++ .slave_tx_disable = 0,
++ .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
++ .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
++ .ctrl_len = SSP_BITS_12,
++ .wait_state = SSP_MWIRE_WAIT_ZERO,
++ .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
++};
++
++static struct pl022_ssp_controller ssp_platform_data[] = {
++ {
++ /* If you have several SPI buses this varies, we have only bus 0 */
++ .bus_id = 0,
++ /*
++ * On the APP CPU GPIO 4, 5 and 6 are connected as generic
++ * chip selects for SPI. (Same on U330, U335 and U365.)
++ * TODO: make sure the GPIO driver can select these properly
++ * and do padmuxing accordingly too.
++ */
++ .num_chipselect = 1,
++ .enable_dma = 1,
++ },
++ {
++ /* If you have several SPI buses this varies, we have only bus 0 */
++ .bus_id = 1,
++ /*
++ * On the APP CPU GPIO 4, 5 and 6 are connected as generic
++ * chip selects for SPI. (Same on U330, U335 and U365.)
++ * TODO: make sure the GPIO driver can select these properly
++ * and do padmuxing accordingly too.
++ */
++ .num_chipselect = 1,
++ .enable_dma = 1,
++ },
++};
++
++static struct spi_board_info iproc_spi_devices[] = {
++ {
++ /* A dummy chip used for loopback tests */
++ .modalias = "spidev0",
++ /* Really dummy, pass in additional chip config here */
++ .platform_data = NULL,
++ /* This defines how the controller shall handle the device */
++ .controller_data = &spi_chip_info,
++ /* .irq - no external IRQ routed from this device */
++ .max_speed_hz = 1000000,
++ .bus_num = 0, /* Only one bus on this chip */
++ .chip_select = 0,
++ /* Means SPI_CS_HIGH, change if e.g low CS */
++ .mode = SPI_MODE_2 | SPI_NO_CS,
++ },
++ {
++ /* A dummy chip used for loopback tests */
++ .modalias = "spidev1",
++ /* Really dummy, pass in additional chip config here */
++ .platform_data = NULL,
++ /* This defines how the controller shall handle the device */
++ .controller_data = &spi_chip_info,
++ /* .irq - no external IRQ routed from this device */
++ .max_speed_hz = 1000000,
++ .bus_num = 1, /* Only one bus on this chip */
++ .chip_select = 0,
++ /* Means SPI_CS_HIGH, change if e.g low CS */
++ .mode = SPI_MODE_2 | SPI_NO_CS,
++ },
++};
++
++/*
++ * The order of device declaration may be important, since some devices
++ * have dependencies on other devices being initialized first.
++ */
++static struct amba_device *amba_pl_devs[] __initdata = {
++ &pl020_device,
++ &pl021_device,
++
++};
++
++void __init iproc_spi_init(struct amba_device *adev, int i)
++{
++ adev->dev.platform_data = &ssp_platform_data[i];
++}
++
++void __init iproc_spi_register_board_devices(void)
++{
++ /* Register any SPI devices */
++ spi_register_board_info(iproc_spi_devices, ARRAY_SIZE(iproc_spi_devices));
++}
++
++void __init iproc_init_devics(void)
++{
++ int i;
++
++ /* Register the AMBA devices in the AMBA bus abstraction layer */
++ for (i = 0; i < ARRAY_SIZE(amba_pl_devs); i++) {
++ struct amba_device *d = amba_pl_devs[i];
++ iproc_spi_init(d, i);
++ amba_device_register(d, &iomem_resource);
++ }
++
++ /* Register SPI bus */
++ iproc_spi_register_board_devices();
++}
++
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++#define IPROC_SDIO_PA IPROC_SDIO3_REG_BASE
++#define SDIO_CORE_REG_SIZE 0x10000
++#define BSC_CORE_REG_SIZE 0x1000
++#define SDIO_IDM_IDM_RESET_CONTROL (0x16800)
++#define IPROC_SDIO_IRQ (177)
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++#define SATA_M0_IDM_IO_CONTROL_DIRECT_VA HW_IO_PHYS_TO_VIRT(SATA_M0_IDM_IO_CONTROL_DIRECT)
++#define SATA_M0_IDM_IDM_RESET_CONTROL_VA HW_IO_PHYS_TO_VIRT(SATA_M0_IDM_IDM_RESET_CONTROL)
++#define SATA_TOP_CTRL_BUS_CTRL_VA HW_IO_PHYS_TO_VIRT(SATA_TOP_CTRL_BUS_CTRL)
++#define SATA3_PCB_UPPER_REG15_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG15)
++#define SATA3_PCB_UPPER_REG0_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG0)
++#define SATA3_PCB_UPPER_REG1_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG1)
++#define SATA3_PCB_UPPER_REG11_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG11)
++#define SATA3_PCB_UPPER_REG5_VA HW_IO_PHYS_TO_VIRT(SATA3_PCB_UPPER_REG5)
++#define AXIIC_sata_m0_fn_mod_VA HW_IO_PHYS_TO_VIRT(AXIIC_sata_m0_fn_mod)
++#define BCM_INT_SATA 190
++#define NSP_CHIPID 0x3F00CF1E
++#endif
++
++#ifndef CONFIG_MACH_CYGNUS
++extern void request_idm_timeout_interrupts(void);
++#endif
++
++extern irqreturn_t idm_timeout_handler(int val, void *ptr);
++#if (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP))
++extern void* bcm5301x_otp_init(void);
++extern int bcm5301x_otp_exit(void);
++extern int bcm5301x_otp_read_dword(void *oh, uint wn, u32 *data);
++#endif /* (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP)) */
++
++#ifdef CONFIG_MACH_CYGNUS_EMULATION //cygnus:emulator:
++ /* This is the main reference clock 25MHz from external crystal */
++ static struct clk clk_ref = {
++ .name = "Refclk",
++ .rate = CONFIG_CYGNUS_EMULATION_SCLK, /* run-time override */
++ .fixed = 1,
++ .type = 0,
++ };
++#else
++/* This is the main reference clock 25MHz from external crystal */
++static struct clk clk_ref = {
++ .name = "Refclk",
++ .rate = 25 * 1000000, /* run-time override */
++ .fixed = 1,
++ .type = 0,
++};
++#endif /* END of CYGNUS */
++
++#ifdef HNDCTF
++ctf_t *kcih = NULL;
++EXPORT_SYMBOL(kcih);
++ctf_attach_t ctf_attach_fn = NULL;
++EXPORT_SYMBOL(ctf_attach_fn);
++#endif /* HNDCTF */
++
++static struct clk_lookup board_clk_lookups[] = {
++ {
++ .con_id = "refclk",
++ .clk = &clk_ref,
++ }
++};
++
++extern void __init northstar_timer_init(struct clk *clk_ref);
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++/* sdio */
++static struct sdio_platform_cfg sdio_platform_data = {
++ .devtype = SDIO_DEV_TYPE_SDMMC,
++};
++static struct resource sdio_resources[] = {
++ [0] = {
++ .start = IPROC_SDIO_PA,
++ .end = IPROC_SDIO_PA + BSC_CORE_REG_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_SDIO_IRQ,
++ .end = IPROC_SDIO_IRQ,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device board_sdio_device = {
++ .name = "iproc-sdio",
++ .id = 0,
++ .dev = {
++ .platform_data = &sdio_platform_data,
++ },
++ .num_resources = ARRAY_SIZE(sdio_resources),
++ .resource = sdio_resources,
++};
++
++static void setup_sdio(void)
++{
++ void __iomem *idm_base;
++ struct platform_device *sdio_plat_dev[1];
++ idm_base = (void __iomem *)IPROC_IDM_REGISTER_VA;
++ printk("%s: %d %p\n", __FUNCTION__, __LINE__, idm_base + SDIO_IDM_IDM_RESET_CONTROL);
++ writel_relaxed(0, idm_base + SDIO_IDM_IDM_RESET_CONTROL);
++ sdio_plat_dev[0] = &board_sdio_device;
++ platform_add_devices(sdio_plat_dev, 1);
++
++}
++#endif /* CONFIG_IPROC_SD || CONFIG_IPROC_SD_MODULE */
++
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++static struct resource iproc_pwm_resources = {
++ .start = IPROC_CCB_PWM_CTL,
++ .end = IPROC_CCB_PWM_CTL + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device board_pwm_device = {
++ .name = "iproc_pwmc",
++ .id = -1,
++ .resource = &iproc_pwm_resources,
++ .num_resources = 1,
++};
++static struct pwm_lookup board_pwm_lookup[] = {
++ PWM_LOOKUP("iproc_pwmc", 0,"iproc_pwmc","pwm-0"),
++ PWM_LOOKUP("iproc_pwmc", 1,"iproc_pwmc","pwm-1"),
++ PWM_LOOKUP("iproc_pwmc", 2,"iproc_pwmc","pwm-2"),
++ PWM_LOOKUP("iproc_pwmc", 3,"iproc_pwmc","pwm-3"),
++
++};
++
++#endif /* CONFIG_IPROC_PWM || CONFIG_IPROC_PWM_MODULE */
++
++#if defined(CONFIG_IPROC_WDT) || defined(CONFIG_IPROC_WDT_MODULE)
++/* watchdog */
++static struct resource wdt_resources[] = {
++ [0] = {
++ .start = IPROC_CCA_REG_BASE,
++ .end = IPROC_CCA_REG_BASE + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device board_wdt_device = {
++ .name = "iproc_wdt",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(wdt_resources),
++ .resource = wdt_resources,
++};
++#endif /* CONFIG_IPROC_WDT || CONFIG_IPROC_WDT_MODULE */
++
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++static AMBA_APB_DEVICE(sp805_wdt, "sp805-wdt", 0x00141805,
++ IPROC_SP805_WDT_REG_BASE, { }, NULL);
++#endif
++
++#if defined(CONFIG_IPROC_CCB_TIMER) || defined(CONFIG_IPROC_CCB_TIMER_MODULE)
++static struct resource ccb_timer_resources[] = {
++ [0] = {
++ .start = IPROC_CCB_TIMER_INT_START,
++ .end = IPROC_CCB_TIMER_INT_START + IPROC_CCB_TIMER_INT_COUNT - 1,
++ .flags = IORESOURCE_IRQ,
++ },
++ [1] = {
++ .start = IPROC_CCB_TIMER0_REGS_VA,
++ .end = IPROC_CCB_TIMER0_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IPROC_CCB_TIMER1_REGS_VA,
++ .end = IPROC_CCB_TIMER1_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [3] = {
++ .start = IPROC_CCB_TIMER2_REGS_VA,
++ .end = IPROC_CCB_TIMER2_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [4] = {
++ .start = IPROC_CCB_TIMER3_REGS_VA,
++ .end = IPROC_CCB_TIMER3_REGS_VA + 0x20 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device board_timer_device = {
++ .name = "iproc_ccb_timer",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(ccb_timer_resources),
++ .resource = ccb_timer_resources,
++};
++#endif /* CONFIG_IPROC_CCB_TIMER || CONFIG_IPROC_CCB_TIMER_MODULE */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++static struct resource fa2_resources[] = {
++ [0] = {
++ .start = CTF_CONTROL_REG, /* Macro is in socregs_nsp.h */
++ .end = CTF_CONTROL_REG + SZ_1K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 178,
++ .end = 178,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#endif
++#endif /* CONFIG_IPROC_FA2 */
++
++#if !(defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++/* Helix4 */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 127,
++ .end = 127,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct resource smbus_resources1[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus1_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus1_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM
++ },
++ [1] = {
++ .start = 128, /* macro in irqs.h (plat-iproc) */
++ .end = 128,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#elif defined(CONFIG_MACH_NSP)
++/* Northstar plus */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = ChipcommonB_SMBus_Config, /* Macro is in socregs_hx4.h */
++ .end = ChipcommonB_SMBus_Config + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = 121,
++ .end = 121,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#else
++/* Northstar */
++static struct resource smbus_resources[] = {
++ [0] = {
++ .start = CCB_SMBUS_START, /* Define this macro is socregs.h, or
++ in iproc_regs.h */
++ .end = CCB_SMBUS_START + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_CCB_SMBUS, /* macro in irqs.h (plat-iproc) */
++ .end = BCM_INT_ID_CCB_SMBUS,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++#endif
++
++/* Common to Northstar, Helix4 */
++static struct platform_device board_smbus_device = {
++ .name= "iproc-smb",
++ .id = 0,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(smbus_resources),
++ .resource = smbus_resources,
++};
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++static struct platform_device board_smbus_device1 = {
++ .name= "iproc-smb",
++ .id = 1,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(smbus_resources1),
++ .resource = smbus_resources1,
++};
++
++#endif /* CONFIG_MACH_HX4 */
++#endif /* Not ACCTON-AS4610-54, dni-3448p */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++static struct platform_device board_fa2_device = {
++ .name= "fa2",
++ .id = 0,
++ .dev= {
++ .platform_data = NULL, /* Can be defined, if reqd */
++ },
++ .num_resources = ARRAY_SIZE(fa2_resources),
++ .resource = fa2_resources,
++};
++#endif
++#endif /* CONFIG_IPROC_FA2 */
++
++#ifdef CONFIG_IPROC_USB3H
++static struct resource bcm_xhci_resources[] = {
++ [0] = {
++ .start = USB30_BASE,
++ .end = USB30_BASE + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_USB3H2CORE_USB2_INT0,
++ .end = BCM_INT_ID_USB3H2CORE_USB2_INT0,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 xhci_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device bcm_xhci_device = {
++ .name = "bcm-xhci",
++ .id = 0,
++ .dev = {
++// .platform_data = &xhci_platform_data,
++ .dma_mask = &xhci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .resource = bcm_xhci_resources,
++ .num_resources = ARRAY_SIZE(bcm_xhci_resources),
++};
++#endif /* CONFIG_IPROC_USB3 */
++
++#ifdef CONFIG_USB_EHCI_BCM
++
++static u64 ehci_dmamask = DMA_BIT_MASK(32);
++
++static struct resource usbh_ehci_resource[] = {
++ [0] = {
++ .start = IPROC_USB20_REG_BASE,
++ .end = IPROC_USB20_REG_BASE + 0x0FFF,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ // FIXME Cumulus: Helix4 IRQ value should be 117,
++ // some #define in plat-iproc irqgs.h is messed up
++ .start = 117,
++ .end = 117,
++ //.start = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ //.end = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device usbh_ehci_device =
++{
++ .name = "bcm-ehci",
++ .id = 0,
++ .resource = usbh_ehci_resource,
++ .num_resources = ARRAY_SIZE(usbh_ehci_resource),
++ .dev = {
++ .dma_mask = &ehci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++#endif
++
++#ifdef CONFIG_USB_OHCI_BCM
++
++static u64 ohci_dmamask = DMA_BIT_MASK(32);
++
++static struct resource usbh_ohci_resource[] = {
++ [0] = {
++ .start = IPROC_USB20_REG_BASE + 0x1000,
++ .end = IPROC_USB20_REG_BASE + 0x1000 + 0x0FFF,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ // FIXME Cumulus: Helix4 IRQ value should be 117,
++ // some #define in plat-iproc irqgs.h is messed up
++ .start = 117,
++ .end = 117,
++ //.start = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ //.end = BCM_INT_ID_USB2H2CORE_USB2_INT,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device usbh_ohci_device =
++{
++ .name = "bcm-ohci",
++ .id = 0,
++ .resource = usbh_ohci_resource,
++ .num_resources = ARRAY_SIZE(usbh_ohci_resource),
++ .dev = {
++ .dma_mask = &ohci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++#endif
++
++#ifdef CONFIG_SATA_AHCI_PLATFORM
++static struct resource bcm_sata_resources[] = {
++ [0] = {
++ .start = SATA_AHCI_GHC_HBA_CAP,
++ .end = SATA_AHCI_GHC_HBA_CAP + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_SATA,
++ .end = BCM_INT_SATA,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++static u64 sata_dmamask = DMA_BIT_MASK(32);
++
++static struct platform_device bcm_sata_device = {
++ .name = "strict-ahci",
++ .id = 0,
++ .dev = {
++ .dma_mask = &sata_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .resource = bcm_sata_resources,
++ .num_resources = ARRAY_SIZE(bcm_sata_resources),
++};
++#endif
++
++#ifdef CONFIG_DMAC_PL330
++#include "../../../../bcmdrivers/dma/pl330-pdata.h"
++static struct iproc_pl330_data iproc_pl330_pdata = {
++ /* Non Secure DMAC virtual base address */
++ .dmac_ns_base = IPROC_DMAC_REG_VA,
++ /* Secure DMAC virtual base address */
++ .dmac_s_base = IPROC_DMAC_REG_VA,
++ /* # of PL330 dmac channels 'configurable' */
++ .num_pl330_chans = 8,
++ /* irq number to use */
++ .irq_base = BCM_INT_ID_DMAC,
++ /* # of PL330 Interrupt lines connected to GIC */
++ .irq_line_count = 16,
++};
++
++static struct platform_device pl330_dmac_device = {
++ .name = "iproc-dmac-pl330",
++ .id = 0,
++ .dev = {
++ .platform_data = &iproc_pl330_pdata,
++ .coherent_dma_mask = DMA_BIT_MASK(64),
++ },
++};
++#endif
++
++
++#if defined(CONFIG_MACH_NSP)
++void config_AHCI( void )
++{
++ volatile unsigned int sata_clk_enable;
++ volatile unsigned int bustopcfg;
++
++ printk("\nConfigure AHCI ...\n");
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ sata_clk_enable |= 0x1;
++ writel_relaxed( sata_clk_enable, SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IO_CONTROL_DIRECT_VA);
++ udelay(1000);
++
++
++ /* Reset core */
++ writel_relaxed(0x0, SATA_M0_IDM_IDM_RESET_CONTROL_VA);
++ udelay(1000);
++ sata_clk_enable = readl_relaxed(SATA_M0_IDM_IDM_RESET_CONTROL_VA);
++ bustopcfg = __raw_readl(SATA_TOP_CTRL_BUS_CTRL_VA); // JIRA:LINUXDEV-39
++ bustopcfg &= ~ (( 3 << 2) | ( 3 << 4 ));
++ bustopcfg |= (( 2 << 2) | ( 2 << 4 ));//| ( 2<< 6 ));
++ //bustopcfg |= ( ( 0x2 << 8 ) | ( 0x2 << 17 ) );
++ writel_relaxed(bustopcfg, SATA_TOP_CTRL_BUS_CTRL_VA);
++}
++void configure_SATA_PHY ( void )
++{
++ unsigned int i, tmp;
++ void __iomem *bs = ioremap(AXIIC_sata_m0_fn_mod, 4);
++
++ void __iomem *id = IOMEM(IPROC_CCA_CORE_REG_VA);
++
++ printk("\nConfigure PHY ...\n");
++
++ writel_relaxed(0x0150,SATA3_PCB_UPPER_REG15_VA);
++ writel_relaxed( 0xF6F6, SATA3_PCB_UPPER_REG0_VA);
++ writel_relaxed( 0x2e96, SATA3_PCB_UPPER_REG1_VA);
++
++ writel_relaxed(0x0160,SATA3_PCB_UPPER_REG15_VA);
++ writel_relaxed( 0xF6F6, SATA3_PCB_UPPER_REG0_VA);
++ writel_relaxed( 0x2e96, SATA3_PCB_UPPER_REG1_VA);
++
++ //access SATA PLL
++ writel_relaxed(0x0050,SATA3_PCB_UPPER_REG15_VA);
++ //Audio PLL 0x8B
++ i = readl_relaxed(SATA3_PCB_UPPER_REG11_VA);
++ i &= ~ (( 0x1f) << 9 );
++ i |= ( 0xC << 9);
++ writel_relaxed( i, SATA3_PCB_UPPER_REG11_VA);
++
++ //Sequence for restarting PLL. Please try after changing the divider.
++ //'PLL_CapCtrl[10] = 1, PLL_CapCtrl[7:0] = F0h
++ //SATA3_PLL: PLL Register Bank address 0x50
++
++ //set register SATA3_PLL_capControl ( 0x85 )
++ i = readl_relaxed(SATA3_PCB_UPPER_REG5_VA);
++ i = ( i | 0x4f0 ) & 0xFF0;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG5_VA);
++
++ //'PLL_Ctrl[13:12] = 11
++ //Set register SATA3_PLL_CONTROL ( 0x81 )
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i |= 0x3000;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++
++ //'PLL_ReStart
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i &= 0x7FFF;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++ mdelay(100);
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ i |= 0x8000;
++ writel_relaxed( i, SATA3_PCB_UPPER_REG1_VA);
++ mdelay(1000);
++ writel_relaxed(0x0000,SATA3_PCB_UPPER_REG15_VA);
++ i = readl_relaxed(SATA3_PCB_UPPER_REG1_VA);
++ tmp = readl(id);
++ if (tmp == NSP_CHIPID)
++ {
++ tmp = readl(bs);
++ tmp |= 0x3;
++ writel(tmp, bs);
++ tmp = readl(bs);
++ }
++}
++#endif
++
++#ifdef CONFIG_MACH_CYGNUS
++#include "include/mach/iproc_regs.h"
++#ifdef CONFIG_IPROC_DS1WM
++#include "../../../../../bcmgpldrivers/d1w/ds1wm.h"
++
++
++static struct ds1wm_driver_data ds1wm_platform_data = {
++ .clock_rate = 80000000,
++ .reset_recover_delay = 1, /*ms*/
++};
++
++static struct resource ds1wm_resources[] = {
++ [0] = {
++ .start = IPROC_D1W_REG_BASE,
++ .end = IPROC_D1W_REG_BASE+0x0F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_D1W_CLK_GATE_CTRL,
++ .end = IPROC_D1W_CLK_GATE_CTRL+0x03
++ },
++ [2] = {
++ .start = IPROC_D1W_IO_MUX_REG,
++ .end = IPROC_D1W_IO_MUX_REG+0x03
++ },
++ [3] = {
++ .start = IPROC_D1W_INTR,
++ .end = IPROC_D1W_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device ds1wm_device = {
++ .name = "ds1wm",
++ .id = -1,
++ .dev = {
++ .platform_data = &ds1wm_platform_data,
++ },
++ .num_resources = ARRAY_SIZE(ds1wm_resources),
++ .resource = ds1wm_resources,
++};
++#endif
++
++#ifdef CONFIG_IPROC_KEYPAD
++#include "../../../../../bcmdrivers/keypad/keypad.h"
++static iproc_keypad_t keypad_info = {
++ .max_rows = 4,
++ .max_cols = 4,
++ .StatFilEn = 1,
++ .StatFilType = 0x5,
++ .ColFilEn = 1,
++ .ColFilType = 0x05,
++ .IoMode = 0,
++ .SwapRc = 0,
++ .ScanMode = 0
++};
++
++static struct resource keypad_resources[] = {
++ [0] = {
++ .start = IPROC_KEYPAD_REG_BASE,
++ .end = IPROC_KEYPAD_REG_BASE+0x4B,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_CRMU_ASIU_KEYPAD_CLK_DIV,
++ .end = IPROC_CRMU_ASIU_KEYPAD_CLK_DIV+0x03,
++ .flags = IORESOURCE_MEM,
++ },
++ [2] = {
++ .start = IPROC_IO_MUX_REG_BASE,
++ .end = IPROC_IO_MUX_REG_BASE+0x07,
++ .flags = IORESOURCE_MEM,
++ },
++ [3] = {
++ .start = IPROC_CLK_GATING_CTRL,
++ .end = IPROC_CLK_GATING_CTRL + 0x03,
++ .flags = IORESOURCE_MEM,
++ },
++ [4] = {
++ .start = IPROC_KEYPAD_INTR,
++ .end = IPROC_KEYPAD_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device keypad_device = {
++ .name = "iproc-keypad",
++ .id = -1,
++ .dev = {
++ .platform_data = &keypad_info,
++ },
++ .num_resources = ARRAY_SIZE(keypad_resources),
++ .resource = keypad_resources,
++};
++#endif
++#ifdef CONFIG_IPROC_TOUCHSCREEN
++static struct resource tsc_resources[] = {
++ [0] = {
++ .start = IPROC_TSC_REG_BASE,
++ .end = IPROC_TSC_REG_BASE+0x3F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_TSC_INTR,
++ .end = IPROC_TSC_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device tsc_device = {
++ .name = "iproc-tsc",
++ .id = -1,
++ .dev = {
++ .platform_data = NULL,
++ },
++ .num_resources = ARRAY_SIZE(tsc_resources),
++ .resource = tsc_resources,
++};
++#endif
++
++#ifdef CONFIG_IPROC_ADC
++static struct resource adc_resources[] = {
++ [0] = {
++ .start = IPROC_ADC_REG_BASE,
++ .end = IPROC_ADC_REG_BASE+0x3F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IPROC_ADC_INTR,
++ .end = IPROC_ADC_INTR,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++static struct platform_device adc_device = {
++ .name = "iproc-adc",
++ .id = -1,
++ .dev = {
++ .platform_data = NULL,
++ },
++ .num_resources = ARRAY_SIZE(adc_resources),
++ .resource = adc_resources,
++};
++#endif
++
++#endif
++
++void __init board_map_io(void)
++{
++
++ /*
++ * Install clock sources in the lookup table.
++ */
++ clkdev_add_table(board_clk_lookups,
++ ARRAY_SIZE(board_clk_lookups));
++
++ /* Map machine specific iodesc here */
++ northstar_map_io();
++}
++
++void __init iproc_init_early(void)
++{
++
++ /*
++ * SDK allocates coherent buffers from atomic
++ * context. Increase size of atomic coherent pool to make sure such
++ * the allocations won't fail.
++ */
++#ifdef CONFIG_CMA
++ init_dma_coherent_pool_size(SZ_1M * 16);
++#endif
++ /*
++ * Allocate contiguous himem block for SDK usage
++ */
++#ifdef CONFIG_EARLY_DMA_ALLOC
++ eda_init();
++#endif
++}
++
++static struct platform_device *board_sata_device[] __initdata = {
++#ifdef CONFIG_SATA_AHCI_PLATFORM
++ &bcm_sata_device,
++#endif
++};
++
++static struct of_dev_auxdata iproc_auxdata_lookup[] __initdata =
++{
++ { /* sentinel */ },
++};
++static struct platform_device *board_devices[] __initdata = {
++#if !(defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++ &board_smbus_device,
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2)
++ &board_smbus_device1,
++#endif
++#endif /*Don't use for Accton */
++
++#if defined(CONFIG_IPROC_FA2)
++#if defined(CONFIG_MACH_NSP)
++ &board_fa2_device,
++#endif
++#endif /* FA+ */
++
++#if defined(CONFIG_IPROC_CCB_TIMER) || defined(CONFIG_IPROC_CCB_TIMER_MODULE)
++ &board_timer_device,
++#endif /* CONFIG_IPROC_CCB_TIMER || CONFIG_IPROC_CCB_TIMER_MODULE */
++#if defined(CONFIG_IPROC_WDT) || defined(CONFIG_IPROC_WDT_MODULE)
++ &board_wdt_device,
++#endif /* CONFIG_IPROC_WDT || CONFIG_IPROC_WDT_MODULE */
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++ &board_pwm_device,
++#endif /* CONFIG_IPROC_PWM || CONFIG_IPROC_PWM_MODULE */
++#ifdef CONFIG_IPROC_USB3H
++ &bcm_xhci_device,
++#endif
++#ifdef CONFIG_USB_EHCI_BCM
++ &usbh_ehci_device,
++#endif
++#ifdef CONFIG_USB_OHCI_BCM
++ &usbh_ohci_device,
++#endif
++#ifdef CONFIG_DMAC_PL330
++ &pl330_dmac_device,
++#endif
++#ifdef CONFIG_MACH_CYGNUS
++#ifdef CONFIG_IPROC_DS1WM
++ &ds1wm_device,
++#endif
++#ifdef CONFIG_IPROC_KEYPAD
++ &keypad_device,
++#endif
++#endif
++};
++
++static struct amba_device *amba_devs[] __initdata = {
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++ &sp805_wdt_device,
++#endif
++};
++
++static void __init board_add_devices(void)
++{
++ int i;
++
++ platform_add_devices(board_devices, ARRAY_SIZE(board_devices));
++// if (iproc_get_chipid() == 53010) {
++// }
++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
++ amba_device_register(amba_devs[i], &iomem_resource);
++ }
++}
++
++static void __init board_add_sata_device(void)
++{
++ platform_add_devices(board_sata_device, sizeof(board_sata_device)/sizeof((board_sata_device)[0]));
++}
++
++
++/* SPI device info of GSIO(SPI) interface */
++static struct spi_board_info bcm5301x_spi_device[] = {
++ {
++ .modalias = "spidev",
++ .platform_data = NULL,
++ .controller_data = NULL,
++ .max_speed_hz = 2 * 1000 * 1000,
++ .bus_num = 0,
++ .chip_select = 0,
++ .mode = SPI_MODE_0,
++ },
++};
++
++void __init board_timer_init(void)
++{
++ northstar_timer_init(&clk_ref);
++}
++
++struct sys_timer board_timer = {
++ .init = board_timer_init,
++};
++
++
++void __init board_init(void)
++{
++ uint32_t sata_enable=0;
++
++#if (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP))
++ void *oh;
++#endif /* (defined(CONFIG_MACH_NSP) && defined(CONFIG_IPROC_OTP)) */
++
++ /*
++ * Add common platform devices that do not have board dependent HW
++ * configurations
++ */
++ board_add_common_devices(&clk_ref);
++#ifndef CONFIG_MACH_CYGNUS
++#ifndef CONFIG_MACH_NS
++ /* register IDM timeout interrupt handler */
++ request_idm_timeout_interrupts();
++#endif
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++ #if defined(CONFIG_IPROC_OTP)
++ /* read otp row 0xd to figure if sata is enabled */
++ oh = bcm5301x_otp_init();
++ if (oh != NULL)
++ {
++ bcm5301x_otp_read_dword(oh, 0xd, &sata_enable);
++ printk("%s: %d %08x\n", __FUNCTION__, __LINE__, sata_enable);
++ if ((sata_enable & 0x40000000) == 0x40000000)
++ {
++ config_AHCI();
++ configure_SATA_PHY();
++ }
++ bcm5301x_otp_exit();
++ }
++ else
++ printk("%s: %d bcm5301x_otp_init failed\n", __FUNCTION__, __LINE__);
++ #else /* defined(CONFIG_IPROC_OTP) */
++ printk("%s(): IPROC OTP not configured, can not determine if SATA is enabled.\n", __FUNCTION__);
++ #endif /* defined(CONFIG_IPROC_OTP) */
++#endif
++
++ board_add_devices();
++ if ((sata_enable & 0x40000000) == 0x40000000)
++ board_add_sata_device();
++
++
++#if defined(CONFIG_IPROC_SD) || defined(CONFIG_IPROC_SD_MODULE)
++ /* only bcm53012 support sdio */
++ if ((__REG32(IPROC_IDM_REGISTER_VA + 0xd500) & 0xc) == 0x0) {
++ setup_sdio();
++ }
++#endif
++
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++ writel_relaxed(0xf, IPROC_CCB_GPIO_REG_VA + IPROC_GPIO_CCB_AUX_SEL);
++ pwm_add_table(board_pwm_lookup, ARRAY_SIZE(board_pwm_lookup));
++#endif
++
++ /* Register SPI device info */
++ spi_register_board_info(bcm5301x_spi_device,
++ ARRAY_SIZE(bcm5301x_spi_device));
++
++ of_platform_populate(NULL, of_default_bus_match_table,
++ iproc_auxdata_lookup, NULL);
++ printk(KERN_DEBUG "board_init: Leave\n");
++}
++
++MACHINE_START(IPROC, "Broadcom iProc")
++
++// Used micro9 as a reference. Micro9 removed these two fields,
++// and replaced them with a call to ep93xx_map_io(), which in turn
++// calls iotable_init(). Northstar appears to have an equivalent
++// init (refer to northstar_io_desc[] array, in io_map.c
++ .map_io = board_map_io,
++ .init_early = iproc_init_early,
++ .init_irq = iproc_init_irq,
++ .handle_irq = gic_handle_irq,
++ .timer = &board_timer,
++ .init_machine = board_init,
++MACHINE_END
++
++static const char * helix4_dt_board_compat[] = {
++ "dni,dni_3448p",
++ "accton,as4610_54",
++ NULL
++};
++
++DT_MACHINE_START(HELIX4_DT, "Broadcom Helix4 (Flattened Device Tree)")
++ .map_io = board_map_io,
++ .init_early = iproc_init_early,
++ .init_irq = iproc_init_irq,
++ .handle_irq = gic_handle_irq,
++ .timer = &board_timer,
++ .init_machine = board_init,
++ .dt_compat = helix4_dt_board_compat,
++MACHINE_END
+diff --git a/arch/arm/mach-iproc/common.c b/arch/arm/mach-iproc/common.c
+new file mode 100644
+index 0000000..b116ffc
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.c.patch
new file mode 100644
index 00000000..2fa4f8f0
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.c.patch
@@ -0,0 +1,353 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/common.c
+@@ -0,0 +1,347 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++//#include
++#include
++#include
++#include
++#include
++#include
++
++#define IPROC_UART0_PA IPROC_CCA_UART0_REG_BASE
++#define IPROC_UART1_PA IPROC_CCA_UART1_REG_BASE
++#define IPROC_UART2_PA IPROC_CCB_UART0_REG_BASE
++#define IPROC_UART3_PA IPROC_CCA_UART3_REG_BASE
++#define IPROC_CCA_UART_CLK_PA IPROC_CCA_UART_CLK_REG_BASE
++#define IPROC_CCA_CCAP_PA IPROC_CCA_CORE_CAP_REG_BASE
++#define IPROC_CCA_CCTL_PA IPROC_CCA_CORE_CTL_REG_BASE
++#define IPROC_CCA_INTMASK_PA IPROC_CCA_INTMASK_REG_BASE
++
++#define IPROC_UART0_VA HW_IO_PHYS_TO_VIRT(IPROC_UART0_PA)
++#define IPROC_UART1_VA HW_IO_PHYS_TO_VIRT(IPROC_UART1_PA)
++#define IPROC_UART2_VA HW_IO_PHYS_TO_VIRT(IPROC_UART2_PA)
++#define IPROC_UART3_VA HW_IO_PHYS_TO_VIRT(IPROC_UART3_PA)
++#define IPROC_CCA_UART_CLK_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_UART_CLK_PA)
++#define IPROC_CCA_CCAP_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_CCAP_PA)
++#define IPROC_CCA_CCTL_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_CCTL_PA)
++#define IPROC_CCA_INTMASK_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_INTMASK_PA)
++
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IRQ_IPROC_UART0 117
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P))
++#define IRQ_IPROC_UART0 123
++#elif defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IRQ_IPROC_UART0 123
++#define IRQ_IPROC_UART2 124
++#elif defined(CONFIG_MACH_HR2)
++#define IRQ_IPROC_UART0 123
++#elif defined(CONFIG_MACH_GH)
++#define IRQ_IPROC_UART0 105
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IRQ_IPROC_UART0 IPROC_INTERRUPTS__chipcommonG_uart0_intr
++ #define IRQ_IPROC_UART1 IPROC_INTERRUPTS__chipcommonG_uart1_intr//chandra:fix
++ #define IRQ_IPROC_UART2 IPROC_INTERRUPTS__chipcommonG_uart2_intr//chandra:fix
++ #define IRQ_IPROC_UART3 IPROC_INTERRUPTS__chipcommonG_uart3_intr//chandra:fix
++#else
++#error "No valid UART IRQ selected"
++#endif
++
++#if defined(CONFIG_MACH_HR2) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (76800)
++#elif defined(CONFIG_MACH_KT2) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (65800)
++#elif defined(CONFIG_MACH_IPROC_P7) && defined(CONFIG_MACH_IPROC_EMULATION)
++#define IPROC_UART_CLK (56864)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_UART_CLK (100000000)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_UART_CLK CONFIG_CYGNUS_EMULATION_SCLK
++#else
++#define IPROC_UART_CLK (62500000)
++#endif
++
++#ifdef CONFIG_MACH_IPROC_P7
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_UART0, \
++ .uartclk = IPROC_UART_CLK, \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++#elif defined(CONFIG_MACH_CYGNUS) /* !CONFIG_MACH_IPROC_P7 */
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_##name, \
++ .uartclk = CONFIG_CYGNUS_EMULATION_SCLK, /*.uartclk = 62500000,*/ \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++#else /* ! CONFIG_MACH_CYGNUS */
++#define IPROC_8250PORT(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = IRQ_IPROC_UART0, \
++ .uartclk = IPROC_UART_CLK, \
++ .regshift = 0, \
++ .iotype = UPIO_MEM, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++
++
++#define IPROC_APB_CLK 125000000
++
++#define IPROC_8250PORT_UART2(name) \
++{ \
++ .membase = (void __iomem *)(IPROC_##name##_VA), \
++ .mapbase = (resource_size_t)(IPROC_##name##_PA), \
++ .irq = 124, \
++ .uartclk = IPROC_APB_CLK, \
++ .regshift = 2, \
++ .iotype = UPIO_MEM32, \
++ .type = PORT_16550A, \
++ .flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ, \
++ .private_data = (void __iomem *)((IPROC_##name##_VA) + 0x00), \
++}
++
++#endif /* CONFIG_MACH_IPROC_P7 */
++
++static struct plat_serial8250_port uart_data[] = {
++#if (defined(CONFIG_MACH_HR2) && !defined(CONFIG_MACH_IPROC_EMULATION))
++ IPROC_8250PORT(UART1), /* Use UART2 as ttys0 */
++ IPROC_8250PORT(UART0),
++#elif defined(CONFIG_MACH_CYGNUS)
++ IPROC_8250PORT(UART3),
++ IPROC_8250PORT(UART0),
++#else
++ IPROC_8250PORT(UART0),
++ IPROC_8250PORT(UART1),
++#endif
++ { .flags = 0, },
++};
++
++static struct platform_device board_serial_device = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = uart_data,
++ },
++};
++
++#if defined(CONFIG_MPCORE_WATCHDOG)
++static struct resource wdt_device_resource[] = {
++ [0] = {
++ .start = IPROC_PERIPH_PVT_TIM_REG_BASE,
++ .end = IPROC_PERIPH_PVT_TIM_REG_BASE + 0x34,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = BCM_INT_ID_CCB_TIM1_INT2,
++ .end = BCM_INT_ID_CCB_TIM1_INT2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device wdt_device =
++{
++ .name = "mpcore_wdt",
++ .id = -1,
++ .resource = wdt_device_resource,
++ .num_resources = ARRAY_SIZE(wdt_device_resource),
++};
++#endif
++enum {
++ HX4_NONE = 0,
++ HX4_DNI_3448P,
++ HX4_ACCTON_AS4610_54
++};
++
++/*
++ * API to return the type of platform retrieved from device tree
++ * Note: This is hack until complete device tree is supported for
++ * for all broadcom iproc device drivers
++ */
++int brcm_get_hx4_model(void)
++{
++ const char *model = NULL;
++ unsigned long dt_root;
++
++ dt_root = of_get_flat_dt_root();
++ model = of_get_flat_dt_prop(dt_root, "model", NULL);
++ if (!model) {
++ model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
++ if (!model)
++ model = "";
++ }
++
++ if (!strcmp(model, "dni,3448p"))
++ return HX4_DNI_3448P;
++ else if (!strcmp(model, "accton,as4610_54"))
++ return HX4_ACCTON_AS4610_54;
++
++ printk( KERN_ERR "Unknown Model %s\n", model );
++ return HX4_NONE;
++}
++
++/* Common devices among all Northstar boards */
++//static struct platform_device *board_common_plat_devices[] __initdata = {
++// &board_serial_device,
++//#if defined(CONFIG_MPCORE_WATCHDOG)
++// &wdt_device,
++//#endif
++//};
++
++void __init iproc_config_boot_console(struct clk *ref_clk)
++{
++ u32 i;
++ u32 clk_rate = IPROC_UART_CLK;
++
++#ifndef CONFIG_MACH_IPROC_P7
++ u8 uart_clk_sel;
++ u8 uart_clk_ovr;
++ u16 uart_clk_div;
++ struct clk * clk = NULL ;
++ int modelnum;
++
++ /* Get Core Capabilities Register, and extract
++ UART Clock Select from bits 4..3 which show
++ the clock source. Values are:
++ 0 = 25Mhz clock input
++ 1 = Internal clock
++ 2 = reserved
++ 3 = reserved
++ */
++ uart_clk_sel = (readl(IPROC_CCA_CCAP_VA) >> 3) & 0x3;
++
++ /* Get UARTClkOvr from bit 0 of the Core Control Register
++ If set, this bit indicates that the UART clock is supplied
++ from the internal ALP (APB) clock. If clear then it indicates
++ that APBX_IDM_IO_CONTROL_DIRECT register bit UARTClkSel controls
++ the clock source
++ */
++ uart_clk_ovr = readl(IPROC_CCA_CCTL_VA) & 0x01;
++
++ /* uart_clk_div: ChipcommonA_ClkDiv bits 0..7 */
++ uart_clk_div = 0xff & readl(IPROC_CCA_UART_CLK_VA);
++ if( uart_clk_div == 0 )
++ uart_clk_div = 0x100 ;
++
++ if( uart_clk_sel == 0 ) {
++ /* uart_clk_sel = 0 -> external reference clock source */
++ clk = ref_clk ;
++ BUG_ON( !clk );
++ clk_rate = clk_get_rate(clk);
++ } else if( uart_clk_sel == 1 ) {
++ /* uart_clk_sel = 1 -> Internal clock optionally divided */
++ clk = clk_get_sys( "iproc_slow", "c_clk125" );
++ BUG_ON( !clk );
++#if defined(CONFIG_MACH_IPROC_EMULATION)
++ clk_rate = IPROC_UART_CLK ;
++#else
++ clk_rate = clk_get_rate(clk) ;
++#endif
++
++ if( ! uart_clk_ovr )
++ clk_rate /= uart_clk_div;
++ }
++
++ printk( KERN_INFO "Sel=%d Ovr=%d Div=%d\n", uart_clk_sel, uart_clk_ovr, uart_clk_div );
++ printk( KERN_INFO "UART clock rate %u\n", clk_rate );
++#endif /* !CONFIG_MACH_IPROC_P7 */
++
++ modelnum = brcm_get_hx4_model();
++ if (modelnum == HX4_ACCTON_AS4610_54) {
++ for(i = 0; i < ARRAY_SIZE(uart_data); i++ ) {
++ switch (i) {
++ case 0:
++ uart_data[i].membase = (void __iomem *)(IPROC_UART1_VA);
++ uart_data[i].mapbase = (resource_size_t)(IPROC_UART1_PA);
++ uart_data[i].irq = IRQ_IPROC_UART0;
++ uart_data[i].uartclk = IPROC_UART_CLK;
++ uart_data[i].regshift = 0;
++ uart_data[i].iotype = UPIO_MEM;
++ uart_data[i].type = PORT_16550A;
++ uart_data[i].flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ;
++ uart_data[i].private_data = (void __iomem *)((IPROC_UART1_VA) + 0x00);
++ break;
++ case 1:
++ uart_data[i].membase = (void __iomem *)(IPROC_UART2_VA);
++ uart_data[i].mapbase = (resource_size_t)(IPROC_UART2_PA);
++ uart_data[i].irq = 124;
++ uart_data[i].uartclk = IPROC_APB_CLK;
++ uart_data[i].regshift = 2;
++ uart_data[i].iotype = UPIO_MEM32;
++ uart_data[i].type = PORT_16550A;
++ uart_data[i].flags = UPF_FIXED_TYPE | UPF_SHARE_IRQ;
++ uart_data[i].private_data = (void __iomem *)((IPROC_UART2_VA) + 0x00);
++ break;
++ }
++ }
++ }
++
++ /* fixup UART port structure */
++ for(i = 0; i < ARRAY_SIZE(uart_data); i++ ) {
++ if( uart_data[i].flags == 0 )
++ break;
++ if( uart_data[i].irq == 0 )
++ uart_data[i].flags |= UPF_AUTO_IRQ;
++
++ /* XXX TBD - UART input clock source and rate */
++ if(i != 1) {
++ uart_data[i].uartclk = clk_rate ;
++ }
++
++ }
++
++ /* Install SoC devices in the system: uarts */
++ platform_device_register(&board_serial_device);
++
++#ifndef CONFIG_MACH_IPROC_P7
++ /* Enable UART interrupt in ChipcommonA */
++ i = readl(IPROC_CCA_INTMASK_VA);
++ i |= 1 << 6;
++ writel(i, IPROC_CCA_INTMASK_VA);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++}
++
++void __init board_add_common_devices(struct clk *ref_clk)
++{
++ /*
++ * Configure boot console
++ */
++ iproc_config_boot_console(ref_clk);
++}
+diff --git a/arch/arm/mach-iproc/common.h b/arch/arm/mach-iproc/common.h
+new file mode 100644
+index 0000000..d49a6b9
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.h.patch
new file mode 100644
index 00000000..42454e17
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_common.h.patch
@@ -0,0 +1,34 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/common.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __MACH_NORTHSTAR_COMMON_H
++#define __MACH_NORTHSTAR_COMMON_H
++#include
++#include
++#include
++#include
++
++#include
++
++void __init board_add_common_devices(struct clk *ref_clk);
++
++#endif /* __MACH_NORTHSTAR_COMMON_H */
+diff --git a/arch/arm/mach-iproc/flash.c b/arch/arm/mach-iproc/flash.c
+new file mode 100644
+index 0000000..8fd637b
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_flash.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_flash.c.patch
new file mode 100644
index 00000000..0f84f3b9
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_flash.c.patch
@@ -0,0 +1,381 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/flash.c
+@@ -0,0 +1,375 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++
++#include
++
++#ifdef CONFIG_MTD
++
++#include
++#include
++#include
++
++/* Since GSIO uses bus number 0, QSPI uses bus number 1 */
++#define IPROC_QSPI_BUS_NUMBER (1)
++
++/* Currently NAND controller only supports 2 LUNs */
++#define IPROC_NAND_MAX_LUNS (2)
++
++int brcm_get_hx4_model(void);
++
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++static struct mtd_partition accton_as4610_sflash_partition_map[] = {
++ {
++ .name = "nboot",
++ .offset = 0x00000000,
++ .size = 0x000e0000,
++ },
++ {
++ .name = "shmoo",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x0010000,
++ },
++ {
++ .name = "uboot-env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00010000,
++ },
++ {
++ .name = "onie",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#if defined(CONFIG_MACH_HX4)
++static struct mtd_partition sflash_partition_map[] = {
++ {
++ .name = "boot",
++ .offset = 0x00000000,
++ .size = 640 * 1024,
++ },
++ {
++ .name = "env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 384 * 1024,
++ },
++ {
++ .name = "system",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 15 * 1024 * 1024,
++ },
++ {
++ .name = "rootfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#endif /* Unused code for Accton AS4610-54 and DNI-3448P */
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++static struct mtd_partition dni_3448p_nand_partition_map[] = {
++ {
++ .name = "uboot",
++ .offset = 0x00000000,
++ .size = 0x00100000,
++ },
++ {
++ .name = "uboot-env",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00400000,
++ },
++ {
++ .name = "vpd",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00200000,
++ },
++ {
++ .name = "shmoo",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00200000,
++ },
++ {
++ .name = "open",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0xf9500000,
++ },
++ {
++ .name = "onie",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00c00000,
++ },
++ {
++ .name = "onie2",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00c00000,
++ },
++ {
++ .name = "board_eeprom",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x00600000,
++ },
++ {
++ .name = "diag",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x02000000,
++ },
++ {
++ .name = "diag2",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 0x02000000,
++ },
++};
++static struct mtd_partition accton_as4610_nand_partition_map[] = {
++};
++
++static struct mtd_partition nand_partition_map[] = {
++ {
++ .name = "nboot",
++ .offset = 0x00000000,
++ .size = 2 * 1024 * 1024,
++ },
++ {
++ .name = "nenv",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 4 * 1024 * 1024,
++ },
++ {
++ .name = "nsystem",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 10 * 1024 * 1024,
++ },
++ {
++ .name = "nrootfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 48 * 1024 * 1024,
++ },
++ {
++ .name = "ncustfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++enum {
++ HX4_NONE = 0,
++ HX4_DNI_3448P,
++ HX4_ACCTON_AS4610_54
++};
++
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++static int __init
++brcm_setup_spi_master(int cs, int bus_id)
++{
++ struct brcmspi_platform_data pdata;
++ struct platform_device *pdev;
++ const struct resource res[] = {
++ {
++ .start = IPROC_QSPI_IRQ_START,
++ .end = IPROC_QSPI_IRQ_END,
++ .flags = IORESOURCE_IRQ
++ },
++ {
++ .start = QSPI_MSPI_SPCR0_LSB,
++ .end = QSPI_MSPI_DISABLE_FLUSH_GEN + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_BSPI_REGS_REV_ID,
++ .end = QSPI_BSPI_REGS_BSPI_PIO_DATA + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_RAF_START_ADDR,
++ .end = QSPI_RAF_CURR_ADDR + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,
++ .end = QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IPROC_IDM_QSPI_REG_BASE,
++ .end = IPROC_IDM_QSPI_REG_BASE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ {
++ .start = IPROC_CRU_REG_BASE,
++ .end = IPROC_CRU_REG_BASE + 3,
++ .flags = IORESOURCE_MEM
++ },
++ };
++
++ memset(&pdata, 0, sizeof(pdata));
++ pdata.flash_cs = cs;
++ pdev = platform_device_alloc("qspi_iproc", bus_id);
++ if (!pdev ||
++ platform_device_add_resources(pdev, res, sizeof(res)/sizeof(res[0])) ||
++ platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
++ platform_device_add(pdev)) {
++ platform_device_put(pdev);
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static int __init
++brcm_setup_spi_flash(int cs, int bus_num, int nr_parts, struct mtd_partition *parts)
++{
++ struct spi_board_info board_info;
++ struct flash_platform_data *pdata;
++ struct spi_master *master;
++
++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
++ if (!pdata)
++ return -ENOMEM;
++
++ pdata->nr_parts = nr_parts;
++ pdata->parts = parts;
++
++ memset(&board_info, 0, sizeof(board_info));
++
++ strcpy(board_info.modalias, "m25p80");
++ board_info.bus_num = bus_num;
++ board_info.chip_select = cs;
++ board_info.max_speed_hz = CONFIG_IPROC_QSPI_MAX_HZ;
++ board_info.mode = SPI_MODE_3;
++ board_info.platform_data = pdata;
++
++ master = spi_busnum_to_master(bus_num);
++ if (master) {
++ /* Master driver already loaded */
++ if (spi_new_device(master, &board_info) == NULL) {
++ printk(KERN_WARNING "%s: can't add SPI device\n", __func__);
++ kfree(pdata);
++ return -ENODEV;
++ }
++ } else {
++ /* Master driver not yet loaded, register the board first. */
++ if (spi_register_board_info(&board_info, 1) != 0) {
++ printk(KERN_WARNING "%s: can't register SPI device\n", __func__);
++ kfree(pdata);
++ return -ENODEV;
++ }
++ }
++
++ return 0;
++}
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++static void __init
++northstar_setup_nand_flash(void)
++{
++ u32 straps;
++ struct platform_device *pdev;
++ struct brcmnand_platform_data pdata;
++ int i, modelnum;
++
++ straps = __REG32(IPROC_DMU_BASE_VA + IPROC_DMU_STRAPS_OFFSET);
++ pdata.strap_boot = ((straps >> IPROC_STRAP_BOOT_DEV_SHIFT) & 3) == 1;
++ pdata.strap_type = (straps >> IPROC_STRAP_NAND_TYPE_SHIFT) & 0xf;
++ pdata.strap_page_size = (straps >> IPROC_STRAP_NAND_PAGE_SHIFT) & 0x3;
++ if (!pdata.strap_boot) {
++ pdata.strap_type &= 0x7;
++ }
++
++ modelnum = brcm_get_hx4_model();
++
++ if (modelnum == HX4_DNI_3448P) {
++ pdata.nr_parts = ARRAY_SIZE(dni_3448p_nand_partition_map);
++ pdata.parts = dni_3448p_nand_partition_map;
++ } else if (modelnum == HX4_ACCTON_AS4610_54) {
++ pdata.nr_parts = ARRAY_SIZE(accton_as4610_nand_partition_map);
++ pdata.parts = accton_as4610_nand_partition_map;
++ } else {
++ pdata.nr_parts = ARRAY_SIZE(nand_partition_map);
++ pdata.parts = nand_partition_map;
++ }
++
++ for(i=0; i 0) {
++ pdata.nr_parts = 0;
++ pdata.parts = NULL;
++ }
++
++ pdata.chip_select = i;
++ pdev = platform_device_alloc("nand_iproc", i);
++ if (!pdev ||
++ platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
++ platform_device_add(pdev)) {
++ platform_device_put(pdev);
++ }
++ }
++}
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++static int __init
++northstar_mtd_setup(void)
++{
++#if defined(CONFIG_IPROC_QSPI) || defined(CONFIG_IPROC_QSPI_MODULE)
++ if (brcm_get_hx4_model() == HX4_ACCTON_AS4610_54) {
++ /* SPI flash (currently used for primary) */
++ brcm_setup_spi_master(
++ 0,
++ IPROC_QSPI_BUS_NUMBER
++ );
++ brcm_setup_spi_flash(
++ 0,
++ IPROC_QSPI_BUS_NUMBER,
++ ARRAY_SIZE(accton_as4610_sflash_partition_map),
++ accton_as4610_sflash_partition_map
++ );
++ } /* Required only for Accton AS4610 54*/
++#endif /* CONFIG_IPROC_QSPI || CONFIG_IPROC_QSPI_MODULE */
++
++#if defined(CONFIG_IPROC_MTD_NAND) || defined(CONFIG_IPROC_MTD_NAND_MODULE)
++#ifdef CONFIG_MACH_NS
++ /* Don't bring up NAND driver if it's BCM53010 */
++ if ((__REG32(IPROC_IDM_REGISTER_VA + 0xd500) & 0xc) != 0x4)
++#endif /* CONFIG_MACH_NS */
++ northstar_setup_nand_flash();
++#endif /* CONFIG_IPROC_MTD_NAND || CONFIG_IPROC_MTD_NAND_MODULE */
++
++ return 0;
++}
++
++/*
++ * late_initcall means the flash drivers are already loaded, so we control
++ * the order in which the /dev/mtd* devices get created.
++ */
++late_initcall(northstar_mtd_setup);
++
++#endif /* CONFIG_MTD */
+diff --git a/arch/arm/mach-iproc/idm.c b/arch/arm/mach-iproc/idm.c
+new file mode 100644
+index 0000000..444c3fe
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_idm.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_idm.c.patch
new file mode 100644
index 00000000..d6aa9c6c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_idm.c.patch
@@ -0,0 +1,729 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/idm.c
+@@ -0,0 +1,723 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++
++#include
++#include
++#include
++#include
++
++#ifdef CONFIG_MACH_NSP
++/* this is actually AXI_PCIE_S2 but for HX4, HR2, and KT2 it has been hijacked by CMICD */
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL AXI_PCIE_S2_IDM_IDM_ERROR_LOG_CONTROL
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE AXI_PCIE_S2_IDM_IDM_ERROR_LOG_COMPLETE
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS AXI_PCIE_S2_IDM_IDM_ERROR_LOG_STATUS
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ADDR_LSB
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ID
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS AXI_PCIE_S2_IDM_IDM_ERROR_LOG_FLAGS
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS AXI_PCIE_S2_IDM_IDM_INTERRUPT_STATUS
++
++#endif
++
++#ifdef CONFIG_MACH_NS
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18106900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18106904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18106908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810690C
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18106914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810691C
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18106A00
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810790C
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810791C
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18107A00
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18108900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18108908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810890C
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18108914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810891C
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18108A00
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810990C
++#define DDR_S2_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810991C
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x18109A00
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810A900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810A904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810A908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810A90C
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810A914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810A91C
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810AA00
++
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810B900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810B904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810B908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810B90C
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810B914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810B91C
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810BA00
++
++/* this is actually AXI_PCIE_S2 but for HX4, HR2, and KT2 it has been hijacked by CMICD */
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810C900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810C904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810C908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810C90C
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810C914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810C91C
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810CA00
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1810D900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1810D904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1810D908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810D90C
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1810D914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1810D91C
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1810DA00
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811A900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811A904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811A908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811A90C
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811A914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811A91C
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811AA00
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811B900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811B904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811B908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811B90C
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811B914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811B91C
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811BA00
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811C900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811C904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811C908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811C90C
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811C914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811C91C
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811CA00
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190C
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1812191C
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x1812A900
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18132900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x181312908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18132910
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x18132904
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18132A00
++
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18133900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18133904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x181313908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1813390c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18133910
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x18133904
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18133A00
++
++#define AXIIC_DS_2_IDM_ERROR_LOG_CONTROL 0x18134900
++#define AXIIC_DS_2_IDM_ERROR_LOG_COMPLETE 0x18134904
++#define AXIIC_DS_2_IDM_ERROR_LOG_STATUS 0x181314908
++#define AXIIC_DS_2_IDM_ERROR_LOG_ADDR_LSB 0x1813490c
++#define AXIIC_DS_2_IDM_ERROR_LOG_ID 0x18134910
++#define AXIIC_DS_2_IDM_ERROR_LOG_FLAGS 0x18134904
++#define AXIIC_DS_2_IDM_INTERRUPT_STATUS 0x18134A00
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18135900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18135904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x181315908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1813590c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18135910
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x18135904
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18135A00
++
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18136900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18136904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x181316908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1813690c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18136910
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x18136904
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18136A00
++
++#define IHOST_L2C_INT_MASK 0x19022214
++#define IHOST_GICDIST_enable_set2 0x19021108
++
++#endif
++
++#define IHOST_L2C_INT_MASK_VA HW_IO_PHYS_TO_VIRT(IHOST_L2C_INT_MASK)
++#define IHOST_GICDIST_enable_set2_VA HW_IO_PHYS_TO_VIRT(IHOST_GICDIST_enable_set2)
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_CONTROL)
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_COMPLETE)
++#define IHOST_S1_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_STATUS)
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_ADDR_LSB)
++#define IHOST_S1_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_ID)
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(IHOST_S1_IDM_ERROR_LOG_FLAGS)
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_CONTROL)
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_COMPLETE)
++#define IHOST_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_STATUS)
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define IHOST_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_ID)
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(IHOST_S0_IDM_ERROR_LOG_FLAGS)
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_CONTROL)
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_COMPLETE)
++#define DDR_S1_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_STATUS)
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_ADDR_LSB)
++#define DDR_S1_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_ID)
++#define DDR_S1_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(DDR_S1_IDM_ERROR_LOG_FLAGS)
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_CONTROL)
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_COMPLETE)
++#define DDR_S2_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_STATUS)
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_ADDR_LSB)
++#define DDR_S2_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_ID)
++#define DDR_S2_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(DDR_S2_IDM_ERROR_LOG_FLAGS)
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID)
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_ID)
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_ID)
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBY_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_CONTROL)
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_COMPLETE)
++#define ROM_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_STATUS)
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define ROM_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_ID)
++#define ROM_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(ROM_S0_IDM_ERROR_LOG_FLAGS)
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_CONTROL)
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_COMPLETE)
++#define NAND_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_STATUS)
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define NAND_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_ID)
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(NAND_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_CONTROL)
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_COMPLETE)
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_STATUS)
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define QSPI_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_ID)
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(QSPI_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_ID)
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_CONTROL)
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_COMPLETE)
++#define SRAM_S0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_STATUS)
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_ADDR_LSB)
++#define SRAM_S0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_ID)
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(SRAM_S0_IDM_ERROR_LOG_FLAGS)
++
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_ID)
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_CONTROL)
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE)
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_STATUS)
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB)
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_ID)
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_3_IDM_ERROR_LOG_FLAGS)
++
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBW_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_STATUS)
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBW_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_ID)
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBW_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_CONTROL)
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_COMPLETE)
++#define APBX_IDM_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_STATUS)
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_ADDR_LSB)
++#define APBX_IDM_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_ID)
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(APBX_IDM_IDM_ERROR_LOG_FLAGS)
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_CONTROL)
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE)
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_STATUS)
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB)
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_ID)
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS_VA HW_IO_PHYS_TO_VIRT(AXIIC_DS_0_IDM_ERROR_LOG_FLAGS)
++
++#define IDM_ERROR_LOG_ENABLE 0x33A
++#define IDM_ERROR_LOG_CLEAR 0x3
++
++#ifdef CONFIG_MACH_IPROC_P7
++#define IHOST_S0_IDM_IRQ 52
++#define DDR_S1_IDM_IRQ 54
++#define DDR_S2_IDM_IRQ 55
++#define AXI_PCIE_S0_IDM_IRQ 56
++#define AXI_PCIE_S1_IDM_IRQ 57
++#define ROM_S0_IDM_IRQ 58
++#define NAND_IDM_IRQ 59
++#define QSPI_IDM_IRQ 60
++#define SRAM_S0_IDM_IRQ 62
++#define A9JTAG_S0_IDM_IRQ 64
++#define APX_IDM_IRQ 68
++#define CMICD_S0_IDM_IRQ 71
++#define AXIIC_DS_0_IDM_IRQ 78
++#define AXIIC_DS_1_IDM_IRQ 79
++#define AXIIC_DS_2_IDM_IRQ 80
++#define AXIIC_DS_3_IDM_IRQ 81
++#define AXIIC_DS_4_IDM_IRQ 83
++#else
++#define IHOST_S1_IDM_IRQ 62
++#define IHOST_S0_IDM_IRQ 63
++#define DDR_S1_IDM_IRQ 64
++#define DDR_S2_IDM_IRQ 65
++#define AXI_PCIE_S0_IDM_IRQ 66
++#define AXI_PCIE_S1_IDM_IRQ 67
++#define CMICD_S0_IDM_IRQ 68
++#define ROM_S0_IDM_IRQ 69
++#define NAND_IDM_IRQ 70
++#define QSPI_IDM_IRQ 71
++#define SATA_IDM_IRQ 72
++#define A9JTAG_S0_IDM_IRQ 73
++#define SRAM_S0_IDM_IRQ 74
++#define APW_IDM_IRQ 75
++#define APX_IDM_IRQ 76
++#define APBY_S0_IDM_IRQ 77
++#define APBZ_S0_IDM_IRQ 78
++#define AXIIC_DS_0_IDM_IRQ 79
++#define AXIIC_DS_1_IDM_IRQ 80
++#define AXIIC_DS_2_IDM_IRQ 81
++#define AXIIC_DS_3_IDM_IRQ 82
++#define AXIIC_DS_4_IDM_IRQ 83
++#endif
++
++static irqreturn_t idm_timeout_handler(int val, void *ptr)
++{
++ u32 errStat;
++// printk("%s: %d, %d entry\n", __FUNCTION__, __LINE__, val);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, IHOST_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(IHOST_S1_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(IHOST_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, DDR_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(DDR_S1_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, DDR_S2_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(DDR_S2_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(CMICD_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBY_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, ROM_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(ROM_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, NAND_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(NAND_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, QSPI_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(QSPI_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, SRAM_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(SRAM_S0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBZ_S0_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXIIC_DS_3_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#if !defined(CONFIG_MACH_NS) && !defined(CONFIG_MACH_IPROC_P7)
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBW_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBW_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++#endif
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, APBX_IDM_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(APBX_IDM_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA);
++ if (errStat > 0)
++ {
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_ID_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_FLAGS_VA);
++// printk("%s: %d, %08x\n", __FUNCTION__, __LINE__, errStat);
++ __raw_writel(IDM_ERROR_LOG_CLEAR, AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE_VA);
++ errStat = __raw_readl(AXIIC_DS_0_IDM_ERROR_LOG_STATUS_VA);
++// printk("%s: %d, %d\n", __FUNCTION__, __LINE__, errStat);
++ }
++// printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++ return IRQ_HANDLED;
++}
++
++int l2cc_interrupt_error_handler(int val, void *ptr)
++{
++ printk("%s: %d, %d entry\n", __FUNCTION__, __LINE__, val);
++ printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++ return 0;
++}
++
++void request_idm_timeout_interrupts(void)
++{
++ u32 l2cc_mask;
++ int ret = 0;
++
++// printk("%s: %d entry\n", __FUNCTION__, __LINE__);
++
++ /* clear all pending idm interrupts */
++ idm_timeout_handler(0, NULL);
++
++ /* enable idm error log for all slaves */
++
++ __raw_writel(IDM_ERROR_LOG_ENABLE, IHOST_S1_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, IHOST_S0_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, DDR_S1_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, DDR_S2_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++
++#ifndef CONFIG_MACH_NS
++ __raw_writel(IDM_ERROR_LOG_ENABLE, SRAM_S0_IDM_ERROR_LOG_CONTROL_VA);
++#ifndef CONFIG_MACH_IPROC_P7
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBY_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBW_IDM_IDM_ERROR_LOG_CONTROL_VA);
++#endif
++#endif
++
++ __raw_writel(IDM_ERROR_LOG_ENABLE, ROM_S0_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, NAND_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, QSPI_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, APBX_IDM_IDM_ERROR_LOG_CONTROL_VA);
++ __raw_writel(IDM_ERROR_LOG_ENABLE, AXIIC_DS_0_IDM_ERROR_LOG_CONTROL_VA);
++
++ /* now enable the idm interrupts */
++
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(IHOST_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(IHOST_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(DDR_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(DDR_S2_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXI_PCIE_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXI_PCIE_S1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(CMICD_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(ROM_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(NAND_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(QSPI_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(SATA_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(A9JTAG_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(SRAM_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APX_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(APW_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APBY_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(APBZ_S0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++ ret = request_irq(AXIIC_DS_0_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_1_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_2_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++ ret = request_irq(AXIIC_DS_3_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#ifndef CONFIG_MACH_IPROC_P7
++ ret = request_irq(AXIIC_DS_4_IDM_IRQ, (irq_handler_t)idm_timeout_handler, IRQF_DISABLED | IRQF_PERCPU, "IDM", NULL);
++ if (ret != 0)
++ printk("%s: %d request_irq return = %d\n", __FUNCTION__, __LINE__, ret);
++#endif /* !CONFIG_MACH_IPROC_P7 */
++// printk("%s: %d exit\n", __FUNCTION__, __LINE__);
++}
+diff --git a/arch/arm/mach-iproc/include/mach/io_map.h b/arch/arm/mach-iproc/include/mach/io_map.h
+new file mode 100644
+index 0000000..01dd6fd
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_io_map.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_io_map.h.patch
new file mode 100644
index 00000000..ea279572
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_io_map.h.patch
@@ -0,0 +1,92 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/io_map.h
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __NORTHSTAR_IO_MAP_H
++#define __NORTHSTAR_IO_MAP_H
++
++#include
++#include
++#include
++
++#define IPROC_CCA_CORE_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_REG_BASE)
++#define IPROC_CCA_UART0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCA_UART0_REG_BASE)
++#define IPROC_CCB_GPIO_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_GPIO_REG_BASE)
++#define IPROC_CCB_PWM_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_PWM_REG_BASE)
++#define IPROC_CCB_MDIO_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_MDIO_REG_BASE)
++#define IPROC_CCB_RNG_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_RNG_REG_BASE)
++#define IPROC_CCB_TIM0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_TIM0_REG_BASE)
++#define IPROC_CCB_TIM1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_TIM1_REG_BASE)
++#define IPROC_CCB_SRAU_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_SRAU_REG_BASE)
++#define IPROC_CCB_UART0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_CCB_UART0_REG_BASE)
++
++#define IPROC_DDRC_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_DDRC_REG_BASE)
++#define IPROC_DMAC_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_DMAC_REG_BASE)
++#define IPROC_PCIE_AXIB0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB0_REG_BASE)
++#define IPROC_PCIE_AXIB1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB1_REG_BASE)
++#define IPROC_PCIE_AXIB2_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PCIE_AXIB2_REG_BASE)
++
++#define IPROC_SDIO3_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_SDIO3_REG_BASE)
++#define IPROC_USB20_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB20_REG_BASE)
++#define IPROC_USB30_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB30_REG_BASE)
++#define IPROC_USB20_PHY_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB20_PHY_REG_BASE)
++#define IPROC_GMAC0_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC0_REG_BASE)
++#define IPROC_GMAC1_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC1_REG_BASE)
++#define IPROC_GMAC2_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC2_REG_BASE)
++#define IPROC_GMAC3_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_GMAC3_REG_BASE)
++#define IPROC_DMU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_DMU_REG_BASE)
++#define IPROC_CRU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_CRU_REG_BASE)
++#define IPROC_IDM_REGISTER_VA HW_IO_PHYS_TO_VIRT(IPROC_IDM_REG_BASE)
++#define IPROC_USB2D_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_USB2D_REG_BASE)
++
++#define IPROC_CTF_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_CTF_REG_BASE)
++
++/* ARM9 Private memory region */
++#define PERIPH_BASE IPROC_PERIPH_BASE
++#define IPROC_PERIPH_VA HW_IO_PHYS_TO_VIRT(IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_SCU_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_INT_CTRL_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x100)
++#define IPROC_PERIPH_GLB_TIM_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x200)
++#define IPROC_PERIPH_PVT_TIM_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x600)
++#define IPROC_PERIPH_PVT_WDT_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x620)
++#define IPROC_PERIPH_INT_DISTR_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x1000)
++#define IPROC_L2CC_REG_VA HW_IO_PHYS_TO_VIRT(PERIPH_BASE + 0x2000)
++
++#define IPROC_ROOT_CLK_VA HW_IO_PHYS_TO_VIRT(IPROC_CLK_WR_ACC_REG_BASE)
++#define IPROC_GICCPU_VA HW_IO_PHYS_TO_VIRT(IPROC_GICCPU_CTL_REG_BASE)
++
++#define CCU_PROF_REG_BASE IPROC_CCU_PROF_CTL_REG_BASE
++#define IPROC_CCU_PROF_CTL_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE)
++#define IPROC_CCU_PROF_SEL_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x004)
++#define IPROC_CCU_PROF_CNT_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x008)
++#define IPROC_CCU_PROF_DBG_REG_VA HW_IO_PHYS_TO_VIRT(CCU_PROF_REG_BASE + 0x00C)
++
++#ifdef CONFIG_MACH_CYGNUS
++ #define IPROC_UART_LLDEBUG_PA IPROC_CCA_UART3_REG_BASE
++ #define IPROC_UART_LLDEBUG_VA HW_IO_PHYS_TO_VIRT(IPROC_UART_LLDEBUG_PA)
++#else
++ #define IPROC_UART_LLDEBUG_PA IPROC_CCA_UART0_REG_BASE
++ #define IPROC_UART_LLDEBUG_VA IPROC_CCA_UART0_REG_VA
++#endif
++
++#define IPROC_I2S_REG_VA HW_IO_PHYS_TO_VIRT(IPROC_I2S_REG_BASE)
++
++#endif /*__NORTHSTAR_IO_MAP_H */
+diff --git a/arch/arm/mach-iproc/include/mach/iproc_regs.h b/arch/arm/mach-iproc/include/mach/iproc_regs.h
+new file mode 100644
+index 0000000..460c436
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_iproc_regs.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_iproc_regs.h.patch
new file mode 100644
index 00000000..d3f9f688
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_iproc_regs.h.patch
@@ -0,0 +1,830 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/iproc_regs.h
+@@ -0,0 +1,824 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __IPROC_REGS_H
++#define __IPROC_REGS_H __FILE__
++#include
++#ifdef CONFIG_MACH_CYGNUS
++#include "socregs-cygnus.h"
++#elif defined(CONFIG_MACH_NS)
++#include "socregs_ns_open.h"
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#include "socregs_ing_open.h"
++#elif defined(CONFIG_MACH_NSP)
++#include "socregs_nsp_open.h"
++#elif defined(CONFIG_MACH_IPROC_P7)
++#include "socregs_p7_open.h"
++#else
++#error "No valid iProc Machine type selected"
++#endif
++
++#if defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_IPROC_P7) || \
++ defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_CPUS (1)
++#else
++#define IPROC_NUM_CPUS (2)
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_IRQS (IPROC_INTERRUPTS_WIDTH)
++#else
++#define IPROC_NUM_IRQS (256)
++#endif /* end of CONFIG_MACH_CYGNUS) */
++
++#define IPROC_CPU0_MIN_INT_PRIORITY (0)
++#define IPROC_CPU1_MIN_INT_PRIORITY (0)
++
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_DDR_MEM_BASE1 (0x02000000)
++#else
++#define IPROC_DDR_MEM_BASE1 (0x0)
++#endif /* end of CONFIG_MACH_CYGNUS */
++
++#if defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_CYGNUS)
++#define IPROC_DDR_MEM_BASE2 (0x60000000)
++#else
++#define IPROC_DDR_MEM_BASE2 (0x80000000)
++#endif
++
++
++/* remap to newer reg file defs */
++#ifndef CONFIG_MACH_NS
++#ifdef CONFIG_MACH_CYGNUS //chandra: todo- has to check
++ #define CCA_CHIPID ICFG_CHIP_ID_REG
++#else
++ #define CCA_CHIPID ChipcommonA_ChipID
++#endif
++
++#define NAND_NAND_FLASH_REV NAND_nand_flash_REVISION
++#define NAND_DIRECT_READ_RD_MISS NAND_direct_read_rd_miss
++#define NAND_ECC_MIPS_CORR NAND_ecc_mips_corr
++#define NAND_NAND_FLASH_FLASH_CACHE127 NAND_nand_flash_FLASH_CACHE127
++#define QSPI_MSPI_SPCR0_LSB QSPI_mspi_SPCR0_LSB
++#define QSPI_MSPI_DISABLE_FLUSH_GEN QSPI_mspi_DISABLE_FLUSH_GEN
++#define QSPI_BSPI_REGS_REV_ID QSPI_bspi_registers_REVISION_ID
++#define QSPI_BSPI_REGS_BSPI_PIO_DATA QSPI_bspi_registers_BSPI_PIO_DATA
++#define QSPI_RAF_START_ADDR QSPI_raf_START_ADDR
++#define QSPI_RAF_CURR_ADDR QSPI_raf_CURR_ADDR
++#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED QSPI_raf_interrupt_LR_fullness_reached
++#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE QSPI_mspi_interrupt_MSPI_halt_set_transaction_done
++
++#define CCB_TIM0_TIM_TMR1_LOAD ChipcommonB_tim0_TIM_TIMER1Load
++#define CCB_TIM1_TIM_TMR1_LOAD ChipcommonB_tim1_TIM_TIMER1Load
++
++#define GMAC0_DEVCT GMAC0_DEVCONTROL
++
++#define CCA_GPIO_EVT_BASE ChipcommonA_GPIOEvent_BASE
++#define CCA_GPIO_INPUT_BASE ChipcommonA_GPIOInput_BASE
++#define CCB_GP_INT_CLR_BASE ChipcommonB_GP_INT_TYPE_BASE
++
++#define PAXB_0_PCIE_CTL (PAXB_0_CLK_CONTROL)
++
++#define CCB_MII_MGMT_CTL ChipcommonB_MII_Management_Control
++
++#endif
++
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_NSP) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define CCB_RNG_CTRL ChipcommonB_rng_CTRL
++#endif
++
++
++/* the below might be NS specific */
++#ifdef CONFIG_MACH_CYGNUS //chandra: todo- only timers are mapped correctly
++ #define IPROC_CCA_REG_BASE CCA_CHIPID
++ #define IPROC_CCB_GPIO_REG_BASE (CCB_GP_DATA_IN)
++ #define IPROC_CCB_PWM_REG_BASE (CCB_PWMCTL)
++ #define IPROC_CCB_MDIO_REG_BASE (CCB_MII_MGMT_CTL)
++ #define IPROC_CCB_RNG_REG_BASE (CCB_RNG_CTRL)
++ #define IPROC_CCB_TIM0_REG_BASE (ChipcommonG_tim0_TIM_TIMER1Load)
++ #define IPROC_CCB_TIM1_REG_BASE (ChipcommonG_tim1_TIM_TIMER1Load)
++ #define IPROC_CCB_SRAU_REG_BASE (CCB_SRAB_CMDSTAT)
++ #define IPROC_D1W_REG_BASE (ASIU_D1W_DIN)
++ #define IPROC_D1W_INTR (CHIP_INTR1__ASIU_D1W_INTR)
++ #define IPROC_D1W_CLK_GATE_CTRL (ASIU_TOP_CLK_GATING_CTRL)
++ #define IPROC_D1W_IO_MUX_REG (CRMU_IOMUX_CTRL4)
++
++ #define IPROC_KEYPAD_INTR (ASIU_INTR_STATUS__asiu_keypad_intr)
++ #define IPROC_KEYPAD_REG_BASE (KEYPAD_TOP_REGS_KPCR)
++ #define IPROC_KEYPAD_TOP_REGS_KPCR (KEYPAD_TOP_REGS_KPCR)
++ #define IPROC_KEYPAD_TOP_REGS_KPIOR (KEYPAD_TOP_REGS_KPIOR)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR0 (KEYPAD_TOP_REGS_KPEMR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR1 (KEYPAD_TOP_REGS_KPEMR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR2 (KEYPAD_TOP_REGS_KPEMR2)
++ #define IPROC_KEYPAD_TOP_REGS_KPEMR3 (KEYPAD_TOP_REGS_KPEMR3)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR0 (KEYPAD_TOP_REGS_KPSSR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR1 (KEYPAD_TOP_REGS_KPSSR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPIMR0 (KEYPAD_TOP_REGS_KPIMR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPIMR1 (KEYPAD_TOP_REGS_KPIMR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPICR0 (KEYPAD_TOP_REGS_KPICR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPICR1 (KEYPAD_TOP_REGS_KPICR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPISR0 (KEYPAD_TOP_REGS_KPISR0)
++ #define IPROC_KEYPAD_TOP_REGS_KPISR1 (KEYPAD_TOP_REGS_KPISR1)
++ #define IPROC_KEYPAD_TOP_REGS_KPSSR0 (KEYPAD_TOP_REGS_KPSSR0)
++ #define IPROC_CRMU_ASIU_KEYPAD_CLK_DIV (CRMU_ASIU_KEYPAD_CLK_DIV)
++ #define IPROC_IO_MUX_REG_BASE (CRMU_IOMUX_CTRL1)
++ #define IPROC_CLK_GATING_CTRL (ASIU_TOP_CLK_GATING_CTRL)
++ #define IPROC_KEYPAD_CLK_GATE_EN_BIT (ASIU_TOP_CLK_GATING_CTRL__KEYPAD_CLK_GATE_EN)
++
++ #define IPROC_TSC_REG_BASE (TSCRegCtl1)
++ #define IPROC_TSC_INTR (ASIU_INTR_STATUS__asiu_touch_screen_intr)
++ #define IPROC_ADC_REG_BASE (TSCRegCtl1)
++ #define IPROC_ADC_INTR (ASIU_INTR_STATUS__asiu_touch_screen_intr)
++// #define IPROC_CCB_UART0_REG_BASE (CCB_UART0_RBR_THR_DLL)
++#else
++#define IPROC_CCA_REG_BASE CCA_CHIPID
++#define IPROC_CCB_GPIO_REG_BASE (IPROC_GPIO_CCB_BASE)
++#define IPROC_CCB_PWM_REG_BASE (CCB_PWMCTL)
++#define IPROC_CCB_MDIO_REG_BASE (CCB_MII_MGMT_CTL)
++#define IPROC_CCB_RNG_REG_BASE (CCB_RNG_CTRL)
++#define IPROC_CCB_TIM0_REG_BASE (CCB_TIM0_TIM_TMR1_LOAD)
++#define IPROC_CCB_TIM1_REG_BASE (CCB_TIM1_TIM_TMR1_LOAD)
++#define IPROC_CCB_SRAU_REG_BASE (CCB_SRAB_CMDSTAT)
++#define CCB_UART0_RBR_THR_DLL (0x18037000)
++#define IPROC_CCB_UART0_REG_BASE (CCB_UART0_RBR_THR_DLL)
++#endif /* end of CONFIG_MACH_CYGNUS */
++
++/* iProc Profile 7 specific remapping */
++#if defined(CONFIG_MACH_IPROC_P7)
++
++#define ChipcommonA_ChipID (ICFG_CHIP_ID_REG)
++#define IPROC_CCA_UART0_REG_BASE (ChipcommonG_UART0_UART_RBR_THR_DLL)
++#define IPROC_CCA_UART1_REG_BASE (ChipcommonG_UART1_UART_RBR_THR_DLL)
++#define IPROC_CCS_RNG_REG_BASE (ChipcommonS_RNG_CTRL)
++
++#else /* !CONFIG_MACH_IPROC_P7 */
++
++#define IPROC_CCA_BASE IPROC_CCA_REG_BASE
++#define IPROC_CCA_CORE_CAP_REG_BASE (IPROC_CCA_BASE + 0x04)
++#define IPROC_CCA_CORE_CTL_REG_BASE (IPROC_CCA_BASE + 0x08)
++
++#if defined(CONFIG_MACH_CYGNUS)
++ #define IPROC_CCA_UART0_REG_BASE (ChipcommonG_UART0_UART_RBR_THR_DLL) //(IPROC_CCA_BASE + 0x300) //chandra:
++ #define IPROC_CCA_UART1_REG_BASE (ChipcommonG_UART1_UART_RBR_THR_DLL) //(IPROC_CCA_BASE + 0x400)
++ #define IPROC_CCA_UART2_REG_BASE (ChipcommonG_UART2_UART_RBR_THR_DLL)
++ #define IPROC_CCA_UART3_REG_BASE (ChipcommonG_UART3_UART_RBR_THR_DLL)
++ #define IPROC_CCA_UART4_REG_BASE (ChipcommonG_UART4_UART_RBR_THR_DLL)
++#else
++#define IPROC_CCA_UART0_REG_BASE (IPROC_CCA_BASE + 0x300)
++#define IPROC_CCA_UART1_REG_BASE (IPROC_CCA_BASE + 0x400)
++#endif /*end of CYGNUS */
++#define IPROC_CCA_INTMASK_REG_BASE (IPROC_CCA_BASE + 0x24)
++#define IPROC_CCA_UART_CLK_REG_BASE (IPROC_CCA_BASE + 0xa4)
++
++#endif /* CONFIG_MACH_IPROC_P7 */
++
++#define IPROC_CLK_WR_ACC_REG_BASE (0x19000000)
++#define IPROC_CLK_WR_ACC_REG_OFFSET (0x000)
++#define IPROC_CLK_POLICY_FREQ_REG (0x19000008)
++#define IPROC_CLK_POLICY_FREQ_OFFSET (0x008)
++#define IPROC_CLK_POLICY_CTL_REG (0x1900000C)
++#define IPROC_CLK_POLICY_CTL_OFFSET (0x00C)
++#define IPROC_CLK_POLICY0_MSK_REG (0x19000010)
++#define IPROC_CLK_POLICY0_MSK_OFFSET (0x010)
++#define IPROC_CLK_POLICY1_MSK_REG (0x19000014)
++#define IPROC_CLK_POLICY1_MSK_OFFSET (0x014)
++#define IPROC_CLK_POLICY2_MSK_REG (0x19000018)
++#define IPROC_CLK_POLICY2_MSK_OFFSET (0x018)
++#define IPROC_CLK_POLICY3_MSK_REG (0x1900001C)
++#define IPROC_CLK_POLICY3_MSK_OFFSET (0x01C)
++#define IPROC_CLK_INT_EN_REG (0x19000020)
++#define IPROC_CLK_INT_EN_OFFSET (0x020)
++#define IPROC_CLK_INT_STAT_REG (0x19000024)
++#define IPROC_CLK_INT_STAT_OFFSET (0x024)
++#define IPROC_CLK_LVM_EN_REG (0x19000034)
++#define IPROC_CLK_LVM_EN_OFFSET (0x034)
++#define IPROC_CLK_LVM0_3_REG (0x19000038)
++#define IPROC_CLK_LVM0_3_OFFSET (0x038)
++#define IPROC_CLK_LVM4_7_REG (0x1900003C)
++#define IPROC_CLK_LVM4_7_OFFSET (0x03C)
++#define IPROC_CLK_VLT0_3_REG (0x19000040)
++#define IPROC_CLK_VLT0_3_OFFSET (0x040)
++#define IPROC_CLK_VLT4_7_REG (0x19000044)
++#define IPROC_CLK_VLT4_7_OFFSET (0x044)
++#define IPROC_CLK_BUS_QUIESC_REG (0x19000100)
++#define IPROC_CLK_BUS_QUIESC_OFFSET (0x100)
++#define IPROC_CLK_CORE0_GATE_REG (0x19000200)
++#define IPROC_CLK_CORE0_GATE_OFFSET (0x200)
++#define IPROC_CLK_CORE1_GATE_REG (0x19000204)
++#define IPROC_CLK_CORE1_GATE_OFFSET (0x204)
++#define IPROC_CLK_ARM_SW_GATE_REG (0x19000210)
++#define IPROC_CLK_ARM_SW_GATE_OFFSET (0x210)
++#define IPROC_CLK_ARM_PERIPH_GATE_REG (0x19000300)
++#define IPROC_CLK_ARM_PERIPH_GATE_OFFSET (0x300)
++#define IPROC_CLK_APB0_CLKGATE_REG (0x19000400)
++#define IPROC_CLK_APB0_CLKGATE_OFFSET (0x400)
++#define IPROC_CLK_PL310_DIV_REG (0x19000A00)
++#define IPROC_CLK_PL310_DIV_OFFSET (0xA00)
++#define IPROC_CLK_PL310_TRG_REG (0x19000A04)
++#define IPROC_CLK_PL310_TRG_OFFSET (0xA04)
++#define IPROC_CLK_ARM_SW_DIV_REG (0x19000A08)
++#define IPROC_CLK_ARM_SW_DIV_OFFSET (0xA08)
++#define IPROC_CLK_ARM_SW_TRG_REG (0x19000A0C)
++#define IPROC_CLK_ARM_SW_TRG_OFFSET (0xA0C)
++#define IPROC_CLK_APB_SW_DIV_REG (0x19000A10)
++#define IPROC_CLK_APB_SW_DIV_OFFSET (0xA10)
++#define IPROC_CLK_APB_SW_TRG_REG (0x19000A14)
++#define IPROC_CLK_APB_SW_TRG_OFFSET (0xA14)
++#define IPROC_CLK_PLL_ARMA_REG (0x19000C00)
++#define IPROC_CLK_PLL_ARMA_OFFSET (0xC00)
++#define IPROC_CLK_PLL_ARMB_REG (0x19000C04)
++#define IPROC_CLK_PLL_ARMB_OFFSET (0xC04)
++#define IPROC_CLK_PLL_ARMC_REG (0x19000C08)
++#define IPROC_CLK_PLL_ARMC_OFFSET (0xC08)
++#define IPROC_CLK_PLL_ARMCTL0_REG (0x19000C0C)
++#define IPROC_CLK_PLL_ARMCTL0_OFFSET (0xC0C)
++#define IPROC_CLK_PLL_ARMCTL1_REG (0x19000C10)
++#define IPROC_CLK_PLL_ARMCTL1_OFFSET (0xC10)
++#define IPROC_CLK_PLL_ARMCTL2_REG (0x19000C14)
++#define IPROC_CLK_PLL_ARMCTL2_OFFSET (0xC14)
++#define IPROC_CLK_PLL_ARMCTL3_REG (0x19000C18)
++#define IPROC_CLK_PLL_ARMCTL3_OFFSET (0xC18)
++#define IPROC_CLK_PLL_ARMCTL4_REG (0x19000C1C)
++#define IPROC_CLK_PLL_ARMCTL4_OFFSET (0xC1C)
++#define IPROC_CLK_PLL_ARMCTL5_REG (0x19000C20)
++#define IPROC_CLK_PLL_ARMCTL5_OFFSET (0xC20)
++#define IPROC_CLK_PLL_ARM_OFFSET_REG (0x19000C24)
++#define IPROC_CLK_PLL_ARM_OFFSET_OFFSET (0xC24)
++#define IPROC_CLK_ARM_DIV_REG (0x19000E00)
++#define IPROC_CLK_ARM_DIV_OFFSET (0xE00)
++#define IPROC_CLK_ARM_SEG_TRG_REG (0x19000E04)
++#define IPROC_CLK_ARM_SEG_TRG_OFFSET (0xE04)
++#define IPROC_CLK_ARM_SEG_TRG_OVRD_REG (0x19000E08)
++#define IPROC_CLK_ARM_SEG_TRG_OVRD_OFFSET (0xE08)
++#define IPROC_CLK_PLL_DEBUG_REG (0x19000E10)
++#define IPROC_CLK_PLL_DEBUG_OFFSET (0xE10)
++#define IPROC_CLK_ACTIVITY_MON1_REG (0x19000E20)
++#define IPROC_CLK_ACTIVITY_MON1_OFFSET (0xE20)
++#define IPROC_CLK_ACTIVITY_MON2_REG (0x19000E24)
++#define IPROC_CLK_ACTIVITY_MON2_OFFSET (0xE24)
++#define IPROC_CLK_GATE_DBG_REG (0x19000E40)
++#define IPROC_CLK_GATE_DBG_OFFSET (0xE40)
++#define IPROC_CLK_APB_CLKGATE_DBG1_REG (0x19000E48)
++#define IPROC_CLK_APB_CLKGATE_DBG1_OFFSET (0xE48)
++#define IPROC_CLK_CLKMON_REG (0x19000E64)
++#define IPROC_CLK_CLKMON_OFFSET (0xE64)
++#define IPROC_CLK_KPROC_CCU_PROF_CTL_REG (0x19000E90)
++#define IPROC_CLK_KPROC_CCU_PROF_CTL_OFFSET (0xE90)
++#define IPROC_CLK_KPROC_CCU_PROF_SEL_REG (0x19000E94)
++#define IPROC_CLK_KPROC_CCU_PROF_SEL_OFFSET (0xE94)
++#define IPROC_CLK_KPROC_CCU_PROF_CNT_REG (0x19000E98)
++#define IPROC_CLK_KPROC_CCU_PROF_CNT_OFFSET (0xE98)
++#define IPROC_CLK_KPROC_CCU_PROF_DBG_REG (0x19000E9C)
++#define IPROC_CLK_KPROC_CCU_PROF_DBG_OFFSET (0xE9C)
++#define IPROC_CLK_POLICY_DBG_REG (0x19000EC0)
++#define IPROC_CLK_POLICY_DBG_OFFSET (0xEC0)
++#define IPROC_CLK_TGTMASK_DBG1_REG (0x19000EC4)
++#define IPROC_CLK_TGTMASK_DBG1_OFFSET (0xEC4)
++#define IPROC_RST_WR_ACCESS_REG (0x19000F00)
++#define IPROC_RST_WR_ACCESS_OFFSET (0xF00)
++#define IPROC_RST_SOFT_RSTN_REG (0x19000F04)
++#define IPROC_RST_SOFT_RSTN_OFFSET (0xF04)
++#define IPROC_RST_A9C_SOFT_RSTN_REG (0x19000F08)
++#define IPROC_RST_A9C_SOFT_RSTN_OFFSET (0xF08)
++#define IPROC_RST_A9CORE_SOFT_RSTN_REG (0x19000F08)
++#define IPROC_RST_A9CORE_SOFT_RSTN_OFFSET (0xF08)
++
++#define PLLARMC_PLLARM_MDIV_SHIFT 0
++#define PLLARMC_PLLARM_LOAD_EN_MASK (0x00000800)
++#define PLLARMA_PLLARM_NDIV_INT_MASK (0x0003FF00)
++#define PLLARMA_PLLARM_NDIV_INT_SHIFT 8
++#define PLLARMB_PLLARM_NDIV_FRAC_MASK (0x000FFFFF)
++#define PLLARMB_PLLARM_NDIV_FRAC_SHIFT 0
++#define ARMCTL5_PLLARM_H_MDIV_MASK (0x000000FF)
++#define ARMCTL5_PLLARM_H_MDIV_SHIFT 0
++
++#define IPROC_CLK_CTL_REG (IPROC_CCA_CLK_CTL_REG_BASE + 0x000)
++#define IPROC_CCA_CLK_HW_REQ_OFF 0x00000020
++
++#define IPROC_DDRC_REG_BASE (DDR_DENALI_CTL_00) //(0x18010000)
++#define IPROC_DMAC_REG_BASE (DMAC_P1330_NON_DS) //(0x1802C000)
++#define IPROC_PCIE_AXIB0_REG_BASE (PAXB_0_PCIE_CTL) //(0x18012000)
++#define IPROC_PCIE_AXIB1_REG_BASE (PAXB_1_PCIE_CTL) //(0x18013000)
++#define IPROC_PCIE_AXIB2_REG_BASE (PAXB_2_PCIE_CTL) //(0x18014000)
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_SDIO3_REG_BASE (SDIO_EMMC_SDXC_SYSADDR) //(0x18020000)
++#define IPROC_SDIO_IDM_RESET_CONTROL (0x16800)
++#define IPROC_SDIO_IRQ (177)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT (0x18116408)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE (22)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_SDIO3_REG_BASE (SDIO_eMMCSDXC_SYSADDR)
++#define IPROC_SDIO_IDM_RESET_CONTROL (0x17800)
++#define IPROC_SDIO_IRQ (177)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT (SDIO_IDM_IO_CONTROL_DIRECT)
++#define IPROC_SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE (SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE)
++
++#endif
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_USB20_REG_BASE (0x18021000)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_NSP) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_USB20_REG_BASE (0x1802A000)
++#define IPROC_UDC_IRQ (238)
++#endif
++#define IPROC_USB30_REG_BASE (0x18023000)
++//#define IPROC_USB30_REG_BASE (0x18022000)
++#define IPROC_USB20_PHY_REG_BASE (0x18023000) /* ??*/
++
++#if (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_USB2D_REG_BASE USB2D_ENDPNT_IN_CTRL_0
++#define IPROC_USB2D_REG_SIZE (0x2000) /* 8KB */
++#endif
++
++#if defined(CONFIG_MACH_NS)
++#define IPROC_NUM_GMACS 4
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCTL) //(0x18024000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCTL) //(0x18025000)
++#define IPROC_GMAC2_REG_BASE (GMAC2_DEVCTL) //(0x18026000)
++#define IPROC_GMAC3_REG_BASE (GMAC3_DEVCTL) //(0x18027000)
++#define IPROC_GMAC0_INT 179
++#define IPROC_GMAC1_INT 180
++#define IPROC_GMAC2_INT 181
++#define IPROC_GMAC3_INT 182
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_NUM_GMACS 2
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCONTROL) //(0x18023000)
++#define IPROC_GMAC2_REG_BASE (0) // n/a
++#define IPROC_GMAC3_REG_BASE (0) // n/a
++#define IPROC_GMAC0_INT 234
++#define IPROC_GMAC1_INT 235
++#define IPROC_GMAC2_INT 0 // n/a
++#define IPROC_GMAC3_INT 0 // n/a
++#elif defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_CYGNUS)
++#define IPROC_NUM_GMACS 1
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (0) // n/a
++#define IPROC_GMAC2_REG_BASE (0) // n/a
++#define IPROC_GMAC3_REG_BASE (0) // n/a
++#define IPROC_GMAC0_INT 234
++#define IPROC_GMAC1_INT 0 // n/a
++#define IPROC_GMAC2_INT 0 // n/a
++#define IPROC_GMAC3_INT 0 // n/a
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_NUM_GMACS 4
++#define IPROC_GMAC0_REG_BASE (GMAC0_DEVCONTROL) //(0x18022000)
++#define IPROC_GMAC1_REG_BASE (GMAC1_DEVCONTROL) //(0x18023000)
++#define IPROC_GMAC2_REG_BASE (FA_GMAC0_DEVCONTROL) //(0x18024000)
++#define IPROC_GMAC3_REG_BASE (FA_GMAC1_DEVCONTROL) //(0x18025000)
++#define IPROC_GMAC0_INT 179
++#define IPROC_GMAC1_INT 180
++#define IPROC_GMAC2_INT 181
++#define IPROC_GMAC3_INT 182
++#endif
++
++#define IPROC_CTF_REG_BASE (0x18027C00)
++
++#define IPROC_I2S_REG_BASE (0x1802A000)
++#define IPROC_CCU_PROF_CTL_REG_BASE (0x19000E90)
++
++/* IDM / CRU / DMU */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CRU_REG_BASE (0x1800b000)
++#define IPROC_DMU_REG_BASE (0x1800c000)
++#define IPROC_IDM_REG_BASE (0x18100000)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined (CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_CRU_REG_BASE CRU_control
++#define IPROC_DMU_REG_BASE DMU_PCU_IPROC_CONTROL
++#define IPROC_IDM_REG_BASE (IHOST_M0_IO_CONTROL_DIRECT - 0x408)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_CRU_REG_BASE CRU_control
++#define IPROC_DMU_REG_BASE PCU_MDIO_MGT
++
++#define IPROC_IDM_REG_BASE (IHOST_M0_IO_CONTROL_DIRECT - 0x408)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_CRU_REG_BASE (CRU_control)
++#define IPROC_DMU_REG_BASE DMU_S0_IDM_IDM_RESET_CONTROL
++#endif
++#ifndef CONFIG_MACH_GH
++#define DMU_PCU_IPROC_CONTROL 0x1803f000
++#endif
++
++/* Straps */
++#if defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP)
++#define IPROC_DMU_STRAPS_OFFSET (0x2a0)
++#define IPROC_STRAP_BOOT_DEV_SHIFT (16)
++#define IPROC_STRAP_NAND_TYPE_SHIFT (12)
++#define IPROC_STRAP_NAND_PAGE_SHIFT (10)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_DMU_STRAPS_OFFSET DMU_PCU_IPROC_STRAPS_CAPTURED_BASE
++#define IPROC_STRAP_BOOT_DEV_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R
++#define IPROC_STRAP_NAND_TYPE_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R
++#define IPROC_STRAP_NAND_PAGE_SHIFT DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R
++#endif
++#define IPROC_STRAP_BOOT_DEV_QSPI (0)
++#define IPROC_STRAP_BOOT_DEV_NAND (1)
++#define IPROC_STRAP_BOOT_DEV_PNOR (4)
++
++/* NAND and QSPI */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_IDM_NAND_REG_BASE (0x1811a408)
++#define IPROC_NAND_IRQ_START (100)
++#define IPROC_IDM_QSPI_REG_BASE (0x1811b408)
++#define IPROC_QSPI_IRQ_START (104)
++#define IPROC_QSPI_IRQ_END (109)
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (100)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (104)
++#define IPROC_QSPI_IRQ_END (109)
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (106)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (110)
++#define IPROC_QSPI_IRQ_END (116)
++#elif defined(CONFIG_MACH_CYGNUS)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (IPROC_INTERRUPTS__chipcommonG_spi0_intr)
++#define IPROC_QSPI_IRQ_END (IPROC_INTERRUPTS__chipcommonG_spi5_intr)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_IDM_NAND_REG_BASE NAND_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_NAND_IRQ_START (101)
++#define IPROC_IDM_QSPI_REG_BASE QSPI_IDM_IDM_IO_CONTROL_DIRECT
++#define IPROC_QSPI_IRQ_START (102)
++#define IPROC_QSPI_IRQ_END (102)
++#endif
++
++/* PNOR */
++#ifdef CONFIG_MACH_IPROC_P7
++#define S29GL_FLASH_SIZE 0x04000000
++#define S29GL_FLASH_PHYS 0xe8000000
++#define PNOR_NAND_SEL_REG ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL
++#define PNOR_NAND_SEL_REG_OVERRIDE ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel_sw_ovwr
++#define PNOR_NAND_SEL_REG_PNOR_SEL ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel
++#elif defined(CONFIG_MACH_HR2)
++#define S29GL_FLASH_SIZE 0x04000000
++#define S29GL_FLASH_PHYS 0x20000000
++#define PNOR_NAND_SEL_REG 0x1803fc3c
++#define PNOR_NAND_SEL_REG_OVERRIDE 2
++#define PNOR_NAND_SEL_REG_PNOR_SEL 3
++#endif
++
++/* ARM9 Private memory region */
++#if defined(CONFIG_MACH_CYGNUS)
++#define IPROC_PERIPH_BASE (IHOST_SCU_CONTROL)//chandra:
++#else
++#define IPROC_PERIPH_BASE (0x19020000) //(IHOST_A9MP_scu_CONTROL)
++#endif
++#define IPROC_PERIPH_SCU_REG_BASE (IPROC_PERIPH_BASE)
++#define IPROC_PERIPH_INT_CTRL_REG_BASE (IPROC_PERIPH_BASE + 0x100)
++#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
++#define IPROC_PERIPH_PVT_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x600)
++#define IPROC_PERIPH_PVT_WDT_REG_BASE (IPROC_PERIPH_BASE + 0x620)
++#define IPROC_PERIPH_INT_DISTR_REG_BASE (IPROC_PERIPH_BASE + 0x1000)
++#define IPROC_L2CC_REG_BASE (IPROC_PERIPH_BASE + 0x2000)
++#define IPROC_GTIM_GLB_LO (0x00000000)
++#define IPROC_GTIM_GLB_HI (0x00000004)
++#define IPROC_GTIM_GLB_CTL (0x00000008)
++#define IPROC_GTIM_GLB_STS (0x0000000C)
++#define IPROC_GTIM_GLB_CMP_LO (0x00000010)
++#define IPROC_GTIM_GLB_CMP_HI (0x00000014)
++#define IPROC_GTIM_GLB_INCR (0x00000018)
++
++/* Structures and bit definitions */
++/* SCU Control register */
++#define IPROC_SCU_CTRL_SCU_EN (0x00000001)
++#define IPROC_SCU_CTRL_ADRFLT_EN (0x00000002)
++#define IPROC_SCU_CTRL_PARITY_EN (0x00000004)
++#define IPROC_SCU_CTRL_SPEC_LNFL_EN (0x00000008)
++#define IPROC_SCU_CTRL_FRC2P0_EN (0x00000010)
++#define IPROC_SCU_CTRL_SCU_STNDBY_EN (0x00000020)
++#define IPROC_SCU_CTRL_IC_STNDBY_EN (0x00000040)
++
++/* ARM A9 Private Timer */
++#define IPROC_PVT_TIM_CTRL_TIM_EN (0x00000001)
++#define IPROC_PVT_TIM_CTRL_AUTO_RELD (0x00000002)
++#define IPROC_PVT_TIM_CTRL_INT_EN (0x00000004)
++#define IPROC_PVT_TIM_CTRL_PRESC_MASK (0x0000FF00)
++#define IPROC_PVT_TIM_INT_STATUS_SET (0x00000001)
++
++/* Global timer */
++#define IPROC_GLB_TIM_CTRL_STCS_EN (0x00000000)
++#define IPROC_GLB_TIM_CTRL_TIM_EN (0x00000001)
++#define IPROC_GLB_TIM_CTRL_COMP_EN (0x00000002)
++#define IPROC_GLB_TIM_CTRL_INT_EN (0x00000004)
++#define IPROC_GLB_TIM_CTRL_AUTO_INC (0x00000008)
++#define IPROC_GLB_TIM_CTRL_STCM_SET (0x0000000C)
++#define IPROC_GLB_TIM_CTRL_PRESC_MASK (0x0000FF00)
++#define IPROC_GLB_TIM_INT_STATUS_SET (0x00000001)
++
++#define GLBTMR_GLOB_STATUS_EVENT_G_SHIFT (0x00000000)
++#define GLBTMR_GLOB_CTRL_TIMER_EN_G_SHIFT (0x00000000)
++
++/* GIC(Generic Interrupt controller) CPU interface registers */
++#if defined(CONFIG_MACH_CYGNUS)
++ #define IPROC_GICCPU_CTL_REG_BASE (IHOST_GICCPU_CONTROL)
++#else
++ #define IPROC_GICCPU_CTL_REG_BASE (0x19020100)
++#endif
++#define IPROC_GICCPU_PRI_MASK_OFFSET (0x04)
++#define IPROC_GICCPU_BIN_PT_OFFSET (0x08)
++#define IPROC_GICCPU_INT_ACK_OFFSET (0x0C)
++#define IPROC_GICCPU_EOI_OFFSET (0x10)
++#define IPROC_GICCPU_RUN_PRI_OFFSET (0x14)
++#define IPROC_GICCPU_HI_PEND_OFFSET (0x18)
++#define IPROC_GICCPU_ALIAS_BIN_PT_NS_OFFSET (0x1C)
++#define IPROC_GICCPU_INT_GFC_OFFSET (0x40)
++#define IPROC_GICCPU_INT_FIQ_SET_OFFSET (0x44)
++#define IPROC_GICCPU_INTEG_MATCH_OFFSET (0x50)
++#define IPROC_GICCPU_INTEG_ENABLE_OFFSET (0x54)
++#define IPROC_GICCPU_CPU_IDENT_OFFSET (0xFC)
++
++#define IPROC_GIC_CI_CTRL_EN (0x00000001)
++#define IPROC_GIC_CI_PMR_PRIO_MASK (0x000000FF)
++#define IPROC_GIC_CI_BPR_BP_MASK (0x00000003)
++#define IPROC_GIC_CI_IAR_INTID_MASK (0x000003FF)
++#define IPROC_GIC_CI_IAR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_IAR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_EOIR_INTID_MASK (0x000003FF)
++#define IPROC_GIC_CI_EOIR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_EOIR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_RPR_PRIO_MASK (0x000000FF)
++#define IPROC_GIC_CI_HPIR_PENDID_MASK (0x000003FF)
++#define IPROC_GIC_CI_HPIR_CPUID_MASK (0x00001C00)
++#define IPROC_GIC_CI_HPIR_CPUID_OFFSET (10)
++#define IPROC_GIC_CI_ABPR_BP_MASK (0x00000003)
++
++#define IPROC_GIC_DIST_CTRL_S_EN_S (0x00000001)
++#define IPROC_GIC_DIST_CTRL_S_EN_NS (0x00000002)
++#define IPROC_GIC_DIST_CTRL_NS_EN_NS (0x00000001)
++
++#define IPROC_GIC_DIST_ISR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISER_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ICER_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISPR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_ISPR_SECURE (1)
++#define IPROC_GIC_DIST_ISPR_NON_SECURE (0)
++#define IPROC_GIC_DIST_ICPR_BIT_SIZE (1)
++#define IPROC_GIC_DIST_IPR_BIT_SIZE (8)
++#define IPROC_GIC_DIST_IPTR_BIT_SIZE (8)
++#define IPROC_GIC_DIST_IPTR_CPU0 (0x01)
++#define IPROC_GIC_DIST_IPTR_CPU1 (0x02)
++#define IPROC_GIC_DIST_SGIR_ID_MASK (0xF)
++#define IPROC_GIC_DIST_SGIR_TR_LIST_MASK (0x00FF0000)
++#define IPROC_GIC_DIST_SGIR_TR_LIST_BOFFSET (16)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_MASK (0x03000000)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_BOFFSET (24)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_LIST (0)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_ALL_EX_ME (0x01)
++#define IPROC_GIC_DIST_SGIR_TR_FILT_FW_ME_ONLY (0x02)
++
++#define IPROC_INTR_LEVEL_SENSITIVE (1)
++#define IPROC_INTR_EDGE_TRIGGERED (2)
++
++/* GPIO Driver */
++#if defined(CONFIG_IPROC_GPIO) || defined(CONFIG_IPROC_GPIO_MODULE) || \
++ defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++
++/* Chipcommon A GPIO */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CCA_INT_STS (CCA_INT_STS_BASE)
++#define IPROC_CCA_INT_MASK (CCA_INT_MASK_BASE)
++#define IPROC_GPIO_CCA_BASE (CCA_GPIO_INPUT)
++#define IPROC_GPIO_CCA_DIN (CCA_GPIO_INPUT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_DOUT (CCA_GPIO_OUT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_EN (CCA_GPIO_OUT_EN_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL (CCA_GPIO_INT_POLARITY_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL_MASK (CCA_GPIOINT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT (CCA_GPIO_EVT_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT_MASK (CCA_GPIO_EVTINT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_WATCHDOG_COUNTER (CCA_WDOG_CTR_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_INT_EDGE (CCA_GPIO_EVT_INT_POLARITY_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_TIMER_VAL (CCA_GPIO_TMR_VAL_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_TIMEOUT_MASK (CCA_GPIO_TMR_OUT_MASK_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_CLK_DIV (CCA_CLK_DIV_BASE - CCA_GPIO_INPUT_BASE)
++#define IPROC_GPIO_CCA_DEBUG (CCA_GPIODBG_SEL_BASE - CCA_GPIO_INPUT_BASE)
++
++#define IPROC_DMU_BASE (0x1800c000)
++
++#define IPROC_GPIO_CCA_PULL_UP (0x01dc)
++#define IPROC_GPIO_CCA_PULL_DOWN (0x01e0)
++#define IPROC_GPIO_CCA_CTRL0 (0x01c0)
++
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_NSP, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_CCA_INT_STS (ChipcommonA_IntStatus_BASE)
++#define IPROC_CCA_INT_MASK (ChipcommonA_IntMask_BASE)
++#define IPROC_GPIO_CCA_BASE (ChipcommonA_GPIOInput)
++#define IPROC_GPIO_CCA_DIN (ChipcommonA_GPIOInput_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_DOUT (ChipcommonA_GPIOOut_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_EN (ChipcommonA_GPIOOutEn_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL (ChipcommonA_GPIOIntPolarity_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_LEVEL_MASK (ChipcommonA_GPIOIntMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT (ChipcommonA_GPIOEvent_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EVENT_MASK (ChipcommonA_GPIOEventIntMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_WATCHDOG_COUNTER (ChipcommonA_WatchdogCounter_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_INT_EDGE (ChipcommonA_GPIOEventIntPolarity_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_TIMER_VAL (ChipcommonA_GPIOTimerVal_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_TIMEOUT_MASK (ChipcommonA_GPIOTimerOutMask_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_CLK_DIV (ChipcommonA_ClkDiv_BASE - ChipcommonA_GPIOInput_BASE)
++#define IPROC_GPIO_CCA_DEBUG (ChipcommonA_GPIODebugSel_BASE - ChipcommonA_GPIOInput_BASE)
++#endif
++
++#if defined(CONFIG_MACH_NSP)
++#define IPROC_DMU_BASE (DMAC_pl330_DS)
++#define IPROC_GPIO_CCA_PULL_UP (CRU_GPIO_CONTROL7_BASE)
++#define IPROC_GPIO_CCA_PULL_DOWN (CRU_GPIO_CONTROL8_BASE)
++#define IPROC_GPIO_CCA_CTRL0 (CRU_GPIO_CONTROL0_BASE)
++#endif
++
++/* Chipcommon B GPIO */
++#if defined(CONFIG_MACH_NS)
++#define IPROC_GPIO_CCB_BASE (CCB_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (CCB_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (CCB_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (CCB_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (CCB_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (CCB_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (CCB_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (CCB_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (CCB_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (CCB_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (CCB_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (CCB_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (CCB_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (CCB_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (CCB_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (CCB_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (CCB_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (CCB_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (CCB_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (CCB_GP_PRB_OE_BASE)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_GPIO_CCG_BASE (ChipcommonG_GP_DATA_IN)
++#define IPROC_GPIO_CCB_BASE (ChipcommonG_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (ChipcommonG_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (ChipcommonG_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (ChipcommonG_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (ChipcommonG_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (ChipcommonG_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (ChipcommonG_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (ChipcommonG_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (ChipcommonG_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (ChipcommonG_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (ChipcommonG_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (ChipcommonG_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (ChipcommonG_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (ChipcommonG_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (ChipcommonG_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (ChipcommonG_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (ChipcommonG_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (ChipcommonG_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (ChipcommonG_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (ChipcommonG_GP_PRB_OE_BASE)
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_NSP, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_GPIO_CCB_BASE (ChipcommonB_GP_DATA_IN)
++#define IPROC_GPIO_CCB_DIN (ChipcommonB_GP_DATA_IN_BASE)
++#define IPROC_GPIO_CCB_DOUT (ChipcommonB_GP_DATA_OUT_BASE)
++#define IPROC_GPIO_CCB_EN (ChipcommonB_GP_OUT_EN_BASE)
++#define IPROC_GPIO_CCB_INT_TYPE (ChipcommonB_GP_INT_TYPE_BASE)
++#define IPROC_GPIO_CCB_INT_DE (ChipcommonB_GP_INT_DE_BASE)
++#define IPROC_GPIO_CCB_INT_EDGE (ChipcommonB_GP_INT_EDGE_BASE)
++#define IPROC_GPIO_CCB_INT_MASK (ChipcommonB_GP_INT_MSK_BASE)
++#define IPROC_GPIO_CCB_INT_STAT (ChipcommonB_GP_INT_STAT_BASE)
++#define IPROC_GPIO_CCB_INT_MSTAT (ChipcommonB_GP_INT_MSTAT_BASE)
++#define IPROC_GPIO_CCB_INT_CLR (ChipcommonB_GP_INT_CLR_BASE)
++#define IPROC_GPIO_CCB_AUX_SEL (ChipcommonB_GP_AUX_SEL_BASE)
++#define IPROC_GPIO_CCB_INIT_VAL (ChipcommonB_GP_INIT_VAL_BASE)
++#define IPROC_GPIO_CCB_PAD_RES (ChipcommonB_GP_PAD_RES_BASE)
++#define IPROC_GPIO_CCB_RES_EN (ChipcommonB_GP_RES_EN_BASE)
++#define IPROC_GPIO_CCB_TST_IN (ChipcommonB_GP_TEST_INPUT_BASE)
++#define IPROC_GPIO_CCB_TST_OUT (ChipcommonB_GP_TEST_OUTPUT_BASE)
++#define IPROC_GPIO_CCB_TST_EN (ChipcommonB_GP_TEST_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_EN (ChipcommonB_GP_PRB_ENABLE_BASE)
++#define IPROC_GPIO_CCB_PRB_OE (ChipcommonB_GP_PRB_OE_BASE)
++#endif
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IPROC_GPIO_CCA_INT (117)
++#define IPROC_GPIO_CCB_INT (119)
++#elif defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_GPIO_CCG_INT (116)
++#else
++/* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_GPIO_CCA_INT (123)
++#define IPROC_GPIO_CCB_INT (125)
++#endif
++#endif /* CONFIG_IPROC_GPIO || CONFIG_IPROC_GPIO_MODULE */
++
++/* PWM Driver */
++#if defined(CONFIG_IPROC_PWM) || defined(CONFIG_IPROC_PWM_MODULE)
++#if defined(CONFIG_MACH_NS)
++#define IPROC_CCB_PWM_CTL (CCB_PWM_CTL)
++#define IPROC_CCB_PWM_CTL_BASE (CCB_PWM_CTL_BASE)
++#define IPROC_CCB_PWM_PRESCALE_BASE (CCB_PWM_PRESCALE_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT0_BASE (CCB_PWM_PERIOD_COUNT0_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT1_BASE (CCB_PWM_PERIOD_COUNT1_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT2_BASE (CCB_PWM_PERIOD_COUNT2_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT3_BASE (CCB_PWM_PERIOD_COUNT3_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT0_BASE (CCB_PWM_DUTY_HI_COUNT0_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT1_BASE (CCB_PWM_DUTY_HI_COUNT1_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT2_BASE (CCB_PWM_DUTY_HI_COUNT2_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT3_BASE (CCB_PWM_DUTY_HI_COUNT3_BASE)
++#endif /* CONFIG_MACH_NS */
++
++#if defined(CONFIG_MACH_NSP)
++#define IPROC_CCB_PWM_CTL (ChipcommonB_PWMCTL)
++#define IPROC_CCB_PWM_CTL_BASE (ChipcommonB_PWMCTL_BASE)
++#define IPROC_CCB_PWM_PRESCALE_BASE (ChipcommonB_PWM_PRESCALE_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT0_BASE (ChipcommonB_PWM_PERIOD_COUNT0_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT1_BASE (ChipcommonB_PWM_PERIOD_COUNT1_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT2_BASE (ChipcommonB_PWM_PERIOD_COUNT2_BASE)
++#define IPROC_CCB_PWM_PERIOD_COUNT3_BASE (ChipcommonB_PWM_PERIOD_COUNT3_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT0_BASE (ChipcommonB_PWM_DUTYHI_COUNT0_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT1_BASE (ChipcommonB_PWM_DUTYHI_COUNT1_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT2_BASE (ChipcommonB_PWM_DUTYHI_COUNT2_BASE)
++#define IPROC_CCB_PWM_DUTY_HI_COUNT3_BASE (ChipcommonB_PWM_DUTYHI_COUNT3_BASE)
++#endif /* CONFIG_MACH_NSP */
++
++#endif /* CONFIG_IPROC_PWM */
++
++/* ChipCommonB Timer */
++#if defined(CONFIG_MACH_IPROC_P7)
++#define IPROC_CCB_TIMER0_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim0_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER1_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim1_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER2_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim2_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER3_REGS_VA HW_IO_PHYS_TO_VIRT(ChipcommonG_tim3_TIM_TIMER1Load)
++#define IPROC_CCB_TIMER_INT_START (119)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#elif (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++#define IPROC_CCB_TIMER0_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x00)
++#define IPROC_CCB_TIMER1_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x20)
++#define IPROC_CCB_TIMER2_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x00)
++#define IPROC_CCB_TIMER3_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x20)
++#define IPROC_CCB_TIMER_INT_START (122)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#else /* CONFIG_MACH_HX4, CONFIG_MACH_HR2, CONFIG_MACH_KT2, CONFIG_MACH_DNI_3448P */
++#define IPROC_CCB_TIMER0_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x00)
++#define IPROC_CCB_TIMER1_REGS_VA (IPROC_CCB_TIM0_REG_VA + 0x20)
++#define IPROC_CCB_TIMER2_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x00)
++#define IPROC_CCB_TIMER3_REGS_VA (IPROC_CCB_TIM1_REG_VA + 0x20)
++#define IPROC_CCB_TIMER_INT_START (129)
++#define IPROC_CCB_TIMER_INT_COUNT (4)
++#endif
++
++/* ChipCommonB Watchdog */
++/*
++ * CCB WDT could be set only when CONFIG_MACH_HR2, CONFIG_MACH_HX4,
++ * CONFIG_MACH_DNI_3448P or CONFIG_MACH_NSP is set
++ */
++#define IPROC_CCB_WDT_WDOGLOAD ChipcommonB_WDT_WDOGLOAD
++#define IPROC_CCB_WDT_REG_BASE IPROC_CCB_WDT_WDOGLOAD
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_CCB_WDT_BOOTSTATUS DMU_PCU_CRU_RESET_REASON
++#define IPROC_CCB_WDT_BOOTSTATUS_BIT DMU_PCU_CRU_RESET_REASON__watchdog_reset
++#elif defined(CONFIG_MACH_NSP)
++#define IPROC_CCB_WDT_BOOTSTATUS CRU_WATCHDOG_PCIE_RESET_STATUS
++#define IPROC_CCB_WDT_BOOTSTATUS_BIT CRU_WATCHDOG_PCIE_RESET_STATUS__CCB_WATCHDOG_RESET_EVENT
++#endif
++
++/* ChipCommonG Watchdog */
++#if defined(CONFIG_IPROC_CCG_WDT) || defined(CONFIG_IPROC_CCG_WDT_MODULE)
++#define IPROC_CCG_WDT_REG_BASE ChipcommonG_WDT_WDOGLOAD
++#define IPROC_CCG_WDT_BOOTSTATUS DMU_PCU_CRU_RESET_REASON
++#define IPROC_CCG_WDT_BOOTSTATUS_BIT DMU_PCU_CRU_RESET_REASON__watchdog_reset
++#endif /* CONFIG_IPROC_CCG_WDT || CONFIG_IPROC_CCG_WDT_MODULE */
++
++#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++#define IPROC_SP805_WDT_REG_BASE IPROC_CCB_WDT_REG_BASE
++#define IPROC_SP805_WDT_BOOTSTATUS IPROC_CCB_WDT_BOOTSTATUS
++#define IPROC_SP805_WDT_BOOTSTATUS_BIT IPROC_CCB_WDT_BOOTSTATUS_BIT
++#endif /* CONFIG_IPROC_SP805_WDT */
++
++#endif /*__IPROC_REGS_H */
+diff --git a/arch/arm/mach-iproc/include/mach/nand_iproc.h b/arch/arm/mach-iproc/include/mach/nand_iproc.h
+new file mode 100644
+index 0000000..9c4d4fc
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_nand_iproc.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_nand_iproc.h.patch
new file mode 100644
index 00000000..90d7b97d
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_nand_iproc.h.patch
@@ -0,0 +1,43 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/nand_iproc.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _NAND_IPROC_H_
++#define _NAND_IPROC_H_
++
++/*
++ * Registers used directly in driver
++ */
++
++/*
++ * Shared Structure
++ */
++struct mtd_partition;
++struct brcmnand_platform_data {
++ int chip_select;
++ int strap_boot;
++ int strap_type;
++ int strap_page_size;
++ int nr_parts;
++ struct mtd_partition *parts;
++};
++
++#endif /* _NAND_IPROC_H_ */
+diff --git a/arch/arm/mach-iproc/include/mach/qspi_iproc.h b/arch/arm/mach-iproc/include/mach/qspi_iproc.h
+new file mode 100644
+index 0000000..14fcac8
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_qspi_iproc.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_qspi_iproc.h.patch
new file mode 100644
index 00000000..d52845fd
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_qspi_iproc.h.patch
@@ -0,0 +1,33 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/qspi_iproc.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _QSPI_IPROC_H_
++#define _QSPI_IPROC_H_
++
++/*
++ * Shared Structure
++ */
++struct brcmspi_platform_data {
++ int flash_cs;
++};
++
++#endif /* _SPI_IPROC_H_ */
+diff --git a/arch/arm/mach-iproc/include/mach/reg_utils.h b/arch/arm/mach-iproc/include/mach/reg_utils.h
+new file mode 100644
+index 0000000..6cc36bf
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_reg_utils.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_reg_utils.h.patch
new file mode 100644
index 00000000..bf6dea5c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_reg_utils.h.patch
@@ -0,0 +1,166 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/reg_utils.h
+@@ -0,0 +1,160 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef REG_UTILS
++#define REG_UTILS
++
++/* ---- Include Files ---------------------------------------------------- */
++
++#include
++
++/* ---- Public Constants and Types --------------------------------------- */
++
++#define __REG32(x) (*((volatile uint32_t *)(x)))
++#define __REG16(x) (*((volatile uint16_t *)(x)))
++#define __REG8(x) (*((volatile uint8_t *) (x)))
++
++/* ---- Public Variable Externs ------------------------------------------ */
++/* ---- Public Function Prototypes --------------------------------------- */
++
++/****************************************************************************/
++/*
++ * 32-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg32_set_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg32_write_masked(volatile uint32_t *reg, uint32_t mask,
++ uint32_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg32_write(volatile uint32_t *reg, uint32_t value)
++{
++ *reg = value;
++}
++
++static inline uint32_t
++reg32_read(volatile uint32_t *reg)
++{
++ return *reg;
++}
++
++/****************************************************************************/
++/*
++ * 16-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg16_set_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg16_write(volatile uint16_t *reg, uint16_t value)
++{
++ *reg = value;
++}
++
++static inline uint16_t
++reg16_read(volatile uint16_t *reg)
++{
++ return *reg;
++}
++
++/****************************************************************************/
++/*
++ * 8-bit register access functions
++ */
++/****************************************************************************/
++
++static inline void
++reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg &= ~(value);
++}
++
++static inline void
++reg8_set_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg |= value;
++}
++
++static inline void
++reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
++{
++ *reg ^= value;
++}
++
++static inline void
++reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
++{
++ *reg = (*reg & (~mask)) | (value & mask);
++}
++
++static inline void
++reg8_write(volatile uint8_t *reg, uint8_t value)
++{
++ *reg = value;
++}
++
++static inline uint8_t
++reg8_read(volatile uint8_t *reg)
++{
++ return *reg;
++}
++#endif /* REG_UTILS */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_ing_open.h b/arch/arm/mach-iproc/include/mach/socregs_ing_open.h
+new file mode 100644
+index 0000000..2431b98
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ing_open.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ing_open.h.patch
new file mode 100644
index 00000000..95057dd1
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ing_open.h.patch
@@ -0,0 +1,781 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_ing_open.h
+@@ -0,0 +1,775 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_ING_OPEN_H
++#define __SOCREGS_ING_OPEN_H
++
++#define ChipcommonA_ChipID 0x18000000
++#define ChipcommonB_PWMCTL 0x18031000
++#define ChipcommonB_WDT_WDOGLOAD 0x18039000
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_SMBus_Config 0x18038000
++#define ChipcommonA_OTPProg 0x18000018
++#define ChipcommonA_OTPLayout 0x1800001c
++#define ChipcommonA_CoreCapabilities 0x18000004
++#define ChipcommonA_OTPStatus 0x18000010
++#define ChipcommonB_rng_CTRL 0x18033000
++#define QSPI_mspi_SPCR0_LSB 0x18027200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
++#define QSPI_bspi_registers_REVISION_ID 0x18027000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
++#define QSPI_raf_START_ADDR 0x18027100
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define QSPI_raf_CURR_ADDR 0x18027120
++#define CRU_control 0x1803e000
++#define GMAC0_DEVCONTROL 0x18022000
++#define GMAC1_DEVCONTROL 0x18023000
++#define ChipcommonA_GPIOEvent_BASE 0x078
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_CLR_BASE 0x024
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOIntMask_BASE 0x074
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonB_GP_INT_DE_BASE 0x010
++#define ChipcommonB_GP_INT_EDGE_BASE 0x014
++#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_GP_PAD_RES_BASE 0x034
++#define ChipcommonB_GP_RES_EN_BASE 0x038
++#define ChipcommonA_ChipID 0x18000000
++#define DMAC_pl330_DS 0x18020000
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define PAXB_0_CLK_CONTROL 0x18012000
++#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
++#define ChipcommonB_MII_Management_Control 0x18032000
++#define ChipcommonB_MII_Management_Command_Data 0x18032004
++#define NAND_nand_flash_REVISION 0x18026000
++#define NAND_direct_read_rd_miss 0x18026f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
++#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
++#define ChipcommonB_PWM_PRESCALE_BASE 0x024
++#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
++#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
++#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
++#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
++#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
++#define ChipcommonB_PWMCTL_BASE 0x000
++#define ChipcommonB_rng_CTRL 0x18033000
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define USB2_IDM_IDM_IO_CONTROL_DIRECT 0x18115408
++#define USB2D_IDM_IDM_IO_CONTROL_DIRECT 0x18116408
++#define USB2D_IDM_IDM_IO_CONTROL_DIRECT__clk_enable 0
++#define USB2D_IDM_IDM_RESET_CONTROL 0x18116800
++#define USB2D_IDM_IDM_RESET_CONTROL__RESET 0
++#endif
++#define DMU_CRU_RESET_BASE 0x200
++#define ChipcommonB_SMBus1_SMBus_Config 0x1803b000
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define USB2D_ENDPNT_IN_CTRL_0 0x18042000
++#endif
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810c900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810c904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810c908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810c90c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810c914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810c91c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810ca00
++#endif
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810d914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810da00
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
++#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define APBV_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18122900
++#define APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18122904
++#define APBV_S0_IDM_IDM_ERROR_LOG_STATUS 0x18122908
++#define APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812290c
++#define APBV_S0_IDM_IDM_ERROR_LOG_ID 0x18122914
++#define APBV_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812291c
++#define APBV_S0_IDM_IDM_INTERRUPT_STATUS 0x18122a00
++#endif
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18124900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18124904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x18124908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1812490c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18124914
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x1812491c
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18124a00
++#endif
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00
++#if (defined(CONFIG_MACH_KT2) || defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18142900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18142904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18142908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1814290c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18142914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1814291c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18142a00
++#endif
++#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
++#define ChipcommonA_IntMask_BASE 0x024
++#define DMU_PCU_CRU_RESET_REASON 0x1803f014
++#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonA_GPIOOut 0x18000064
++#define ChipcommonA_GPIOOutEn 0x18000068
++#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
++#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM0_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
++#define AMAC_IDM0_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
++#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
++#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM1_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
++#define AMAC_IDM1_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
++#if defined(CONFIG_MACH_KT2)
++#define IPROC_WRAP_USBPHY_CTRL 0x1803fc20
++#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_CTRL_SEL 1
++#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 3
++#define IPROC_WRAP_MISC_CONTROL 0x1803fc24
++#define IPROC_WRAP_MISC_CONTROL__UNICORE_SERDES_MDIO_SEL 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0 0x1803fc00
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_BASE 0xc00
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__CH0_MDEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__NDIV_RELOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__FAST_LOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2 26
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DIV2_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_L 25
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_R 24
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__VCO_DLY_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_L 23
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_R 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__PWM_RATE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_L 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_R 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_WIDTH 2
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_MODE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL 19
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__AUX_CTRL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT 18
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__TESTCLKOUT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE 17
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_UPDATE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_L 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_R 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_SELECT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__STAT_RESET_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_L 11
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_WIDTH 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__DCO_CTRL_BYPASS_RESETVALUE 0x000
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_0__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_0_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1 0x1803fc04
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_BASE 0xc04
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KA_RESETVALUE 0x2
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_L 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_R 26
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KI_RESETVALUE 0x3
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_L 25
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_R 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_WIDTH 4
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__KP_RESETVALUE 0x7
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_L 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_WIDTH 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__SSC_LIMIT_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_1__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_1_RESETVALUE 0x4dc00000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2 0x1803fc08
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_BASE 0xc08
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__PDIV_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_PHASE_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_L 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_R 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_WIDTH 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__FB_OFFSET_RESETVALUE 0x000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_L 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_WIDTH 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__SSC_STEP_RESETVALUE 0x0000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_2__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_2_RESETVALUE 0x20000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3 0x1803fc0c
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_BASE 0xc0c
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__SSC_MODE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN 30
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__PHASE8_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_L 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_R 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_WIDTH 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_FRAC_RESETVALUE 0x00000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_L 9
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_WIDTH 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__NDIV_INT_RESETVALUE 0x80
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_3__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_3_RESETVALUE 0x80
++#define IPROC_DDR_PLL_CTRL_REGISTER_4 0x1803fc10
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_BASE 0xc10
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_R 29
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN 28
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__PWRDWN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_L 27
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_R 24
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_WIDTH 4
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__SPARE_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN 23
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL 22
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__TEST_SEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN 21
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__D2C_HYST_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR 20
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__BYPASS_POR_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_L 19
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_R 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_WIDTH 6
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__LOAD_EN_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_L 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_R 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_WIDTH 6
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__HOLD_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_L 7
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_WIDTH 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__CH0_MDIV_RESETVALUE 0x08
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_4__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_4_RESETVALUE 0x8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5 0x1803fc14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_BASE 0xc14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_R 17
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_WIDTH 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR 16
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_SW_OVWR_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN 15
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT1_EN_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN 14
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_OUT0_EN_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL 13
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_CLK_IN_SEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB 12
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_POST_RESETB_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB 11
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_WIDTH 1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__IPROC_DDR_PLL_RESETB_RESETVALUE 0x1
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_L 10
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_R 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_WIDTH 3
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDEL_RESETVALUE 0x0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_L 7
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_WIDTH 8
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__CH1_MDIV_RESETVALUE 0x64
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__WIDTH 32
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_L 31
++#define IPROC_DDR_PLL_CTRL_REGISTER_5__ALL_R 0
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_CTRL_REGISTER_5_RESETVALUE 0xd864
++#define IPROC_DDR_PLL_STATUS 0x1803fc18
++#define IPROC_DDR_PLL_STATUS_BASE 0xc18
++#define IPROC_DDR_PLL_STATUS__RESERVED_L 31
++#define IPROC_DDR_PLL_STATUS__RESERVED_R 14
++#define IPROC_DDR_PLL_STATUS__RESERVED_WIDTH 18
++#define IPROC_DDR_PLL_STATUS__RESERVED_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST 13
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_WIDTH 1
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_LOST_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK 12
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_WIDTH 1
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_LOCK_RESETVALUE 0x0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_L 11
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_R 0
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_WIDTH 12
++#define IPROC_DDR_PLL_STATUS__IPROC_DDR_PLL_STAT_OUT_RESETVALUE 0x000
++#define IPROC_DDR_PLL_STATUS_WIDTH 32
++#define IPROC_DDR_PLL_STATUS__WIDTH 32
++#define IPROC_DDR_PLL_STATUS_ALL_L 31
++#define IPROC_DDR_PLL_STATUS_ALL_R 0
++#define IPROC_DDR_PLL_STATUS__ALL_L 31
++#define IPROC_DDR_PLL_STATUS__ALL_R 0
++#define IPROC_DDR_PLL_STATUS_DATAMASK 0xffffffff
++#define IPROC_DDR_PLL_STATUS_RDWRMASK 0x00000000
++#define IPROC_DDR_PLL_STATUS_RESETVALUE 0x0
++#endif
++#if (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++#define IPROC_WRAP_USBPHY_CTRL 0x1803fc34
++#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 3
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 13
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 21
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0 0x1803fc1c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_BASE 0xc1c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_R 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH5_MDIV_RESETVALUE 0x18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_L 23
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_R 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH4_MDIV_RESETVALUE 0x0f
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_L 15
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH3_MDIV_RESETVALUE 0x64
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__CH0_MDIV_RESETVALUE 0x1e
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_0_RESETVALUE 0x180f641e
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1 0x1803fc20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_BASE 0xc20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__Reserved_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB 26
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB 25
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_L 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_R 22
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__PDIV_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_L 21
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_R 18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KP_RESETVALUE 0x8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_L 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_R 15
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KI_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_L 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_R 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__KA_RESETVALUE 0x4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_L 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_R 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_WIDTH 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__LOAD_EN_CH_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_L 5
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_WIDTH 6
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__HOLD_CH_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RESETVALUE 0x660c000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2 0x1803fc24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_BASE 0xc24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__RSVD_0_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_R 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH2_MDIV_RESETVALUE 0x00
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_L 19
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_R 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH5_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_L 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_R 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH4_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_L 13
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_R 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH3_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_L 10
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH0_MDEL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__CH1_MDIV_RESETVALUE 0x0f
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_2_RESETVALUE 0xf
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3 0x1803fc28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_BASE 0xc28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_R 30
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__RSVD_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN 29
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT2_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_2ED_OUT_EN_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_R 26
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DIG_LDO_CTRL_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_L 25
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_R 24
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_WIDTH 2
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ANA_LDO_CTRL_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN 23
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__TESTOUT_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN 22
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_OUTPUT_EN_RESETVALUE 0x1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN 21
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__CML_BYP_EN_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__VCOdiv2_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL 19
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__AUX_CTRL_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT 18
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__REFCLKOUT_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE 17
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_UPDATE_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_L 16
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_R 14
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_WIDTH 3
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_SELECT_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET 13
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__STAT_RESET_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_ENABLE_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_L 11
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_WIDTH 12
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__DCO_CTRL_BYPASS_RESETVALUE 0x000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_3_RESETVALUE 0x15400000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4 0x1803fc2c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_BASE 0xc2c
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_R 28
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_WIDTH 4
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__RSVD_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_L 27
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_R 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_WIDTH 20
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_FRAC_RESETVALUE 0x00000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_L 7
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_WIDTH 8
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__NDIV_INT_RESETVALUE 0x78
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_CTRL_4_RESETVALUE 0x78
++#define IPROC_WRAP_IPROC_XGPLL_STATUS 0x1803fc30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_BASE 0xc30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_WIDTH 1
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_L 30
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_WIDTH 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__XGPLL_STATUS_RESETVALUE 0x0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__WIDTH 32
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_L 31
++#define IPROC_WRAP_IPROC_XGPLL_STATUS__ALL_R 0
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_DATAMASK 0xffffffff
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_RDWRMASK 0x00000000
++#define IPROC_WRAP_IPROC_XGPLL_STATUS_RESETVALUE 0x0
++#if defined(CONFIG_MACH_HX4) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_MDIO_SEL 3
++#define IPROC_WRAP_MISC_CONTROL__QUAD_SERDES_CTRL_SEL 2
++#define IPROC_WRAP_MISC_CONTROL__IPROC_MDIO_SEL 4
++#endif
++#define IPROC_WRAP_MISC_CONTROL 0x1803fc3c
++#endif
++
++#endif /* __SOCREGS_ING_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_ns_open.h b/arch/arm/mach-iproc/include/mach/socregs_ns_open.h
+new file mode 100644
+index 0000000..8f3d2eb
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ns_open.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ns_open.h.patch
new file mode 100644
index 00000000..f694a373
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_ns_open.h.patch
@@ -0,0 +1,87 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_ns_open.h
+@@ -0,0 +1,81 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_NS_OPEN_H
++#define __SOCREGS_NS_OPEN_H
++
++
++#define CCA_CHIPID 0x18000000
++#define CCA_CHIPID_BASE 0x000
++#define CCB_GP_DATA_IN 0x18001000
++#define USB30_BASE 0x18023000
++#define SDIO_EMMC_SDXC_SYSADDR 0x18020000
++#define CCB_PWM_CTL 0x18002000
++#define CCB_TIM0_TIM_TMR1_LOAD 0x18005000
++#define CCB_TIM1_TIM_TMR1_LOAD 0x18006000
++#define CCB_SMBUS_START 0x18009000
++#define CCB_GP_AUX_SEL_BASE 0x028
++#define QSPI_MSPI_SPCR0_LSB 0x18029200
++#define QSPI_MSPI_DISABLE_FLUSH_GEN 0x18029384
++#define QSPI_BSPI_REGS_REV_ID 0x18029000
++#define QSPI_BSPI_REGS_BSPI_PIO_DATA 0x1802904c
++#define QSPI_RAF_START_ADDR 0x18029100
++#define QSPI_RAF_CURR_ADDR 0x18029120
++#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED 0x180293a0
++#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE 0x180293b8
++#define GMAC0_DEVCTL 0x18024000
++#define GMAC1_DEVCTL 0x18025000
++#define GMAC2_DEVCTL 0x18026000
++#define GMAC3_DEVCTL 0x18027000
++#define CCA_GPIO_EVT_BASE 0x078
++#define CCA_GPIO_INPUT 0x18000060
++#define CCA_GPIO_INPUT_BASE 0x060
++#define CCB_GP_INT_CLR_BASE 0x024
++#define CCA_GPIO_EVTINT_MASK_BASE 0x07c
++#define CCB_GP_INT_MSK_BASE 0x018
++#define CCA_GPIOINT_MASK_BASE 0x074
++#define CCA_GPIO_EVT_INT_POLARITY_BASE 0x084
++#define CCA_GPIO_INT_POLARITY_BASE 0x070
++#define CCA_INT_MASK_BASE 0x024
++#define CCB_GP_INT_TYPE_BASE 0x00c
++#define CCB_GP_INT_DE_BASE 0x010
++#define CCB_GP_INT_EDGE_BASE 0x014
++#define CCA_INT_STS_BASE 0x020
++#define CCB_GP_INT_MSTAT_BASE 0x020
++#define CCB_GP_PAD_RES_BASE 0x034
++#define CCB_GP_RES_EN_BASE 0x038
++#define CCB_MII_MGMT_CTL 0x18003000
++#define CCB_MII_MGMT_DATA 0x18003004
++#define NAND_NAND_FLASH_REV 0x18028000
++#define ChipcommonB_MII_Management_Control CCB_MII_MGMT_CTL
++#define ChipcommonB_MII_Management_Command_Data CCB_MII_MGMT_DATA
++#define NAND_DIRECT_READ_RD_MISS 0x18028f00
++#define CCB_PWM_PRESCALE_BASE 0x024
++#define CCB_PWM_PERIOD_COUNT0_BASE 0x004
++#define CCB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define CCB_PWM_DUTY_HI_COUNT2_BASE 0x018
++#define CCB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define CCB_PWM_DUTY_HI_COUNT0_BASE 0x008
++#define CCB_PWM_DUTY_HI_COUNT1_BASE 0x010
++#define CCB_PWM_DUTY_HI_COUNT2_BASE 0x018
++#define CCB_PWM_DUTY_HI_COUNT3_BASE 0x020
++#define CCB_PWM_CTL_BASE 0x000
++#define CCB_PWM_PERIOD_COUNT2_BASE 0x014
++#define CCB_RNG_CTRL 0x18004000
++
++
++#endif /* __SOCREGS_NS_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h b/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h
+new file mode 100644
+index 0000000..e98c003
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_nsp_open.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_nsp_open.h.patch
new file mode 100644
index 00000000..a0d18cd2
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_nsp_open.h.patch
@@ -0,0 +1,404 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_nsp_open.h
+@@ -0,0 +1,398 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_NSP_OPEN_H
++#define __SOCREGS_NSP_OPEN_H
++
++#define ChipcommonA_ChipID 0x18000000
++#define PCU_MDIO_MGT 0x1803f000
++#define ChipcommonB_PWMCTL 0x18031000
++#define ChipcommonB_WDT_WDOGLOAD 0x18039000
++#define USB3_CAPLENGTH 0x18029000
++#define USB30_BASE USB3_CAPLENGTH
++#define SATA_AHCI_GHC_HBA_CAP 0x18041000
++#define SATA_M0_IDM_IO_CONTROL_DIRECT 0x1811e408
++#define SATA_M0_IDM_IDM_RESET_CONTROL 0x1811e800
++#define SATA3_PCB_UPPER_REG1 0x18040304
++#define SATA3_PCB_UPPER_REG0 0x18040300
++#define SATA3_PCB_UPPER_REG1 0x18040304
++#define SATA3_PCB_UPPER_REG11 0x1804032c
++#define SATA3_PCB_UPPER_REG5 0x18040314
++#define SATA3_PCB_UPPER_REG15 0x1804033c
++#define SATA_TOP_CTRL_BUS_CTRL 0x18040024
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define ChipcommonB_SMBus_Config 0x18038000
++#define ChipcommonB_tim0_TIM_TIMER1Load 0x18034000
++#define ChipcommonB_tim1_TIM_TIMER1Load 0x18035000
++#define QSPI_mspi_SPCR0_LSB 0x18027200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
++#define QSPI_bspi_registers_REVISION_ID 0x18027000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
++#define QSPI_raf_START_ADDR 0x18027100
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define QSPI_raf_CURR_ADDR 0x18027120
++#define CRU_control 0x1803e000
++#define GMAC0_DEVCONTROL 0x18022000
++#define GMAC1_DEVCONTROL 0x18023000
++#define FA_GMAC0_DEVCONTROL 0x18024000
++#define FA_GMAC1_DEVCONTROL 0x18025000
++#define CRU_CLKSET_KEY_OFFSET 0x1803f180
++#define CRU_LCPLL2_CONTROL0 0x1803f548
++#define CRU_LCPLL2_CONTROL0__PWRDWN 12
++#define CRU_LCPLL2_CONTROL0__RESETB 11
++#define CRU_LCPLL2_STATUS__LOCK 12
++#define CRU_LCPLL2_CONTROL0__PWRDWN 12
++#define CRU_LCPLL2_CONTROL0__RESETB 11
++#define CRU_RESET__SGMII_RESET_N 8
++#define CRU_RESET 0x1803f184
++#define SGMII_CONFIG 0x1803f410
++#define SGMII_CONFIG__RSTB_PLL 17
++#define SGMII_CONFIG__RSTB_MDIOREGS 16
++#define SGMII_CONFIG__TXD1G_FIFO_RSTB_WIDTH 4
++#define SGMII_CONFIG__TXD1G_FIFO_RSTB_R 11
++#define P5_MUX_CONFIG__P5_MODE_WIDTH 3
++#define CRU_LCPLL2_CONTROL0__POST_RESETB 10
++#define P5_MUX_CONFIG 0x1803f308
++#define P5_MUX_CONFIG__P5_MODE_R 0
++#define P5_MUX_CONFIG__P5_MODE_SGMII 0x0
++#define P5_MUX_CONFIG__P5_MODE_GPHY3 0x4
++#define P4_MUX_CONFIG 0x1803f30c
++#define P4_MUX_CONFIG__P4_MODE_R 0
++#define P4_MUX_CONFIG__P4_MODE_WIDTH 3
++#define P4_MUX_CONFIG__P4_MODE_SGMII 0x0
++#define ChipcommonA_GPIOEvent_BASE 0x078
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_CLR_BASE 0x024
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonA_GPIOInput_BASE 0x060
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOIntMask_BASE 0x074
++#define ChipcommonB_GP_INT_MSK_BASE 0x018
++#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
++#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define ChipcommonA_IntStatus_BASE 0x020
++#define ChipcommonB_GP_INT_DE_BASE 0x010
++#define ChipcommonB_GP_INT_EDGE_BASE 0x014
++#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonA_GPIOIntPolarity_BASE 0x070
++#define CRU_GPIO_CONTROL0_BASE 0x1f1c0
++#define ChipcommonB_GP_AUX_SEL_BASE 0x028
++#define CRU_GPIO_CONTROL7_BASE 0x1f1dc
++#define CRU_GPIO_CONTROL8_BASE 0x1f1e0
++#define ChipcommonB_GP_PAD_RES_BASE 0x034
++#define ChipcommonB_GP_RES_EN_BASE 0x038
++#define ChipcommonA_ChipID 0x18000000
++#define DMAC_pl330_DS 0x18020000
++#define ChipcommonA_GPIOInput 0x18000060
++#define ChipcommonB_GP_DATA_IN 0x18030000
++#define PAXB_0_CLK_CONTROL 0x18012000
++#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
++#define ChipcommonB_MII_Management_Control 0x18032000
++#define ChipcommonB_MII_Management_Command_Data 0x18032004
++#define NAND_nand_flash_REVISION 0x18026000
++#define NAND_direct_read_rd_miss 0x18026f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
++#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
++#define ChipcommonB_PWM_PRESCALE_BASE 0x024
++#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
++#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
++#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
++#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
++#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
++#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
++#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
++#define ChipcommonB_PWMCTL_BASE 0x000
++#define ChipcommonB_rng_CTRL 0x18033000
++#define USB2_IDM_IDM_IO_CONTROL_DIRECT 0x18115408
++#define USB3_IDM_IDM_RESET_CONTROL 0x18104800
++#define CRU_WATCHDOG_PCIE_RESET_STATUS 0x1803f564
++#define CRU_WATCHDOG_PCIE_RESET_STATUS__CCB_WATCHDOG_RESET_EVENT 0
++#define SDIO_eMMCSDXC_SYSADDR 0x18021000
++#define IHOST_M0_IO_CONTROL_DIRECT 0x18100408
++#define ChipcommonA_IntMask_BASE 0x024
++#define ChipcommonA_OTPProg 0x18000018
++#define ChipcommonA_OTPLayout 0x1800001c
++#define ChipcommonA_CoreCapabilities 0x18000004
++#define ChipcommonA_OTPStatus 0x18000010
++#define SDIO_IDM_IO_CONTROL_DIRECT 0x18117408
++#define SDIO_IDM_IO_CONTROL_DIRECT__CMD_COMFLICT_DISABLE 22
++
++
++/* IDM registers */
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x1810c900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x1810c904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x1810c908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810c90c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x1810c914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810c91c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x1810ca00
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_ID 0x1810d914
++#define AXI_PCIE_S2_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
++#define AXI_PCIE_S2_IDM_IDM_INTERRUPT_STATUS 0x1810da00
++#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
++#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
++#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
++#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
++#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
++#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
++#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
++#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
++#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
++#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
++#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
++#define APBV_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18122900
++#define APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18122904
++#define APBV_S0_IDM_IDM_ERROR_LOG_STATUS 0x18122908
++#define APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812290c
++#define APBV_S0_IDM_IDM_ERROR_LOG_ID 0x18122914
++#define APBV_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812291c
++#define APBV_S0_IDM_IDM_INTERRUPT_STATUS 0x18122a00
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
++#define AXIIC_DS_4_IDM_ERROR_LOG_CONTROL 0x18124900
++#define AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE 0x18124904
++#define AXIIC_DS_4_IDM_ERROR_LOG_STATUS 0x18124908
++#define AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB 0x1812490c
++#define AXIIC_DS_4_IDM_ERROR_LOG_ID 0x18124914
++#define AXIIC_DS_4_IDM_ERROR_LOG_FLAGS 0x1812491c
++#define AXIIC_DS_4_IDM_INTERRUPT_STATUS 0x18124a00
++#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18142900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18142904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18142908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1814290c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18142914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1814291c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18142a00
++#define CTF_CONTROL_REG 0x18025c00
++#define CTF_CONTROL_BASE 0x5c00
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP37 0x0
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_TWO_EXP26 0x2
++#define CTF_FLOW_TIMER_CONFIG0__TCP_ESTABLISHED_TIMEBASE_R 2
++#define CTF_FLOW_TIMER_CONFIG0__TCP_FINISHED_TIMEBASE_R 0
++#define CTF_FLOW_TIMER_CONFIG1__TCP_ESTABLISHED_TIMEOUT_R 8
++#define CTF_FLOW_TIMER_CONFIG1__UDP_ESTABLISHED_TIMEOUT_R 16
++#define CTF_FLOW_TIMER_CONFIG1__TCP_FINISHED_TIMEOUT_R 0
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_R 4
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_R 4
++#define CTF_FLOW_TIMER_CONFIG0__UDP_ESTABLISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMER_CONFIG0__TCP_ESTABLISHED_TIMEBASE_TWO_EXP31 0x1
++#define CTF_FLOW_TIMEOUT_CONTROL__FLOW_ENTRY_POINTER_R 5
++
++#define CTF_DRR_CONFIG__MAC_WEIGHT_R 7
++#define CTF_MEM_ACC_CONTROL__RD_WR_N 15
++#define CTF_MEM_ACC_CONTROL__TABLE_SELECT_R 12
++#define CTF_MEM_ACC_CONTROL__ALL_R 0
++
++#define PAE_M0_IDM_IDM_RESET_CONTROL 0x1811f800
++#define PAE_S0_IDM_IDM_RESET_CONTROL 0x18125800
++#define CTF_CONTROL__MEM_INIT 1
++#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
++#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
++#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
++#define CTF_CONTROL__CTF_MODE 0
++#define CTF_CONTROL__FRAGMENTATION_ENABLE 2
++#define CTF_CONTROL__DISABLE_MAC_DA_CHECK 3
++#define CTF_CONTROL__PAE_ENABLED 5
++#define CTF_CONTROL__SPU_ENABLE 6
++#define CTF_BRCM_HDR_CONTROL 0x18025c08
++#define CTF_BRCM_HDR_CONTROL__BRCM_HDR_REASON_CODE_MASK_WIDTH 8
++#define CTF_BRCM_HDR_CONTROL__BRCM_HDR_REASON_CODE_MASK_R 0
++#define SPU_CONTROL 0x1802f000
++#define SPU_CONTROL__OUT_ENDIAN 12
++#define SPU_CONTROL__IN_ENDIAN 11
++#define SPU_CONTROL__SOFT_RST 1
++#define R5_CONFIG0 0x180490d8
++#define R5_CONFIG0__TE_INIT 31
++#define R5_CONFIG0__SYS_PORESET 30
++#define R5_CONFIG0__RESET_N 29
++#define R5_CONFIG0__PARITY_ODD 28
++#define R5_CONFIG0__PADDR_DEBUG31 27
++#define R5_CONFIG0__LOC_ZERO_RAMA 26
++#define R5_CONFIG0__INTERRUPT_ASYNC 25
++#define R5_CONFIG0__INITRAMB 24
++#define R5_CONFIG0__INITRAMA 23
++#define R5_CONFIG0__DEBUG_RESTART 22
++#define R5_CONFIG0__DEBUG_RESET_N 21
++#define R5_CONFIG0__DEBUG_RESET 20
++#define R5_CONFIG0__DEBUG_RESET 20
++#define R5_CONFIG0__DEBUG_NO_CLK_STOP 19
++#define R5_CONFIG0__DEBUG_NIDEN 18
++#define R5_CONFIG0__DEBUG_ENTCM1IF 17
++#define R5_CONFIG0__DEBUG_EN 16
++#define R5_CONFIG0__DEBUG_EDBGRQ 15
++#define R5_CONFIG0__DAP_DAP_TO_DEBUG_APB_EN 14
++#define R5_CONFIG0__CPU_HALT 13
++#define R5_CONFIG0__CFG_ENDIAN 12
++#define R5_CONFIG0__CFG_EE 11
++#define R5_CONFIG0__BTCM_SPLIT 10
++#define R5_CONFIG0__BTCM_SIZE_R 6
++#define R5_CONFIG0__BTCM_SIZE_WIDTH 4
++#define R5_CONFIG0__ATCM_SIZE_R 2
++#define R5_CONFIG0__ATCM_SIZE_WIDTH 4
++#define R5_CONFIG0__RMW_RAM_R 0
++#define R5_CONFIG0__RMW_RAM_WIDTH 2
++
++#define PAE_ECC_DEBUG 0x180490cc
++#define PAE_ECC_DEBUG__ECC_DISABLE 10
++#define PAE_BUFFER_CONFIG 0x18049010
++#define PAE_BUFFER_CONFIG__PAE_MEM_INIT 1
++#define PAE_BUFFER_CONFIG__PAE_SYS_INIT 0
++#define PAE_BUFFER_CONFIG__PAE_MEM_INIT_DONE 2
++#define PAE_BUFFER_ALLOCATION0 0x18049018
++#define PAE_BUFFER_ALLOCATION0 0x18049018
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_END_ADDR_R 16
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_END_ADDR_WIDTH 12
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_START_ADDR_R 0
++#define PAE_BUFFER_ALLOCATION__INTERCEPT_PT_START_ADDR_WIDTH 12
++
++#define PAE_BUFFER_ALLOCATION1 0x1804901c
++#define PAE_BUFFER_BACKPRESSURE_CONFIG0 0x18049020
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XOFF_R 16
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XOFF_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XON_R 0
++#define PAE_BUFFER_BACKPRESSURE_CONFIG__WATERMARK_DEPTH_XON_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_CONFIG1 0x18049024
++#define PAE_BUFFER_CONGESTION_CONFIG 0x18049028
++#define PAE_BUFFER_CONGESTION_CONFIG__ENQ0_STOP_LEVEL_R 0
++#define PAE_BUFFER_CONGESTION_CONFIG__ENQ0_STOP_LEVEL_WIDTH 12
++#define PAE_BUFFER_BACKPRESSURE_MAP0 0x1804902c
++#define PAE_BUFFER_BACKPRESSURE_MAP__INTERCEPT_PT_BACKPRESSURE_CONTRIBUTOR_MASK_R 0
++#define PAE_BUFFER_BACKPRESSURE_MAP__INTERCEPT_PT_BACKPRESSURE_CONTRIBUTOR_MASK_WIDTH 2
++#define PAE_BUFFER_BACKPRESSURE_MAP1 0x18049030
++#define PAE_SCRATCHPAD_ALLOCATION 0x18049014
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_END_ADDR_R 16
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_END_ADDR_WIDTH 12
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_START_ADDR_R 0
++#define PAE_SCRATCHPAD_ALLOCATION__SCRATCHPAD_START_ADDR_WIDTH 12
++#define CTF_DEBUG_CONTROL 0x18025ca0
++#define CTF_DEBUG_CONTROL__DM_FIFO_BP_LEVEL_R 10
++#define CTF_DEBUG_CONTROL__DM_FIFO_BP_LEVEL_WIDTH 8
++#define AXIIC_sata_m0_fn_mod 0x1a051108
++
++#endif /* __SOCREGS_NSP_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/socregs_p7_open.h b/arch/arm/mach-iproc/include/mach/socregs_p7_open.h
+new file mode 100644
+index 0000000..4ffeeba
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_p7_open.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_p7_open.h.patch
new file mode 100644
index 00000000..4a9e13f3
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_socregs_p7_open.h.patch
@@ -0,0 +1,267 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/socregs_p7_open.h
+@@ -0,0 +1,261 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#ifndef __SOCREGS_P7_OPEN_H
++#define __SOCREGS_P7_OPEN_H
++
++#ifdef CONFIG_MACH_GH
++/*
++ * Greyhound only registers
++ */
++#define DMU_PCU_IPROC_CONTROL 0x1800f000
++#define DMU_CRU_RESET_BASE 0x200
++
++#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
++#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
++
++#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
++#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 4
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 14
++#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 22
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
++#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
++
++#endif /* End of Greyhound only registers */
++
++#define ICFG_CHIP_ID_REG 0x18000000
++#define ChipcommonG_UART0_UART_RBR_THR_DLL 0x18020000
++#define ChipcommonG_UART1_UART_RBR_THR_DLL 0x18021000
++
++#define QSPI_mspi_SPCR0_LSB 0x18047200
++#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18047384
++#define QSPI_bspi_registers_REVISION_ID 0x18047000
++#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1804704c
++#define QSPI_raf_START_ADDR 0x18047100
++#define QSPI_raf_CURR_ADDR 0x18047120
++#define QSPI_raf_interrupt_LR_fullness_reached 0x180473a0
++#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180473b8
++#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
++#define CRU_control 0x1800e000
++
++#define NAND_nand_flash_REVISION 0x18046000
++#define NAND_direct_read_rd_miss 0x18046f00
++#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0xf8105408
++
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL 0x18000c8c
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel 1
++#define ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL__iproc_pnor_sel_sw_ovwr 0
++#define ICFG_PNOR_STRAPS 0x18000a5c
++#define ICFG_PNOR_STRAPS__PNOR_SRAM_MW_R 0
++#define PNOR_set_opmode 0x18045018
++#define PNOR_set_opmode__set_mw_R 0
++#define PNOR_direct_cmd 0x18045010
++#define PNOR_direct_cmd__cmd_type_R 21
++
++#define ChipcommonG_tim0_TIM_TIMER1Load 0x18003000
++#define ChipcommonG_tim1_TIM_TIMER1Load 0x18004000
++#define ChipcommonG_tim2_TIM_TIMER1Load 0x18005000
++#define ChipcommonG_tim3_TIM_TIMER1Load 0x18006000
++
++#define ChipcommonS_RNG_CTRL 0x18032000
++
++#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18107900
++#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18107904
++#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18107908
++#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
++#define IHOST_S0_IDM_ERROR_LOG_ID 0x18107914
++#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810791c
++#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18107a00
++
++#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18106900
++#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18106904
++#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18106908
++#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810690c
++#define IHOST_S1_IDM_ERROR_LOG_ID 0x18106914
++#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810691c
++#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18106a00
++
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18108900
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18108904
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x18108908
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x18108914
++#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810891c
++#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x18108a00
++
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL 0x18109900
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE 0x18109904
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS 0x18109908
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID 0x18109914
++#define AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS 0x1810991c
++#define AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS 0x18109a00
++
++#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810a900
++#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810a904
++#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810a908
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
++#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810a914
++#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810a91c
++#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810aa00
++
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18119900
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18119904
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x18119908
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811990c
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x18119914
++#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811991c
++#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x18119a00
++
++#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x1811b900
++#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x1811b904
++#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x1811b908
++#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
++#define SRAM_S0_IDM_ERROR_LOG_ID 0x1811b914
++#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1811b91c
++#define SRAM_S0_IDM_INTERRUPT_STATUS 0x1811ba00
++
++#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18130900
++#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18130904
++#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18130908
++#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813090c
++#define APBX_IDM_IDM_ERROR_LOG_ID 0x18130914
++#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813091c
++#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18130a00
++
++#define APBY_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
++#define APBY_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
++#define APBY_IDM_IDM_ERROR_LOG_STATUS 0x18131908
++#define APBY_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
++#define APBY_IDM_IDM_ERROR_LOG_ID 0x18131914
++#define APBY_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
++#define APBY_IDM_IDM_INTERRUPT_STATUS 0x18131a00
++
++#define APBZ_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
++#define APBZ_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
++#define APBZ_IDM_IDM_ERROR_LOG_STATUS 0x18132908
++#define APBZ_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
++#define APBZ_IDM_IDM_ERROR_LOG_ID 0x18132914
++#define APBZ_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
++#define APBZ_IDM_IDM_INTERRUPT_STATUS 0x18132a00
++
++#define DDR_S1_IDM_ERROR_LOG_CONTROL 0xf8102900
++#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0xf8102904
++#define DDR_S1_IDM_ERROR_LOG_STATUS 0xf8102908
++#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0xf810290c
++#define DDR_S1_IDM_ERROR_LOG_ID 0xf8102914
++#define DDR_S1_IDM_ERROR_LOG_FLAGS 0xf810291c
++#define DDR_S1_IDM_INTERRUPT_STATUS 0xf8102a00
++
++#define DDR_S2_IDM_ERROR_LOG_CONTROL 0xf8103900
++#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0xf8103904
++#define DDR_S2_IDM_ERROR_LOG_STATUS 0xf8103908
++#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0xf810390c
++#define DDR_S2_IDM_ERROR_LOG_ID 0xf8103914
++#define DDR_S2_IDM_ERROR_LOG_FLAGS 0xf810391c
++#define DDR_S2_IDM_INTERRUPT_STATUS 0xf8103a00
++
++#define ROM_S0_IDM_ERROR_LOG_CONTROL 0xf8104900
++#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0xf8104904
++#define ROM_S0_IDM_ERROR_LOG_STATUS 0xf8104908
++#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0xf810490c
++#define ROM_S0_IDM_ERROR_LOG_ID 0xf8104914
++#define ROM_S0_IDM_ERROR_LOG_FLAGS 0xf810491c
++#define ROM_S0_IDM_INTERRUPT_STATUS 0xf8104a00
++
++#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0xf8105900
++#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0xf8105904
++#define NAND_IDM_IDM_ERROR_LOG_STATUS 0xf8105908
++#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0xf810590c
++#define NAND_IDM_IDM_ERROR_LOG_ID 0xf8105914
++#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0xf810591c
++#define NAND_IDM_IDM_INTERRUPT_STATUS 0xf8105a00
++
++#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0xf8106900
++#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0xf8106904
++#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0xf8106908
++#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0xf810690c
++#define QSPI_IDM_IDM_ERROR_LOG_ID 0xf8106914
++#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0xf810691c
++#define QSPI_IDM_IDM_INTERRUPT_STATUS 0xf8106a00
++
++#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18120900
++#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18120904
++#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18120908
++#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
++#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18120914
++#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1812091c
++#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18120a00
++
++#define AXIIC_DS_1_IDM_ERROR_LOG_CONTROL 0x18121900
++#define AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE 0x18121904
++#define AXIIC_DS_1_IDM_ERROR_LOG_STATUS 0x18121908
++#define AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
++#define AXIIC_DS_1_IDM_ERROR_LOG_ID 0x18121914
++#define AXIIC_DS_1_IDM_ERROR_LOG_FLAGS 0x1812191c
++#define AXIIC_DS_1_IDM_INTERRUPT_STATUS 0x18121a00
++
++#define AXIIC_DS_2_IDM_ERROR_LOG_CONTROL 0x1811d900
++#define AXIIC_DS_2_IDM_ERROR_LOG_COMPLETE 0x1811d904
++#define AXIIC_DS_2_IDM_ERROR_LOG_STATUS 0x1811d908
++#define AXIIC_DS_2_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
++#define AXIIC_DS_2_IDM_ERROR_LOG_ID 0x1811d914
++#define AXIIC_DS_2_IDM_ERROR_LOG_FLAGS 0x1811d91c
++#define AXIIC_DS_2_IDM_INTERRUPT_STATUS 0x1811da00
++
++#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x1811e900
++#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x1811e904
++#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x1811e908
++#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1811e90c
++#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x1811e914
++#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1811e91c
++#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x1811ea00
++
++/* GPIO */
++#define ChipcommonG_GP_DATA_IN 0x1800a000
++#define ChipcommonG_GP_DATA_IN_BASE 0x000
++#define ChipcommonG_GP_DATA_OUT_BASE 0x004
++#define ChipcommonG_GP_OUT_EN_BASE 0x008
++#define ChipcommonG_GP_INT_TYPE_BASE 0x00c
++#define ChipcommonG_GP_INT_DE_BASE 0x010
++#define ChipcommonG_GP_INT_EDGE_BASE 0x014
++#define ChipcommonG_GP_INT_MSK_BASE 0x018
++#define ChipcommonG_GP_INT_STAT_BASE 0x01c
++#define ChipcommonG_GP_INT_MSTAT_BASE 0x020
++#define ChipcommonG_GP_INT_CLR_BASE 0x024
++#define ChipcommonG_GP_AUX_SEL_BASE 0x028
++#define ChipcommonG_GP_INIT_VAL_BASE 0x030
++#define ChipcommonG_GP_PAD_RES_BASE 0x034
++#define ChipcommonG_GP_RES_EN_BASE 0x038
++#define ChipcommonG_GP_TEST_INPUT_BASE 0x03c
++#define ChipcommonG_GP_TEST_OUTPUT_BASE 0x040
++#define ChipcommonG_GP_TEST_ENABLE_BASE 0x044
++#define ChipcommonG_GP_PRB_ENABLE_BASE 0x048
++#define ChipcommonG_GP_PRB_OE_BASE 0x04c
++
++/* Watchdog */
++#define ChipcommonG_WDT_WDOGLOAD 0x18009000
++#define DMU_PCU_CRU_RESET_REASON 0x1800f014
++#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
++
++#endif /* __SOCREGS_P7_OPEN_H */
+diff --git a/arch/arm/mach-iproc/include/mach/vmalloc.h b/arch/arm/mach-iproc/include/mach/vmalloc.h
+new file mode 100644
+index 0000000..0611b30
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_vmalloc.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_vmalloc.h.patch
new file mode 100644
index 00000000..94925e96
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_include_mach_vmalloc.h.patch
@@ -0,0 +1,30 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/include/mach/vmalloc.h
+@@ -0,0 +1,24 @@
++/*
++ * arch/arm/mach-iproc/include/mach/vmalloc.h
++ *
++ * Copyright (C) 2014
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#ifdef __ASSEMBLY__
++#define VMALLOC_END 0xff000000
++#else
++#define VMALLOC_END 0xff000000UL
++#endif
+diff --git a/arch/arm/mach-iproc/io_map.c b/arch/arm/mach-iproc/io_map.c
+new file mode 100644
+index 0000000..cbea0a2
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_io_map.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_io_map.c.patch
new file mode 100644
index 00000000..8a1283a1
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_io_map.c.patch
@@ -0,0 +1,63 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/io_map.c
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++#include
++
++#define IO_DESC(va, sz) { .virtual = va, \
++ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
++ .length = sz, \
++ .type = MT_DEVICE }
++
++
++static struct map_desc northstar_io_desc[] __initdata =
++{
++ IO_DESC(IO_CORE_IDM_VA,IO_CORE_IDM_SIZE),
++ IO_DESC(IO_ARMCORE_VA, IO_ARMCORE_SIZE),
++#ifdef CONFIG_MACH_IPROC_P7
++ IO_DESC(IO_SMAU_IDM_VA, IO_SMAU_IDM_SIZE),
++#endif /* !CONFIG_MACH_IPROC_P7 */
++};
++
++extern void __init iproc_map_io(void);
++
++void __init northstar_map_io(void)
++{
++ iotable_init(northstar_io_desc, ARRAY_SIZE(northstar_io_desc));
++}
+diff --git a/arch/arm/mach-iproc/localtimer.c b/arch/arm/mach-iproc/localtimer.c
+new file mode 100644
+index 0000000..b139cac
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_localtimer.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_localtimer.c.patch
new file mode 100644
index 00000000..5294b538
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_localtimer.c.patch
@@ -0,0 +1,33 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/localtimer.c
+@@ -0,0 +1,27 @@
++/*
++ * linux/arch/arm/mach-iproc/localtimer.c
++ *
++ * Copyright (C) 2002 ARM Ltd.
++ * All Rights Reserved
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include
++#include
++#include
++
++#include
++#include
++#include
++
++/*
++ * Setup the local clock events for a CPU.
++ */
++int __cpuinit local_timer_setup(struct clock_event_device *evt)
++{
++ evt->irq = IRQ_LOCALTIMER;
++ twd_timer_setup(evt);
++ return 0;
++}
+diff --git a/arch/arm/mach-iproc/northstar.c b/arch/arm/mach-iproc/northstar.c
+new file mode 100644
+index 0000000..dc23a34
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.c.patch
new file mode 100644
index 00000000..9ed0bde4
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.c.patch
@@ -0,0 +1,172 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar.c
+@@ -0,0 +1,166 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++
++
++
++
++#define TIMER_LOAD 0x00
++#define TIMER_VALUE 0x04
++#define TIMER_CTRL 0x08
++#define TIMER_CTRL_PRESC_SHFT (8)
++#define TIMER_CTRL_IE (1 << 2)
++#define TIMER_CTRL_PERIODIC (1 << 1)
++#define TIMER_CTRL_ENABLE (1 << 0)
++
++#define TIMER_INTCLR 0x0c
++#define IPROC_L2CC_REG_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_L2CC_REG_BASE)
++
++extern void __iomem *twd_base;
++extern void iproc_clocksource_init(void __iomem *);
++extern void iproc_clockevents_init(void __iomem *, unsigned int);
++extern void __init northstar_dmu_init(struct clk *clk_ref);
++extern void __init iproc_cru_init(struct clk *clk_ref);
++extern void iproc_enable_data_prefetch_aborts(void);
++extern void northstar_restart(char mode, const char *cmd);
++
++static void
++northstar_poweroff(void)
++{
++ while(1)
++ ;
++}
++
++
++#ifdef CONFIG_CACHE_L2X0
++static void __init northstar_l2x0_init(void)
++{
++ void __iomem *l2cache_base = IOMEM(IPROC_L2CC_REG_VA);
++ void __iomem *cca = IOMEM(IPROC_CCA_CORE_REG_VA);
++ unsigned int chipid = (readl(cca) & 0x0000ffff);
++
++ /*
++ * 16KB way size, 16-way associativity
++ */
++#if defined(CONFIG_MACH_NS)
++ if (chipid >= 0xcf19 /* costar */) {
++#ifdef CONFIG_BCM_IPROC_CA9_PREFETCH
++ /* inst/data prefetch & Early BRESP & Fill line zero (also need A9) */
++ l2x0_init(l2cache_base, (0x0A150000 | 0x3 << 28 | 0x1 << 30 | 0x1 << 0), ~(0x000F0000));
++#else
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#endif /* CONFIG_BCM_IPROC_CA9_PREFETCH */
++ } else { /* northstar */
++ l2x0_init(l2cache_base, 0x0A130000, ~(0x000F0000));
++ }
++#elif (defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54))
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#elif defined(CONFIG_MACH_HR2)
++ l2x0_init(l2cache_base, 0x0A120000, ~(0x000F0000));
++#elif defined(CONFIG_MACH_NSP)
++#ifdef CONFIG_BCM_IPROC_CA9_PREFETCH
++ /* inst/data prefetch & Early BRESP & Fill line zero (also need A9) */
++ l2x0_init(l2cache_base, (0x0A150000 | 0x3 << 28 | 0x1 << 30 | 0x1 << 0), ~(0x000F0000));
++#else
++ l2x0_init(l2cache_base, 0x0A150000, ~(0x000F0000));
++#endif /* CONFIG_BCM_IPROC_CA9_PREFETCH */
++#elif defined(CONFIG_MACH_IPROC_P7)
++ l2x0_init(l2cache_base, 0x0A130000, ~(0x000F0000));
++#endif
++}
++#endif
++
++static int __init northstar_init(void)
++{
++#ifdef CONFIG_PM
++ pm_power_off = northstar_poweroff;
++#endif
++ arm_pm_restart = northstar_restart;
++
++#ifdef CONFIG_MACH_CYGNUS
++#else
++#ifdef CONFIG_CACHE_L2X0
++ northstar_l2x0_init();
++#endif
++#endif /* END of CYGNUS */
++
++ return 0;
++}
++early_initcall(northstar_init);
++
++/*
++ * CPU global and MPCORE Per CPU local timer
++ */
++#define GLB_TIMER IOMEM(IPROC_PERIPH_GLB_TIM_REG_VA);
++#define PVT_TIMER IOMEM(IPROC_PERIPH_PVT_TIM_REG_VA);
++
++void __iomem *gtimer_va_base = GLB_TIMER;
++void __iomem *ptimer_va_base = PVT_TIMER;
++
++/*
++ * Set up the clock source and clock events devices
++ */
++void __init northstar_timer_init(struct clk *clk_ref)
++{
++ int err;
++
++ /*
++ * Setup DMU and CRU early
++ */
++ northstar_dmu_init(clk_ref);
++ iproc_cru_init(clk_ref);
++
++ /*
++ * Initialise to a known state (all timers off)
++ */
++ writel(0, ptimer_va_base + TIMER_CTRL);
++ writel(0, gtimer_va_base + TIMER_CTRL);
++
++#ifdef CONFIG_HAVE_ARM_TWD
++ /*
++ * Setup the local clock events for a CPU.
++ */
++ twd_base = IO_ADDRESS(IPROC_PERIPH_PVT_TIM_REG_VA);
++#endif
++
++ iproc_clocksource_init(gtimer_va_base);
++ iproc_clockevents_init(gtimer_va_base, BCM_INT_ID_PPI11);
++
++ iproc_enable_data_prefetch_aborts();
++}
+diff --git a/arch/arm/mach-iproc/northstar.h b/arch/arm/mach-iproc/northstar.h
+new file mode 100644
+index 0000000..09b3ccc
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.h.patch
new file mode 100644
index 00000000..eb6fa038
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar.h.patch
@@ -0,0 +1,33 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __NORTHSTAR_H
++#define __NORTHSTAR_H
++
++#include
++#include
++
++extern struct platform_device northstar_ipc_device;
++
++void __init northstar_map_io(void);
++
++#endif /* __NORTHSTAR_H */
+diff --git a/arch/arm/mach-iproc/northstar_dmu.c b/arch/arm/mach-iproc/northstar_dmu.c
+new file mode 100644
+index 0000000..f95b0e3
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar_dmu.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar_dmu.c.patch
new file mode 100644
index 00000000..02de3943
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_northstar_dmu.c.patch
@@ -0,0 +1,808 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/northstar_dmu.c
+@@ -0,0 +1,802 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include
++#include
++
++#include
++#include
++#include
++#include
++
++#define IPROC_DMU_BASE_PA IPROC_DMU_BASE_REG
++//#define IPROC_DMU_BASE_VA HW_IO_PHYS_TO_VIRT(IPROC_DMU_BASE_PA)
++
++static struct resource dmu_regs = {
++ .name = "dmu_regs",
++ .start = (resource_size_t) IOMEM(IPROC_DMU_BASE_VA),
++ .end = (resource_size_t) (IOMEM(IPROC_DMU_BASE_VA) + SZ_4K - 1),
++ .flags = IORESOURCE_MEM,
++};
++
++/*
++ * Clock management scheme is a provisional implementation
++ * only intended to retreive the pre-set frequencies for each
++ * of the clocks.
++ * Better handling of post-dividers and fractional part of
++ * feedbeck dividers need to be added.
++ * Need to understand what diagnostics from CRU registers could
++ * be handy, and export that via a sysfs interface.
++ */
++
++/*
++ * The CRU contains two similar PLLs: LCPLL and GENPLL,
++ * both with several output channels divided from the PLL
++ * output
++ */
++
++/*
++ * Get PLL running status and update output frequency
++ */
++static int lcpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv, ndiv_int, ndiv_frac;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* read status register */
++ reg = readl(clk->regs_base + 0x10);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if ((reg & (1 << 12)) == 0) {
++ clk->rate = 0;
++ }
++
++ /* Update PLL frequency */
++
++ /* control1 register */
++ reg = readl(clk->regs_base + 0x04);
++
++ /* feedback divider integer and fraction parts */
++ pdiv = (reg >> 28) & 7 ;
++ ndiv_int = (reg >> 20) & 0xff;
++ ndiv_frac = reg & ((1<<20)-1);
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv ;
++
++ x = x * ((u64) ndiv_int << 20 | ndiv_frac) ;
++
++ clk->rate = x >> 20 ;
++
++ return 0;
++}
++
++static const struct clk_ops lcpll_ops = {
++ .status = lcpll_status,
++};
++
++static int lcpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++ BUG_ON(base == NULL);
++
++ /* enable bit is in enableb_ch[] inversed */
++ enable = ((readl(base + 0) >> 6) & 7) ^ 7;
++
++ if (0 == (enable & (1 << clk->chan))) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* get divider */
++ reg = readl(base + 0x08);
++
++ mdiv = 0xff & (reg >> ((0x3^clk->chan) << 3));
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("LCPLL[%d] mdiv=%u rate=%lu\n", clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = (clk->parent->rate / mdiv);
++ return 0;
++}
++
++
++static const struct clk_ops lcpll_chan_ops = {
++ .status = lcpll_chan_status,
++};
++
++/*
++ * LCPLL has 4 output channels
++ */
++static struct clk clk_lcpll = {
++ .ops = &lcpll_ops,
++ .name = "LCPLL",
++ .type = CLK_PLL,
++ .chan = 4,
++};
++
++/*
++ * LCPLL output clocks -
++ * chan 0 - PCIe ref clock, should be 1 GHz,
++ * chan 1 - SDIO clock, e.g. 200 MHz,
++ * chan 2 - DDR clock, typical 166.667 MHz for DDR667,
++ * chan 3 - Unknown
++ */
++
++static struct clk clk_lcpll_ch[4] = {
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = &lcpll_chan_ops,
++ .parent = &clk_lcpll,
++ .type = CLK_DIV,
++ .name = "lcpll_ch3",
++ .chan = 3,
++ },
++};
++
++/*
++ * Get PLL running status and update output frequency
++ */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++static int genpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv;
++ unsigned ndiv_int;
++ unsigned ndiv_frac;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* Offset of the PLL status register */
++ reg = readl(clk->regs_base + 0x20);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if((reg & (1 << 12)) == 0) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* Update PLL frequency */
++
++ /* get PLL feedback divider values from control5 */
++ reg = readl(clk->regs_base + 0x14);
++
++ /* feedback divider integer and fraction parts */
++ ndiv_int = reg >> 20;
++ ndiv_frac = reg & ((1 << 20) - 1);
++
++ /* get pdiv */
++ reg = readl(clk->regs_base + 0x18);
++ pdiv = (reg >> 24) & 7;
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv;
++
++ x = x * ((u64) ndiv_int << 20 | ndiv_frac);
++
++ clk->rate = x >> 20;
++
++ return 0;
++}
++#endif
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++static int genpll_status(struct clk * clk)
++{
++ u32 reg;
++ u64 x;
++ unsigned pdiv;
++ unsigned ndiv_int;
++
++ if (clk->type != CLK_PLL)
++ return -EINVAL;
++
++ /* Offset of the PLL status register */
++ reg = readl(clk->regs_base + 0x18);
++
++ /* bit 12 is "lock" signal, has to be "1" for proper PLL operation */
++ if((reg & (1 << IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK)) == 0) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* Update PLL frequency */
++
++ /* get PLL feedback divider values from control5 */
++ reg = readl(clk->regs_base + 0x04);
++
++ /* feedback divider integer and fraction parts */
++ ndiv_int = (reg >> IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R) & ((1 << IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH) -1);
++
++ /* get pdiv */
++ pdiv = (reg >> IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R) & ((1 << IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH) -1);
++
++ if (pdiv == 0)
++ return -EIO;
++
++ x = clk->parent->rate / pdiv;
++
++ x = x * ((u64) ndiv_int);
++
++ clk->rate = x;
++
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_KT2)
++static int genpll_status(struct clk * clk)
++{
++ clk->rate = 2475000000;
++
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS) //chandra: todo
++static int genpll_status(struct clk * clk)
++{
++
++}
++#endif
++static const struct clk_ops genpll_ops = {
++ .status = genpll_status,
++};
++
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++static int genpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv;
++ unsigned off, shift;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++
++ BUG_ON (base == NULL);
++
++ /* enable bit is in enableb_ch[0..5] inversed */
++ enable = ((readl(base + 0x04) >> 12) & 0x3f) ^ 0x3f ;
++
++ if (0 == (enable & (1 << clk->chan))) {
++ clk->rate = 0;
++ return -EIO;
++ }
++
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ off = 0x18; shift = 16;
++ break;
++
++ case 1:
++ off = 0x18; shift = 8;
++ break;
++
++ case 2:
++ off = 0x18; shift = 0;
++ break;
++
++ case 3:
++ off = 0x1c; shift = 16;
++ break;
++
++ case 4:
++ off = 0x1c; shift = 8;
++ break;
++
++ case 5:
++ off = 0x1c; shift = 16; /* Set to AXI clock */
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ off = shift = 0; /* fend off warnings */
++ }
++
++ reg = readl(base + off);
++
++ mdiv = 0xff & (reg >> shift);
++ /* APB clock is always AXIclock/4 */
++ if(clk->chan == 5)
++ mdiv = mdiv * 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++static int genpll_chan_status(struct clk * clk)
++{
++ void * __iomem base;
++ u32 reg;
++ unsigned enable;
++ unsigned mdiv = 0;
++ unsigned off, shift;
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* Register address is only stored in PLL structure */
++ base = clk->parent->regs_base;
++
++ BUG_ON (base == NULL);
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ off = 0x04; shift = IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R;
++ break;
++
++ case 1:
++ off = 0x04; shift = IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R;
++ break;
++
++ case 2:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R;
++ break;
++
++ case 3:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R;
++ break;
++
++ case 4:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R;
++ break;
++
++ case 5:
++ off = 0x08; shift = IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R;
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ off = shift = 0; /* fend off warnings */
++ }
++
++ reg = readl(base + off);
++
++ mdiv = 0xff & (reg >> shift);
++ if(clk->chan == 5)
++ mdiv *= 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_KT2)
++static int genpll_chan_status(struct clk * clk)
++{
++ unsigned mdiv = 0;
++
++
++ if (clk->parent == NULL || clk->type != CLK_DIV)
++ return -EINVAL;
++
++ /* GENPLL has the 6 channels spread over two regs */
++ switch (clk->chan) {
++ case 0:
++ mdiv = 10;
++ break;
++
++ case 3:
++ mdiv = 5;
++ break;
++
++ case 4:
++ mdiv = 10;
++ break;
++
++ case 5:
++ mdiv = 5;
++ break;
++
++ default:
++ BUG_ON(clk->chan);
++ }
++
++ if(clk->chan == 5)
++ mdiv *= 4;
++
++ /* when divisor is 0, it behaves as max+1 */
++ if (mdiv == 0)
++ mdiv = 1 << 8;
++
++ printk("GENPLL[%d] mdiv=%u rate=%lu\n",
++ clk->chan, mdiv, clk->parent->rate);
++
++ clk->rate = clk->parent->rate / mdiv;
++ return 0;
++}
++#endif
++
++#if defined(CONFIG_MACH_CYGNUS) //chandra: todo
++static int genpll_chan_status(struct clk * clk)
++{
++
++}
++#endif
++
++static const struct clk_ops genpll_chan_ops = {
++ .status = genpll_chan_status,
++};
++
++
++/*
++ * GENPLL has 6 output channels
++ */
++static struct clk clk_genpll = {
++ .ops = &genpll_ops,
++ .name = "GENPLL",
++ .type = CLK_PLL,
++ .chan = 6,
++};
++
++/*
++ * chan 0 - Ethernet switch and MAC, RGMII, need 250 MHz
++ * chan 1 - Ethernet switch slow clock, 150 Mhz
++ * chan 2 - USB PHY clock, need 30 MHz
++ * chan 3 - iProc N MHz clock, set from OTP
++ * chan 4 - iProc N/2 MHz clock, set from OTP
++ * chan 5 - iProc N/4 MHz clock, set from OTP
++ *
++ * To Do: which clock goes to MPCORE PERIPHCLOCK?
++ */
++#ifdef CONFIG_MACH_CYGNUS_EMULATION //chandra:emul
++ static struct clk clk_genpll_ch[6] = {
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .type = CLK_DIV,
++ .name = "genpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = 992000,
++ .type = CLK_DIV,
++ .name = "genpll_ch3",
++ .chan = 3,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = 644800,
++ .type = CLK_DIV,
++ .name = "genpll_ch4",
++ .chan = 4,
++ },
++ {
++ .ops = NULL,
++ .parent = NULL,
++ .rate = CONFIG_CYGNUS_EMULATION_CLK_125,//25000000,
++ .type = CLK_DIV,
++ .name = "genpll_ch5",
++ .chan = 5,
++ },
++ };
++
++#else
++static struct clk clk_genpll_ch[6] = {
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch0",
++ .chan = 0,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch1",
++ .chan = 1,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch2",
++ .chan = 2,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch3",
++ .chan = 3,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch4",
++ .chan = 4,
++ },
++ {
++ .ops = &genpll_chan_ops,
++ .parent = &clk_genpll,
++ .type = CLK_DIV,
++ .name = "genpll_ch5",
++ .chan = 5,
++ },
++};
++#endif
++
++/*
++ * This table is used to locate clock sources
++ * from device drivers
++ */
++
++static struct clk_lookup ns_clk_lookups[] = {
++ {
++ .dev_id = "pcie",
++ .con_id = "c_clk100",
++ .clk = &clk_lcpll_ch[0],
++ },{
++ .dev_id = "sdio",
++ .con_id = "c_clk200",
++ .clk = &clk_lcpll_ch[1],
++ },{
++ .dev_id = "ddr",
++ .con_id = "c_clk400",
++ .clk = &clk_lcpll_ch[2],
++ },{
++ .dev_id = "tbd",
++ .con_id = "c_clk120",
++ .clk = &clk_lcpll_ch[3],
++ },{
++ .dev_id = "en_phy",
++ .con_id = "c_clk250",
++ .clk = &clk_genpll_ch[0],
++ },{
++ .dev_id = "en",
++ .con_id = "c_clk150",
++ .clk = &clk_genpll_ch[1],
++ },{
++ .dev_id = "usb_phy",
++ .con_id = "c_clk30",
++ .clk = &clk_genpll_ch[2],
++ },{
++ .dev_id = "iproc_fast",
++ .con_id = "c_clk500",
++ .clk = &clk_genpll_ch[3],
++ },{
++ .dev_id = "iproc_med",
++ .con_id = "c_clk250",
++ .clk = &clk_genpll_ch[4],
++ },{
++ .dev_id = "iproc_slow",
++ .con_id = "c_clk125",
++ .clk = &clk_genpll_ch[5],
++ }
++#ifdef CONFIG_ARM_AMBA
++ ,{
++ .con_id = "apb_pclk",
++ .clk = &clk_genpll_ch[5],
++ }
++#if defined (CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
++ ,{
++ .dev_id = "sp805-wdt",
++ .clk = &clk_genpll_ch[5],
++ }
++#endif
++#endif
++};
++
++/*
++ * Install above clocks into clock lookup table
++ * and initialize the register base address for each
++*/
++static void __init northstar_clocks_init(void *__iomem cru_regs_base,
++ struct clk * clk_ref)
++{
++ /*
++ * Registers are already mapped with the rest of DMU block
++ * Update register base address
++ */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ clk_lcpll.regs_base = cru_regs_base + 0x00 ;
++ clk_genpll.regs_base = cru_regs_base + 0x40 ;
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++ clk_lcpll.regs_base = cru_regs_base + 0x1c ;
++ clk_genpll.regs_base = cru_regs_base + 0x00 ;
++#endif
++
++ /* Set parent as reference ckock */
++ clk_lcpll.parent = clk_ref;
++ clk_genpll.parent = clk_ref;
++
++ /* Install clock sources into the lookup table */
++ clkdev_add_table(ns_clk_lookups,
++ ARRAY_SIZE(ns_clk_lookups));
++}
++
++void __init northstar_dmu_init(struct clk *clk_ref)
++{
++ void * __iomem reg_base;
++
++ if (IS_ERR_OR_NULL(clk_ref )) {
++ printk(KERN_ERR "CRU no clock source - skip init\n");
++ return;
++ }
++
++ BUG_ON (request_resource(&iomem_resource, &dmu_regs));
++
++ /* DMU regs are mapped as part of the fixed mapping with CCA+CCB */
++ reg_base = (void * __iomem) dmu_regs.start;
++
++ BUG_ON (IS_ERR_OR_NULL(reg_base));
++
++ /* Initialize clocks */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ northstar_clocks_init(reg_base + 0x100, clk_ref); /* CRU LCPLL control0 */
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || \
++ defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || \
++ defined(CONFIG_MACH_ACCTON_AS4610_54)
++ northstar_clocks_init(reg_base + 0xc00, clk_ref); /* IPROC_WRAP_GEN_PLL_CTRL0 */
++#elif defined(CONFIG_MACH_KT2)
++ northstar_clocks_init(NULL, clk_ref); /* IPROC_WRAP_GEN_PLL_CTRL0 */
++#endif
++}
++
++void (*cpld_system_reset)(void);
++EXPORT_SYMBOL(cpld_system_reset); /* used in dni_3448p_cpld.c module */
++
++/*
++ * Reset the system
++ */
++void northstar_restart(char mode, const char *cmd)
++{
++ void * __iomem reg_addr;
++ u32 reg;
++
++ if (cpld_system_reset) {
++ printk( KERN_INFO "Using CPLD reset\n");
++ cpld_system_reset();
++ }
++
++ /* CRU_RESET register */
++#if (defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP))
++ reg_addr = (void * __iomem) dmu_regs.start + 0x184 ;
++ /* set iproc_reset_n to 0, it may come back or not ... TBD */
++ reg = readl_relaxed(reg_addr);
++ reg &= ~((u32) 1 << 1);
++ writel_relaxed(reg, reg_addr);
++#elif defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_HR2) || defined(CONFIG_MACH_KT2) \
++ || defined(CONFIG_MACH_GH) || defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++ reg_addr = (void * __iomem) dmu_regs.start + DMU_CRU_RESET_BASE ;
++ /* Reset iproc and cmicd/switch */
++ writel_relaxed(0, reg_addr);
++#endif
++
++
++}
++
++
++
++
++
++
++
++void northstar_clocks_show( void )
++{
++ unsigned i;
++// struct clk * clk ;
++
++ printk("=========== CLOCKS =================\n");
++
++ printk( "DMU Clocks:\n" );
++ for (i = 0; i < ARRAY_SIZE( ns_clk_lookups); i++) {
++ printk("%s, %s: (%s) %lu\n",
++ ns_clk_lookups[i].con_id,
++ ns_clk_lookups[i].dev_id,
++ ns_clk_lookups[i].clk->name,
++ clk_get_rate( ns_clk_lookups[i].clk));
++ }
++ printk( "DMU Clocks# %u\n", i );
++}
+diff --git a/arch/arm/mach-iproc/pm.c b/arch/arm/mach-iproc/pm.c
+new file mode 100644
+index 0000000..ca2eef4
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_pm.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_pm.c.patch
new file mode 100644
index 00000000..8c902f15
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mach-iproc_pm.c.patch
@@ -0,0 +1,45 @@
+--- /dev/null
++++ b/arch/arm/mach-iproc/pm.c
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++
++int iproc_arm_cpu_do_idle(void)
++{
++ return cpu_do_idle();
++}
++EXPORT_SYMBOL(iproc_arm_cpu_do_idle);
++
++inline void iproc_arm_cpu_resume(void)
++{
++ cpu_resume();
++}
++EXPORT_SYMBOL(iproc_arm_cpu_resume);
++
++int iproc_arm_cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
++{
++ return cpu_suspend(arg, fn);
++}
++EXPORT_SYMBOL(iproc_arm_cpu_suspend);
+diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
+index ffb9d6a..6ec5258 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_Kconfig.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_Kconfig.patch
new file mode 100644
index 00000000..d29ac419
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_Kconfig.patch
@@ -0,0 +1,14 @@
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -821,7 +821,8 @@ config CACHE_L2X0
+ REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
+ ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
+- ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
++ ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK || \
++ ARCH_IPROC
+ default y
+ select OUTER_CACHE
+ select OUTER_CACHE_SYNC
+diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
+index cc3f35d..ee3a9f1 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_init.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_init.c.patch
new file mode 100644
index 00000000..0be49e07
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_init.c.patch
@@ -0,0 +1,13 @@
+--- a/arch/arm/mm/init.c
++++ b/arch/arm/mm/init.c
+@@ -406,8 +406,6 @@ void __init bootmem_init(void)
+ */
+ arm_bootmem_free(min, max_low, max_high);
+
+- high_memory = __va(((phys_addr_t)max_low << PAGE_SHIFT) - 1) + 1;
+-
+ /*
+ * This doesn't seem to be used by the Linux memory manager any
+ * more, but is used by ll_rw_block. If we can get rid of it, we
+diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
+index bdb248c..0bf7e90 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_ioremap.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_ioremap.c.patch
new file mode 100644
index 00000000..c3e4590f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_ioremap.c.patch
@@ -0,0 +1,131 @@
+--- a/arch/arm/mm/ioremap.c
++++ b/arch/arm/mm/ioremap.c
+@@ -36,12 +36,6 @@
+ #include
+ #include "mm.h"
+
+-/*
+- * Used by ioremap() and iounmap() code to mark (super)section-mapped
+- * I/O regions in vm_struct->flags field.
+- */
+-#define VM_ARM_SECTION_MAPPING 0x80000000
+-
+ int ioremap_page(unsigned long virt, unsigned long phys,
+ const struct mem_type *mtype)
+ {
+@@ -201,12 +195,6 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
+ if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
+ return NULL;
+
+- /*
+- * Don't allow RAM to be mapped - this causes problems with ARMv6+
+- */
+- if (WARN_ON(pfn_valid(pfn)))
+- return NULL;
+-
+ type = get_mem_type(mtype);
+ if (!type)
+ return NULL;
+@@ -216,6 +204,38 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
+ */
+ size = PAGE_ALIGN(offset + size);
+
++ /*
++ * Try to reuse one of the static mapping whenever possible.
++ */
++ read_lock(&vmlist_lock);
++ for (area = vmlist; area; area = area->next) {
++ if (!size || (sizeof(phys_addr_t) == 4 && pfn >= 0x100000))
++ break;
++ if (!(area->flags & VM_ARM_STATIC_MAPPING))
++ continue;
++ if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
++ continue;
++ if (__phys_to_pfn(area->phys_addr) > pfn ||
++ __pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
++ continue;
++ /* we can drop the lock here as we know *area is static */
++ read_unlock(&vmlist_lock);
++ addr = (unsigned long)area->addr;
++ addr += __pfn_to_phys(pfn) - area->phys_addr;
++ return (void __iomem *) (offset + addr);
++ }
++ read_unlock(&vmlist_lock);
++
++ /*
++ * Don't allow RAM to be mapped - this causes problems with ARMv6+
++ */
++#ifdef CONFIG_ARCH_IPROC
++#warning "ioremap test for remapping RAM has been disabled for IPROC"
++#else
++ if (WARN_ON(pfn_valid(pfn)))
++ return NULL;
++#endif
++
+ area = get_vm_area_caller(size, VM_IOREMAP, caller);
+ if (!area)
+ return NULL;
+@@ -313,29 +333,43 @@ __arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
+ void __iounmap(volatile void __iomem *io_addr)
+ {
+ void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
+-#ifndef CONFIG_SMP
+- struct vm_struct **p, *tmp;
++ struct vm_struct *vm;
+
+- /*
+- * If this is a section based mapping we need to handle it
+- * specially as the VM subsystem does not know how to handle
+- * such a beast. We need the lock here b/c we need to clear
+- * all the mappings before the area can be reclaimed
+- * by someone else.
+- */
+- write_lock(&vmlist_lock);
+- for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
+- if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
+- if (tmp->flags & VM_ARM_SECTION_MAPPING) {
+- unmap_area_sections((unsigned long)tmp->addr,
+- tmp->size);
+- }
++ read_lock(&vmlist_lock);
++ for (vm = vmlist; vm; vm = vm->next) {
++ if (vm->addr > addr)
++ break;
++ if (!(vm->flags & VM_IOREMAP))
++ continue;
++ /* If this is a static mapping we must leave it alone */
++ if ((vm->flags & VM_ARM_STATIC_MAPPING) &&
++ (vm->addr <= addr) && (vm->addr + vm->size > addr)) {
++ read_unlock(&vmlist_lock);
++ return;
++ }
++#if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE)
++ /*
++ * If this is a section based mapping we need to handle it
++ * specially as the VM subsystem does not know how to handle
++ * such a beast.
++ */
++ if ((vm->addr == addr) &&
++ (vm->flags & VM_ARM_SECTION_MAPPING)) {
++ unmap_area_sections((unsigned long)vm->addr, vm->size);
+ break;
+ }
+- }
+- write_unlock(&vmlist_lock);
+ #endif
++ }
++ read_unlock(&vmlist_lock);
+
+ vunmap(addr);
+ }
++
++void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
++
++void __arm_iounmap(volatile void __iomem *io_addr)
++{
++ arch_iounmap(io_addr);
++}
+ EXPORT_SYMBOL(__iounmap);
++EXPORT_SYMBOL(__arm_iounmap);
+diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
+index ad7cce3..70f6d3ea 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mm.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mm.h.patch
new file mode 100644
index 00000000..df2243fa
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mm.h.patch
@@ -0,0 +1,25 @@
+--- a/arch/arm/mm/mm.h
++++ b/arch/arm/mm/mm.h
+@@ -21,6 +21,20 @@ const struct mem_type *get_mem_type(unsigned int type);
+
+ extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
+
++/*
++ * ARM specific vm_struct->flags bits.
++ */
++
++/* (super)section-mapped I/O regions used by ioremap()/iounmap() */
++#define VM_ARM_SECTION_MAPPING 0x80000000
++
++/* permanent static mappings from iotable_init() */
++#define VM_ARM_STATIC_MAPPING 0x40000000
++
++/* mapping type (attributes) for permanent static mappings */
++#define VM_ARM_MTYPE(mt) ((mt) << 20)
++#define VM_ARM_MTYPE_MASK (0x1f << 20)
++
+ #endif
+
+ #ifdef CONFIG_ZONE_DMA
+diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
+index 44b628e..ce8cb19 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmap.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmap.c.patch
new file mode 100644
index 00000000..dbb38afa
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmap.c.patch
@@ -0,0 +1,204 @@
+--- a/arch/arm/mm/mmap.c
++++ b/arch/arm/mm/mmap.c
+@@ -11,10 +11,49 @@
+ #include
+ #include
+
++static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
++ unsigned long pgoff)
++{
++ unsigned long base = addr & ~(SHMLBA-1);
++ unsigned long off = (pgoff << PAGE_SHIFT) & (SHMLBA-1);
++
++ if (base + off <= addr)
++ return base + off;
++
++ return base - off;
++}
++
+ #define COLOUR_ALIGN(addr,pgoff) \
+ ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
+ (((pgoff)<personality & ADDR_COMPAT_LAYOUT)
++ return 1;
++
++ if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
++ return 1;
++
++ return sysctl_legacy_va_layout;
++}
++
++static unsigned long mmap_base(unsigned long rnd)
++{
++ unsigned long gap = rlimit(RLIMIT_STACK);
++
++ if (gap < MIN_GAP)
++ gap = MIN_GAP;
++ else if (gap > MAX_GAP)
++ gap = MAX_GAP;
++
++ return PAGE_ALIGN(TASK_SIZE - gap - rnd);
++}
++
+ /*
+ * We need to ensure that shared mappings are correctly aligned to
+ * avoid aliasing issues with VIPT caches. We need to ensure that
+@@ -68,13 +107,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
+ if (len > mm->cached_hole_size) {
+ start_addr = addr = mm->free_area_cache;
+ } else {
+- start_addr = addr = TASK_UNMAPPED_BASE;
++ start_addr = addr = mm->mmap_base;
+ mm->cached_hole_size = 0;
+ }
+- /* 8 bits of randomness in 20 address space bits */
+- if ((current->flags & PF_RANDOMIZE) &&
+- !(current->personality & ADDR_NO_RANDOMIZE))
+- addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
+
+ full_search:
+ if (do_align)
+@@ -111,6 +146,134 @@ full_search:
+ }
+ }
+
++unsigned long
++arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
++ const unsigned long len, const unsigned long pgoff,
++ const unsigned long flags)
++{
++ struct vm_area_struct *vma;
++ struct mm_struct *mm = current->mm;
++ unsigned long addr = addr0;
++ int do_align = 0;
++ int aliasing = cache_is_vipt_aliasing();
++
++ /*
++ * We only need to do colour alignment if either the I or D
++ * caches alias.
++ */
++ if (aliasing)
++ do_align = filp || (flags & MAP_SHARED);
++
++ /* requested length too big for entire address space */
++ if (len > TASK_SIZE)
++ return -ENOMEM;
++
++ if (flags & MAP_FIXED) {
++ if (aliasing && flags & MAP_SHARED &&
++ (addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1))
++ return -EINVAL;
++ return addr;
++ }
++
++ /* requesting a specific address */
++ if (addr) {
++ if (do_align)
++ addr = COLOUR_ALIGN(addr, pgoff);
++ else
++ addr = PAGE_ALIGN(addr);
++ vma = find_vma(mm, addr);
++ if (TASK_SIZE - len >= addr &&
++ (!vma || addr + len <= vma->vm_start))
++ return addr;
++ }
++
++ /* check if free_area_cache is useful for us */
++ if (len <= mm->cached_hole_size) {
++ mm->cached_hole_size = 0;
++ mm->free_area_cache = mm->mmap_base;
++ }
++
++ /* either no address requested or can't fit in requested address hole */
++ addr = mm->free_area_cache;
++ if (do_align) {
++ unsigned long base = COLOUR_ALIGN_DOWN(addr - len, pgoff);
++ addr = base + len;
++ }
++
++ /* make sure it can fit in the remaining address space */
++ if (addr > len) {
++ vma = find_vma(mm, addr-len);
++ if (!vma || addr <= vma->vm_start)
++ /* remember the address as a hint for next time */
++ return (mm->free_area_cache = addr-len);
++ }
++
++ if (mm->mmap_base < len)
++ goto bottomup;
++
++ addr = mm->mmap_base - len;
++ if (do_align)
++ addr = COLOUR_ALIGN_DOWN(addr, pgoff);
++
++ do {
++ /*
++ * Lookup failure means no vma is above this address,
++ * else if new region fits below vma->vm_start,
++ * return with success:
++ */
++ vma = find_vma(mm, addr);
++ if (!vma || addr+len <= vma->vm_start)
++ /* remember the address as a hint for next time */
++ return (mm->free_area_cache = addr);
++
++ /* remember the largest hole we saw so far */
++ if (addr + mm->cached_hole_size < vma->vm_start)
++ mm->cached_hole_size = vma->vm_start - addr;
++
++ /* try just below the current vma->vm_start */
++ addr = vma->vm_start - len;
++ if (do_align)
++ addr = COLOUR_ALIGN_DOWN(addr, pgoff);
++ } while (len < vma->vm_start);
++
++bottomup:
++ /*
++ * A failed mmap() very likely causes application failure,
++ * so fall back to the bottom-up function here. This scenario
++ * can happen with large stack limits and large mmap()
++ * allocations.
++ */
++ mm->cached_hole_size = ~0UL;
++ mm->free_area_cache = TASK_UNMAPPED_BASE;
++ addr = arch_get_unmapped_area(filp, addr0, len, pgoff, flags);
++ /*
++ * Restore the topdown base:
++ */
++ mm->free_area_cache = mm->mmap_base;
++ mm->cached_hole_size = ~0UL;
++
++ return addr;
++}
++
++void arch_pick_mmap_layout(struct mm_struct *mm)
++{
++ unsigned long random_factor = 0UL;
++
++ /* 8 bits of randomness in 20 address space bits */
++ if ((current->flags & PF_RANDOMIZE) &&
++ !(current->personality & ADDR_NO_RANDOMIZE))
++ random_factor = (get_random_int() % (1 << 8)) << PAGE_SHIFT;
++
++ if (mmap_is_legacy()) {
++ mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
++ mm->get_unmapped_area = arch_get_unmapped_area;
++ mm->unmap_area = arch_unmap_area;
++ } else {
++ mm->mmap_base = mmap_base(random_factor);
++ mm->get_unmapped_area = arch_get_unmapped_area_topdown;
++ mm->unmap_area = arch_unmap_area_topdown;
++ }
++}
+
+ /*
+ * You really shouldn't be using read() or write() on /dev/mem. This
+diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
+index 082fa18..704031c 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmu.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmu.c.patch
new file mode 100644
index 00000000..fe6390cd
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_mmu.c.patch
@@ -0,0 +1,110 @@
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -15,6 +15,7 @@
+ #include
+ #include
+ #include
++#include
+
+ #include
+ #include
+@@ -537,13 +538,18 @@ EXPORT_SYMBOL(phys_mem_access_prot);
+
+ #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
+
+-static void __init *early_alloc(unsigned long sz)
++static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
+ {
+- void *ptr = __va(memblock_alloc(sz, sz));
++ void *ptr = __va(memblock_alloc(sz, align));
+ memset(ptr, 0, sz);
+ return ptr;
+ }
+
++static void __init *early_alloc(unsigned long sz)
++{
++ return early_alloc_aligned(sz, sz);
++}
++
+ static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
+ {
+ if (pmd_none(*pmd)) {
+@@ -693,9 +699,10 @@ static void __init create_mapping(struct map_desc *md)
+ }
+
+ if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
+- md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
++ md->virtual >= PAGE_OFFSET &&
++ (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
+ printk(KERN_WARNING "BUG: mapping for 0x%08llx"
+- " at 0x%08lx overlaps vmalloc space\n",
++ " at 0x%08lx out of vmalloc space\n",
+ (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
+ }
+
+@@ -737,18 +744,34 @@ static void __init create_mapping(struct map_desc *md)
+ */
+ void __init iotable_init(struct map_desc *io_desc, int nr)
+ {
+- int i;
+-
+- for (i = 0; i < nr; i++)
+- create_mapping(io_desc + i);
++ struct map_desc *md;
++ struct vm_struct *vm;
++
++ if (!nr)
++ return;
++
++ vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
++
++ for (md = io_desc; nr; md++, nr--) {
++ create_mapping(md);
++ vm->addr = (void *)(md->virtual & PAGE_MASK);
++ vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
++ vm->phys_addr = __pfn_to_phys(md->pfn);
++ vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
++ vm->flags |= VM_ARM_MTYPE(md->type);
++ vm->caller = iotable_init;
++ vm_area_add_early(vm++);
++ }
+ }
+
+-static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
++
++static void * __initdata vmalloc_min =
++ (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
+
+ /*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the vmalloc
+- * area - the default is 128m.
++ * area - the default is 240m.
+ */
+ static int __init early_vmalloc(char *arg)
+ {
+@@ -868,7 +891,8 @@ void __init sanity_check_meminfo(void)
+ }
+ #endif
+ meminfo.nr_banks = j;
+- memblock_set_current_limit(lowmem_limit);
++ high_memory = __va(lowmem_limit - 1) + 1;
++ memblock_set_current_limit(lowmem_limit);
+ }
+
+ static inline void prepare_page_table(void)
+@@ -898,10 +922,10 @@ static inline void prepare_page_table(void)
+
+ /*
+ * Clear out all the kernel space mappings, except for the first
+- * memory bank, up to the end of the vmalloc region.
++ * memory bank, up to the vmalloc region.
+ */
+ for (addr = __phys_to_virt(end);
+- addr < VMALLOC_END; addr += PMD_SIZE)
++ addr < VMALLOC_START; addr += PMD_SIZE)
+ pmd_clear(pmd_off_k(addr));
+ }
+
+diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
+index a5018fb..13d8194 100644
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_nommu.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_nommu.c.patch
new file mode 100644
index 00000000..0c54ffdd
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_mm_nommu.c.patch
@@ -0,0 +1,14 @@
+--- a/arch/arm/mm/nommu.c
++++ b/arch/arm/mm/nommu.c
+@@ -29,6 +29,8 @@ void __init arm_mm_memblock_reserve(void)
+
+ void __init sanity_check_meminfo(void)
+ {
++ phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
++ high_memory = __va(end - 1) + 1;
+ }
+
+ /*
+diff --git a/arch/arm/net/Makefile b/arch/arm/net/Makefile
+new file mode 100644
+index 0000000..c2c1084
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_Makefile.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_Makefile.patch
new file mode 100644
index 00000000..655fb068
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_Makefile.patch
@@ -0,0 +1,9 @@
+--- /dev/null
++++ b/arch/arm/net/Makefile
+@@ -0,0 +1,3 @@
++# ARM-specific networking code
++
++obj-$(CONFIG_BPF_JIT) += bpf_jit_32.o
+diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
+new file mode 100644
+index 0000000..62135849
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.c.patch
new file mode 100644
index 00000000..8b475d7f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.c.patch
@@ -0,0 +1,921 @@
+--- /dev/null
++++ b/arch/arm/net/bpf_jit_32.c
+@@ -0,0 +1,915 @@
++/*
++ * Just-In-Time compiler for BPF filters on 32bit ARM
++ *
++ * Copyright (c) 2011 Mircea Gherzan
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; version 2 of the License.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++#include "bpf_jit_32.h"
++
++/*
++ * ABI:
++ *
++ * r0 scratch register
++ * r4 BPF register A
++ * r5 BPF register X
++ * r6 pointer to the skb
++ * r7 skb->data
++ * r8 skb_headlen(skb)
++ */
++
++#define r_scratch ARM_R0
++/* r1-r3 are (also) used for the unaligned loads on the non-ARMv7 slowpath */
++#define r_off ARM_R1
++#define r_A ARM_R4
++#define r_X ARM_R5
++#define r_skb ARM_R6
++#define r_skb_data ARM_R7
++#define r_skb_hl ARM_R8
++
++#define SCRATCH_SP_OFFSET 0
++#define SCRATCH_OFF(k) (SCRATCH_SP_OFFSET + (k))
++
++#define SEEN_MEM ((1 << BPF_MEMWORDS) - 1)
++#define SEEN_MEM_WORD(k) (1 << (k))
++#define SEEN_X (1 << BPF_MEMWORDS)
++#define SEEN_CALL (1 << (BPF_MEMWORDS + 1))
++#define SEEN_SKB (1 << (BPF_MEMWORDS + 2))
++#define SEEN_DATA (1 << (BPF_MEMWORDS + 3))
++
++#define FLAG_NEED_X_RESET (1 << 0)
++
++struct jit_ctx {
++ const struct sk_filter *skf;
++ unsigned idx;
++ unsigned prologue_bytes;
++ int ret0_fp_idx;
++ u32 seen;
++ u32 flags;
++ u32 *offsets;
++ u32 *target;
++#if __LINUX_ARM_ARCH__ < 7
++ u16 epilogue_bytes;
++ u16 imm_count;
++ u32 *imms;
++#endif
++};
++
++int bpf_jit_enable __read_mostly;
++
++static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
++{
++ u8 ret;
++ int err;
++
++ err = skb_copy_bits(skb, offset, &ret, 1);
++
++ return (u64)err << 32 | ret;
++}
++
++static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
++{
++ u16 ret;
++ int err;
++
++ err = skb_copy_bits(skb, offset, &ret, 2);
++
++ return (u64)err << 32 | ntohs(ret);
++}
++
++static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
++{
++ u32 ret;
++ int err;
++
++ err = skb_copy_bits(skb, offset, &ret, 4);
++
++ return (u64)err << 32 | ntohl(ret);
++}
++
++/*
++ * Wrapper that handles both OABI and EABI and assures Thumb2 interworking
++ * (where the assembly routines like __aeabi_uidiv could cause problems).
++ */
++static u32 jit_udiv(u32 dividend, u32 divisor)
++{
++ return dividend / divisor;
++}
++
++static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
++{
++ if (ctx->target != NULL)
++ ctx->target[ctx->idx] = inst | (cond << 28);
++
++ ctx->idx++;
++}
++
++/*
++ * Emit an instruction that will be executed unconditionally.
++ */
++static inline void emit(u32 inst, struct jit_ctx *ctx)
++{
++ _emit(ARM_COND_AL, inst, ctx);
++}
++
++static u16 saved_regs(struct jit_ctx *ctx)
++{
++ u16 ret = 0;
++
++ if ((ctx->skf->len > 1) ||
++ (ctx->skf->insns[0].code == BPF_S_RET_A))
++ ret |= 1 << r_A;
++
++#ifdef CONFIG_FRAME_POINTER
++ ret |= (1 << ARM_FP) | (1 << ARM_IP) | (1 << ARM_LR) | (1 << ARM_PC);
++#else
++ if (ctx->seen & SEEN_CALL)
++ ret |= 1 << ARM_LR;
++#endif
++ if (ctx->seen & (SEEN_DATA | SEEN_SKB))
++ ret |= 1 << r_skb;
++ if (ctx->seen & SEEN_DATA)
++ ret |= (1 << r_skb_data) | (1 << r_skb_hl);
++ if (ctx->seen & SEEN_X)
++ ret |= 1 << r_X;
++
++ return ret;
++}
++
++static inline int mem_words_used(struct jit_ctx *ctx)
++{
++ /* yes, we do waste some stack space IF there are "holes" in the set" */
++ return fls(ctx->seen & SEEN_MEM);
++}
++
++static inline bool is_load_to_a(u16 inst)
++{
++ switch (inst) {
++ case BPF_S_LD_W_LEN:
++ case BPF_S_LD_W_ABS:
++ case BPF_S_LD_H_ABS:
++ case BPF_S_LD_B_ABS:
++ case BPF_S_ANC_CPU:
++ case BPF_S_ANC_IFINDEX:
++ case BPF_S_ANC_MARK:
++ case BPF_S_ANC_PROTOCOL:
++ case BPF_S_ANC_RXHASH:
++ case BPF_S_ANC_QUEUE:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static void build_prologue(struct jit_ctx *ctx)
++{
++ u16 reg_set = saved_regs(ctx);
++ u16 first_inst = ctx->skf->insns[0].code;
++ u16 off;
++
++#ifdef CONFIG_FRAME_POINTER
++ emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
++ emit(ARM_PUSH(reg_set), ctx);
++ emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
++#else
++ if (reg_set)
++ emit(ARM_PUSH(reg_set), ctx);
++#endif
++
++ if (ctx->seen & (SEEN_DATA | SEEN_SKB))
++ emit(ARM_MOV_R(r_skb, ARM_R0), ctx);
++
++ if (ctx->seen & SEEN_DATA) {
++ off = offsetof(struct sk_buff, data);
++ emit(ARM_LDR_I(r_skb_data, r_skb, off), ctx);
++ /* headlen = len - data_len */
++ off = offsetof(struct sk_buff, len);
++ emit(ARM_LDR_I(r_skb_hl, r_skb, off), ctx);
++ off = offsetof(struct sk_buff, data_len);
++ emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
++ emit(ARM_SUB_R(r_skb_hl, r_skb_hl, r_scratch), ctx);
++ }
++
++ if (ctx->flags & FLAG_NEED_X_RESET)
++ emit(ARM_MOV_I(r_X, 0), ctx);
++
++ /* do not leak kernel data to userspace */
++ if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
++ emit(ARM_MOV_I(r_A, 0), ctx);
++
++ /* stack space for the BPF_MEM words */
++ if (ctx->seen & SEEN_MEM)
++ emit(ARM_SUB_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
++}
++
++static void build_epilogue(struct jit_ctx *ctx)
++{
++ u16 reg_set = saved_regs(ctx);
++
++ if (ctx->seen & SEEN_MEM)
++ emit(ARM_ADD_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
++
++ reg_set &= ~(1 << ARM_LR);
++
++#ifdef CONFIG_FRAME_POINTER
++ /* the first instruction of the prologue was: mov ip, sp */
++ reg_set &= ~(1 << ARM_IP);
++ reg_set |= (1 << ARM_SP);
++ emit(ARM_LDM(ARM_SP, reg_set), ctx);
++#else
++ if (reg_set) {
++ if (ctx->seen & SEEN_CALL)
++ reg_set |= 1 << ARM_PC;
++ emit(ARM_POP(reg_set), ctx);
++ }
++
++ if (!(ctx->seen & SEEN_CALL))
++ emit(ARM_BX(ARM_LR), ctx);
++#endif
++}
++
++static int16_t imm8m(u32 x)
++{
++ u32 rot;
++
++ for (rot = 0; rot < 16; rot++)
++ if ((x & ~ror32(0xff, 2 * rot)) == 0)
++ return rol32(x, 2 * rot) | (rot << 8);
++
++ return -1;
++}
++
++#if __LINUX_ARM_ARCH__ < 7
++
++static u16 imm_offset(u32 k, struct jit_ctx *ctx)
++{
++ unsigned i = 0, offset;
++ u16 imm;
++
++ /* on the "fake" run we just count them (duplicates included) */
++ if (ctx->target == NULL) {
++ ctx->imm_count++;
++ return 0;
++ }
++
++ while ((i < ctx->imm_count) && ctx->imms[i]) {
++ if (ctx->imms[i] == k)
++ break;
++ i++;
++ }
++
++ if (ctx->imms[i] == 0)
++ ctx->imms[i] = k;
++
++ /* constants go just after the epilogue */
++ offset = ctx->offsets[ctx->skf->len];
++ offset += ctx->prologue_bytes;
++ offset += ctx->epilogue_bytes;
++ offset += i * 4;
++
++ ctx->target[offset / 4] = k;
++
++ /* PC in ARM mode == address of the instruction + 8 */
++ imm = offset - (8 + ctx->idx * 4);
++
++ return imm;
++}
++
++#endif /* __LINUX_ARM_ARCH__ */
++
++/*
++ * Move an immediate that's not an imm8m to a core register.
++ */
++static inline void emit_mov_i_no8m(int rd, u32 val, struct jit_ctx *ctx)
++{
++#if __LINUX_ARM_ARCH__ < 7
++ emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
++#else
++ emit(ARM_MOVW(rd, val & 0xffff), ctx);
++ if (val > 0xffff)
++ emit(ARM_MOVT(rd, val >> 16), ctx);
++#endif
++}
++
++static inline void emit_mov_i(int rd, u32 val, struct jit_ctx *ctx)
++{
++ int imm12 = imm8m(val);
++
++ if (imm12 >= 0)
++ emit(ARM_MOV_I(rd, imm12), ctx);
++ else
++ emit_mov_i_no8m(rd, val, ctx);
++}
++
++#if __LINUX_ARM_ARCH__ < 6
++
++static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
++{
++ _emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
++ _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
++ _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
++ _emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
++ _emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
++ _emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
++ _emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx);
++ _emit(cond, ARM_ORR_S(r_res, ARM_R3, ARM_R0, SRTYPE_LSL, 8), ctx);
++}
++
++static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
++{
++ _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
++ _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 1), ctx);
++ _emit(cond, ARM_ORR_S(r_res, ARM_R2, ARM_R1, SRTYPE_LSL, 8), ctx);
++}
++
++static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
++{
++ emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
++ emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
++ emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
++ emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
++}
++
++#else /* ARMv6+ */
++
++static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
++{
++ _emit(cond, ARM_LDR_I(r_res, r_addr, 0), ctx);
++#ifdef __LITTLE_ENDIAN
++ _emit(cond, ARM_REV(r_res, r_res), ctx);
++#endif
++}
++
++static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
++{
++ _emit(cond, ARM_LDRH_I(r_res, r_addr, 0), ctx);
++#ifdef __LITTLE_ENDIAN
++ _emit(cond, ARM_REV16(r_res, r_res), ctx);
++#endif
++}
++
++static inline void emit_swap16(u8 r_dst __maybe_unused,
++ u8 r_src __maybe_unused,
++ struct jit_ctx *ctx __maybe_unused)
++{
++#ifdef __LITTLE_ENDIAN
++ emit(ARM_REV16(r_dst, r_src), ctx);
++#endif
++}
++
++#endif /* __LINUX_ARM_ARCH__ < 6 */
++
++
++/* Compute the immediate value for a PC-relative branch. */
++static inline u32 b_imm(unsigned tgt, struct jit_ctx *ctx)
++{
++ u32 imm;
++
++ if (ctx->target == NULL)
++ return 0;
++ /*
++ * BPF allows only forward jumps and the offset of the target is
++ * still the one computed during the first pass.
++ */
++ imm = ctx->offsets[tgt] + ctx->prologue_bytes - (ctx->idx * 4 + 8);
++
++ return imm >> 2;
++}
++
++#define OP_IMM3(op, r1, r2, imm_val, ctx) \
++ do { \
++ imm12 = imm8m(imm_val); \
++ if (imm12 < 0) { \
++ emit_mov_i_no8m(r_scratch, imm_val, ctx); \
++ emit(op ## _R((r1), (r2), r_scratch), ctx); \
++ } else { \
++ emit(op ## _I((r1), (r2), imm12), ctx); \
++ } \
++ } while (0)
++
++static inline void emit_err_ret(u8 cond, struct jit_ctx *ctx)
++{
++ if (ctx->ret0_fp_idx >= 0) {
++ _emit(cond, ARM_B(b_imm(ctx->ret0_fp_idx, ctx)), ctx);
++ /* NOP to keep the size constant between passes */
++ emit(ARM_MOV_R(ARM_R0, ARM_R0), ctx);
++ } else {
++ _emit(cond, ARM_MOV_I(ARM_R0, 0), ctx);
++ _emit(cond, ARM_B(b_imm(ctx->skf->len, ctx)), ctx);
++ }
++}
++
++static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
++{
++#if __LINUX_ARM_ARCH__ < 5
++ emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
++
++ if (elf_hwcap & HWCAP_THUMB)
++ emit(ARM_BX(tgt_reg), ctx);
++ else
++ emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
++#else
++ emit(ARM_BLX_R(tgt_reg), ctx);
++#endif
++}
++
++static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
++{
++#if __LINUX_ARM_ARCH__ == 7
++ if (elf_hwcap & HWCAP_IDIVA) {
++ emit(ARM_UDIV(rd, rm, rn), ctx);
++ return;
++ }
++#endif
++ if (rm != ARM_R0)
++ emit(ARM_MOV_R(ARM_R0, rm), ctx);
++ if (rn != ARM_R1)
++ emit(ARM_MOV_R(ARM_R1, rn), ctx);
++
++ ctx->seen |= SEEN_CALL;
++ emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
++ emit_blx_r(ARM_R3, ctx);
++
++ if (rd != ARM_R0)
++ emit(ARM_MOV_R(rd, ARM_R0), ctx);
++}
++
++static inline void update_on_xread(struct jit_ctx *ctx)
++{
++ if (!(ctx->seen & SEEN_X))
++ ctx->flags |= FLAG_NEED_X_RESET;
++
++ ctx->seen |= SEEN_X;
++}
++
++static int build_body(struct jit_ctx *ctx)
++{
++ void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
++ const struct sk_filter *prog = ctx->skf;
++ const struct sock_filter *inst;
++ unsigned i, load_order, off, condt;
++ int imm12;
++ u32 k;
++
++ for (i = 0; i < prog->len; i++) {
++ inst = &(prog->insns[i]);
++ /* K as an immediate value operand */
++ k = inst->k;
++
++ /* compute offsets only in the fake pass */
++ if (ctx->target == NULL)
++ ctx->offsets[i] = ctx->idx * 4;
++
++ switch (inst->code) {
++ case BPF_S_LD_IMM:
++ emit_mov_i(r_A, k, ctx);
++ break;
++ case BPF_S_LD_W_LEN:
++ ctx->seen |= SEEN_SKB;
++ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
++ emit(ARM_LDR_I(r_A, r_skb,
++ offsetof(struct sk_buff, len)), ctx);
++ break;
++ case BPF_S_LD_MEM:
++ /* A = scratch[k] */
++ ctx->seen |= SEEN_MEM_WORD(k);
++ emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
++ break;
++ case BPF_S_LD_W_ABS:
++ load_order = 2;
++ goto load;
++ case BPF_S_LD_H_ABS:
++ load_order = 1;
++ goto load;
++ case BPF_S_LD_B_ABS:
++ load_order = 0;
++load:
++ /* the interpreter will deal with the negative K */
++ if ((int)k < 0)
++ return -ENOTSUPP;
++ emit_mov_i(r_off, k, ctx);
++load_common:
++ ctx->seen |= SEEN_DATA | SEEN_CALL;
++
++ if (load_order > 0) {
++ emit(ARM_SUB_I(r_scratch, r_skb_hl,
++ 1 << load_order), ctx);
++ emit(ARM_CMP_R(r_scratch, r_off), ctx);
++ condt = ARM_COND_HS;
++ } else {
++ emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
++ condt = ARM_COND_HI;
++ }
++
++ _emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
++ ctx);
++
++ if (load_order == 0)
++ _emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
++ ctx);
++ else if (load_order == 1)
++ emit_load_be16(condt, r_A, r_scratch, ctx);
++ else if (load_order == 2)
++ emit_load_be32(condt, r_A, r_scratch, ctx);
++
++ _emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
++
++ /* the slowpath */
++ emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
++ emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
++ /* the offset is already in R1 */
++ emit_blx_r(ARM_R3, ctx);
++ /* check the result of skb_copy_bits */
++ emit(ARM_CMP_I(ARM_R1, 0), ctx);
++ emit_err_ret(ARM_COND_NE, ctx);
++ emit(ARM_MOV_R(r_A, ARM_R0), ctx);
++ break;
++ case BPF_S_LD_W_IND:
++ load_order = 2;
++ goto load_ind;
++ case BPF_S_LD_H_IND:
++ load_order = 1;
++ goto load_ind;
++ case BPF_S_LD_B_IND:
++ load_order = 0;
++load_ind:
++ OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
++ goto load_common;
++ case BPF_S_LDX_IMM:
++ ctx->seen |= SEEN_X;
++ emit_mov_i(r_X, k, ctx);
++ break;
++ case BPF_S_LDX_W_LEN:
++ ctx->seen |= SEEN_X | SEEN_SKB;
++ emit(ARM_LDR_I(r_X, r_skb,
++ offsetof(struct sk_buff, len)), ctx);
++ break;
++ case BPF_S_LDX_MEM:
++ ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
++ emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
++ break;
++ case BPF_S_LDX_B_MSH:
++ /* x = ((*(frame + k)) & 0xf) << 2; */
++ ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
++ /* the interpreter should deal with the negative K */
++ if (k < 0)
++ return -1;
++ /* offset in r1: we might have to take the slow path */
++ emit_mov_i(r_off, k, ctx);
++ emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
++
++ /* load in r0: common with the slowpath */
++ _emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
++ ARM_R1), ctx);
++ /*
++ * emit_mov_i() might generate one or two instructions,
++ * the same holds for emit_blx_r()
++ */
++ _emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
++
++ emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
++ /* r_off is r1 */
++ emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
++ emit_blx_r(ARM_R3, ctx);
++ /* check the return value of skb_copy_bits */
++ emit(ARM_CMP_I(ARM_R1, 0), ctx);
++ emit_err_ret(ARM_COND_NE, ctx);
++
++ emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
++ emit(ARM_LSL_I(r_X, r_X, 2), ctx);
++ break;
++ case BPF_S_ST:
++ ctx->seen |= SEEN_MEM_WORD(k);
++ emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
++ break;
++ case BPF_S_STX:
++ update_on_xread(ctx);
++ ctx->seen |= SEEN_MEM_WORD(k);
++ emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
++ break;
++ case BPF_S_ALU_ADD_K:
++ /* A += K */
++ OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
++ break;
++ case BPF_S_ALU_ADD_X:
++ update_on_xread(ctx);
++ emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_SUB_K:
++ /* A -= K */
++ OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
++ break;
++ case BPF_S_ALU_SUB_X:
++ update_on_xread(ctx);
++ emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_MUL_K:
++ /* A *= K */
++ emit_mov_i(r_scratch, k, ctx);
++ emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
++ break;
++ case BPF_S_ALU_MUL_X:
++ update_on_xread(ctx);
++ emit(ARM_MUL(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_DIV_K:
++ /* current k == reciprocal_value(userspace k) */
++ emit_mov_i(r_scratch, k, ctx);
++ /* A = top 32 bits of the product */
++ emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
++ break;
++ case BPF_S_ALU_DIV_X:
++ update_on_xread(ctx);
++ emit(ARM_CMP_I(r_X, 0), ctx);
++ emit_err_ret(ARM_COND_EQ, ctx);
++ emit_udiv(r_A, r_A, r_X, ctx);
++ break;
++ case BPF_S_ALU_OR_K:
++ /* A |= K */
++ OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
++ break;
++ case BPF_S_ALU_OR_X:
++ update_on_xread(ctx);
++ emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_AND_K:
++ /* A &= K */
++ OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
++ break;
++ case BPF_S_ALU_AND_X:
++ update_on_xread(ctx);
++ emit(ARM_AND_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_LSH_K:
++ if (unlikely(k > 31))
++ return -1;
++ emit(ARM_LSL_I(r_A, r_A, k), ctx);
++ break;
++ case BPF_S_ALU_LSH_X:
++ update_on_xread(ctx);
++ emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_RSH_K:
++ if (unlikely(k > 31))
++ return -1;
++ emit(ARM_LSR_I(r_A, r_A, k), ctx);
++ break;
++ case BPF_S_ALU_RSH_X:
++ update_on_xread(ctx);
++ emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
++ break;
++ case BPF_S_ALU_NEG:
++ /* A = -A */
++ emit(ARM_RSB_I(r_A, r_A, 0), ctx);
++ break;
++ case BPF_S_JMP_JA:
++ /* pc += K */
++ emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
++ break;
++ case BPF_S_JMP_JEQ_K:
++ /* pc += (A == K) ? pc->jt : pc->jf */
++ condt = ARM_COND_EQ;
++ goto cmp_imm;
++ case BPF_S_JMP_JGT_K:
++ /* pc += (A > K) ? pc->jt : pc->jf */
++ condt = ARM_COND_HI;
++ goto cmp_imm;
++ case BPF_S_JMP_JGE_K:
++ /* pc += (A >= K) ? pc->jt : pc->jf */
++ condt = ARM_COND_HS;
++cmp_imm:
++ imm12 = imm8m(k);
++ if (imm12 < 0) {
++ emit_mov_i_no8m(r_scratch, k, ctx);
++ emit(ARM_CMP_R(r_A, r_scratch), ctx);
++ } else {
++ emit(ARM_CMP_I(r_A, imm12), ctx);
++ }
++cond_jump:
++ if (inst->jt)
++ _emit(condt, ARM_B(b_imm(i + inst->jt + 1,
++ ctx)), ctx);
++ if (inst->jf)
++ _emit(condt ^ 1, ARM_B(b_imm(i + inst->jf + 1,
++ ctx)), ctx);
++ break;
++ case BPF_S_JMP_JEQ_X:
++ /* pc += (A == X) ? pc->jt : pc->jf */
++ condt = ARM_COND_EQ;
++ goto cmp_x;
++ case BPF_S_JMP_JGT_X:
++ /* pc += (A > X) ? pc->jt : pc->jf */
++ condt = ARM_COND_HI;
++ goto cmp_x;
++ case BPF_S_JMP_JGE_X:
++ /* pc += (A >= X) ? pc->jt : pc->jf */
++ condt = ARM_COND_CS;
++cmp_x:
++ update_on_xread(ctx);
++ emit(ARM_CMP_R(r_A, r_X), ctx);
++ goto cond_jump;
++ case BPF_S_JMP_JSET_K:
++ /* pc += (A & K) ? pc->jt : pc->jf */
++ condt = ARM_COND_NE;
++ /* not set iff all zeroes iff Z==1 iff EQ */
++
++ imm12 = imm8m(k);
++ if (imm12 < 0) {
++ emit_mov_i_no8m(r_scratch, k, ctx);
++ emit(ARM_TST_R(r_A, r_scratch), ctx);
++ } else {
++ emit(ARM_TST_I(r_A, imm12), ctx);
++ }
++ goto cond_jump;
++ case BPF_S_JMP_JSET_X:
++ /* pc += (A & X) ? pc->jt : pc->jf */
++ update_on_xread(ctx);
++ condt = ARM_COND_NE;
++ emit(ARM_TST_R(r_A, r_X), ctx);
++ goto cond_jump;
++ case BPF_S_RET_A:
++ emit(ARM_MOV_R(ARM_R0, r_A), ctx);
++ goto b_epilogue;
++ case BPF_S_RET_K:
++ if ((k == 0) && (ctx->ret0_fp_idx < 0))
++ ctx->ret0_fp_idx = i;
++ emit_mov_i(ARM_R0, k, ctx);
++b_epilogue:
++ if (i != ctx->skf->len - 1)
++ emit(ARM_B(b_imm(prog->len, ctx)), ctx);
++ break;
++ case BPF_S_MISC_TAX:
++ /* X = A */
++ ctx->seen |= SEEN_X;
++ emit(ARM_MOV_R(r_X, r_A), ctx);
++ break;
++ case BPF_S_MISC_TXA:
++ /* A = X */
++ update_on_xread(ctx);
++ emit(ARM_MOV_R(r_A, r_X), ctx);
++ break;
++ case BPF_S_ANC_PROTOCOL:
++ /* A = ntohs(skb->protocol) */
++ ctx->seen |= SEEN_SKB;
++ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
++ protocol) != 2);
++ off = offsetof(struct sk_buff, protocol);
++ emit(ARM_LDRH_I(r_scratch, r_skb, off), ctx);
++ emit_swap16(r_A, r_scratch, ctx);
++ break;
++ case BPF_S_ANC_CPU:
++ /* r_scratch = current_thread_info() */
++ OP_IMM3(ARM_BIC, r_scratch, ARM_SP, THREAD_SIZE - 1, ctx);
++ /* A = current_thread_info()->cpu */
++ BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4);
++ off = offsetof(struct thread_info, cpu);
++ emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
++ break;
++ case BPF_S_ANC_IFINDEX:
++ /* A = skb->dev->ifindex */
++ ctx->seen |= SEEN_SKB;
++ off = offsetof(struct sk_buff, dev);
++ emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
++
++ emit(ARM_CMP_I(r_scratch, 0), ctx);
++ emit_err_ret(ARM_COND_EQ, ctx);
++
++ BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
++ ifindex) != 4);
++ off = offsetof(struct net_device, ifindex);
++ emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
++ break;
++ case BPF_S_ANC_MARK:
++ ctx->seen |= SEEN_SKB;
++ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
++ off = offsetof(struct sk_buff, mark);
++ emit(ARM_LDR_I(r_A, r_skb, off), ctx);
++ break;
++ case BPF_S_ANC_RXHASH:
++ ctx->seen |= SEEN_SKB;
++ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
++ off = offsetof(struct sk_buff, rxhash);
++ emit(ARM_LDR_I(r_A, r_skb, off), ctx);
++ break;
++ case BPF_S_ANC_QUEUE:
++ ctx->seen |= SEEN_SKB;
++ BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
++ queue_mapping) != 2);
++ BUILD_BUG_ON(offsetof(struct sk_buff,
++ queue_mapping) > 0xff);
++ off = offsetof(struct sk_buff, queue_mapping);
++ emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
++ break;
++ default:
++ return -1;
++ }
++ }
++
++ /* compute offsets only during the first pass */
++ if (ctx->target == NULL)
++ ctx->offsets[i] = ctx->idx * 4;
++
++ return 0;
++}
++
++
++void bpf_jit_compile(struct sk_filter *fp)
++{
++ struct jit_ctx ctx;
++ unsigned tmp_idx;
++ unsigned alloc_size;
++
++ if (!bpf_jit_enable)
++ return;
++
++ memset(&ctx, 0, sizeof(ctx));
++ ctx.skf = fp;
++ ctx.ret0_fp_idx = -1;
++
++ ctx.offsets = kzalloc(GFP_KERNEL, 4 * (ctx.skf->len + 1));
++ if (ctx.offsets == NULL)
++ return;
++
++ /* fake pass to fill in the ctx->seen */
++ if (unlikely(build_body(&ctx)))
++ goto out;
++
++ tmp_idx = ctx.idx;
++ build_prologue(&ctx);
++ ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
++
++#if __LINUX_ARM_ARCH__ < 7
++ tmp_idx = ctx.idx;
++ build_epilogue(&ctx);
++ ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
++
++ ctx.idx += ctx.imm_count;
++ if (ctx.imm_count) {
++ ctx.imms = kzalloc(GFP_KERNEL, 4 * ctx.imm_count);
++ if (ctx.imms == NULL)
++ goto out;
++ }
++#else
++ /* there's nothing after the epilogue on ARMv7 */
++ build_epilogue(&ctx);
++#endif
++
++ alloc_size = 4 * ctx.idx;
++ ctx.target = module_alloc(max(sizeof(struct work_struct),
++ alloc_size));
++ if (unlikely(ctx.target == NULL))
++ goto out;
++
++ ctx.idx = 0;
++ build_prologue(&ctx);
++ build_body(&ctx);
++ build_epilogue(&ctx);
++
++ flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
++
++#if __LINUX_ARM_ARCH__ < 7
++ if (ctx.imm_count)
++ kfree(ctx.imms);
++#endif
++
++ if (bpf_jit_enable > 1)
++ print_hex_dump(KERN_INFO, "BPF JIT code: ",
++ DUMP_PREFIX_ADDRESS, 16, 4, ctx.target,
++ alloc_size, false);
++
++ fp->bpf_func = (void *)ctx.target;
++out:
++ kfree(ctx.offsets);
++ return;
++}
++
++static void bpf_jit_free_worker(struct work_struct *work)
++{
++ module_free(NULL, work);
++}
++
++void bpf_jit_free(struct sk_filter *fp)
++{
++ struct work_struct *work;
++
++ if (fp->bpf_func != sk_run_filter) {
++ work = (struct work_struct *)fp->bpf_func;
++
++ INIT_WORK(work, bpf_jit_free_worker);
++ schedule_work(work);
++ }
++}
+diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
+new file mode 100644
+index 0000000..99ae5e3
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.h.patch
new file mode 100644
index 00000000..eaadc907
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_net_bpf_jit_32.h.patch
@@ -0,0 +1,196 @@
+--- /dev/null
++++ b/arch/arm/net/bpf_jit_32.h
+@@ -0,0 +1,190 @@
++/*
++ * Just-In-Time compiler for BPF filters on 32bit ARM
++ *
++ * Copyright (c) 2011 Mircea Gherzan
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; version 2 of the License.
++ */
++
++#ifndef PFILTER_OPCODES_ARM_H
++#define PFILTER_OPCODES_ARM_H
++
++#define ARM_R0 0
++#define ARM_R1 1
++#define ARM_R2 2
++#define ARM_R3 3
++#define ARM_R4 4
++#define ARM_R5 5
++#define ARM_R6 6
++#define ARM_R7 7
++#define ARM_R8 8
++#define ARM_R9 9
++#define ARM_R10 10
++#define ARM_FP 11
++#define ARM_IP 12
++#define ARM_SP 13
++#define ARM_LR 14
++#define ARM_PC 15
++
++#define ARM_COND_EQ 0x0
++#define ARM_COND_NE 0x1
++#define ARM_COND_CS 0x2
++#define ARM_COND_HS ARM_COND_CS
++#define ARM_COND_CC 0x3
++#define ARM_COND_LO ARM_COND_CC
++#define ARM_COND_MI 0x4
++#define ARM_COND_PL 0x5
++#define ARM_COND_VS 0x6
++#define ARM_COND_VC 0x7
++#define ARM_COND_HI 0x8
++#define ARM_COND_LS 0x9
++#define ARM_COND_GE 0xa
++#define ARM_COND_LT 0xb
++#define ARM_COND_GT 0xc
++#define ARM_COND_LE 0xd
++#define ARM_COND_AL 0xe
++
++/* register shift types */
++#define SRTYPE_LSL 0
++#define SRTYPE_LSR 1
++#define SRTYPE_ASR 2
++#define SRTYPE_ROR 3
++
++#define ARM_INST_ADD_R 0x00800000
++#define ARM_INST_ADD_I 0x02800000
++
++#define ARM_INST_AND_R 0x00000000
++#define ARM_INST_AND_I 0x02000000
++
++#define ARM_INST_BIC_R 0x01c00000
++#define ARM_INST_BIC_I 0x03c00000
++
++#define ARM_INST_B 0x0a000000
++#define ARM_INST_BX 0x012FFF10
++#define ARM_INST_BLX_R 0x012fff30
++
++#define ARM_INST_CMP_R 0x01500000
++#define ARM_INST_CMP_I 0x03500000
++
++#define ARM_INST_LDRB_I 0x05d00000
++#define ARM_INST_LDRB_R 0x07d00000
++#define ARM_INST_LDRH_I 0x01d000b0
++#define ARM_INST_LDR_I 0x05900000
++
++#define ARM_INST_LDM 0x08900000
++
++#define ARM_INST_LSL_I 0x01a00000
++#define ARM_INST_LSL_R 0x01a00010
++
++#define ARM_INST_LSR_I 0x01a00020
++#define ARM_INST_LSR_R 0x01a00030
++
++#define ARM_INST_MOV_R 0x01a00000
++#define ARM_INST_MOV_I 0x03a00000
++#define ARM_INST_MOVW 0x03000000
++#define ARM_INST_MOVT 0x03400000
++
++#define ARM_INST_MUL 0x00000090
++
++#define ARM_INST_POP 0x08bd0000
++#define ARM_INST_PUSH 0x092d0000
++
++#define ARM_INST_ORR_R 0x01800000
++#define ARM_INST_ORR_I 0x03800000
++
++#define ARM_INST_REV 0x06bf0f30
++#define ARM_INST_REV16 0x06bf0fb0
++
++#define ARM_INST_RSB_I 0x02600000
++
++#define ARM_INST_SUB_R 0x00400000
++#define ARM_INST_SUB_I 0x02400000
++
++#define ARM_INST_STR_I 0x05800000
++
++#define ARM_INST_TST_R 0x01100000
++#define ARM_INST_TST_I 0x03100000
++
++#define ARM_INST_UDIV 0x0730f010
++
++#define ARM_INST_UMULL 0x00800090
++
++/* register */
++#define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
++/* immediate */
++#define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
++
++#define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm)
++#define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm)
++
++#define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm)
++#define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm)
++
++#define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm)
++#define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm)
++
++#define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff))
++#define ARM_BX(rm) (ARM_INST_BX | (rm))
++#define ARM_BLX_R(rm) (ARM_INST_BLX_R | (rm))
++
++#define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm)
++#define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm)
++
++#define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
++ | (off))
++#define ARM_LDRB_I(rt, rn, off) (ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \
++ | (off))
++#define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \
++ | (rm))
++#define ARM_LDRH_I(rt, rn, off) (ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \
++ | (((off) & 0xf0) << 4) | ((off) & 0xf))
++
++#define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs))
++
++#define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
++#define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
++
++#define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
++#define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
++
++#define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm)
++#define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm)
++
++#define ARM_MOVW(rd, imm) \
++ (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
++
++#define ARM_MOVT(rd, imm) \
++ (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
++
++#define ARM_MUL(rd, rm, rn) (ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn))
++
++#define ARM_POP(regs) (ARM_INST_POP | (regs))
++#define ARM_PUSH(regs) (ARM_INST_PUSH | (regs))
++
++#define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm)
++#define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm)
++#define ARM_ORR_S(rd, rn, rm, type, rs) \
++ (ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7)
++
++#define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm))
++#define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm))
++
++#define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm)
++
++#define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm)
++#define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm)
++
++#define ARM_STR_I(rt, rn, off) (ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \
++ | (off))
++
++#define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm)
++#define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm)
++
++#define ARM_UDIV(rd, rn, rm) (ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8)
++
++#define ARM_UMULL(rd_lo, rd_hi, rn, rm) (ARM_INST_UMULL | (rd_hi) << 16 \
++ | (rd_lo) << 12 | (rm) << 8 | rn)
++
++#endif /* PFILTER_OPCODES_ARM_H */
+diff --git a/arch/arm/plat-iproc/Kconfig b/arch/arm/plat-iproc/Kconfig
+new file mode 100644
+index 0000000..5b8675f
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Kconfig.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Kconfig.patch
new file mode 100644
index 00000000..f72b82cb
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Kconfig.patch
@@ -0,0 +1,102 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/Kconfig
+@@ -0,0 +1,96 @@
++# Kernel configuration for Broadcom iProc based boards
++
++menu "Broadcom IPROC architecture based implementations"
++ depends on ARCH_IPROC
++
++choice
++ prompt "Broadcom iProc SoC Type"
++ default ARCH_NORTHSTAR
++
++config ARCH_NORTHSTAR
++ bool "BROADCOM Northstar SoC"
++ help
++ Support for the Broadcom Northstar SoC platform.
++
++config MACH_IPROC
++ bool "BROADCOM Generic IPROC SoC"
++ help
++ Support for the Broadcom IPROC SoC platform.
++
++endchoice
++
++config IPROC_64K_PAGE
++ bool "64K page support"
++ depends on ARCH_IPROC
++ help
++
++config GP_TIMER_CLOCK_OFF_FIX
++ bool "Enable the fix for general purpose timer clock off issue."
++ depends on ARCH_RHEA || ARCH_SAMOA
++ help
++ Say Y if you want to enable the general purpose timer clock off fix
++
++config GP_TIMER_COMPARATOR_LOAD_DELAY
++ bool "Enable the delay after loading general purpose timer compare register"
++ depends on ARCH_RHEA || ARCH_ISLAND || ARCH_SAMOA || ARCH_HANA || ARCH_NORTHSTAR || MACH_IPROC
++ default y
++
++config IPROC_DCACHE_INVALIDATION
++ bool "Have Linux invalidate D-Cache"
++ default y
++ help
++ Say Y if you want Linux to invalidate primary core D-Cache during Linux
++ decompression and boot.
++
++config IPROC_TIMER_UNIT_TESTS
++ bool "Include iProc Timer unit test code"
++ help
++ Say Y if you want to test the AON,Peripheral Timer modules using the sysfs interface
++
++config IPROC_SW_RESET_RECORD
++ bool "Include Software Reset Records"
++ help
++ Say Y if you want to enable interface to access Software Reset Record.
++ Software Reset Record is a set of variables whose value could be retained
++ after reset (but will be cleared if powered off).
++
++config BRCM_PROP_MODULES
++ bool "Include Broadcom proprietary modules"
++ default n
++ help
++ Say Y if you want to include the Broadcom proprietary modules.
++
++config BCM_STM
++ bool "Enable System Trace Module"
++ default n
++ help
++ Say Y if you want to enable the Broadcom System Trace Module
++
++config DMAC_PL330
++ bool "PL330 DMAC driver support for Kona architecture"
++ depends on ARCH_RHEA
++ select PL330
++ help
++ Support for PL330 DMA Controller driver for Rhea SOC/KONA architecture
++
++config BCM_ZRELADDR
++ hex "Compressed ZREL address"
++
++config BCM_PARAMS_PHYS
++ hex "Address where tagged parameters are to be found"
++
++config BCM_RAM_BASE
++ hex "RAM base address"
++ help
++ Set the physical base address of RAM
++
++config BCM_RAM_START_RESERVED_SIZE
++ hex "RAM start reserved memory size in bytes"
++ default 0
++ help
++ Reserve memory at the start of RAM. This memory
++ may be used for LCD frame buffer, DSP, modem, etc.
++
++#source "drivers/bcmdrivers/Kconfig"
++
++endmenu
+diff --git a/arch/arm/plat-iproc/Makefile b/arch/arm/plat-iproc/Makefile
+new file mode 100644
+index 0000000..2474a9d
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Makefile.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Makefile.patch
new file mode 100644
index 00000000..3d8ae55f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_Makefile.patch
@@ -0,0 +1,23 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/Makefile
+@@ -0,0 +1,17 @@
++
++
++# obj-y := irq.o iproc_timer.o timer.o sysfs.o
++obj-y := irq.o timer-sp.o sysfs.o bcm5301x.o iproc-cache.o headsmp.o shm.o
++obj-$(CONFIG_SMP) += platsmp.o
++
++
++obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
++obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
++obj-$(CONFIG_USB_GADGET_DWC_OTG) += lm.o
++obj-$(CONFIG_HAVE_CLK) += clock.o
++obj-$(CONFIG_ARCH_IPROC) += iproc_cru.o
++obj-$(CONFIG_IPROC_SW_RESET_RECORD) += swreset_rec.o
++
++export DRIVERS_MMC_HOST_DIR := drivers/mmc/host/
++export DRIVERS_MTD_DIR := drivers/mtd/
++# obj-y+=../../../../../bcmdrivers/
+diff --git a/arch/arm/plat-iproc/bcm5301x.c b/arch/arm/plat-iproc/bcm5301x.c
+new file mode 100644
+index 0000000..87ae083
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_bcm5301x.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_bcm5301x.c.patch
new file mode 100644
index 00000000..c17f2d9c
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_bcm5301x.c.patch
@@ -0,0 +1,90 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/bcm5301x.c
+@@ -0,0 +1,84 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++#include
++
++void __init iproc_map_io(void)
++{
++ struct map_desc desc ;
++ phys_addr_t base_addr;
++
++ /*
++ * Cortex A9 Architecture Manual specifies this as a way to get
++ * MPCORE PERHIPHBASE address at run-time
++ */
++ asm( "mrc p15,4,%0,c15,c0,0 @ Read Configuration Base Address Register"
++ : "=&r" (base_addr) : : "cc" );
++
++ printk(KERN_INFO "MPCORE found at %p\n", (void *)base_addr);
++
++ /* Fix-map the entire PERIPHBASE 2*4K register block */
++ desc.virtual = IPROC_PERIPH_VA;
++ desc.pfn = __phys_to_pfn(base_addr);
++ desc.length = SZ_8K;
++ desc.type = MT_DEVICE ;
++
++ iotable_init(&desc, 1);
++}
++
++static int iproc_data_abort_handler(unsigned long addr, unsigned int fsr,
++ struct pt_regs *regs)
++{
++ /*
++ * These happen for no good reason
++ */
++// printk(KERN_WARNING "Data abort at addr=%#lx, fsr=%#x ignored.\n", addr, fsr);
++ return 0;
++}
++
++void __init iproc_enable_data_prefetch_aborts(void)
++{
++ u32 x;
++
++ /* Install our hook */
++ hook_fault_code(16 + 6, iproc_data_abort_handler, SIGBUS, 0,
++ "imprecise external data abort");
++
++ /* Enable external aborts - clear "A" bit in CPSR */
++
++ /* Read CPSR */
++// asm("mrs %0,cpsr": "=&r" (x) : : );
++ asm("mrs %0,cpsr": "=&r" (x) );
++
++ x &= ~ PSR_A_BIT;
++
++ /* Update CPSR, affect bits 8-15 */
++ asm("msr cpsr_x,%0; nop; nop": : "r" (x) : "cc");
++
++}
+diff --git a/arch/arm/plat-iproc/clock.c b/arch/arm/plat-iproc/clock.c
+new file mode 100644
+index 0000000..98da8f5
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_clock.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_clock.c.patch
new file mode 100644
index 00000000..de6a28ae
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_clock.c.patch
@@ -0,0 +1,171 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/clock.c
+@@ -0,0 +1,165 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++#include
++
++int clk_enable(struct clk *clk)
++{
++ int ret ;
++
++ ret = atomic_inc_return(&clk->ena_cnt);
++ if (ret > 1)
++ return 0;
++ /* Continue of count was moved from 0 to 1 - reentrant */
++ if (clk->parent)
++ ret = clk_enable( clk->parent );
++ else
++ ret = 0;
++
++ if (ret == 0) {
++ if (!clk->ops || !clk->ops->enable) {
++ if (clk->rate)
++ ret = 0 ;
++ else {
++ if (clk_get_rate(clk))
++ ret = 0;
++ else
++ ret = -EIO;
++ }
++ } else {
++ ret = clk->ops->enable(clk);
++ }
++ }
++
++ if (ret != 0)
++ atomic_dec(&clk->ena_cnt);
++
++ return ret ;
++}
++
++EXPORT_SYMBOL(clk_enable);
++
++void clk_disable(struct clk *clk)
++{
++ int ret ;
++
++ ret = atomic_dec_return(&clk->ena_cnt);
++
++ /* Continue if this is the last client to disable - reentrant */
++ if (ret > 0)
++ return ;
++ BUG_ON(ret < 0);
++
++ if (!clk->ops || !clk->ops->disable)
++ return;
++
++ clk->ops->disable(clk);
++
++ if (clk->parent)
++ clk_disable(clk->parent);
++
++ return ;
++}
++
++EXPORT_SYMBOL(clk_disable);
++
++unsigned long clk_get_rate(struct clk *clk)
++{
++#ifndef CONFIG_MACH_CYGNUS
++ /* Recurse to update parent's frequency */
++ if (clk->parent)
++ clk_get_rate(clk->parent);
++
++ /* Read hardware registers if needed */
++ if (clk->ops && clk->ops->status)
++ clk->ops->status(clk);
++#endif
++
++#ifdef CONFIG_MACH_CYGNUS
++ printk(KERN_INFO "INFO-Cygnus:%d:%s() clk->name= %s clk->rate= %d\n", __LINE__, __func__, clk->name, clk->rate);
++#endif
++ return clk->rate;
++
++}
++
++EXPORT_SYMBOL(clk_get_rate);
++
++long clk_round_rate(struct clk *clk, unsigned long rate)
++{
++ long ret = -EIO;
++
++ if (clk->ops && clk->ops->round)
++ ret = clk->ops->round(clk, rate);
++
++ return ret;
++}
++
++EXPORT_SYMBOL(clk_round_rate);
++
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int ret = -EIO;
++
++ if (rate == clk->rate)
++ return 0;
++
++ if (clk->ops && clk->ops->setrate)
++ ret = clk->ops->setrate(clk, rate);
++
++ return ret;
++}
++
++EXPORT_SYMBOL(clk_set_rate);
++
++/*
++ * clk_get(), clk_put() are implemented in arch/arm/common/clock.c
++ * but it needs these two stub functions for platform-specific operations.
++ * Reeturn 1 on success 0 on failure.
++ */
++
++int __clk_get(struct clk *clk)
++{
++ int ret ;
++
++ ret = atomic_inc_return( &clk->use_cnt );
++ if (ret > 1)
++ return 1;
++
++ if (clk->parent)
++ return __clk_get( clk->parent );
++
++ return 1;
++}
++
++void __clk_put(struct clk *clk)
++{
++ int ret;
++
++ ret = atomic_dec_return( &clk->use_cnt);
++ if (ret > 0)
++ return;
++
++ BUG_ON(ret < 0);
++
++ if (clk->parent)
++ __clk_put(clk->parent);
++}
+diff --git a/arch/arm/plat-iproc/headsmp.S b/arch/arm/plat-iproc/headsmp.S
+new file mode 100644
+index 0000000..4cf0efa
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_headsmp.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_headsmp.S.patch
new file mode 100644
index 00000000..fb9d8c07
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_headsmp.S.patch
@@ -0,0 +1,112 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/headsmp.S
+@@ -0,0 +1,106 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/* Based on arch/arm/mach-realview/headsmp.S */
++/*
++ * linux/arch/arm/mach-realview/headsmp.S
++ *
++ * Copyright (c) 2003 ARM Limited
++ * All Rights Reserved
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include
++#include
++#include
++#include
++#include
++
++/*
++ * This is called from head.S to fix the u-boot not initializing
++ * MMU and cache the way Linux likes it to be. I have talked to
++ * u-boot developer to fix it in u-boot. This will remain as a
++ * safety. Don't use r1 and r2 as u-boot/CFE may pass some parameters
++ * for the kernel.
++ * When this code completes execution, we expect the following:
++ * MMU = OFF
++ * D-Cache = OFF
++ * I-Cache = Don't Care
++ * regs r0 = 0 r1 = machine id and r2 = atags pointer or 0
++ */
++ __HEAD
++ENTRY(__iproc_head_fixup)
++ mov r12, lr @ Save the return address
++ mrc p15, 0, r8, c1, c0, 0 @ Read SCTLR
++ mrc p15, 0, r9, c1, c0, 1 @ Read ACTLR
++ mrc p15, 0, r10, c2, c0, 0 @ Read TTBR0
++ mrc p15, 0, r11, c2, c0, 1 @ Read TTBR1
++ mrc p15, 0, r7, c2, c0, 2 @ Read TTBCR
++ mov r0, r8
++ bic r0, #CR_C||CR_M
++ mcr p15, 0, r0, c1, c0, 0 @ Write the control register
++ nop
++ mrc p15, 0, r0, c1, c0, 0 @ Read the control register
++ bic r0, #CR_C|CR_A|CR_M|CR_W
++ bic r0, #CR_I|CR_Z
++ mcr p15, 0, r0, c1, c0, 0 @ Write the control register
++ nop
++ mov r0, #0
++ @ L2 cache controller control register
++ ldr r3, =IPROC_L2CC_REG_BASE
++ str r0, [r3, #0x100] @ Disable L2 cache
++ bl __v7_invalidate_dcache_all
++
++ mov r0, #0
++ mov pc, r12 @ Return for regular boot
++ nop
++ENDPROC(__iproc_head_fixup)
++
++/*
++ * iProc specific entry point for secondary CPUs. This provides
++ * a "holding pen" into which all secondary cores are held until we're
++ * ready for them to initialise.
++ */
++#ifdef CONFIG_SMP
++ENTRY(iproc_secondary_startup)
++#ifdef CONFIG_CPU_ENDIAN_BE8
++ setend be
++#endif
++ bl v7_invalidate_l1
++ bl v7_flush_dcache_all
++ mrc p15, 0, r0, c0, c0, 5
++ and r0, r0, #15
++ adr r4, 1f
++ ldmia r4, {r5, r6}
++ sub r4, r4, r5
++ add r6, r6, r4
++pen: ldr r7, [r6]
++ cmp r7, r0
++ bne pen
++
++ /*
++ * we've been released from the holding pen: secondary_stack
++ * should now contain the SVC stack for this core
++ */
++ b secondary_startup
++
++1: .long .
++ .long pen_release
++
++ENDPROC(iproc_secondary_startup)
++#endif
+diff --git a/arch/arm/plat-iproc/hotplug.c b/arch/arm/plat-iproc/hotplug.c
+new file mode 100644
+index 0000000..94dd062
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_hotplug.c.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_hotplug.c.patch
new file mode 100644
index 00000000..775242dd
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_hotplug.c.patch
@@ -0,0 +1,153 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/hotplug.c
+@@ -0,0 +1,147 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include
++#include
++#include
++#include
++
++#include
++
++extern volatile int pen_release;
++
++static DECLARE_COMPLETION(cpu_killed);
++
++static inline void cpu_enter_lowpower(void)
++{
++ unsigned int v;
++
++ flush_cache_all();
++ asm volatile(
++ " mcr p15, 0, %1, c7, c5, 0\n"
++ " mcr p15, 0, %1, c7, c10, 4\n"
++ /*
++ * Turn off coherency
++ */
++ " mrc p15, 0, %0, c1, c0, 1\n"
++ " bic %0, %0, #0x20\n"
++ " mcr p15, 0, %0, c1, c0, 1\n"
++ " mrc p15, 0, %0, c1, c0, 0\n"
++ " bic %0, %0, #0x04\n"
++ " mcr p15, 0, %0, c1, c0, 0\n"
++ : "=&r" (v)
++ : "r" (0)
++ : "cc");
++}
++
++static inline void cpu_leave_lowpower(void)
++{
++ unsigned int v;
++
++ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
++ " orr %0, %0, #0x04\n"
++ " mcr p15, 0, %0, c1, c0, 0\n"
++ " mrc p15, 0, %0, c1, c0, 1\n"
++ " orr %0, %0, #0x20\n"
++ " mcr p15, 0, %0, c1, c0, 1\n"
++ : "=&r" (v)
++ :
++ : "cc");
++}
++
++static inline void platform_do_lowpower(unsigned int cpu)
++{
++ /*
++ * there is no power-control hardware on this platform, so all
++ * we can do is put the core into WFI; this is safe as the calling
++ * code will have already disabled interrupts
++ */
++ for (;;) {
++ /*
++ * here's the WFI
++ */
++ asm(".inst 0xe320f003\n"
++ :
++ :
++ : "memory", "cc");
++
++ if (pen_release == cpu) {
++ /*
++ * OK, proper wakeup, we're done
++ */
++ break;
++ }
++
++ /*
++ * getting here, means that we have come out of WFI without
++ * having been woken up - this shouldn't happen
++ *
++ * The trouble is, letting people know about this is not really
++ * possible, since we are currently running incoherently, and
++ * therefore cannot safely call printk() or anything else
++ */
++#ifdef DEBUG
++ printk("CPU%u: spurious wakeup call\n", cpu);
++#endif
++ }
++}
++
++int platform_cpu_kill(unsigned int cpu)
++{
++ return wait_for_completion_timeout(&cpu_killed, 5000);
++}
++
++/*
++ * platform-specific code to shutdown a CPU
++ *
++ * Called with IRQs disabled
++ */
++void platform_cpu_die(unsigned int cpu)
++{
++#ifdef DEBUG
++ unsigned int this_cpu = hard_smp_processor_id();
++
++ if (cpu != this_cpu) {
++ printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
++ this_cpu, cpu);
++ BUG();
++ }
++#endif
++
++ printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
++ complete(&cpu_killed);
++
++ /*
++ * we're ready for shutdown now, so do it
++ */
++ cpu_enter_lowpower();
++ platform_do_lowpower(cpu);
++
++ /*
++ * bring this CPU back into the world of cache
++ * coherency, and then restore interrupts
++ */
++ cpu_leave_lowpower();
++}
++
++int platform_cpu_disable(unsigned int cpu)
++{
++ /*
++ * we don't allow CPU 0 to be shutdown (it is still too special
++ * e.g. clock tick interrupts)
++ */
++ return cpu == 0 ? -EPERM : 0;
++}
+diff --git a/arch/arm/plat-iproc/include/mach/brcm_rdb_rng.h b/arch/arm/plat-iproc/include/mach/brcm_rdb_rng.h
+new file mode 100644
+index 0000000..c17e951
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_brcm_rdb_rng.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_brcm_rdb_rng.h.patch
new file mode 100644
index 00000000..38227ca9
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_brcm_rdb_rng.h.patch
@@ -0,0 +1,70 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/brcm_rdb_rng.h
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __BRCM_RDB_RNG_H__
++#define __BRCM_RDB_RNG_H__
++
++#define RNG_CTRL_OFFSET 0x00000000
++#define RNG_CTRL_TYPE UInt32
++#define RNG_CTRL_RESERVED_MASK 0xF00000CC
++#define RNG_CTRL_RNG_COMBLK2_OSC_DIS_SHIFT 22
++#define RNG_CTRL_RNG_COMBLK2_OSC_DIS_MASK 0x0FC00000
++#define RNG_CTRL_RNG_COMBLK1_OSC_DIS_SHIFT 16
++#define RNG_CTRL_RNG_COMBLK1_OSC_DIS_MASK 0x003F0000
++#define RNG_CTRL_RNG_JCLK_BYP_DIV_CNT_SHIFT 8
++#define RNG_CTRL_RNG_JCLK_BYP_DIV_CNT_MASK 0x0000FF00
++#define RNG_CTRL_RNG_JCLK_BYP_SRC_SHIFT 5
++#define RNG_CTRL_RNG_JCLK_BYP_SRC_MASK 0x00000020
++#define RNG_CTRL_RNG_JCLK_BYP_SEL_SHIFT 4
++#define RNG_CTRL_RNG_JCLK_BYP_SEL_MASK 0x00000010
++#define RNG_CTRL_RNG_RBG2X_SHIFT 1
++#define RNG_CTRL_RNG_RBG2X_MASK 0x00000002
++#define RNG_CTRL_RNG_RBGEN_SHIFT 0
++#define RNG_CTRL_RNG_RBGEN_MASK 0x00000001
++
++#define RNG_STATUS_OFFSET 0x00000004
++#define RNG_STATUS_TYPE UInt32
++#define RNG_STATUS_RESERVED_MASK 0x00F00000
++#define RNG_STATUS_RND_VAL_SHIFT 24
++#define RNG_STATUS_RND_VAL_MASK 0xFF000000
++#define RNG_STATUS_RNG_WARM_CNT_SHIFT 0
++#define RNG_STATUS_RNG_WARM_CNT_MASK 0x000FFFFF
++
++#define RNG_DATA_OFFSET 0x00000008
++#define RNG_DATA_TYPE UInt32
++#define RNG_DATA_RESERVED_MASK 0x00000000
++#define RNG_DATA_RNG_NUM_SHIFT 0
++#define RNG_DATA_RNG_NUM_MASK 0xFFFFFFFF
++
++#define RNG_FF_THRES_OFFSET 0x0000000C
++#define RNG_FF_THRES_TYPE UInt32
++#define RNG_FF_THRES_RESERVED_MASK 0xFFFFFFE0
++#define RNG_FF_THRES_RNG_FF_THRESH_SHIFT 0
++#define RNG_FF_THRES_RNG_FF_THRESH_MASK 0x0000001F
++
++#define RNG_INT_MASK_OFFSET 0x00000010
++#define RNG_INT_MASK_TYPE UInt32
++#define RNG_INT_MASK_RESERVED_MASK 0xFFFFFFFE
++#define RNG_INT_MASK_RNG_INT_OFF_SHIFT 0
++#define RNG_INT_MASK_RNG_INT_OFF_MASK 0x00000001
++
++#endif /* __BRCM_RDB_RNG_H__ */
+diff --git a/arch/arm/plat-iproc/include/mach/bridge-regs.h b/arch/arm/plat-iproc/include/mach/bridge-regs.h
+new file mode 100644
+index 0000000..1d2299b
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_bridge-regs.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_bridge-regs.h.patch
new file mode 100644
index 00000000..7b6375ab
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_bridge-regs.h.patch
@@ -0,0 +1,74 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/bridge-regs.h
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/*
++ * Mbus-L to Mbus Bridge Registers
++ *
++ */
++
++#ifndef __ASM_ARCH_BRIDGE_REGS_H
++#define __ASM_ARCH_BRIDGE_REGS_H
++
++#include
++
++#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
++
++#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
++#define CPU_CTRL_PCIE0_LINK 0x00000001
++#define CPU_RESET 0x00000002
++#define CPU_CTRL_PCIE1_LINK 0x00000008
++
++#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
++#define SOFT_RESET_OUT_EN 0x00000004
++
++#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
++#define SOFT_RESET 0x00000001
++
++#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
++#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
++#define BRIDGE_INT_TIMER0 0x0002
++#define BRIDGE_INT_TIMER1 0x0004
++#define BRIDGE_INT_TIMER1_CLR (~0x0004)
++
++#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
++#define IRQ_CAUSE_LOW_OFF 0x0000
++#define IRQ_MASK_LOW_OFF 0x0004
++#define FIQ_MASK_LOW_OFF 0x0008
++#define ENDPOINT_MASK_LOW_OFF 0x000c
++#define IRQ_CAUSE_HIGH_OFF 0x0010
++#define IRQ_MASK_HIGH_OFF 0x0014
++#define FIQ_MASK_HIGH_OFF 0x0018
++#define ENDPOINT_MASK_HIGH_OFF 0x001c
++#define PCIE_INTERRUPT_MASK_OFF 0x0020
++
++#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
++#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
++#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
++#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
++#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
++#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
++#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
++
++#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
++
++#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
++
++#endif
+diff --git a/arch/arm/plat-iproc/include/mach/clkdev.h b/arch/arm/plat-iproc/include/mach/clkdev.h
+new file mode 100644
+index 0000000..d77f186
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clkdev.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clkdev.h.patch
new file mode 100644
index 00000000..6ea65748
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clkdev.h.patch
@@ -0,0 +1,49 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/clkdev.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __MACH_CLKDEV_H
++#define __MACH_CLKDEV_H
++
++#include
++#include
++
++struct clk {
++ const struct clk_ops *ops;
++ const char *name;
++ atomic_t ena_cnt;
++ atomic_t use_cnt;
++ unsigned long rate;
++ unsigned gated :1;
++ unsigned fixed :1;
++ unsigned chan :6;
++ void __iomem *regs_base;
++ struct clk *parent;
++ /* TBD: could it have multiple parents to select from ? */
++ enum {
++ CLK_XTAL, CLK_GATE, CLK_PLL, CLK_DIV, CLK_PHA
++ } type;
++};
++
++extern int __clk_get(struct clk *);
++extern void __clk_put(struct clk *);
++
++#endif
+diff --git a/arch/arm/plat-iproc/include/mach/clock.h b/arch/arm/plat-iproc/include/mach/clock.h
+new file mode 100644
+index 0000000..3ad8a76
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clock.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clock.h.patch
new file mode 100644
index 00000000..5018d5fc
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_clock.h.patch
@@ -0,0 +1,41 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/clock.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef CLOCK_H
++#define CLOCK_H
++
++#include
++
++/*
++ * Operations on clocks -
++ * See for description
++ */
++struct clk_ops {
++ int (* enable)(struct clk *);
++ void (* disable)(struct clk *);
++ long (* round)(struct clk *, unsigned long);
++ int (* setrate)(struct clk *, unsigned long);
++ /* Update current rate and return running status */
++ int (* status)(struct clk *);
++};
++
++#endif
+diff --git a/arch/arm/plat-iproc/include/mach/common.h b/arch/arm/plat-iproc/include/mach/common.h
+new file mode 100644
+index 0000000..69f8f95
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_common.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_common.h.patch
new file mode 100644
index 00000000..0a644892
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_common.h.patch
@@ -0,0 +1,57 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/common.h
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/*
++ *
++ * Core functions for Broadcom Northstar SoC Chip
++ */
++
++#ifndef __ARCH_IPROC_COMMON_H
++#define __ARCH_IPROC_COMMON_H
++
++struct mv643xx_eth_platform_data;
++struct mv_sata_platform_data;
++
++extern struct sys_timer IPROC_timer;
++extern struct mbus_dram_target_info iproc_mbus_dram_info;
++
++/*
++ * Basic IPROC init functions used early by machine-setup.
++ */
++void IPROC_map_io(void);
++void IPROC_init(void);
++void IPROC_init_irq(void);
++void IPROC_setup_cpu_mbus(void);
++void IPROC_ge00_init(struct mv643xx_eth_platform_data *eth_data);
++void IPROC_sata_init(struct mv_sata_platform_data *sata_data);
++void IPROC_pcie_init(int init_port0, int init_port1);
++void IPROC_ehci0_init(void);
++void IPROC_ehci1_init(void);
++void IPROC_uart0_init(void);
++void IPROC_uart1_init(void);
++void IPROC_uart2_init(void);
++void IPROC_uart3_init(void);
++void IPROC_spi0_init(void);
++void IPROC_spi1_init(void);
++void IPROC_i2c_init(void);
++
++#endif
+diff --git a/arch/arm/plat-iproc/include/mach/debug-macro.S b/arch/arm/plat-iproc/include/mach/debug-macro.S
+new file mode 100644
+index 0000000..6c963a4
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_debug-macro.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_debug-macro.S.patch
new file mode 100644
index 00000000..dbb5963a
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_debug-macro.S.patch
@@ -0,0 +1,41 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/debug-macro.S
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/*
++ * Debugging macro include header
++ */
++#include
++#include
++#include
++
++ .macro addruart, tmp, tmp2, rx
++ ldr \tmp, =IPROC_UART_LLDEBUG_PA @ MMU off, Physical
++ ldr \tmp2, =IPROC_UART_LLDEBUG_VA @ MMU on, Virtual
++ .endm
++
++#chandra:
++#ifdef CONFIG_MACH_CYGNUS
++ #define UART_SHIFT 2 //for synopsysUart has 4 byte addressing
++#else
++ #define UART_SHIFT 0 //for CCA_UART has 1 byte addressing
++#endif
++
++#include
+diff --git a/arch/arm/plat-iproc/include/mach/entry-macro.S b/arch/arm/plat-iproc/include/mach/entry-macro.S
+new file mode 100644
+index 0000000..d859b49
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_entry-macro.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_entry-macro.S.patch
new file mode 100644
index 00000000..e16ade85
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_entry-macro.S.patch
@@ -0,0 +1,105 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/entry-macro.S
+@@ -0,0 +1,99 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include
++#include
++
++ .macro disable_fiq
++ .endm
++
++ /*
++ * This is the interrupt handling part of the GIC code -
++ * the base_va exists in a variable, but here is defined
++ * at compile time for effeciency (?)
++ */
++
++ .macro get_irqnr_preamble, base, tmp
++ ldr \base, =IPROC_GICCPU_VA
++ .endm
++
++ /*
++ * Interrupts 0-15 are IPI
++ * 16-31 are local
++ * 32-1020 are global
++ * 1021-1022 are reserved
++ * 1023 is "spurious" (no interrupt)
++ *
++ * Spurious interrupt must be ignored in all events.
++ * When in SMP mode, then IPI interrupts must be ignored here,
++ * amd picked up later with the test_for_ipi macro.
++ * When in SMP mode and local timers are enabled,
++ * the private timer/watchdog interrupt must be ignored here
++ * so it can be handled later in test_for_ltirq routine.
++ *
++ * A simple read from the controller will tell us the number of the
++ * highest priority enabled interrupt. We then just need to check
++ * whether it is in the range that must be handled.
++ *
++ * Upon return, Z=1 tells to ignore this interrupt
++ */
++
++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
++
++ /* bits 12-10 = src CPU, 9-0 = int # */
++ ldr \irqstat, [\base, #GIC_CPU_INTACK]
++ ldr \tmp, =1021
++
++ bic \irqnr, \irqstat, #0x1c00
++
++ /* Private timers to call do_local_timer() */
++ cmp \irqnr, #29
++ beq 29f
++
++ /* SPI to call asm_do_IRQ(); IPI to call do_IPI() */
++ cmp \irqnr, #15
++ cmpcc \irqnr, \irqnr
++ cmpne \irqnr, \tmp
++ cmpcs \irqnr, \irqnr
++
++ /* SPI if NE; IPI (0-15) or private timer (29) if EQ */
++29:
++ .endm
++
++ @code taken from realview/entry-macro.S
++ /* We assume that irqstat (the raw value of the IRQ acknowledge
++ * register) is preserved from the macro above.
++ * If there is an IPI, we immediately signal end of interrupt on the
++ * controller, since this requires the original irqstat value which
++ * we won't easily be able to recreate later.
++ */
++ .macro test_for_ipi, irqnr, irqstat, base, tmp
++ bic \irqnr, \irqstat, #0x1c00
++ cmp \irqnr, #16
++ strcc \irqstat, [\base, #GIC_CPU_EOI]
++ cmpcs \irqnr, \irqnr
++ .endm
++
++ .macro test_for_ltirq, irqnr, irqstat, base,tmp
++ bic \irqnr, \irqstat, #0x1c00
++ mov \tmp, #0
++ cmp \irqnr, #29
++ moveq \tmp, #1
++ streq \irqstat, [\base, #GIC_CPU_EOI]
++ cmp \tmp, #0
++ .endm
++
++ .macro arch_ret_to_user, tmp1, tmp2
++ .endm
+diff --git a/arch/arm/plat-iproc/include/mach/gpio.h b/arch/arm/plat-iproc/include/mach/gpio.h
+new file mode 100644
+index 0000000..326b73c
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_gpio.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_gpio.h.patch
new file mode 100644
index 00000000..811aa9ba
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_gpio.h.patch
@@ -0,0 +1,36 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/gpio.h
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_GPIO_H
++#define __PLAT_GPIO_H
++
++#include
++#include
++
++#include
++
++
++#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
++//#define gpio_get_value(gpio) __gpio_get_value(gpio)
++//#define gpio_set_value(gpio,value) __gpio_set_value(gpio,value)
++//#define gpio_cansleep(gpio) __gpio_cansleep(gpio)
++
++#endif
+diff --git a/arch/arm/plat-iproc/include/mach/hardware.h b/arch/arm/plat-iproc/include/mach/hardware.h
+new file mode 100644
+index 0000000..b373b58
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_hardware.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_hardware.h.patch
new file mode 100644
index 00000000..9baa1080
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_hardware.h.patch
@@ -0,0 +1,49 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/hardware.h
+@@ -0,0 +1,43 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_HARDWARE_H
++#define __PLAT_IPROC_HARDWARE_H
++
++#include
++#include
++#include
++
++/* Hardware addresses of major areas.
++ * *_START is the physical address
++ * *_SIZE is the size of the region
++ * *_BASE is the virtual address
++ */
++#define RAM_START PHYS_OFFSET
++
++#define RAM_BASE PAGE_OFFSET
++
++#define IO_START IO_START_PA
++#define IO_BASE IO_START_VA
++
++/* In case we use physical addresses */
++#define IO_ADDRESS(x) (x)
++
++#define pcibios_assign_all_busses() 1
++
++#define PCIBIOS_MIN_IO 0x1000
++#define PCIBIOS_MIN_MEM 0x01000000
++
++#endif /* __PLAT_IPROC_HARDWARE_H */
+diff --git a/arch/arm/plat-iproc/include/mach/io.h b/arch/arm/plat-iproc/include/mach/io.h
+new file mode 100644
+index 0000000..b980406
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_io.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_io.h.patch
new file mode 100644
index 00000000..51ae7c3f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_io.h.patch
@@ -0,0 +1,41 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/io.h
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_IO_H
++#define __PLAT_IPROC_IO_H
++
++#define IO_SPACE_LIMIT (0xffffffff)
++
++#define __io(a) __typesafe_io(a)
++#define __mem_pci(a) (a)
++
++#ifdef __ASSEMBLER__
++#define IOMEM(x) (x)
++#else
++#define IOMEM(x) ((void __force __iomem *)(x))
++#endif
++
++#define VC_DIRECT_ACCESS_BASE 0xC0000000UL
++#define ARM_VC_PHYS_ADDR_BASE 0x40000000UL
++#define __VC_BUS_TO_ARM_PHYS_ADDR(x) ((x) - (VC_DIRECT_ACCESS_BASE) + \
++ (ARM_VC_PHYS_ADDR_BASE))
++
++#endif /*__PLAT_IPROC_IO_H */
+diff --git a/arch/arm/plat-iproc/include/mach/iproc.h b/arch/arm/plat-iproc/include/mach/iproc.h
+new file mode 100644
+index 0000000..bf01f6e
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc.h.patch
new file mode 100644
index 00000000..1d561ecd
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc.h.patch
@@ -0,0 +1,32 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/iproc.h
+@@ -0,0 +1,26 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_H
++#define __PLAT_IPROC_H
++
++#include
++
++extern struct sys_timer iproc_timer;
++
++extern void __init iproc_init_irq(void);
++//static void __init gic_dist_init(struct gic_chip_data *gic);
++
++#endif /* __PLAT_IPROC_H */
+diff --git a/arch/arm/plat-iproc/include/mach/iproc_timer.h b/arch/arm/plat-iproc/include/mach/iproc_timer.h
+new file mode 100644
+index 0000000..5809403
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc_timer.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc_timer.h.patch
new file mode 100644
index 00000000..609e8db9
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_iproc_timer.h.patch
@@ -0,0 +1,154 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/iproc_timer.h
+@@ -0,0 +1,148 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_TIMER_H
++#define __PLAT_IPROC_TIMER_H
++
++/* Timer module specific data structures */
++enum timer_rate {
++ KHZ_32 = 0,
++ MHZ_1,
++ MHZ_19_5,
++};
++
++struct iproc_timer;
++
++/* Channel specific data structures */
++typedef int (*intr_callback)(void *data);
++
++enum timer_mode {
++ MODE_PERIODIC=0,
++ MODE_ONESHOT,
++};
++
++struct timer_ch_cfg {
++ void *arg;
++ enum timer_mode mode;
++ intr_callback cb;
++ unsigned long reload; /* Holds the reload value in
++ * case of periodic timers
++ */
++};
++
++/* Timer Module related APIs */
++
++/*
++ * USAGE OF THIS APIs
++ * ------------------
++ * From the board specific file, the iproc_timer_modules_init will be called
++ * After that it will call the init function of timer.c and will pass the
++ * following information in a platform structure
++ * 1) Timer name to be used as system timer
++ * 2) Frequency to be configured for system timer
++ * 3) The channel of the timer to use as clock source (optional)
++ * 4) The channel of the timer to use as clock event (optional)
++ *
++ * from the init function of timer.c iproc_timer_modules_set_rate will be called
++ * to set the system timer frequency.
++ * Then the appropriate channels would be setup for clock source/event by
++ * calling iproc_timer_request()
++ */
++
++/*
++ * iproc_timer_modules_init - Initialize the data structures
++ * that depcits the iProc timer modules
++ */
++void iproc_timer_modules_init (void);
++
++/*
++ * iproc_timer_module_set_rate - Set the speed in which a timer module should count
++ * name - Name of the Timer to configure
++ * rate - Speed
++ */
++int iproc_timer_module_set_rate(char* name, enum timer_rate);
++
++/*
++ * iproc_timer_module_get_rate - Get the speed in which a timer module is running
++ * name - Name of the Timer module
++ */
++int iproc_timer_module_get_rate (char* name);
++
++
++/* Channel/Timer related APIs */
++/*
++ * iproc_timer_request - Get access to a channel in the given timer
++ * name - Name of the Timer module
++ * channel - Channel number requested. If this is -1 then by default
++ * the next available channel will be returned
++ */
++struct iproc_timer* iproc_timer_request(char* name, int channel);
++
++/*
++ * iproc_timer_config - Configure the following parameters of the timer
++ * 1) mode of the timer - periodic/one shot
++ * 2) call back function that will be called from the ISR context
++ * 3) context to be passed back in the call back function
++ *
++ * pit - iProc timer context (returned by iproc_timer_request())
++ * pcfg - pointer to the configuration structure
++ */
++int iproc_timer_config (struct iproc_timer *pit, struct timer_ch_cfg *pcfg);
++
++/*
++ * iproc_timer_set_match_start - Set the match register for the timer and start
++ * counting
++ *
++ * pit - iProc timer context (returned by iproc_timer_request())
++ * load - The load value to be programmed. This function will internally
++ * add this value to the current counter and program the resultant in the
++ * match register. Once the timer is started when the counter
++ * reaches this value an interrupt will be raised
++ */
++int iproc_timer_set_match_start (struct iproc_timer* pit, unsigned int load);
++
++/*
++ * iproc_timer_free - Read the counter register of the timer
++ *
++ * pit - Timer context to be freed.
++ * msw - pointer to the Most Significant Word (32 bits)
++ * lsw - pointer to the Leas Significant Word (32 bits)
++ */
++int iproc_timer_get_counter(struct iproc_timer* pit,
++ unsigned long *msw, unsigned long *lsw);
++/*
++ * iproc_timer_disable_and_clear - Disable the timer and clear the
++ * interrupt
++ *
++ * pit - Timer context to be freed.
++ */
++int iproc_timer_disable_and_clear(struct iproc_timer *pit);
++
++/*
++ * iproc_timer_stop - Stop the timer.
++ *
++ * pit - The timer context to be stopped.
++ */
++int iproc_timer_stop (struct iproc_timer* pit);
++
++/*
++ * iproc_timer_free - Release the timer, after this call the timer can be used
++ * again by others.
++ *
++ * pit - Timer context to be freed.
++ */
++int iproc_timer_free (struct iproc_timer* pit);
++
++#endif /* __PLAT_IPROC_TIMER_H */
+diff --git a/arch/arm/plat-iproc/include/mach/irqs.h b/arch/arm/plat-iproc/include/mach/irqs.h
+new file mode 100644
+index 0000000..4078b05
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_irqs.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_irqs.h.patch
new file mode 100644
index 00000000..6b781664
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_irqs.h.patch
@@ -0,0 +1,255 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/irqs.h
+@@ -0,0 +1,249 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_IRQS_H
++#define __PLAT_IPROC_IRQS_H
++
++#define IRQ_LOCALTIMER BCM_INT_ID_PPI13
++#define BCM_INT_PRIORITY_MAX 32 /* there are only 32 priority are supported */
++#define BCM_INT_SPI_MAX 128 /* there are 128 shared peripheral interrupt*/
++/*=====================================================================*/
++/* Software Trigger Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_STI0 0
++#define BCM_INT_ID_STI1 1
++#define BCM_INT_ID_STI2 2
++#define BCM_INT_ID_STI3 3
++#define BCM_INT_ID_STI4 4
++#define BCM_INT_ID_STI5 5
++#define BCM_INT_ID_STI6 6
++#define BCM_INT_ID_STI7 7
++#define BCM_INT_ID_STI8 8
++#define BCM_INT_ID_STI9 9
++#define BCM_INT_ID_STI10 10
++#define BCM_INT_ID_STI11 11
++#define BCM_INT_ID_STI12 12
++#define BCM_INT_ID_STI13 13
++#define BCM_INT_ID_STI14 14
++#define BCM_INT_ID_STI15 15
++#define BCM_INT_ID_STI_MAX 16 /* terminating ID */
++
++/*=====================================================================*/
++/* Private Peripheral Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_PPI0 ( 0 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI1 ( 1 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI2 ( 2 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI3 ( 3 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI4 ( 4 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI5 ( 5 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI6 ( 6 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI7 ( 7 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI8 ( 8 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI9 ( 9 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI10 (10 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI11 (11 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI12 (12 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI13 (13 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI14 (14 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI15 (15 + BCM_INT_ID_STI_MAX)
++#define BCM_INT_ID_PPI_MAX (16 + BCM_INT_ID_STI_MAX) /* terminating ID */
++
++/*=====================================================================*/
++/* iHost Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_IHOST_L2CC 32
++#define BCM_INT_ID_IHOST_PWRWDOG 33
++#define BCM_INT_ID_IHOST_TRAP8 34
++#define BCM_INT_ID_IHOST_TRAP1 35
++#define BCM_INT_ID_IHOST_COMMTX 36
++#define BCM_INT_ID_IHOST_COMMRX 38
++#define BCM_INT_ID_IHOST_PMU 40
++#define BCM_INT_ID_IHOST_CT 42
++#define BCM_INT_ID_IHOST_DEFFLG_CPU0 44
++#define BCM_INT_ID_IHOST_DEFFLG_CPU1 45
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define BCM_INT_ID_IHOST_CPU0_PAR 46
++#define BCM_INT_ID_IHOST_CPU1_PAR 47
++#define BCM_INT_ID_IHOST_SCU0_PAR 48
++#define BCM_INT_ID_IHOST_SCU1_PAR 49
++#define BCM_INT_ID_IHOST_I2_SEC 50
++#define BCM_INT_ID_IHOST_MAX 51 /* terminating ID */
++#else
++#define BCM_INT_ID_IHOST_MAX 46 /* terminating ID */
++#endif
++
++
++/*=====================================================================*/
++/* IDM Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_IHOST_M1 ( 0 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE0_M0 ( 1 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE1_M0 ( 2 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE2_M0 ( 3 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DMA_M0 ( 4 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_AMAC_M0 ( 5 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_AMAC_M1 ( 6 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_AMAC_M2 ( 7 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_AMAC_M3 ( 8 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_USBH_M0 ( 9 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_USBH_M1 (10 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_SDIO_M0 (11 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_I2S_M0 (12 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_A9JTAG_M0 (13 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_INIT_SEQ_M0 (14 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_JTAG_M0 (15 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_IHOST_ACP (16 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_IHOST_S0 (17 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DDR_S1 (18 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DDR_S2 (19 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE0_S0 (20 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE1_S0 (21 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_PCIE2_S0 (22 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_ROM_S0 (23 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_NAND_S0 (24 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_QPSI_S0 (25 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_A9JTAG_S0 (26 + BCM_INT_ID_IHOST_MAX)
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define BCM_INT_ID_SATA_S0 (27 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_SRAM_S0 (28+ BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_APBW (29 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_APBX (30 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_APBY (31 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_APBZ (32 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_0 (33 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_1 (34 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_2 (35 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_3 (36 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_4 (37 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_IDM_MAX (38 + BCM_INT_ID_IHOST_MAX)
++#elif defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP)
++#define BCM_INT_ID_APBX (27 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_0 (28 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_1 (29 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_2 (30 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_3 (31 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_DS_4 (32 + BCM_INT_ID_IHOST_MAX)
++#define BCM_INT_ID_IDM_MAX (33 + BCM_INT_ID_IHOST_MAX)
++#endif
++
++/*=====================================================================*/
++/* DDR Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_DDR_CONT (0 + BCM_INT_ID_IDM_MAX)
++#define BCM_INT_ID_DDR_MAX (1 + BCM_INT_ID_IDM_MAX)
++
++/*=====================================================================*/
++/* DMAC Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_DMAC (0 + BCM_INT_ID_DDR_MAX)
++#if defined(CONFIG_MACH_HX4) || defined(CONFIG_MACH_KT2) || \
++ defined(CONFIG_MACH_DNI_3448P) || defined(CONFIG_MACH_ACCTON_AS4610_54)
++#define BCM_INT_ID_DMAC_ABORT (16 + BCM_INT_ID_DDR_MAX)
++#define BCM_INT_ID_DMAC_MAX (17 + BCM_INT_ID_DDR_MAX)
++#elif defined(CONFIG_MACH_NS) || defined(CONFIG_MACH_NSP)
++#define BCM_INT_ID_DMAC_MAX (16 + BCM_INT_ID_DDR_MAX)
++#endif
++
++/*=====================================================================*/
++/* NAND Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_NAND2CORE_RD_MISS ( 0 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_ER_COMP ( 1 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_CB_COMP ( 2 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_PP_COMP ( 3 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_ROCTL_RDY ( 4 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_NAND_RBB ( 5 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_ECC_MIPS_UNCOR ( 6 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_ECC_MIPS_COR ( 7 + BCM_INT_ID_DMAC_MAX)
++#define BCM_INT_ID_NAND2CORE_MAX ( 8 + BCM_INT_ID_DMAC_MAX)
++
++/*=====================================================================*/
++/* QPSI Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_QPSI2CORE_FULL_RCHD ( 0 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_TRUNCATED ( 1 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_IMAPTIENT ( 2 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_SES_DONE ( 3 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_OVERREAD ( 4 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_MPSI_DONE ( 5 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_MPSI_HLT_SET ( 6 + BCM_INT_ID_NAND2CORE_MAX)
++#define BCM_INT_ID_QPSI2CORE_MAX ( 7 + BCM_INT_ID_NAND2CORE_MAX)
++
++/*=====================================================================*/
++/* USB2 Host Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_USB2H2CORE_USB2_INT (0 + BCM_INT_ID_QPSI2CORE_MAX)
++#define BCM_INT_ID_USB2H2CORE_MAX (1 + BCM_INT_ID_QPSI2CORE_MAX)
++
++/*=====================================================================*/
++/* USB3 Host Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_USB3H2CORE_USB2_INT0 (0 + BCM_INT_ID_USB2H2CORE_MAX)
++#define BCM_INT_ID_USB3H2CORE_USB2_INT1 (1 + BCM_INT_ID_USB2H2CORE_MAX)
++#define BCM_INT_ID_USB3H2CORE_USB2_INT2 (2 + BCM_INT_ID_USB2H2CORE_MAX)
++#define BCM_INT_ID_USB3H2CORE_USB2_INT3 (3 + BCM_INT_ID_USB2H2CORE_MAX)
++#define BCM_INT_ID_USB3H2CORE_USB2_HSE (4 + BCM_INT_ID_USB2H2CORE_MAX)
++#define BCM_INT_ID_USB3H2CORE_MAX (5 + BCM_INT_ID_USB2H2CORE_MAX)
++
++/*=====================================================================*/
++/* CCA Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_CCA_INT (0 + BCM_INT_ID_USB3H2CORE_MAX)
++#define BCM_INT_ID_CCA_MAX (1 + BCM_INT_ID_USB3H2CORE_MAX)
++
++/*=====================================================================*/
++/* CCB Interrupt IDs */
++/*=====================================================================*/
++#define BCM_INT_ID_CCB_UART0 (0 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_GPIO (1 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_I2S (2 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_SMBUS (3 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_TIM0_INT1 (4 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_TIM0_INT2 (5 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_TIM1_INT1 (6 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_TIM1_INT2 (7 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_RNG (8 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_SW_SOC (9 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_PCIE_INT0 (10 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_PCIE_INT1 (11 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_PCIE_INT2 (12 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_SDIO2CORE (13 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_CTF (14 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_GMAC_INT0 (15 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_GMAC_INT1 (16 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_GMAC_INT2 (17 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_GMAC_INT3 (18 + BCM_INT_ID_CCA_MAX)
++#define BCM_INT_ID_CCB_MAX (19 + BCM_INT_ID_CCA_MAX)
++
++#define BCM_INT_ID_FA 178
++
++
++#ifdef CONFIG_ARCH_REQUIRE_GPIOLIB
++#define IPROC_NR_IRQS (256)
++#define IPROC_IRQ_GPIO_0 (IPROC_NR_IRQS)
++#define IPROC_NR_GPIO_IRQS (32 + 4)
++#ifdef CONFIG_MACH_CYGNUS
++ #define NR_IRQS 256
++#else
++#define NR_IRQS (IPROC_NR_IRQS + IPROC_NR_GPIO_IRQS)
++#endif
++#else
++#define NR_IRQS 256
++#endif
++
++#endif /* __PLAT_IPROC_IRQS_H */
+diff --git a/arch/arm/plat-iproc/include/mach/lm.h b/arch/arm/plat-iproc/include/mach/lm.h
+new file mode 100644
+index 0000000..5c550a8
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_lm.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_lm.h.patch
new file mode 100644
index 00000000..5fe5c287
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_lm.h.patch
@@ -0,0 +1,54 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/lm.h
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _LM_DEVICE_H_
++#define _LM_DEVICE_H_
++
++#include
++#include
++
++
++struct lm_device {
++ struct device dev;
++ struct resource resource;
++ unsigned int irq;
++ unsigned int id;
++};
++
++struct lm_driver {
++ struct device_driver drv;
++ int (*probe) (struct lm_device *);
++ void (*remove) (struct lm_device *);
++ int (*suspend) (struct lm_device *, pm_message_t);
++ int (*resume) (struct lm_device *);
++};
++
++int lm_driver_register(struct lm_driver *drv);
++void lm_driver_unregister(struct lm_driver *drv);
++
++int lm_device_register(struct lm_device *dev);
++void lm_device_unregister(struct lm_device *dev);
++
++#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
++#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
++
++#endif /* _LM_DEVICE_H_ */
+diff --git a/arch/arm/plat-iproc/include/mach/memory.h b/arch/arm/plat-iproc/include/mach/memory.h
+new file mode 100644
+index 0000000..87bee64
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_memory.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_memory.h.patch
new file mode 100644
index 00000000..eadc8b6b
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_memory.h.patch
@@ -0,0 +1,84 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/memory.h
+@@ -0,0 +1,78 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __PLAT_IPROC_MEMORY_H
++#define __PLAT_IPROC_MEMORY_H
++
++#include
++
++//#define PHYS_OFFSET (CONFIG_BCM_RAM_BASE+CONFIG_BCM_RAM_START_RESERVED_SIZE)
++
++/* BCM5301x Reference Guide (Section 3) defines three regions of IO memory,
++ * CORE, IDM, and ARMCORE. The CORE and IDM regions are contiguous, so they
++ * are combined into a single region for mapping and translation purposes
++ */
++
++#define IO_CORE_IDM_PA 0x18000000
++#define IO_CORE_IDM_SIZE 0x200000
++#define IO_ARMCORE_PA 0x19000000
++#define IO_ARMCORE_SIZE 0x100000
++#define IO_SMAU_IDM_PA 0xf8100000
++#define IO_SMAU_IDM_SIZE 0x100000
++
++#define IO_TOTAL_SIZE (IO_CORE_IDM_SIZE + \
++ IO_ARMCORE_SIZE + \
++ IO_SMAU_IDM_SIZE)
++
++/* VA should be in the range of VMALLOC_START ~ VMALLOC_END-1 */
++#define IO_CORE_IDM_VA (VMALLOC_END - IO_TOTAL_SIZE)
++#define IO_ARMCORE_VA (IO_CORE_IDM_VA + IO_CORE_IDM_SIZE)
++#define IO_SMAU_IDM_VA (IO_ARMCORE_VA + IO_ARMCORE_SIZE)
++
++#define IO_CORE_IDM_PV_DELTA (IO_CORE_IDM_VA - IO_CORE_IDM_PA)
++#define IO_ARMCORE_PV_DELTA (IO_ARMCORE_VA - IO_ARMCORE_PA)
++#define IO_SMAU_IDM_PV_DELTA (IO_SMAU_IDM_VA - IO_SMAU_IDM_PA)
++
++#define HW_IO_VIRT_TO_PHYS(virt) \
++ (((virt) < IO_ARMCORE_VA) ? \
++ ((virt) - IO_CORE_IDM_PV_DELTA) : \
++ (((virt) < IO_SMAU_IDM_VA) ? \
++ ((virt) - IO_ARMCORE_PV_DELTA) : \
++ ((virt) - IO_SMAU_IDM_PV_DELTA)))
++
++/*
++ * HW_IO_PHYS_TO_VIRT used in asm, so the macro that performs this conversion
++ * is written using only simple math so that the assembler's constant folding
++ * can produce the correct result.
++
++ #define HW_IO_PHYS_TO_VIRT(phys) \
++ (((phys) < IO_ARMCORE_PA) ? \
++ ((phys) + IO_CORE_IDM_PV_DELTA) : \
++ ((phys) + IO_ARMCORE_PV_DELTA))
++ */
++
++#define HW_IO_PHYS_TO_VIRT(phys) \
++ (((phys) + IO_CORE_IDM_PV_DELTA) + \
++ (((phys) >= IO_ARMCORE_PA) * (IO_ARMCORE_PV_DELTA - IO_CORE_IDM_PV_DELTA)) + \
++ (((phys) >= IO_SMAU_IDM_PA) * (IO_SMAU_IDM_PV_DELTA - IO_ARMCORE_PV_DELTA)))
++
++#define CONSISTENT_DMA_SIZE SZ_128M
++
++#ifndef PHYS_RAM_SIZE
++#define PHYS_RAM_SIZE 0x08000000
++#endif
++
++#endif /* __PLAT_IPROC_MEMORY_H */
+diff --git a/arch/arm/plat-iproc/include/mach/sdio_platform.h b/arch/arm/plat-iproc/include/mach/sdio_platform.h
+new file mode 100644
+index 0000000..f8f17e1
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_sdio_platform.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_sdio_platform.h.patch
new file mode 100644
index 00000000..c65d3a3e
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_sdio_platform.h.patch
@@ -0,0 +1,73 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/sdio_platform.h
+@@ -0,0 +1,67 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef _SDIO_PLATFORM_H
++#define _SDIO_PLATFORM_H
++
++/*
++ * SDIO device type
++ */
++enum sdio_devtype {
++ SDIO_DEV_TYPE_SDMMC = 0,
++ SDIO_DEV_TYPE_WIFI,
++ SDIO_DEV_TYPE_EMMC,
++
++ /* used for internal array indexing, DO NOT modify */
++ SDIO_DEV_TYPE_MAX,
++};
++
++/*
++ * SDIO WiFi GPIO configuration
++ */
++struct sdio_wifi_gpio_cfg {
++ int reset;
++ int shutdown;
++ int reg;
++ int host_wake;
++};
++
++struct sdio_platform_cfg {
++ /* specify which SDIO device */
++ unsigned id;
++
++ /*
++ * For boards without the SDIO pullup registers, data_pullup needs to set
++ * to 1
++ */
++ unsigned int data_pullup;
++
++ /* for devices with 8-bit lines */
++ int is_8bit;
++
++ /* card detection GPIO, required for SD/MMC */
++ int cd_gpio;
++ enum sdio_devtype devtype;
++
++ /* clocks */
++ char *peri_clk_name;
++ char *ahb_clk_name;
++ char *sleep_clk_name;
++ unsigned long peri_clk_rate;
++
++ struct sdio_wifi_gpio_cfg wifi_gpio;
++};
++
++#endif /* SDIO_PLATFORM_H */
+diff --git a/arch/arm/plat-iproc/include/mach/smp.h b/arch/arm/plat-iproc/include/mach/smp.h
+new file mode 100644
+index 0000000..5a4b1f4
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_smp.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_smp.h.patch
new file mode 100644
index 00000000..16cfc53f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_smp.h.patch
@@ -0,0 +1,48 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/smp.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/*
++ * derived from arch/arm/mach-realview/include/mach/smp.h
++ */
++
++#ifndef __ASM_ARCH_SMP_H
++#define __ASM_ARCH_SMP_H __FILE__
++
++#include
++
++/*
++ * set_event() is used to wake up secondary core from wfe using sev. ROM
++ * code puts the second core into wfe(standby).
++ *
++ */
++#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
++
++extern void iproc_secondary_startup(void);
++
++#define hard_smp_processor_id() \
++ ({ \
++ unsigned int cpunum; \
++ __asm__("mrc p15, 0, %0, c0, c0, 5" \
++ : "=r" (cpunum)); \
++ cpunum &= 0x0F; \
++ })
++
++#endif /* __ASM_ARCH_SMP_H */
+diff --git a/arch/arm/plat-iproc/include/mach/system.h b/arch/arm/plat-iproc/include/mach/system.h
+new file mode 100644
+index 0000000..bdabd06
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_system.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_system.h.patch
new file mode 100644
index 00000000..5e307d63
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_system.h.patch
@@ -0,0 +1,42 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/system.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_IPROC_SYSTEM_H
++#define __PLAT_IPROC_SYSTEM_H
++
++#include
++#include
++
++
++static void arch_idle(void)
++{
++ /*
++ * This should do all the clock switching
++ * and wait for interrupt tricks
++ */
++ cpu_do_idle();
++}
++
++static inline void arch_reset(char mode, const char *cmd)
++{
++}
++
++#endif /*__PLAT_IPROC_SYSTEM_H */
+diff --git a/arch/arm/plat-iproc/include/mach/timer.h b/arch/arm/plat-iproc/include/mach/timer.h
+new file mode 100644
+index 0000000..1b28414
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timer.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timer.h.patch
new file mode 100644
index 00000000..d9cf6991
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timer.h.patch
@@ -0,0 +1,55 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/timer.h
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_TIMER_H
++#define __PLAT_TIMER_H
++
++#ifdef __KERNEL__
++
++typedef unsigned int timer_tick_count_t;
++typedef unsigned int timer_tick_rate_t;
++typedef unsigned int timer_msec_t;
++
++
++enum gp_timer_rate {
++ GPT_KHZ_32 = 0,
++ GPT_MHZ_1,
++};
++
++/**
++ * timer configuration identifying the timer to use
++ * as system timer (GP Timer)
++ */
++ struct gp_timer_setup {
++ char *name;
++ int ch_num;
++ enum gp_timer_rate rate;
++ };
++
++void iproc_timer_init (struct gp_timer_setup *gpt);
++
++timer_tick_count_t timer_get_tick_count(void);
++timer_tick_rate_t timer_get_tick_rate(void);
++timer_msec_t timer_get_msec(void);
++timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
++
++#endif /* __KERNEL__ */
++#endif /* __PLAT_TIMER_H */
+diff --git a/arch/arm/plat-iproc/include/mach/timex.h b/arch/arm/plat-iproc/include/mach/timex.h
+new file mode 100644
+index 0000000..265c48b
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timex.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timex.h.patch
new file mode 100644
index 00000000..62f00537
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_timex.h.patch
@@ -0,0 +1,31 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/timex.h
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef __PLAT_IPROC_TIMEX_H
++#define __PLAT_IPROC_TIMEX_H
++
++/*
++ * Not very sure what the clock rate is. Revisit later
++*/
++#define CLOCK_TICK_RATE (351875)
++
++#endif /* __PLAT_IPROC_TIMEX_H */
+diff --git a/arch/arm/plat-iproc/include/mach/uncompress.h b/arch/arm/plat-iproc/include/mach/uncompress.h
+new file mode 100644
+index 0000000..19002a6
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_uncompress.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_uncompress.h.patch
new file mode 100644
index 00000000..957a06da
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_mach_uncompress.h.patch
@@ -0,0 +1,60 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/mach/uncompress.h
+@@ -0,0 +1,54 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __ASM_ARCH_UNCOMPRESS_H
++#define __ASM_ARCH_UNCOMPRESS_H
++
++#include
++#include
++
++#define IPROC_UART0_PA IPROC_CCA_UART0_REG_BASE
++#define UART0_LSR_OFFSET 0x14
++#define UART0_RBR_THR_DLL_OFFSET 0x00
++#define UART0_LSR_THRE_MASK 0x60
++#define UART0_LSR_TEMT_MASK 0x40
++
++static inline void putc(int c)
++{
++ /*
++ * data should be written to THR register only
++ * if THRE (LSR bit5) is set)
++ */
++ while (0 == (__raw_readl(IPROC_UART0_PA +
++ UART0_LSR_OFFSET) & UART0_LSR_THRE_MASK ))
++ {
++ }
++
++ __raw_writel((unsigned long)c, IPROC_UART0_PA + UART0_RBR_THR_DLL_OFFSET);
++}
++
++static inline void flush(void)
++{
++ /* Wait for the tx fifo to be empty and last char to be sent */
++ while (0 == (__raw_readl(IPROC_UART0_PA +
++ UART0_LSR_OFFSET) & UART0_LSR_TEMT_MASK ))
++ {
++ }
++}
++
++#define arch_decomp_setup()
++#define arch_decomp_wdog()
++
++#endif /* __ASM_ARCH_UNCOMPRESS_H */
+diff --git a/arch/arm/plat-iproc/include/plat/dma-pl330.h b/arch/arm/plat-iproc/include/plat/dma-pl330.h
+new file mode 100644
+index 0000000..bf45e7b
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma-pl330.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma-pl330.h.patch
new file mode 100644
index 00000000..b500b554
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma-pl330.h.patch
@@ -0,0 +1,109 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/dma-pl330.h
+@@ -0,0 +1,103 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __PLAT_DMA_H
++#define __PLAT_DMA_H
++
++#include
++
++#define MAX_CHAN_NAME_LENGTH 32
++
++/* DMA direction control */
++enum dma_direction {
++ DMA_DIRECTION_MEM_TO_MEM = 0,
++ DMA_DIRECTION_MEM_TO_DEV_FLOW_CTRL_DMAC = 1,
++ DMA_DIRECTION_MEM_TO_DEV_FLOW_CTRL_PERI = 2,
++ DMA_DIRECTION_DEV_TO_MEM_FLOW_CTRL_DMAC = 3,
++ DMA_DIRECTION_DEV_TO_MEM_FLOW_CTRL_PERI = 4,
++ DMA_DIRECTION_DEV_TO_DEV = 5 /* Invalid, unsupported */
++};
++#define DMA_DIRECTION_MASK 0x7
++
++/* Channel configurations definition */
++#define DMA_CFG_SRC_ADDR_FIXED (0x0 << 0)
++#define DMA_CFG_SRC_ADDR_INCREMENT (0x1 << 0)
++#define DMA_CFG_DST_ADDR_FIXED (0x0 << 14)
++#define DMA_CFG_DST_ADDR_INCREMENT (0x1 << 14)
++
++#define DMA_CFG_BURST_SIZE_MASK (0x7 << 1)
++#define DMA_CFG_BURST_SIZE_1 (0x0 << 1)
++#define DMA_CFG_BURST_SIZE_2 (0x1 << 1)
++#define DMA_CFG_BURST_SIZE_4 (0x2 << 1)
++#define DMA_CFG_BURST_SIZE_8 (0x3 << 1)
++#define DMA_CFG_BURST_SIZE_16 (0x4 << 1)
++#define DMA_CFG_BURST_SIZE_32 (0x5 << 1)
++#define DMA_CFG_BURST_SIZE_64 (0x6 << 1)
++#define DMA_CFG_BURST_SIZE_128 (0x7 << 1)
++
++#define DMA_CFG_BURST_LENGTH_MASK (0xF << 4)
++#define DMA_CFG_BURST_LENGTH_1 (0x0 << 4)
++#define DMA_CFG_BURST_LENGTH_2 (0x1 << 4)
++#define DMA_CFG_BURST_LENGTH_3 (0x2 << 4)
++#define DMA_CFG_BURST_LENGTH_4 (0x3 << 4)
++#define DMA_CFG_BURST_LENGTH_5 (0x4 << 4)
++#define DMA_CFG_BURST_LENGTH_6 (0x5 << 4)
++#define DMA_CFG_BURST_LENGTH_7 (0x6 << 4)
++#define DMA_CFG_BURST_LENGTH_8 (0x7 << 4)
++#define DMA_CFG_BURST_LENGTH_9 (0x8 << 4)
++#define DMA_CFG_BURST_LENGTH_10 (0x9 << 4)
++#define DMA_CFG_BURST_LENGTH_11 (0xA << 4)
++#define DMA_CFG_BURST_LENGTH_12 (0xB << 4)
++#define DMA_CFG_BURST_LENGTH_13 (0xC << 4)
++#define DMA_CFG_BURST_LENGTH_14 (0xD << 4)
++#define DMA_CFG_BURST_LENGTH_15 (0xE << 4)
++#define DMA_CFG_BURST_LENGTH_16 (0xF << 4)
++
++#define DMA_CFG_BURST_LEN(x) (((x - 1) & 0xF) << 4)
++
++/* src and dest burst size and burst length are assumed to be same */
++
++enum pl330_xfer_status {
++ DMA_PL330_XFER_OK,
++ DMA_PL330_XFER_ERR,
++ DMA_PL330_XFER_ABORT,
++};
++
++struct dma_transfer_list {
++ dma_addr_t srcaddr; /* src address */
++ dma_addr_t dstaddr; /* dst address */
++ unsigned int xfer_size; /* In bytes */
++ struct list_head next; /* Next item */
++};
++
++typedef void (*pl330_xfer_callback_t) (void *private_data,
++ enum pl330_xfer_status status);
++
++int dma_request_chan(unsigned int *chan, const char *name);
++int dma_free_chan(unsigned int chan);
++int dma_map_peripheral(unsigned int chan, const char *peri_name);
++int dma_unmap_peripheral(unsigned int chan);
++int dma_setup_transfer(unsigned int chan, dma_addr_t s, dma_addr_t d,
++ unsigned int xfer_size, int ctrl, int cfg);
++int dma_setup_transfer_list(unsigned int chan, struct list_head *head,
++ int ctrl, int cfg);
++int dma_start_transfer(unsigned int chan);
++int dma_stop_transfer(unsigned int chan);
++int dma_shutdown_all_chan(void);
++int dma_register_callback(unsigned int chan,
++ pl330_xfer_callback_t cb, void *pri);
++int dma_free_callback(unsigned int chan);
++
++#endif /* __PLAT_DMA_H */
+diff --git a/arch/arm/plat-iproc/include/plat/dma_drv.h b/arch/arm/plat-iproc/include/plat/dma_drv.h
+new file mode 100644
+index 0000000..a7f8631
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma_drv.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma_drv.h.patch
new file mode 100644
index 00000000..b1db4e8d
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dma_drv.h.patch
@@ -0,0 +1,609 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/dma_drv.h
+@@ -0,0 +1,603 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/**
++*
++* @file dma_drv.h
++*
++* @brief DMA device driver defines and prototypes.
++*
++****************************************************************************/
++/**
++*
++* @defgroup DMAGroup Direct Memory Access
++* @ingroup CSLGroup
++* @brief This group defines the APIs for DMA driver
++
++Click here to navigate back to the Chip Support Library Overview page: \ref CSLOverview. \n
++*****************************************************************************/
++#ifndef _DMA_DRV_H_
++#define _DMA_DRV_H_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/**
++ * @addtogroup DMAGroup
++ * @{
++ */
++
++/**
++*
++* DMA driver status definition
++*
++*****************************************************************************/
++#define DMADRV_STATUS_t DMADRV_STATUS
++typedef enum
++{
++ DMADRV_STATUS_CLOSED,
++ DMADRV_STATUS_OPEN,
++ DMADRV_STATUS_OK,
++ DMADRV_STATUS_FAIL
++}DMADRV_STATUS_t;
++
++/**
++*
++* DMA driver callback status definition
++*
++*****************************************************************************/
++#define DMADRV_CALLBACK_STATUS_t DMADRV_CALLBACK_STATUS
++typedef enum
++{
++ DMADRV_CALLBACK_OK = 0,
++ DMADRV_CALLBACK_FAIL
++} DMADRV_CALLBACK_STATUS_t;
++
++/**
++*
++* DMA driver channel descriptor definition
++*
++*****************************************************************************/
++typedef struct
++{
++ UInt32 src;
++ UInt32 dest;
++ UInt32 next;
++ UInt32 control;
++ UInt32 size;
++ UInt32 owner;
++} Dma_Chan_Desc;
++
++/**
++*
++* DMA driver data buffer feature definition
++*
++*****************************************************************************/
++typedef struct
++{
++ UInt32 srcAddr;
++ UInt32 destAddr;
++ UInt32 length;
++ UInt32 bRepeat;
++ UInt32 interrupt;
++} Dma_Buffer;
++
++/**
++*
++* DMA driver data buffer definition
++*
++*****************************************************************************/
++typedef struct
++{
++ Dma_Buffer buffers[1];
++} Dma_Buffer_List;
++
++/**
++*
++* DMA driver data buffer list definition
++*
++*****************************************************************************/
++typedef struct
++{
++ UInt32 numBuffer;
++ Dma_Buffer_List *pBufList;
++} Dma_Data;
++
++
++/**
++*
++* DMA data transfer width definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_DATA_SIZE_8BIT = 0x00,
++ DMA_DATA_SIZE_16BIT = 0x01,
++ DMA_DATA_SIZE_32BIT = 0x02
++} DMA_DWIDTH;
++
++/**
++*
++* DMA data transfer type definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_FCTRL_MEM_TO_MEM = 0,
++ DMA_FCTRL_MEM_TO_PERI = 1,
++ DMA_FCTRL_PERI_TO_MEM = 2,
++ DMA_FCTRL_SRCPERI_TO_DESTPERI = 3,
++ DMA_FCTRL_SRCPERI_TO_DESTPERI_CTRL_DESTPERI = 4,
++ DMA_FCTRL_MEM_TO_PERI_CTRL_PERI = 5,
++ DMA_FCTRL_PERI_TO_MEM_CTRL_PERI = 6,
++ DMA_FCTRL_SRCPERI_TO_DESTPERI_CTRL_SRCPERI = 7
++} DMA_CHAN_TYPE;
++
++/**
++*
++* DMA burst length definition
++*
++*****************************************************************************/
++#if (defined(_HERA_) || defined(_RHEA_) || defined(_SAMOA_))
++typedef enum {
++ DMA_BURST_LEN_1 = 0x00, ///<
++ DMA_BURST_LEN_2 = 0x01, ///<
++ DMA_BURST_LEN_3 = 0x02, ///<
++ DMA_BURST_LEN_4 = 0x03, ///<
++ DMA_BURST_LEN_5 = 0x04, ///<
++ DMA_BURST_LEN_6 = 0x05, ///<
++ DMA_BURST_LEN_7 = 0x06, ///<
++ DMA_BURST_LEN_8 = 0x07, ///<
++ DMA_BURST_LEN_9 = 0x08, ///<
++ DMA_BURST_LEN_10 = 0x09, ///<
++ DMA_BURST_LEN_11 = 0x0A, ///<
++ DMA_BURST_LEN_12 = 0x0B, ///<
++ DMA_BURST_LEN_13 = 0x0C, ///<
++ DMA_BURST_LEN_14 = 0x0D, ///<
++ DMA_BURST_LEN_15 = 0x0E, ///<
++ DMA_BURST_LEN_16 = 0x0F ///<
++} DMADRV_BLENGTH;
++
++typedef enum
++{
++ DMA_BURST_SIZE_1 = 0x00,
++ DMA_BURST_SIZE_2 = 0x01,
++ DMA_BURST_SIZE_4 = 0x02,
++ DMA_BURST_SIZE_8 = 0x03,
++ DMA_BURST_SIZE_16 = 0x04,
++ DMA_BURST_SIZE_32 = 0x05,
++ DMA_BURST_SIZE_64 = 0x06,
++ DMA_BURST_SIZE_128 = 0x07
++} DMA_BSIZE;
++
++#else
++/**
++*
++* DMA burst size definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_BURST_SIZE_1 = 0x00,
++ DMA_BURST_SIZE_4 = 0x01,
++ DMA_BURST_SIZE_8 = 0x02,
++ DMA_BURST_SIZE_16 = 0x03,
++ DMA_BURST_SIZE_32 = 0x04,
++ DMA_BURST_SIZE_64 = 0x05,
++ DMA_BURST_SIZE_128 = 0x06,
++ DMA_BURST_SIZE_256 = 0x07
++} DMA_BSIZE;
++#endif
++
++/**
++*
++* DMA alignment definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_ALIGNMENT_8 = 8,
++ DMA_ALIGNMENT_16 = 16,
++ DMA_ALIGNMENT_32 = 32
++} DMA_ALIGN;
++
++/**
++*
++* DMA data transfer incremnet definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_INC_MODE_NONE = 0,
++ DMA_INC_MODE_SRC,
++ DMA_INC_MODE_DST,
++ DMA_INC_MODE_BOTH,
++} DMA_INC_MODE;
++
++/**
++*
++* DMA driver client type definition
++*
++*****************************************************************************/
++#if (defined(_HERA_) || defined(_RHEA_) || defined(_SAMOA_))
++typedef enum {
++ DMA_CLIENT_EP_INVALID = 0xff,
++ DMA_CLIENT_EP_UARTB_A = 8,
++ DMA_CLIENT_EP_UARTB_B = 9,
++ DMA_CLIENT_EP_UARTB2_A = 10,
++ DMA_CLIENT_EP_UARTB2_B = 11,
++ DMA_CLIENT_EP_UARTB3_A = 12,
++ DMA_CLIENT_EP_UARTB3_B = 13,
++ DMA_CLIENT_EP_SSP_0A_RX0 = 16,
++ DMA_CLIENT_EP_SSP_0B_TX0 = 17,
++ DMA_CLIENT_EP_SSP_0C_RX1 = 18,
++ DMA_CLIENT_EP_SSP_0D_TX1 = 19,
++ DMA_CLIENT_EP_SSP_1A_RX0 = 20,
++ DMA_CLIENT_EP_SSP_1B_TX0 = 21,
++ DMA_CLIENT_EP_SSP_1C_RX1 = 22,
++ DMA_CLIENT_EP_SSP_1D_TX1 = 23,
++ DMA_CLIENT_EP_HSIA = 32,
++ DMA_CLIENT_EP_HSIB = 33,
++ DMA_CLIENT_EP_HSIC = 34,
++ DMA_CLIENT_EP_HSID = 35,
++ DMA_CLIENT_EP_EANC = 40,
++ DMA_CLIENT_EP_STEREO = 41,
++ DMA_CLIENT_EP_NVIN = 42,
++ DMA_CLIENT_EP_VIN = 43,
++ DMA_CLIENT_EP_VIBRA = 44,
++ DMA_CLIENT_EP_IHF_0 = 45,
++ DMA_CLIENT_EP_VOUT = 46,
++ DMA_CLIENT_EP_SLIMA = 47,
++ DMA_CLIENT_EP_SLIMB = 48,
++ DMA_CLIENT_EP_SLIMC = 49,
++ DMA_CLIENT_EP_SLIMD = 50,
++ DMA_CLIENT_EP_SIM_A = 51,
++ DMA_CLIENT_EP_SIM_B = 52,
++ DMA_CLIENT_EP_SIM2_A = 53,
++ DMA_CLIENT_EP_SIM2_B = 54,
++ DMA_CLIENT_EP_IHF_1 = 55,
++#if defined(_RHEA_)
++ DMA_CLIENT_EP_SSP_3A_RX0 = 56,
++ DMA_CLIENT_EP_SSP_3B_TX0 = 57,
++ DMA_CLIENT_EP_SSP_3C_RX1 = 58,
++ DMA_CLIENT_EP_SSP_3D_TX1 = 59,
++#else
++ DMA_CLIENT_EP_SSP_2A_RX0 = 56,
++ DMA_CLIENT_EP_SSP_2B_TX0 = 57,
++ DMA_CLIENT_EP_SSP_2C_RX1 = 58,
++ DMA_CLIENT_EP_SSP_2D_TX1 = 59,
++#endif
++ DMA_CLIENT_EP_SPUM_SecureA = 65,
++ DMA_CLIENT_EP_SPUM_SecureB = 66,
++ DMA_CLIENT_EP_SPUM_OpenA = 67,
++ DMA_CLIENT_EP_SPUM_OpenB = 68,
++ DMA_CLIENT_MEMORY = 69,
++#if defined(_RHEA_)
++ DMA_CLIENT_EP_SSP_4A_RX0 = 76,
++ DMA_CLIENT_EP_SSP_4B_TX0 = 77,
++ DMA_CLIENT_EP_SSP_4C_RX1 = 78,
++ DMA_CLIENT_EP_SSP_4D_TX1 = 79,
++#endif
++ DMA_CLIENT_TOTAL
++} DMA_CLIENT;
++#else
++typedef enum
++{
++ DMA_CLIENT_BULK_CRYPT_OUT = 0,
++ DMA_CLIENT_CAM = 1,
++ DMA_CLIENT_I2S_TX = 2,
++ DMA_CLIENT_I2S_RX = 3,
++ DMA_CLIENT_SIM_RX = 4,
++ DMA_CLIENT_SIM_TX = 4,
++ DMA_CLIENT_CRC = 5,
++ DMA_CLIENT_SPI_RX = 6,
++ DMA_CLIENT_SPI_TX = 7,
++ DMA_CLIENT_UARTA_RX = 8,
++ DMA_CLIENT_UARTA_TX = 9,
++ DMA_CLIENT_UARTB_RX = 10,
++ DMA_CLIENT_UARTB_TX = 11,
++ DMA_CLIENT_DES_IN = 12,
++ DMA_CLIENT_DES_OUT = 13,
++ DMA_CLIENT_USB_RX = 14,
++ DMA_CLIENT_USB_TX = 15,
++ DMA_CLIENT_UARTC_RX = 16,
++ DMA_CLIENT_UARTC_TX = 17,
++ DMA_CLIENT_BULK_CRYPT_IN = 18,
++ DMA_CLIENT_LCD = 19,
++ DMA_CLIENT_MSPRO = 20,
++ DMA_CLIENT_DSI_CM = 21,
++ DMA_CLIENT_DSI_VM = 22,
++ DMA_CLIENT_TVENC1 = 23,
++ DMA_CLIENT_TVENC2 = 24,
++#if defined(_ATHENA_)
++ DMA_CLIENT_AUDIO_IN_FIFO = 25,
++ DMA_CLIENT_AUDIO_OUT_FIFO = 26,
++ DMA_CLIENT_POLYRING_OUT_FIFO = 27,
++ DMA_CLIENT_AUDIO_WB_MIXERTAP = 28,
++ DMA_CLIENT_MEMORY = 29,
++#else
++ DMA_CLIENT_MEMORY = 25,
++#endif
++ DMA_CLIENT_TOTAL
++} DMA_CLIENT;
++#endif
++
++/**
++*
++* DMA driver channel definition
++*
++*****************************************************************************/
++typedef enum
++{
++ DMA_CHANNEL_INVALID = 0xFF,
++ DMA_CHANNEL_0 = 0,
++ DMA_CHANNEL_1 = 1,
++ DMA_CHANNEL_2 = 2,
++ DMA_CHANNEL_3 = 3,
++#if !defined(_SAMOA_)
++ DMA_CHANNEL_4 = 4,
++ DMA_CHANNEL_5 = 5,
++ DMA_CHANNEL_6 = 6,
++ DMA_CHANNEL_7 = 7,
++#if defined(_ATHENA_)
++ DMA_CHANNEL_8 = 8, //used for DMA_CLIENT_AUDIO_OUT_FIFO
++ DMA_CHANNEL_9 = 9, //used for DMA_CLIENT_POLYRING_OUT_FIFO
++ DMA_CHANNEL_10 = 10, //used for DMA_CLIENT_AUDIO_WB_MIXERTAP
++ DMA_CHANNEL_11 = 11, //used for DMA_CLIENT_AUDIO_IN_FIFO
++#endif
++#endif
++ TOTAL_DMA_CHANNELS
++} DMA_CHANNEL;
++
++/**
++*
++* DMA driver callback function definition
++*
++*****************************************************************************/
++#define DMADRV_CALLBACK_t DmaDrv_Callback
++typedef void (*DMADRV_CALLBACK_t)(DMADRV_CALLBACK_STATUS_t Err);
++
++/**
++*
++* DMA driver channel info structure definition
++*
++*****************************************************************************/
++typedef struct
++{
++ DMA_CLIENT srcID;
++ DMA_CLIENT dstID;
++ DMA_CHAN_TYPE type;
++ DMA_ALIGN alignment;
++ DMA_BSIZE srcBstSize;
++ DMA_BSIZE dstBstSize;
++ DMA_DWIDTH srcDataWidth;
++ DMA_DWIDTH dstDataWidth;
++ UInt32 priority;
++ UInt32 chanNumber;
++ UInt32 dmaCfgReg;
++ UInt32 incMode;
++ DmaDrv_Callback xferCompleteCb;
++ UInt32 prot;
++ UInt32 dstMaster;
++ UInt32 srcMaster;
++ UInt32 dstIncrement;
++ UInt32 srcIncrement;
++#if (defined(_HERA_) || defined(_RHEA_) || defined(_SAMOA_))
++ DMADRV_BLENGTH srcBstLength;
++ DMADRV_BLENGTH dstBstLength;
++#endif
++ Boolean freeChan;
++ Boolean bCircular;
++} Dma_Chan_Info, *pChanInfo;
++
++/**
++*
++* DMA driver LLI structure definition
++*
++*****************************************************************************/
++typedef void *DMADRV_LLI_T;
++
++/**
++*
++* This function initialize dma driver
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Init(void);
++
++/**
++*
++* This function deinitialize dma driver
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_DeInit(void);
++
++/**
++*
++* This function allocates dma channel
++*
++* @param srcID (in) source identification
++* @param dstID (in) destination identification
++* @param chanID (in) buffer to store channel number
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Obtain_Channel(
++ DMA_CLIENT srcID,
++ DMA_CLIENT dstID,
++ DMA_CHANNEL *chanID
++);
++
++/**
++*
++* This function release dma channel
++*
++* @param chanID (in) channel identification
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Release_Channel(DMA_CHANNEL chanID);
++
++/**
++*
++* This function configure dma channel
++*
++* @param chanID (in) channel number
++* @param pChanInfo (in) pointer to dma channe info structure
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Config_Channel(
++ DMA_CHANNEL chanID,
++ Dma_Chan_Info *pChanInfo
++);
++
++/**
++*
++* This function bind data buffer for the DMA channel
++*
++* @param chanID (in) channel to bind data
++* @param pData (in) pointer to dma channel data buffer
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Bind_Data(DMA_CHANNEL chanID, Dma_Data *pData);
++
++/**
++*
++* This function start dma channel transfer
++*
++* @param chanID (in) channel identification
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Start_Transfer(DMA_CHANNEL chanID);
++
++/**
++*
++* This function bind data buffer for the DMA channel
++*
++* @param chanID (in) channel to bind data
++* @param pData (in) pointer to dma channel data buffer
++* @param pLLI (in) buffer to store returned LLI table
++* identification info
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Bind_Data_Ex(
++ DMA_CHANNEL chanID,
++ Dma_Data *pData,
++ DMADRV_LLI_T *pLLI
++);
++
++/**
++*
++* This function start dma channel transfer
++*
++* @param chanID (in) channel identification
++* @param pLLI (in) one of the LLI tables needs to be used for DMA
++* transfer
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Start_Transfer_Ex(
++ DMA_CHANNEL chanID,
++ DMADRV_LLI_T pLLI
++);
++
++/**
++*
++* This function stop dma channel trnasfer
++*
++* @param chanID (in) channel identification
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Stop_Transfer(DMA_CHANNEL chanID);
++
++/**
++*
++* This function stop dma channel trnasfer and lose all data in FIFO
++*
++* @param chanID (in) channel identification
++*
++* @return DMA driver return status
++*
++*****************************************************************************/
++DMADRV_STATUS DMADRV_Force_Shutdown_Channel(DMA_CHANNEL chanID);
++
++/**
++*
++* This function register hisr for client usage
++*
++* @param client (in) client identification
++* @param hisr (in) registered hisr
++*
++* @return void
++*
++*****************************************************************************/
++void DMADRV_Register_HISR(DMA_CLIENT client, void *hisr);
++
++/**
++*
++* This function unregister hisr from client usage
++*
++* @param client (in) client identification
++*
++* @return void
++*
++*****************************************************************************/
++void DMADRV_UnRegister_HISR(DMA_CLIENT client);
++
++/**
++*
++* This function get hisr for client usage
++*
++* @param client (in) client identification
++*
++* @return hisr (out) return registered client's hisr
++*
++*****************************************************************************/
++void *DMADRV_Get_HISR(DMA_CLIENT client);
++
++/**
++*
++* This function get DMA driver version number
++*
++* @return driver version number
++*
++*****************************************************************************/
++UInt32 DMADRV_Get_Version(void);
++
++/** @} */
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* _DMA_DRV_H_ */
+diff --git a/arch/arm/plat-iproc/include/plat/dmux.h b/arch/arm/plat-iproc/include/plat/dmux.h
+new file mode 100644
+index 0000000..575f783
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dmux.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dmux.h.patch
new file mode 100644
index 00000000..03df92e2
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_dmux.h.patch
@@ -0,0 +1,82 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/dmux.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef __MACH_DMUX_H
++#define __MACH_DMUX_H
++
++enum dmac_mux {
++ KONA_DMUX_UARTB_A = 8,
++ KONA_DMUX_UARTB_B = 9,
++ KONA_DMUX_UARTB2_A = 10,
++ KONA_DMUX_UARTB2_B = 11,
++ KONA_DMUX_UARTB3_A = 12,
++ KONA_DMUX_UARTB3_B = 13,
++ KONA_DMUX_SSP_0A_RX0 = 16,
++ KONA_DMUX_SSP_0B_TX0 = 17,
++ KONA_DMUX_SSP_0C_RX1 = 18,
++ KONA_DMUX_SSP_0D_TX1 = 19,
++ KONA_DMUX_SSP_1A_RX0 = 20,
++ KONA_DMUX_SSP_1B_TX0 = 21,
++ KONA_DMUX_SSP_1C_RX1 = 22,
++ KONA_DMUX_SSP_1D_TX1 = 23,
++ KONA_DMUX_HSIA = 32,
++ KONA_DMUX_HSIB = 33,
++ KONA_DMUX_HSIC = 34,
++ KONA_DMUX_HSID = 35,
++ KONA_DMUX_EANC = 40,
++ KONA_DMUX_STEREO = 41,
++ KONA_DMUX_NVIN = 42,
++ KONA_DMUX_VIN = 43,
++ KONA_DMUX_VIBRA = 44,
++ KONA_DMUX_IHF_0 = 45,
++ KONA_DMUX_VOUT = 46,
++ KONA_DMUX_SLIMA = 47,
++ KONA_DMUX_SLIMB = 48,
++ KONA_DMUX_SLIMC = 49,
++ KONA_DMUX_SLIMD = 50,
++ KONA_DMUX_SIM_A = 51,
++ KONA_DMUX_SIM_B = 52,
++ KONA_DMUX_SIM2_A = 53,
++ KONA_DMUX_SIM2_B = 54,
++ KONA_DMUX_IHF_1 = 55,
++ KONA_DMUX_SSP_2A_RX0 = 56,
++ KONA_DMUX_SSP_2B_TX0 = 57,
++ KONA_DMUX_SSP_2C_RX1 = 58,
++ KONA_DMUX_SSP_2D_TX1 = 59,
++ KONA_DMUX_SPUM_SecureA = 65,
++ KONA_DMUX_SPUM_SecureB = 66,
++ KONA_DMUX_SPUM_OpenA = 67,
++ KONA_DMUX_SPUM_OpenB = 68,
++ KONA_DMUX_INVALID = 0x7f,
++};
++
++enum dma_peri dmux_name_to_id(const char *name);
++int dmux_id_to_name(enum dma_peri peri, char *pname);
++int dmux_sema_protect(void);
++int dmux_sema_unprotect(void);
++int dmux_alloc_channel(u32 * pchan);
++int dmux_release_channel(u32 channel);
++int dmux_alloc_peripheral(u32 channel, enum dma_peri peri, u8 * peri_req_id);
++int dmux_alloc_multi_peripheral(u32 channel, enum dma_peri a, enum dma_peri b,
++ u8 * src_id, u8 * dst_id);
++int dmux_dealloc_peripheral(u32 channel);
++
++#endif /* __MACH_DMUX_H */
+diff --git a/arch/arm/plat-iproc/include/plat/osdal_os.h b/arch/arm/plat-iproc/include/plat/osdal_os.h
+new file mode 100644
+index 0000000..76e61a6
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_osdal_os.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_osdal_os.h.patch
new file mode 100644
index 00000000..0c8a55f3
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_osdal_os.h.patch
@@ -0,0 +1,66 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/osdal_os.h
+@@ -0,0 +1,60 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef _OSDAL_OS_H_
++#define _OSDAL_OS_H_
++
++#include
++#include "asm/posix_types.h"
++#include "asm/string.h"
++/* Heap memory */
++#define OSDAL_ALLOCHEAPMEM(s) kzalloc((s), GFP_KERNEL)
++
++#define OSDAL_FREEHEAPMEM(a) kfree((a))
++
++
++/* IRQ */
++#define OSDAL_IRQ_Enable(irq) enable_irq((irq))
++#define OSDAL_IRQ_Disable(irq) disable_irq((irq))
++#define OSDAL_IRQ_Clear(irq)
++#define OSDAL_IRQ_IsEnabled(irq)
++
++
++/* Synchronization */
++#define OSDAL_SENDEVENT(e) complete((struct completion *)&(e))
++
++#define OSDAL_WAITEVENT(e) \
++wait_for_completion((struct completion *)&(e))
++
++#define OSDAL_WAITEVENT_TIMEOUT(e, t) \
++wait_for_completion_timeout((struct completion *)&(e), (t))
++
++#define OSDAL_CLEAREVENT(e)
++
++
++/* Time stamp in ms */
++#define OSDAL_TIMEVAL()
++
++
++/* Delays */
++#define OSDAL_MDELAY(x) mdelay(x)
++
++#define OSDAL_UDELAY(x) udelay(x)
++
++/* Debug Print */
++//#define dprintf(prio, format, args...) pr_info("%s:%s"" format", __FILE__, __FUNCTION__)
++#define dprintf(prio, fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
++
++#endif /*_OSDAL_OS_H_*/
+diff --git a/arch/arm/plat-iproc/include/plat/shm.h b/arch/arm/plat-iproc/include/plat/shm.h
+new file mode 100644
+index 0000000..59fcb83
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_shm.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_shm.h.patch
new file mode 100644
index 00000000..04a1280f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_shm.h.patch
@@ -0,0 +1,50 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/shm.h
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/*
++ * Header for declaring shim layer exports.
++ */
++
++#ifndef __SHM_DOT_H_INCLUDED__
++#define __SHM_DOT_H_INCLUDED__
++
++#include
++#include
++
++extern int iproc_platform_get_irq(struct platform_device *dev, unsigned int num);
++extern struct resource *
++iproc_platform_get_resource_byname(struct platform_device *dev, unsigned int type, const char *name);
++extern struct resource *
++iproc_platform_get_resource(struct platform_device *dev, unsigned int type,
++ unsigned int num);
++extern int iproc_platform_device_register(struct platform_device * pdev);
++extern void iproc_platform_device_unregister(struct platform_device * pdev);
++extern int iproc_platform_driver_register(struct platform_driver *drv);
++extern void iproc_platform_driver_unregister(struct platform_driver *drv);
++
++extern struct platform_device *iproc_platform_device_alloc(const char *name, int id);
++extern int iproc_platform_device_add(struct platform_device *pdev);
++extern void iproc_platform_device_put(struct platform_device *pdev);
++
++extern int iproc_sysfs_create_group(struct kobject *kobj, const struct attribute_group *grp);
++extern void iproc_sysfs_remove_group(struct kobject *kobj, const struct attribute_group *grp);
++
++#endif /*#ifndef __SHM_DOT_H_INCLUDED__*/
+diff --git a/arch/arm/plat-iproc/include/plat/spi_iproc.h b/arch/arm/plat-iproc/include/plat/spi_iproc.h
+new file mode 100644
+index 0000000..3258d69
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_spi_iproc.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_spi_iproc.h.patch
new file mode 100644
index 00000000..8af39b07
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_spi_iproc.h.patch
@@ -0,0 +1,33 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/spi_iproc.h
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++/*
++ * Broadcom IPROC SSPI based SPI master controller
++ */
++#ifndef __ARCH_PLAT_SPI_IPROC_H__
++#define __ARCH_PLAT_SPI_IPROC_H__
++
++struct spi_iproc_platform_data {
++ u8 enable_dma;
++ u8 cs_line;
++ u8 mode;
++};
++#endif /* __ARCH_PLAT_SPI_IPROC_H__ */
+diff --git a/arch/arm/plat-iproc/include/plat/swreset_rec.h b/arch/arm/plat-iproc/include/plat/swreset_rec.h
+new file mode 100644
+index 0000000..924fa5a
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_swreset_rec.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_swreset_rec.h.patch
new file mode 100644
index 00000000..58bb7484
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_swreset_rec.h.patch
@@ -0,0 +1,46 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/swreset_rec.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef _SWRESET_REC_H_
++#define _SWRESET_REC_H_
++
++/* Handle to access Software Record Record */
++typedef void *SWRR_HANDLE;
++
++/* Get number of software reset records for the SoC; 0 if not suppprted */
++extern unsigned int swreset_record_get_record_count(void);
++
++/* Get number of bits per software reset record for the SoC */
++extern unsigned int swreset_record_get_record_width(void);
++
++/* Register to use one software reset record; return NULL if used out */
++extern SWRR_HANDLE swreset_record_register(const char *name);
++
++/* Unregister to return the record */
++extern void swreset_record_unregister(SWRR_HANDLE handle);
++
++/* Set value of the software reset record */
++extern int swreset_record_set(SWRR_HANDLE handle, int value);
++
++/* Get value of the software reset record */
++extern int swreset_record_get(SWRR_HANDLE handle, int *value);
++
++#endif /* _SWRESET_REC_H_ */
+diff --git a/arch/arm/plat-iproc/include/plat/timer-sp.h b/arch/arm/plat-iproc/include/plat/timer-sp.h
+new file mode 100644
+index 0000000..b73ef9a
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_timer-sp.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_timer-sp.h.patch
new file mode 100644
index 00000000..a3734f49
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_timer-sp.h.patch
@@ -0,0 +1,24 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/timer-sp.h
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++void iproc_clocksource_init(void __iomem *);
++void iproc_clockevents_init(void __iomem *, unsigned int);
+diff --git a/arch/arm/plat-iproc/include/plat/types.h b/arch/arm/plat-iproc/include/plat/types.h
+new file mode 100644
+index 0000000..d03df1e
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_types.h.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_types.h.patch
new file mode 100644
index 00000000..a48d719f
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_include_plat_types.h.patch
@@ -0,0 +1,26 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/include/plat/types.h
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef _TYPES_H_
++#define _TYPES_H_
++
++#include
++#endif
+diff --git a/arch/arm/plat-iproc/iproc-cache.S b/arch/arm/plat-iproc/iproc-cache.S
+new file mode 100644
+index 0000000..2a5e37d
diff --git a/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_iproc-cache.S.patch b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_iproc-cache.S.patch
new file mode 100644
index 00000000..01568c44
--- /dev/null
+++ b/packages/base/any/kernels/3.2-lts/patches/arch_arm_plat-iproc_iproc-cache.S.patch
@@ -0,0 +1,126 @@
+--- /dev/null
++++ b/arch/arm/plat-iproc/iproc-cache.S
+@@ -0,0 +1,120 @@
++/*
++ * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include
++#include
++
++ __INIT
++
++/*
++ * The secondary kernel init calls v7_flush_dcache_all before it enables
++ * the L1; however, the L1 comes out of reset in an undefined state, so
++ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
++ * of cache lines with uninitialized data and uninitialized tags to get
++ * written out to memory, which does really unpleasant things to the main
++ * processor. We fix this by performing an invalidate, rather than a
++ * clean + invalidate, before jumping into the kernel.
++ */
++
++ENTRY(v7_invalidate_l1)
++ mov r0, #0
++ mcr p15, 2, r0, c0, c0, 0
++ mrc p15, 1, r0, c0, c0, 0
++
++ ldr r1, =0x7fff
++ and r2, r1, r0, lsr #13
++
++ ldr r1, =0x3ff
++
++ and r3, r1, r0, lsr #3 @ NumWays - 1
++ add r2, r2, #1 @ NumSets
++
++ and r0, r0, #0x7
++ add r0, r0, #4 @ SetShift
++
++ clz r1, r3 @ WayShift
++ add r4, r3, #1 @ NumWays
++1: sub r2, r2, #1 @ NumSets--
++ mov r3, r4 @ Temp = NumWays
++2: subs r3, r3, #1 @ Temp--
++ mov r5, r3, lsl r1
++ mov r6, r2, lsl r0
++ orr r5, r5, r6 @ Reg = (Temp<
++#include
++#include
++#include
++#include
++#include