mirror of
https://github.com/Telecominfraproject/ols-nos.git
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[device]: Add a new supported device AS7312-54XS (#1821)
* Switch Vendor: Edge-core * Switch SKU: AS7312-54XS * ASIC Vendor: Broadcom * Swich ASIC: Tomahawk+ * Port Configuration: 48x25G + 6x100G * SONiC Image: SONiC-ONIE-Broadcom Signed-off-by: polly_hsu@edge-core.com
This commit is contained in:
Polly Hsu
@@ -0,0 +1,55 @@
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# name lanes alias index
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Ethernet0 41 twentyfiveGigE1 0
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Ethernet1 42 twentyfiveGigE2 1
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Ethernet2 43 twentyfiveGigE3 2
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Ethernet3 44 twentyfiveGigE4 3
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Ethernet4 49 twentyfiveGigE5 4
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Ethernet5 50 twentyfiveGigE6 5
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Ethernet6 51 twentyfiveGigE7 6
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Ethernet7 52 twentyfiveGigE8 7
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Ethernet8 53 twentyfiveGigE9 8
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Ethernet9 54 twentyfiveGigE10 9
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Ethernet10 55 twentyfiveGigE11 10
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Ethernet11 56 twentyfiveGigE12 11
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Ethernet12 65 twentyfiveGigE13 12
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Ethernet13 66 twentyfiveGigE14 13
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Ethernet14 67 twentyfiveGigE15 14
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Ethernet15 68 twentyfiveGigE16 15
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Ethernet16 33 twentyfiveGigE17 16
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Ethernet17 34 twentyfiveGigE18 17
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Ethernet18 35 twentyfiveGigE19 18
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Ethernet19 36 twentyfiveGigE20 19
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Ethernet20 37 twentyfiveGigE21 20
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Ethernet21 38 twentyfiveGigE22 21
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Ethernet22 39 twentyfiveGigE23 22
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Ethernet23 40 twentyfiveGigE24 23
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Ethernet24 69 twentyfiveGigE25 24
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Ethernet25 70 twentyfiveGigE26 25
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Ethernet26 71 twentyfiveGigE27 26
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Ethernet27 72 twentyfiveGigE28 27
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Ethernet28 81 twentyfiveGigE29 28
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Ethernet29 82 twentyfiveGigE30 29
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Ethernet30 83 twentyfiveGigE31 30
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Ethernet31 84 twentyfiveGigE32 31
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Ethernet32 85 twentyfiveGigE33 32
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Ethernet33 86 twentyfiveGigE34 33
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Ethernet34 87 twentyfiveGigE35 34
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Ethernet35 88 twentyfiveGigE36 35
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Ethernet36 97 twentyfiveGigE37 36
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Ethernet37 98 twentyfiveGigE38 37
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Ethernet38 99 twentyfiveGigE39 38
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Ethernet39 100 twentyfiveGigE40 39
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Ethernet40 101 twentyfiveGigE41 40
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Ethernet41 102 twentyfiveGigE42 41
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Ethernet42 103 twentyfiveGigE43 42
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Ethernet43 104 twentyfiveGigE44 43
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Ethernet44 105 twentyfiveGigE45 44
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Ethernet45 106 twentyfiveGigE46 45
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Ethernet46 107 twentyfiveGigE47 46
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Ethernet47 108 twentyfiveGigE48 47
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Ethernet48 5,6,7,8 hundredGigE49 48
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Ethernet52 1,2,3,4 hundredGigE50 52
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Ethernet56 109,110,111,112 hundredGigE51 56
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Ethernet60 21,22,23,24 hundredGigE52 60
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Ethernet64 9,10,11,12 hundredGigE53 64
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Ethernet68 117,118,119,120 hundredGigE54 68
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@@ -0,0 +1 @@
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SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th-as7312-48x25G+6x100G.config.bcm
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@@ -0,0 +1,519 @@
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# accton_as7312_54x 48x25G+6x100G SDK config
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os=unix
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schan_intr_enable=0
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l2_mem_entries=40960
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l2xmsg_mode=1
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l3_mem_entries=40960
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mem_cache_enable=0
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parity_correction=0
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parity_enable=0
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mmu_lossless=1
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pbmp_oversubscribe=0x0407ffc00ff00ff003fc3ffc00200222
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pbmp_xport_xe=0x0407ffd00ff00ff403fc3ffc00200222
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## FC10 ##
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dport_map_port_42=1
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dport_map_port_43=2
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dport_map_port_44=3
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dport_map_port_45=4
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## FC12 ##
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dport_map_port_50=5
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dport_map_port_51=6
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dport_map_port_52=7
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dport_map_port_53=8
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## FC13 ##
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dport_map_port_54=9
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dport_map_port_55=10
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dport_map_port_56=11
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dport_map_port_57=12
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## FC16 ##
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dport_map_port_68=13
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dport_map_port_69=14
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dport_map_port_70=15
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dport_map_port_71=16
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## FC8 ##
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dport_map_port_34=17
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dport_map_port_35=18
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dport_map_port_36=19
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dport_map_port_37=20
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## FC9 ##
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dport_map_port_38=21
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dport_map_port_39=22
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dport_map_port_40=23
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dport_map_port_41=24
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## FC17 ##
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dport_map_port_72=25
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dport_map_port_73=26
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dport_map_port_74=27
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dport_map_port_75=28
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## FC20 ##
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dport_map_port_84=29
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dport_map_port_85=30
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dport_map_port_86=31
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dport_map_port_87=32
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## FC21 ##
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dport_map_port_88=33
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dport_map_port_89=34
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dport_map_port_90=35
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dport_map_port_91=36
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## FC24 ##
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dport_map_port_102=37
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dport_map_port_103=38
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dport_map_port_104=39
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dport_map_port_105=40
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## FC25 ##
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dport_map_port_106=41
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dport_map_port_107=42
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dport_map_port_108=43
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dport_map_port_109=44
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## FC26 ##
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dport_map_port_110=45
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dport_map_port_111=46
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dport_map_port_112=47
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dport_map_port_113=48
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## FC1 ##
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dport_map_port_5=49
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## FC0 ##
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dport_map_port_1=50
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## FC27 ##
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dport_map_port_114=51
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## FC5 ##
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dport_map_port_21=52
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## FC2 ##
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dport_map_port_9=53
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## FC29 ##
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dport_map_port_122=54
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#for KR
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#dport_map_port_66=55
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#dport_map_port_100=56
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/* Port Map */
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## FC10 ##
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portmap_42=41:25
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portmap_43=42:25
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portmap_44=43:25
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portmap_45=44:25
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## FC12 ##
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portmap_50=49:25
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portmap_51=50:25
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portmap_52=51:25
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portmap_53=52:25
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## FC13 ##
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portmap_54=53:25
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portmap_55=54:25
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portmap_56=55:25
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portmap_57=56:25
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## FC16 ##
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portmap_68=65:25
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portmap_69=66:25
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portmap_70=67:25
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portmap_71=68:25
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## FC8 ##
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portmap_34=33:25
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portmap_35=34:25
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portmap_36=35:25
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portmap_37=36:25
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## FC9 ##
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portmap_38=37:25
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portmap_39=38:25
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portmap_40=39:25
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portmap_41=40:25
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## FC17 ##
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portmap_72=69:25
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portmap_73=70:25
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portmap_74=71:25
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portmap_75=72:25
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## FC20 ##
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portmap_84=81:25
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portmap_85=82:25
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portmap_86=83:25
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portmap_87=84:25
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## FC21 ##
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portmap_88=85:25
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portmap_89=86:25
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portmap_90=87:25
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portmap_91=88:25
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## FC24 ##
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portmap_102=97:25
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portmap_103=98:25
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portmap_104=99:25
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portmap_105=100:25
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## FC25 ##
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portmap_106=101:25
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portmap_107=102:25
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portmap_108=103:25
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portmap_109=104:25
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## FC26 ##
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portmap_110=105:25
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portmap_111=106:25
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portmap_112=107:25
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portmap_113=108:25
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## FC1 ##
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portmap_5=5:100
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## FC0 ##
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portmap_1=1:100
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## FC27 ##
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portmap_114=109:100
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## FC5 ##
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portmap_21=21:100
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## FC2 ##
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portmap_9=9:100
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## FC29 ##
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portmap_122=117:100
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# CPU to MAC
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# TSC-E management port 1
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#portmap_66=129:10
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# TSC-E management port 2
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#portmap_100=131:10
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xgxs_rx_lane_map_42=0x2310
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xgxs_rx_lane_map_43=0x2310
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xgxs_rx_lane_map_44=0x2310
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xgxs_rx_lane_map_45=0x2310
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xgxs_rx_lane_map_50=0x3210
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xgxs_rx_lane_map_51=0x3210
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xgxs_rx_lane_map_52=0x3210
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xgxs_rx_lane_map_53=0x3210
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xgxs_rx_lane_map_54=0x3210
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xgxs_rx_lane_map_55=0x3210
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xgxs_rx_lane_map_56=0x3210
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xgxs_rx_lane_map_57=0x3210
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xgxs_rx_lane_map_68=0x0123
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xgxs_rx_lane_map_69=0x0123
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xgxs_rx_lane_map_70=0x0123
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xgxs_rx_lane_map_71=0x0123
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xgxs_rx_lane_map_34=0x0123
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xgxs_rx_lane_map_35=0x0123
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xgxs_rx_lane_map_36=0x0123
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xgxs_rx_lane_map_37=0x0123
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xgxs_rx_lane_map_38=0x0123
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xgxs_rx_lane_map_39=0x0123
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xgxs_rx_lane_map_40=0x0123
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xgxs_rx_lane_map_41=0x0123
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xgxs_rx_lane_map_72=0x3210
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xgxs_rx_lane_map_73=0x3210
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xgxs_rx_lane_map_74=0x3210
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xgxs_rx_lane_map_75=0x3210
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xgxs_rx_lane_map_84=0x1032
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xgxs_rx_lane_map_85=0x1032
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xgxs_rx_lane_map_86=0x1032
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xgxs_rx_lane_map_87=0x1032
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xgxs_rx_lane_map_88=0x2301
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xgxs_rx_lane_map_89=0x2301
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xgxs_rx_lane_map_90=0x2301
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xgxs_rx_lane_map_91=0x2301
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xgxs_rx_lane_map_102=0x0123
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xgxs_rx_lane_map_103=0x0123
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xgxs_rx_lane_map_104=0x0123
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xgxs_rx_lane_map_105=0x0123
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xgxs_rx_lane_map_106=0x3210
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xgxs_rx_lane_map_107=0x3210
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xgxs_rx_lane_map_108=0x3210
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xgxs_rx_lane_map_109=0x3210
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xgxs_rx_lane_map_110=0x1032
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xgxs_rx_lane_map_111=0x1032
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xgxs_rx_lane_map_112=0x1032
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xgxs_rx_lane_map_113=0x1032
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xgxs_rx_lane_map_5=0x3210
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xgxs_rx_lane_map_1=0x3210
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xgxs_rx_lane_map_114=0x0123
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xgxs_rx_lane_map_21=0x0213
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xgxs_rx_lane_map_9=0x3210
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xgxs_rx_lane_map_122=0x1230
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xgxs_tx_lane_map_42=0x0132
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xgxs_tx_lane_map_43=0x0132
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xgxs_tx_lane_map_44=0x0132
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xgxs_tx_lane_map_45=0x0132
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xgxs_tx_lane_map_50=0x3210
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xgxs_tx_lane_map_51=0x3210
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xgxs_tx_lane_map_52=0x3210
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xgxs_tx_lane_map_53=0x3210
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xgxs_tx_lane_map_54=0x3210
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xgxs_tx_lane_map_55=0x3210
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xgxs_tx_lane_map_56=0x3210
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xgxs_tx_lane_map_57=0x3210
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xgxs_tx_lane_map_68=0x0123
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xgxs_tx_lane_map_69=0x0123
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xgxs_tx_lane_map_70=0x0123
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xgxs_tx_lane_map_71=0x0123
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xgxs_tx_lane_map_34=0x0123
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xgxs_tx_lane_map_35=0x0123
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xgxs_tx_lane_map_36=0x0123
|
||||
xgxs_tx_lane_map_37=0x0123
|
||||
xgxs_tx_lane_map_38=0x0123
|
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xgxs_tx_lane_map_39=0x0123
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xgxs_tx_lane_map_40=0x0123
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||||
xgxs_tx_lane_map_41=0x0123
|
||||
xgxs_tx_lane_map_72=0x0123
|
||||
xgxs_tx_lane_map_73=0x0123
|
||||
xgxs_tx_lane_map_74=0x0123
|
||||
xgxs_tx_lane_map_75=0x0123
|
||||
xgxs_tx_lane_map_84=0x0123
|
||||
xgxs_tx_lane_map_85=0x0123
|
||||
xgxs_tx_lane_map_86=0x0123
|
||||
xgxs_tx_lane_map_87=0x0123
|
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xgxs_tx_lane_map_88=0x2301
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xgxs_tx_lane_map_89=0x2301
|
||||
xgxs_tx_lane_map_90=0x2301
|
||||
xgxs_tx_lane_map_91=0x2301
|
||||
xgxs_tx_lane_map_102=0x0123
|
||||
xgxs_tx_lane_map_103=0x0123
|
||||
xgxs_tx_lane_map_104=0x0123
|
||||
xgxs_tx_lane_map_105=0x0123
|
||||
xgxs_tx_lane_map_106=0x3210
|
||||
xgxs_tx_lane_map_107=0x3210
|
||||
xgxs_tx_lane_map_108=0x3210
|
||||
xgxs_tx_lane_map_109=0x3210
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||||
xgxs_tx_lane_map_110=0x1032
|
||||
xgxs_tx_lane_map_111=0x1032
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||||
xgxs_tx_lane_map_112=0x1032
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||||
xgxs_tx_lane_map_113=0x1032
|
||||
xgxs_tx_lane_map_5=0x3210
|
||||
xgxs_tx_lane_map_1=0x3210
|
||||
xgxs_tx_lane_map_114=0x0123
|
||||
xgxs_tx_lane_map_21=0x3210
|
||||
xgxs_tx_lane_map_9=0x3210
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||||
xgxs_tx_lane_map_122=0x3210
|
||||
|
||||
#Polarity RX
|
||||
phy_xaui_rx_polarity_flip_34=0x1
|
||||
phy_xaui_rx_polarity_flip_35=0x1
|
||||
phy_xaui_rx_polarity_flip_36=0x1
|
||||
phy_xaui_rx_polarity_flip_37=0x1
|
||||
phy_xaui_rx_polarity_flip_38=0x1
|
||||
phy_xaui_rx_polarity_flip_39=0x1
|
||||
phy_xaui_rx_polarity_flip_40=0x1
|
||||
phy_xaui_rx_polarity_flip_41=0x1
|
||||
phy_xaui_rx_polarity_flip_84=0x1
|
||||
phy_xaui_rx_polarity_flip_85=0x0
|
||||
phy_xaui_rx_polarity_flip_86=0x1
|
||||
phy_xaui_rx_polarity_flip_87=0x0
|
||||
phy_xaui_rx_polarity_flip_88=0x1
|
||||
phy_xaui_rx_polarity_flip_89=0x0
|
||||
phy_xaui_rx_polarity_flip_90=0x1
|
||||
phy_xaui_rx_polarity_flip_91=0x1
|
||||
phy_xaui_rx_polarity_flip_102=0x0
|
||||
phy_xaui_rx_polarity_flip_103=0x0
|
||||
phy_xaui_rx_polarity_flip_104=0x1
|
||||
phy_xaui_rx_polarity_flip_105=0x0
|
||||
phy_xaui_rx_polarity_flip_122=0xf
|
||||
#Polarity TX
|
||||
phy_xaui_tx_polarity_flip_42=0x1
|
||||
phy_xaui_tx_polarity_flip_43=0x1
|
||||
phy_xaui_tx_polarity_flip_44=0x1
|
||||
phy_xaui_tx_polarity_flip_45=0x1
|
||||
phy_xaui_tx_polarity_flip_34=0x1
|
||||
phy_xaui_tx_polarity_flip_35=0x1
|
||||
phy_xaui_tx_polarity_flip_36=0x1
|
||||
phy_xaui_tx_polarity_flip_37=0x1
|
||||
phy_xaui_tx_polarity_flip_38=0x0
|
||||
phy_xaui_tx_polarity_flip_39=0x1
|
||||
phy_xaui_tx_polarity_flip_40=0x0
|
||||
phy_xaui_tx_polarity_flip_41=0x1
|
||||
phy_xaui_tx_polarity_flip_72=0x1
|
||||
phy_xaui_tx_polarity_flip_73=0x1
|
||||
phy_xaui_tx_polarity_flip_74=0x1
|
||||
phy_xaui_tx_polarity_flip_75=0x1
|
||||
phy_xaui_tx_polarity_flip_84=0x1
|
||||
phy_xaui_tx_polarity_flip_85=0x1
|
||||
phy_xaui_tx_polarity_flip_86=0x1
|
||||
phy_xaui_tx_polarity_flip_87=0x1
|
||||
phy_xaui_tx_polarity_flip_88=0x1
|
||||
phy_xaui_tx_polarity_flip_89=0x1
|
||||
phy_xaui_tx_polarity_flip_90=0x1
|
||||
phy_xaui_tx_polarity_flip_91=0x1
|
||||
phy_xaui_tx_polarity_flip_102=0x1
|
||||
phy_xaui_tx_polarity_flip_103=0x1
|
||||
phy_xaui_tx_polarity_flip_104=0x1
|
||||
phy_xaui_tx_polarity_flip_105=0x1
|
||||
phy_xaui_tx_polarity_flip_122=0xb
|
||||
|
||||
#Driver Current
|
||||
serdes_driver_current_42=0x8
|
||||
serdes_driver_current_43=0x8
|
||||
serdes_driver_current_44=0x8
|
||||
serdes_driver_current_45=0x8
|
||||
serdes_driver_current_50=0x8
|
||||
serdes_driver_current_51=0x8
|
||||
serdes_driver_current_52=0x8
|
||||
serdes_driver_current_53=0x8
|
||||
serdes_driver_current_54=0x8
|
||||
serdes_driver_current_55=0x8
|
||||
serdes_driver_current_56=0x8
|
||||
serdes_driver_current_57=0x8
|
||||
serdes_driver_current_68=0x8
|
||||
serdes_driver_current_69=0x8
|
||||
serdes_driver_current_70=0x8
|
||||
serdes_driver_current_71=0x8
|
||||
serdes_driver_current_34=0x8
|
||||
serdes_driver_current_35=0x8
|
||||
serdes_driver_current_36=0x8
|
||||
serdes_driver_current_37=0x8
|
||||
serdes_driver_current_38=0x8
|
||||
serdes_driver_current_39=0x8
|
||||
serdes_driver_current_40=0x8
|
||||
serdes_driver_current_41=0x8
|
||||
serdes_driver_current_72=0x8
|
||||
serdes_driver_current_73=0x8
|
||||
serdes_driver_current_74=0x8
|
||||
serdes_driver_current_75=0x8
|
||||
serdes_driver_current_84=0x8
|
||||
serdes_driver_current_85=0x8
|
||||
serdes_driver_current_86=0x8
|
||||
serdes_driver_current_87=0x8
|
||||
serdes_driver_current_88=0x8
|
||||
serdes_driver_current_89=0x8
|
||||
serdes_driver_current_90=0x8
|
||||
serdes_driver_current_91=0x8
|
||||
serdes_driver_current_102=0x8
|
||||
serdes_driver_current_103=0x8
|
||||
serdes_driver_current_104=0x8
|
||||
serdes_driver_current_105=0x8
|
||||
serdes_driver_current_106=0x8
|
||||
serdes_driver_current_107=0x8
|
||||
serdes_driver_current_108=0x8
|
||||
serdes_driver_current_109=0x8
|
||||
serdes_driver_current_110=0x8
|
||||
serdes_driver_current_111=0x8
|
||||
serdes_driver_current_112=0x8
|
||||
serdes_driver_current_113=0x8
|
||||
serdes_driver_current_lane0_5=0x8
|
||||
serdes_driver_current_lane1_5=0x8
|
||||
serdes_driver_current_lane2_5=0x8
|
||||
serdes_driver_current_lane3_5=0x8
|
||||
serdes_driver_current_lane0_1=0x8
|
||||
serdes_driver_current_lane1_1=0x8
|
||||
serdes_driver_current_lane2_1=0x8
|
||||
serdes_driver_current_lane3_1=0x8
|
||||
serdes_driver_current_lane0_114=0x8
|
||||
serdes_driver_current_lane1_114=0x8
|
||||
serdes_driver_current_lane2_114=0x8
|
||||
serdes_driver_current_lane3_114=0x8
|
||||
serdes_driver_current_lane0_21=0x8
|
||||
serdes_driver_current_lane1_21=0x8
|
||||
serdes_driver_current_lane2_21=0x8
|
||||
serdes_driver_current_lane3_21=0x8
|
||||
serdes_driver_current_lane0_9=0x8
|
||||
serdes_driver_current_lane1_9=0x8
|
||||
serdes_driver_current_lane2_9=0x8
|
||||
serdes_driver_current_lane3_9=0x8
|
||||
serdes_driver_current_lane0_122=0x8
|
||||
serdes_driver_current_lane1_122=0x8
|
||||
serdes_driver_current_lane2_122=0x8
|
||||
serdes_driver_current_lane3_122=0x8
|
||||
|
||||
#Preemphasis
|
||||
serdes_preemphasis_42=0x264006
|
||||
serdes_preemphasis_43=0x264006
|
||||
serdes_preemphasis_44=0x254106
|
||||
serdes_preemphasis_45=0x254106
|
||||
serdes_preemphasis_50=0x254106
|
||||
serdes_preemphasis_51=0x254106
|
||||
serdes_preemphasis_52=0x254106
|
||||
serdes_preemphasis_53=0x254106
|
||||
serdes_preemphasis_54=0x254106
|
||||
serdes_preemphasis_55=0x254106
|
||||
serdes_preemphasis_56=0x254106
|
||||
serdes_preemphasis_57=0x234306
|
||||
serdes_preemphasis_68=0x234306
|
||||
serdes_preemphasis_69=0x204606
|
||||
serdes_preemphasis_70=0x204606
|
||||
serdes_preemphasis_71=0x204606
|
||||
serdes_preemphasis_34=0x234306
|
||||
serdes_preemphasis_35=0x234306
|
||||
serdes_preemphasis_36=0x234306
|
||||
serdes_preemphasis_37=0x234306
|
||||
serdes_preemphasis_38=0x234306
|
||||
serdes_preemphasis_39=0x234306
|
||||
serdes_preemphasis_40=0x234306
|
||||
serdes_preemphasis_41=0x234306
|
||||
serdes_preemphasis_72=0x1e4806
|
||||
serdes_preemphasis_73=0x1e4806
|
||||
serdes_preemphasis_74=0x1e4806
|
||||
serdes_preemphasis_75=0x1e4806
|
||||
serdes_preemphasis_84=0x1e4806
|
||||
serdes_preemphasis_85=0x1a4c06
|
||||
serdes_preemphasis_86=0x1a4c06
|
||||
serdes_preemphasis_87=0x1b4b06
|
||||
serdes_preemphasis_88=0x1b4b06
|
||||
serdes_preemphasis_89=0x1e4806
|
||||
serdes_preemphasis_90=0x1e4806
|
||||
serdes_preemphasis_91=0x1e4806
|
||||
serdes_preemphasis_102=0x1e4806
|
||||
serdes_preemphasis_103=0x1e4806
|
||||
serdes_preemphasis_104=0x1e4806
|
||||
serdes_preemphasis_105=0x1e4806
|
||||
serdes_preemphasis_106=0x1e4806
|
||||
serdes_preemphasis_107=0x1e4806
|
||||
serdes_preemphasis_108=0x1e4806
|
||||
serdes_preemphasis_109=0x1e4806
|
||||
serdes_preemphasis_110=0x1e4806
|
||||
serdes_preemphasis_111=0x1d4906
|
||||
serdes_preemphasis_112=0x234306
|
||||
serdes_preemphasis_113=0x1f4706
|
||||
serdes_preemphasis_lane0_5=0x294106
|
||||
serdes_preemphasis_lane1_5=0x294106
|
||||
serdes_preemphasis_lane2_5=0x294106
|
||||
serdes_preemphasis_lane3_5=0x294106
|
||||
serdes_preemphasis_lane0_1=0x294106
|
||||
serdes_preemphasis_lane1_1=0x294106
|
||||
serdes_preemphasis_lane2_1=0x294106
|
||||
serdes_preemphasis_lane3_1=0x294106
|
||||
serdes_preemphasis_lane0_114=0x2a4006
|
||||
serdes_preemphasis_lane1_114=0x2a4006
|
||||
serdes_preemphasis_lane2_114=0x2a4006
|
||||
serdes_preemphasis_lane3_114=0x2a4006
|
||||
serdes_preemphasis_lane0_21=0x2c3c08
|
||||
serdes_preemphasis_lane1_21=0x2a4006
|
||||
serdes_preemphasis_lane2_21=0x2a4006
|
||||
serdes_preemphasis_lane3_21=0x2a4006
|
||||
serdes_preemphasis_lane0_9=0x284206
|
||||
serdes_preemphasis_lane1_9=0x284206
|
||||
serdes_preemphasis_lane2_9=0x284206
|
||||
serdes_preemphasis_lane3_9=0x284206
|
||||
serdes_preemphasis_lane0_122=0x283e06
|
||||
serdes_preemphasis_lane1_122=0x283e06
|
||||
serdes_preemphasis_lane2_122=0x283e06
|
||||
serdes_preemphasis_lane3_122=0x294601
|
||||
@@ -0,0 +1,3 @@
|
||||
CONSOLE_PORT=0x2f8
|
||||
CONSOLE_DEV=1
|
||||
CONSOLE_SPEED=115200
|
||||
79
device/accton/x86_64-accton_as7312_54xs-r0/led_proc_init.soc
Executable file
79
device/accton/x86_64-accton_as7312_54xs-r0/led_proc_init.soc
Executable file
@@ -0,0 +1,79 @@
|
||||
# accton_as7312_54x 48x25G+6x100G SDK port LED macro init SOC
|
||||
s CMIC_LEDUP0_DATA_RAM 0
|
||||
s CMIC_LEDUP1_DATA_RAM 0
|
||||
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=63 REMAP_PORT_1=63 REMAP_PORT_2=63 REMAP_PORT_3=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=63 REMAP_PORT_5=63 REMAP_PORT_6=63 REMAP_PORT_7=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=27 REMAP_PORT_9=26 REMAP_PORT_10=25 REMAP_PORT_11=24
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=63 REMAP_PORT_13=63 REMAP_PORT_14=63 REMAP_PORT_15=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=63 REMAP_PORT_17=63 REMAP_PORT_18=63 REMAP_PORT_19=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=31 REMAP_PORT_21=30 REMAP_PORT_22=29 REMAP_PORT_23=28
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=15 REMAP_PORT_25=14 REMAP_PORT_26=13 REMAP_PORT_27=12
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=19 REMAP_PORT_29=18 REMAP_PORT_30=17 REMAP_PORT_31=16
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=63 REMAP_PORT_33=63 REMAP_PORT_34=63 REMAP_PORT_35=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=63 REMAP_PORT_37=63 REMAP_PORT_38=63 REMAP_PORT_39=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=35 REMAP_PORT_41=34 REMAP_PORT_42=33 REMAP_PORT_43=32
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=63 REMAP_PORT_45=63 REMAP_PORT_46=63 REMAP_PORT_47=63
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=23 REMAP_PORT_49=22 REMAP_PORT_50=21 REMAP_PORT_51=20
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=11 REMAP_PORT_53=10 REMAP_PORT_54=9 REMAP_PORT_55=8
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=7 REMAP_PORT_57=6 REMAP_PORT_58=5 REMAP_PORT_59=4
|
||||
m CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=3 REMAP_PORT_61=2 REMAP_PORT_62=1 REMAP_PORT_63=0
|
||||
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 REMAP_PORT_0=19 REMAP_PORT_1=18 REMAP_PORT_2=17 REMAP_PORT_3=16
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 REMAP_PORT_4=23 REMAP_PORT_5=22 REMAP_PORT_6=21 REMAP_PORT_7=20
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 REMAP_PORT_8=3 REMAP_PORT_9=2 REMAP_PORT_10=1 REMAP_PORT_11=0
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 REMAP_PORT_12=63 REMAP_PORT_13=63 REMAP_PORT_14=63 REMAP_PORT_15=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 REMAP_PORT_16=7 REMAP_PORT_17=6 REMAP_PORT_18=5 REMAP_PORT_19=4
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 REMAP_PORT_20=11 REMAP_PORT_21=10 REMAP_PORT_22=9 REMAP_PORT_23=8
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 REMAP_PORT_24=63 REMAP_PORT_25=63 REMAP_PORT_26=63 REMAP_PORT_27=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 REMAP_PORT_28=63 REMAP_PORT_29=63 REMAP_PORT_30=63 REMAP_PORT_31=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 REMAP_PORT_32=15 REMAP_PORT_33=14 REMAP_PORT_34=13 REMAP_PORT_35=12
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 REMAP_PORT_36=27 REMAP_PORT_37=26 REMAP_PORT_38=25 REMAP_PORT_39=24
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 REMAP_PORT_40=63 REMAP_PORT_41=63 REMAP_PORT_42=63 REMAP_PORT_43=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 REMAP_PORT_44=63 REMAP_PORT_45=63 REMAP_PORT_46=63 REMAP_PORT_47=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 REMAP_PORT_48=31 REMAP_PORT_49=30 REMAP_PORT_50=29 REMAP_PORT_51=28
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 REMAP_PORT_52=35 REMAP_PORT_53=34 REMAP_PORT_54=33 REMAP_PORT_55=32
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 REMAP_PORT_56=63 REMAP_PORT_57=63 REMAP_PORT_58=63 REMAP_PORT_59=63
|
||||
m CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 REMAP_PORT_60=63 REMAP_PORT_61=63 REMAP_PORT_62=63 REMAP_PORT_63=63
|
||||
|
||||
led 0 stop
|
||||
led 0 prog \
|
||||
02 FD 42 80 02 FF 42 00 02 FE 42 00 02 FA 42 7E \
|
||||
02 FB 42 24 06 F9 D2 00 74 1E 02 F9 42 03 67 AC \
|
||||
67 C3 67 52 86 FE 67 C3 67 52 86 FE 67 C3 67 52 \
|
||||
86 FE 67 C3 67 52 86 FE 06 FB D6 FE 74 1E 86 FC \
|
||||
3E FA 06 FE 88 4A 03 71 4C 67 84 57 67 84 57 67 \
|
||||
98 57 06 FE 88 80 4A 00 27 97 75 4F 90 4A 00 27 \
|
||||
4A 01 27 B7 97 71 69 77 42 06 F9 D6 FC 74 7C 02 \
|
||||
F9 4A 07 37 4E 07 02 FC 42 00 4E 07 06 F9 0A 07 \
|
||||
71 4F 77 42 16 FF 06 FD 17 4D DA 07 74 95 12 FF \
|
||||
52 00 86 FD 57 86 FF 57 16 FF 06 FD 07 4D DA 07 \
|
||||
74 A9 12 FF 52 00 86 FD 57 86 FF 57 06 FE C2 FC \
|
||||
98 98 12 F4 50 C2 FC 98 98 F2 F0 14 06 F4 C2 03 \
|
||||
88 77 D1 06 FE C2 FC 98 98 F2 E0 14 06 FE C2 03 \
|
||||
88 18 71 E2 80 18 71 DD 67 98 67 98 57 67 98 67 \
|
||||
84 57 80 18 71 EB 67 84 67 98 57 67 84 67 84 57 \
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
led 0 start
|
||||
led auto on
|
||||
|
||||
led 1 stop
|
||||
led 1 prog \
|
||||
02 FD 42 80 02 FF 42 00 02 FE 42 00 02 FA 42 7E \
|
||||
02 FB 42 24 06 F9 D2 00 74 1E 02 F9 42 03 67 AC \
|
||||
67 C3 67 52 86 FE 67 C3 67 52 86 FE 67 C3 67 52 \
|
||||
86 FE 67 C3 67 52 86 FE 06 FB D6 FE 74 1E 86 FC \
|
||||
3E FA 06 FE 88 4A 03 71 4C 67 84 57 67 84 57 67 \
|
||||
98 57 06 FE 88 80 4A 00 27 97 75 4F 90 4A 00 27 \
|
||||
4A 01 27 B7 97 71 69 77 42 06 F9 D6 FC 74 7C 02 \
|
||||
F9 4A 07 37 4E 07 02 FC 42 00 4E 07 06 F9 0A 07 \
|
||||
71 4F 77 42 16 FF 06 FD 17 4D DA 07 74 95 12 FF \
|
||||
52 00 86 FD 57 86 FF 57 16 FF 06 FD 07 4D DA 07 \
|
||||
74 A9 12 FF 52 00 86 FD 57 86 FF 57 06 FE C2 FC \
|
||||
98 98 12 F4 50 C2 FC 98 98 F2 F0 14 06 F4 C2 03 \
|
||||
88 77 D1 06 FE C2 FC 98 98 F2 E0 14 06 FE C2 03 \
|
||||
88 18 71 E2 80 18 71 DD 67 98 67 98 57 67 98 67 \
|
||||
84 57 80 18 71 EB 67 84 67 98 57 67 84 67 84 57 \
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
led 1 start
|
||||
led auto on
|
||||
1184
device/accton/x86_64-accton_as7312_54xs-r0/minigraph.xml
Normal file
1184
device/accton/x86_64-accton_as7312_54xs-r0/minigraph.xml
Normal file
File diff suppressed because it is too large
Load Diff
24
device/accton/x86_64-accton_as7312_54xs-r0/plugins/eeprom.py
Normal file
24
device/accton/x86_64-accton_as7312_54xs-r0/plugins/eeprom.py
Normal file
@@ -0,0 +1,24 @@
|
||||
#!/usr/bin/env python
|
||||
|
||||
try:
|
||||
import exceptions
|
||||
import binascii
|
||||
import time
|
||||
import optparse
|
||||
import warnings
|
||||
import os
|
||||
import sys
|
||||
from sonic_eeprom import eeprom_base
|
||||
from sonic_eeprom import eeprom_tlvinfo
|
||||
import subprocess
|
||||
except ImportError, e:
|
||||
raise ImportError (str(e) + "- required module not found")
|
||||
|
||||
class board(eeprom_tlvinfo.TlvInfoDecoder):
|
||||
_TLV_INFO_MAX_LEN = 256
|
||||
def __init__(self, name, path, cpld_root, ro):
|
||||
self.eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
|
||||
#Two i2c buses might get flipped order, check them both.
|
||||
if not os.path.exists(self.eeprom_path):
|
||||
self.eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
|
||||
super(board, self).__init__(self.eeprom_path, 0, '', True)
|
||||
@@ -0,0 +1,61 @@
|
||||
#!/usr/bin/env python
|
||||
|
||||
#############################################################################
|
||||
# Accton
|
||||
#
|
||||
# Module contains an implementation of SONiC PSU Base API and
|
||||
# provides the PSUs status which are available in the platform
|
||||
#
|
||||
#############################################################################
|
||||
|
||||
import os.path
|
||||
|
||||
try:
|
||||
from sonic_psu.psu_base import PsuBase
|
||||
except ImportError as e:
|
||||
raise ImportError (str(e) + "- required module not found")
|
||||
|
||||
class PsuUtil(PsuBase):
|
||||
"""Platform-specific PSUutil class"""
|
||||
|
||||
def __init__(self):
|
||||
PsuBase.__init__(self)
|
||||
|
||||
self.psu_path = "/sys/bus/i2c/devices/"
|
||||
self.psu_presence = "/psu_present"
|
||||
self.psu_oper_status = "/psu_power_good"
|
||||
self.psu_mapping = {
|
||||
2: "11-0053",
|
||||
1: "10-0050",
|
||||
}
|
||||
|
||||
def get_num_psus(self):
|
||||
return len(self.psu_mapping)
|
||||
|
||||
def get_psu_status(self, index):
|
||||
if index is None:
|
||||
return False
|
||||
|
||||
status = 0
|
||||
node = self.psu_path + self.psu_mapping[index]+self.psu_oper_status
|
||||
try:
|
||||
with open(node, 'r') as power_status:
|
||||
status = int(power_status.read())
|
||||
except IOError:
|
||||
return False
|
||||
|
||||
return status == 1
|
||||
|
||||
def get_psu_presence(self, index):
|
||||
if index is None:
|
||||
return False
|
||||
|
||||
status = 0
|
||||
node = self.psu_path + self.psu_mapping[index] + self.psu_presence
|
||||
try:
|
||||
with open(node, 'r') as presence_status:
|
||||
status = int(presence_status.read())
|
||||
except IOError:
|
||||
return False
|
||||
|
||||
return status == 1
|
||||
215
device/accton/x86_64-accton_as7312_54xs-r0/plugins/sfputil.py
Normal file
215
device/accton/x86_64-accton_as7312_54xs-r0/plugins/sfputil.py
Normal file
@@ -0,0 +1,215 @@
|
||||
# sfputil.py
|
||||
#
|
||||
# Platform-specific SFP transceiver interface for SONiC
|
||||
#
|
||||
|
||||
try:
|
||||
import time
|
||||
from sonic_sfp.sfputilbase import SfpUtilBase
|
||||
except ImportError as e:
|
||||
raise ImportError("%s - required module not found" % str(e))
|
||||
|
||||
|
||||
class SfpUtil(SfpUtilBase):
|
||||
"""Platform-specific SfpUtil class"""
|
||||
|
||||
PORT_START = 0
|
||||
PORT_END = 71
|
||||
PORTS_IN_BLOCK = 72
|
||||
QSFP_PORT_START = 48
|
||||
QSFP_PORT_END = 72
|
||||
|
||||
BASE_VAL_PATH = "/sys/class/i2c-adapter/i2c-{0}/{1}-0050/"
|
||||
|
||||
_port_to_is_present = {}
|
||||
_port_to_lp_mode = {}
|
||||
|
||||
_port_to_eeprom_mapping = {}
|
||||
_cpld_mapping = {
|
||||
0: "4-0060",
|
||||
1: "5-0062",
|
||||
2: "6-0064",
|
||||
}
|
||||
_port_to_i2c_mapping = {
|
||||
0: 18,
|
||||
1: 19,
|
||||
2: 20,
|
||||
3: 21,
|
||||
4: 22,
|
||||
5: 23,
|
||||
6: 24,
|
||||
7: 25,
|
||||
8: 26,
|
||||
9: 27,
|
||||
10: 28,
|
||||
11: 29,
|
||||
12: 30,
|
||||
13: 31,
|
||||
14: 32,
|
||||
15: 33,
|
||||
16: 34,
|
||||
17: 35,
|
||||
18: 36,
|
||||
19: 37,
|
||||
20: 38,
|
||||
21: 39,
|
||||
22: 40,
|
||||
23: 41,
|
||||
24: 42,
|
||||
25: 43,
|
||||
26: 44,
|
||||
27: 45,
|
||||
28: 46,
|
||||
29: 47,
|
||||
30: 48,
|
||||
31: 49,
|
||||
32: 50,
|
||||
33: 51,
|
||||
34: 52,
|
||||
35: 53,
|
||||
36: 54,
|
||||
37: 55,
|
||||
38: 56,
|
||||
39: 57,
|
||||
40: 58,
|
||||
41: 59,
|
||||
42: 60,
|
||||
43: 61,
|
||||
44: 62,
|
||||
45: 63,
|
||||
46: 64,
|
||||
47: 65,
|
||||
48: 66, #QSFP49
|
||||
49: 66,
|
||||
50: 66,
|
||||
51: 66,
|
||||
52: 67, #QSFP50
|
||||
53: 67,
|
||||
54: 67,
|
||||
55: 67,
|
||||
56: 68, #QSFP51
|
||||
57: 68,
|
||||
58: 68,
|
||||
59: 68,
|
||||
60: 69, #QSFP52
|
||||
61: 69,
|
||||
62: 69,
|
||||
63: 69,
|
||||
64: 70, #QSFP53
|
||||
65: 70,
|
||||
66: 70,
|
||||
67: 70,
|
||||
68: 71, #QSFP54
|
||||
69: 71,
|
||||
70: 71,
|
||||
71: 71,
|
||||
}
|
||||
|
||||
@property
|
||||
def port_start(self):
|
||||
return self.PORT_START
|
||||
|
||||
@property
|
||||
def port_end(self):
|
||||
return self.PORT_END
|
||||
|
||||
@property
|
||||
def qsfp_port_start(self):
|
||||
return self.QSFP_PORT_START
|
||||
|
||||
@property
|
||||
def qsfp_port_end(self):
|
||||
return self.QSFP_PORT_END
|
||||
|
||||
@property
|
||||
def qsfp_ports(self):
|
||||
return range(self.QSFP_PORT_START, self.PORTS_IN_BLOCK + 1)
|
||||
|
||||
@property
|
||||
def port_to_eeprom_mapping(self):
|
||||
return self._port_to_eeprom_mapping
|
||||
|
||||
def __init__(self):
|
||||
eeprom_path = '/sys/bus/i2c/devices/{0}-0050/eeprom'
|
||||
for x in range(0, self.port_end+1):
|
||||
self.port_to_eeprom_mapping[x] = eeprom_path.format(
|
||||
self._port_to_i2c_mapping[x])
|
||||
|
||||
SfpUtilBase.__init__(self)
|
||||
|
||||
|
||||
# For port 48~51 are QSFP, here presumed they're all split to 4 lanes.
|
||||
def get_cage_num(self, port_num):
|
||||
cage_num = port_num
|
||||
if (port_num >= self.QSFP_PORT_START):
|
||||
cage_num = (port_num - self.QSFP_PORT_START)/4
|
||||
cage_num = cage_num + self.QSFP_PORT_START
|
||||
|
||||
return cage_num
|
||||
|
||||
# For cage 0~23 and 48~51 are at cpld2, others are at cpld3.
|
||||
def get_cpld_num(self, port_num):
|
||||
cpld_i = 1
|
||||
cage_num = self.get_cage_num(port_num)
|
||||
if (port_num > 23 and port_num < self.QSFP_PORT_START):
|
||||
cpld_i = 2
|
||||
|
||||
if (cage_num >= 52):
|
||||
cpld_i = 2
|
||||
|
||||
return cpld_i
|
||||
|
||||
def get_presence(self, port_num):
|
||||
# Check for invalid port_num
|
||||
if port_num < self.port_start or port_num > self.port_end:
|
||||
return False
|
||||
|
||||
cage_num = self.get_cage_num(port_num)
|
||||
cpld_i = self.get_cpld_num(port_num)
|
||||
|
||||
cpld_ps = self._cpld_mapping[cpld_i]
|
||||
path = "/sys/bus/i2c/devices/{0}/module_present_{1}"
|
||||
port_ps = path.format(cpld_ps, cage_num+1)
|
||||
|
||||
try:
|
||||
val_file = open(port_ps)
|
||||
except IOError as e:
|
||||
print "Error: unable to open file: %s" % str(e)
|
||||
return False
|
||||
|
||||
content = val_file.readline().rstrip()
|
||||
val_file.close()
|
||||
|
||||
# content is a string, either "0" or "1"
|
||||
if content == "1":
|
||||
return True
|
||||
|
||||
return False
|
||||
|
||||
def get_low_power_mode(self, port_num):
|
||||
raise NotImplementedError
|
||||
|
||||
def set_low_power_mode(self, port_num, lpmode):
|
||||
raise NotImplementedError
|
||||
|
||||
def reset(self, port_num):
|
||||
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
|
||||
return False
|
||||
|
||||
cage_num = self.get_cage_num(port_num)
|
||||
cpld_i = self.get_cpld_num(port_num)
|
||||
cpld_ps = self._cpld_mapping[cpld_i]
|
||||
path = "/sys/bus/i2c/devices/{0}/module_reset_{1}"
|
||||
port_ps = path.format(cpld_ps, cage_num+1)
|
||||
try:
|
||||
reg_file = open(port_ps, 'w')
|
||||
except IOError as e:
|
||||
print "Error: unable to open file: %s" % str(e)
|
||||
return False
|
||||
|
||||
reg_value = '0'
|
||||
|
||||
reg_file.write(reg_value)
|
||||
reg_file.close()
|
||||
|
||||
return True
|
||||
Reference in New Issue
Block a user