mirror of
https://github.com/Telecominfraproject/ols-nos.git
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a582c13e98
Add new platform x86_64-ruijie_b6510-48vs8cq-r0 (Trident 3)
ASIC Vendor: Broadcom
Switch ASIC: Trident 3
Port Config: 48x25G+8x100G
Signed-off-by: tim-rj <sonic_rd@ruijie.com.cn>
358 lines
9.2 KiB
C
358 lines
9.2 KiB
C
/*
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* GPIO interface for XEON Super I/O chip
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*
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* Author: sonic_rd <sonic_rd@ruijie.com.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/platform_data/i2c-gpio.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <asm/delay.h>
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#include <linux/miscdevice.h>
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#include <linux/gpio/machine.h>
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#define GPIO_NAME "xeon-gpio"
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#define GPIO_IOSIZE 7
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#define GPIO_BASE 0x500
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#define GPIO_USE_SEL GPIO_BASE
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#define GP_IO_SEL (GPIO_BASE+0x4)
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#define GP_LVL (GPIO_BASE+0xC)
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#define GPIO_USE_SEL2 (GPIO_BASE+0x30)
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#define GP_IO_SEL2 (GPIO_BASE+0x34)
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#define GP_LVL2 (GPIO_BASE+0x38)
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#define GPIO_USE_SEL3 (GPIO_BASE+0x40)
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#define GP_IO_SEL3 (GPIO_BASE+0x44)
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#define GP_LVL3 (GPIO_BASE+0x48)
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#define GPIO_BASE_ID 0
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#define BANKSIZE 32
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#define GPIO_SDA 17
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#define GPIO_SCL 1
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#define GPIO_XEON_SPIN_LOCK(lock, flags) spin_lock_irqsave(&(lock), (flags))
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#define GPIO_XEON_SPIN_UNLOCK(lock, flags) spin_unlock_irqrestore(&(lock), (flags))
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static DEFINE_SPINLOCK(sio_lock);
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/****************** i2c adapter with gpio ***********************/
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static struct i2c_gpio_platform_data i2c_pdata = {
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.timeout = 200,
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.udelay = 10,
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.scl_is_output_only = 0,
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.sda_is_open_drain = 0,
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.scl_is_open_drain = 0,
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};
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static struct gpiod_lookup_table rg_gpio_lookup_table = {
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.dev_id = "i2c-gpio",
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.table = {
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GPIO_LOOKUP(GPIO_NAME, GPIO_SDA, "sda",
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GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP(GPIO_NAME, GPIO_SCL, "scl",
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GPIO_ACTIVE_HIGH),
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},
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};
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static void i2c_gpio_release(struct device *dev)
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{
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return;
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}
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static struct platform_device i2c_gpio = {
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.name = "i2c-gpio",
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.num_resources = 0,
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.id = -1,
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.dev = {
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.platform_data = &i2c_pdata,
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.release = i2c_gpio_release,
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}
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};
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static int xeon_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
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{
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unsigned int data;
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unsigned int bank, offset;
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unsigned long flags;
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data = 0;
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bank = gpio_num / BANKSIZE;
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offset = gpio_num % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GP_LVL) & (1 << offset);
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if (data) {
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data = 1;
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}
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} else if (bank == 1) {
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data = inl(GP_LVL2) & (1 << offset);
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if (data) {
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data = 1;
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}
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} else if (bank == 2) {
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data = inl(GP_LVL3) & (1 << offset);
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if (data) {
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data = 1;
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}
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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return data;
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}
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static int xeon_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
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{
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unsigned int data;
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unsigned int bank, offset;
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unsigned long flags;
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bank = gpio_num / BANKSIZE;
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offset = gpio_num % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GP_IO_SEL);
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data = data | (1 << offset);
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outl(data, GP_IO_SEL);
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} else if (bank == 1) {
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data = inl(GP_IO_SEL2);
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data = data | (1 << offset);
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outl(data, GP_IO_SEL2);
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} else if (bank == 2) {
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data = inl(GP_IO_SEL3);
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data = data | (1 << offset);
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outl(data, GP_IO_SEL3);
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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return 0;
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}
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static void xeon_gpio_set(struct gpio_chip *gc,
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unsigned gpio_num, int val)
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{
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unsigned int data;
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unsigned int bank, offset;
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unsigned long flags;
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bank = gpio_num / BANKSIZE;
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offset = gpio_num % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GP_LVL);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL);
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} else if (bank == 1) {
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data = inl(GP_LVL2);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL2);
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} else if (bank == 2) {
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data = inl(GP_LVL3);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL3);
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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}
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static int xeon_gpio_direction_out(struct gpio_chip *gc,
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unsigned gpio_num, int val)
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{
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unsigned int data;
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unsigned int bank, offset;
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unsigned long flags;
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bank = gpio_num / BANKSIZE;
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offset = gpio_num % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GP_IO_SEL);
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data = data & ~(1 << offset);
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outl(data, GP_IO_SEL);
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data = inl(GP_LVL);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL);
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} else if (bank == 1) {
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data = inl(GP_IO_SEL2);
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data = data & ~(1 << offset);
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outl(data, GP_IO_SEL2);
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data = inl(GP_LVL2);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL2);
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} else if (bank == 2) {
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data = inl(GP_IO_SEL3);
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data = data & ~(1 << offset);
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outl(data, GP_IO_SEL3);
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data = inl(GP_LVL3);
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if (val) {
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data = data | (1 << offset);
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} else {
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data = data & ~(1 << offset);
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}
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outl(data, GP_LVL3);
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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return 0;
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}
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static int xeon_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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unsigned int data;
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unsigned int bank, tmp_offset;
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unsigned long flags;
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bank = offset / BANKSIZE;
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tmp_offset = offset % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GPIO_USE_SEL);
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data = data | (1 << tmp_offset);
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outl(data, GPIO_USE_SEL);
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} else if (bank == 1) {
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data = inl(GPIO_USE_SEL2);
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data = data | (1 << tmp_offset);
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outl(data, GPIO_USE_SEL2);
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} else if (bank == 2) {
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data = inl(GPIO_USE_SEL3);
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data = data | (1 << tmp_offset);
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outl(data, GPIO_USE_SEL3);
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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return 0;
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}
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static void xeon_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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unsigned int data;
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unsigned int bank, tmp_offset;
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unsigned long flags;
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bank = offset / BANKSIZE;
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tmp_offset = offset % BANKSIZE;
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GPIO_XEON_SPIN_LOCK(sio_lock, flags);
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if (bank == 0) {
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data = inl(GPIO_USE_SEL);
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data = data & ~(1 << tmp_offset);
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outl(data, GPIO_USE_SEL);
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} else if (bank == 1) {
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data = inl(GPIO_USE_SEL2);
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data = data & ~(1 << tmp_offset);
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outl(data, GPIO_USE_SEL2);
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} else if (bank == 2) {
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data = inl(GPIO_USE_SEL3);
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data = data & ~(1 << tmp_offset);
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outl(data, GPIO_USE_SEL3);
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}
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GPIO_XEON_SPIN_UNLOCK(sio_lock, flags);
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}
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static struct gpio_chip xeon_gpio_chip = {
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.label = GPIO_NAME,
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.owner = THIS_MODULE,
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.get = xeon_gpio_get,
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.direction_input = xeon_gpio_direction_in,
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.set = xeon_gpio_set,
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.direction_output = xeon_gpio_direction_out,
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.request = xeon_gpio_request,
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.free = xeon_gpio_free,
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};
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static int __init xeon_gpio_init(void)
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{
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int err;
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if (!request_region(GPIO_BASE, GPIO_IOSIZE, GPIO_NAME))
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return -EBUSY;
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xeon_gpio_chip.base = GPIO_BASE_ID;
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xeon_gpio_chip.ngpio = 96;
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err = gpiochip_add_data(&xeon_gpio_chip, NULL);
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if (err < 0)
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goto gpiochip_add_err;
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gpiod_add_lookup_table(&rg_gpio_lookup_table);
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err = platform_device_register(&i2c_gpio);
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if (err < 0) {
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goto i2c_get_adapter_err;
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}
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return 0;
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i2c_get_adapter_err:
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gpiod_remove_lookup_table(&rg_gpio_lookup_table);
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platform_device_unregister(&i2c_gpio);
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gpiochip_remove(&xeon_gpio_chip);
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gpiochip_add_err:
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release_region(GPIO_BASE, GPIO_IOSIZE);
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return -1;
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}
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static void __exit xeon_gpio_exit(void)
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{
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gpiod_remove_lookup_table(&rg_gpio_lookup_table);
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platform_device_unregister(&i2c_gpio);
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mdelay(100);
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gpiochip_remove(&xeon_gpio_chip);
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release_region(GPIO_BASE, GPIO_IOSIZE);
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}
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module_init(xeon_gpio_init);
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module_exit(xeon_gpio_exit);
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MODULE_AUTHOR("sonic_rd <sonic_rd@ruijie.com.cn>");
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MODULE_DESCRIPTION("GPIO interface for XEON Super I/O chip");
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MODULE_LICENSE("GPL");
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