mirror of
https://github.com/optim-enterprises-bv/openwrt-ipq.git
synced 2025-10-30 01:43:02 +00:00
f02f6aaa8d
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
156 lines
4.0 KiB
Diff
156 lines
4.0 KiB
Diff
From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Date: Sat, 30 Jan 2021 10:50:05 +0530
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Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
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PRNG clock is needed by the secure PIL, support for the same
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is added in subsequent patches.
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Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
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---
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drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
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1 file changed, 47 insertions(+), 18 deletions(-)
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--- a/drivers/remoteproc/qcom_q6v5_wcss.c
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+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
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@@ -91,19 +91,6 @@ enum {
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WCSS_QCS404,
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};
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-struct wcss_data {
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- const char *firmware_name;
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- unsigned int crash_reason_smem;
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- u32 version;
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- bool aon_reset_required;
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- bool wcss_q6_reset_required;
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- const char *ssr_name;
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- const char *sysmon_name;
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- int ssctl_id;
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- const struct rproc_ops *ops;
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- bool requires_force_stop;
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-};
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-
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struct q6v5_wcss {
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struct device *dev;
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@@ -128,6 +115,7 @@ struct q6v5_wcss {
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struct clk *qdsp6ss_xo_cbcr;
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struct clk *qdsp6ss_core_gfmux;
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struct clk *lcc_bcr_sleep;
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+ struct clk *prng_clk;
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struct regulator *cx_supply;
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struct qcom_sysmon *sysmon;
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@@ -151,6 +139,21 @@ struct q6v5_wcss {
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struct qcom_rproc_ssr ssr_subdev;
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};
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+struct wcss_data {
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+ int (*init_clock)(struct q6v5_wcss *wcss);
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+ int (*init_regulator)(struct q6v5_wcss *wcss);
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+ const char *firmware_name;
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+ unsigned int crash_reason_smem;
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+ u32 version;
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+ bool aon_reset_required;
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+ bool wcss_q6_reset_required;
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+ const char *ssr_name;
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+ const char *sysmon_name;
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+ int ssctl_id;
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+ const struct rproc_ops *ops;
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+ bool requires_force_stop;
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+};
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+
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static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
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{
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int ret;
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@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
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struct q6v5_wcss *wcss = rproc->priv;
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int ret;
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+ ret = clk_prepare_enable(wcss->prng_clk);
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+ if (ret) {
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+ dev_err(wcss->dev, "prng clock enable failed\n");
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+ return ret;
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+ }
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+
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qcom_q6v5_prepare(&wcss->q6v5);
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/* Release Q6 and WCSS reset */
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@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
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return ret;
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}
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+ clk_disable_unprepare(wcss->prng_clk);
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qcom_q6v5_unprepare(&wcss->q6v5);
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return 0;
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@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
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return 0;
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}
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-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
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+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
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+{
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+ int ret;
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+
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+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
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+ if (IS_ERR(wcss->prng_clk)) {
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+ ret = PTR_ERR(wcss->prng_clk);
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+ if (ret != -EPROBE_DEFER)
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+ dev_err(wcss->dev, "Failed to get prng clock\n");
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+static int qcs404_init_clock(struct q6v5_wcss *wcss)
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{
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int ret;
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@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
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return 0;
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}
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-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
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+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
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{
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wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
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if (IS_ERR(wcss->cx_supply))
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@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
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if (ret)
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goto free_rproc;
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- if (wcss->version == WCSS_QCS404) {
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- ret = q6v5_wcss_init_clock(wcss);
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+ if (desc->init_clock) {
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+ ret = desc->init_clock(wcss);
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if (ret)
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goto free_rproc;
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+ }
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- ret = q6v5_wcss_init_regulator(wcss);
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+ if (desc->init_regulator) {
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+ ret = desc->init_regulator(wcss);
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if (ret)
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goto free_rproc;
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}
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@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
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}
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static const struct wcss_data wcss_ipq8074_res_init = {
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+ .init_clock = ipq8074_init_clock,
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.firmware_name = "IPQ8074/q6_fw.mdt",
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.crash_reason_smem = WCSS_CRASH_REASON,
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.aon_reset_required = true,
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@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
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};
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static const struct wcss_data wcss_qcs404_res_init = {
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+ .init_clock = qcs404_init_clock,
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+ .init_regulator = qcs404_init_regulator,
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.crash_reason_smem = WCSS_CRASH_REASON,
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.firmware_name = "wcnss.mdt",
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.version = WCSS_QCS404,
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