/dts-v1/;
/*
 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
#include "qcom-ipq807x-soc.dtsi"
#include "qcom-ipq807x-audio.dtsi"
#include "qcom-ipq807x-hk-cpu.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "CIG WF196";
	compatible = "cig,wf196", "qcom,ipq807x";
	qcom,msm-id = <0x187 0x0>;
	interrupt-parent = <&intc>;
	qcom,board-id = <0x8 0x0>;
	qcom,pmic-id = <0x0 0x0 0x0 0x0>;

	aliases {
		/*
		 * Aliases as required by u-boot
		 * to patch MAC addresses
		 */
		ethernet0 = "/soc/dp1";
		ethernet1 = "/soc/dp2";
		ethernet2 = "/soc/dp3";
		ethernet3 = "/soc/dp4";
		ethernet4 = "/soc/dp5";
		ethernet5 = "/soc/dp6";

		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	chosen {
		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
		#ifdef __IPQ_MEM_PROFILE_256_MB__
			bootargs-append = " swiotlb=1";
		#else
			bootargs-append = " swiotlb=1 coherent_pool=2M vmalloc=600M";
		#endif
	};

	reserved-memory {
/* No Pine attach in 256M profile */
#if !defined(__IPQ_MEM_PROFILE_256_MB__)
#ifdef __IPQ_MEM_PROFILE_512_MB__
	/*                      512 MB Profile
	 * +========+==============+=========================+
	 * | Region | Start Offset |          Size           |
	 * +--------+--------------+-------------------------+
	 * |  NSS   |  0x40000000  |          16MB           |
	 * +--------+--------------+-------------------------+
	 * | Linux  |  0x41000000  | Depends on total memory |
	 * +--------+--------------+-------------------------+
	 * | TZ APP |  0x4A400000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | uboot  |  0x4A600000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |  SBL   |  0x4AA00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  smem  |  0x4AB00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |   TZ   |  0x4AC00000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |   Q6   |  0x4B000000  |          55MB           |
	 * +--------+--------------+-------------------------+
	 * |  QDSS  |  0x4E700000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | M3 Dump|  0x4E800000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  Pine0 |  0x4E900000  |          30MB           |
	 * +--------+--------------+-------------------------+
	 * |  MHI0  |  0x50700000  |          16MB           |
	 * +--------+--------------+-------------------------+
	 * |                                                 |
	 * |      Rest of the memory for Linux               |
	 * |                                                 |
	 * +=================================================+
	 */
		/delete-node/ wifi_dump@4e900000;
		qcn9000_pcie0@4e900000 {
			no-map;
			reg = <0x0 0x4e900000 0x0 0x01e00000>;
		};

		mhi_region0: dma_pool0@50700000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x50700000 0x0 0x01000000>;
		};
#else
	/*                   Default Profile
	 * +========+==============+=========================+
	 * | Region | Start Offset |          Size           |
	 * +--------+--------------+-------------------------+
	 * |  NSS   |  0x40000000  |          16MB           |
	 * +--------+--------------+-------------------------+
	 * | Linux  |  0x41000000  | Depends on total memory |
	 * +--------+--------------+-------------------------+
	 * | TZ APP |  0x4A400000  |           2MB           |
	 * +--------+--------------+-------------------------+
	 * | uboot  |  0x4A600000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |  SBL   |  0x4AA00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  smem  |  0x4AB00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |   TZ   |  0x4AC00000  |           4MB           |
	 * +--------+--------------+-------------------------+
	 * |   Q6   |  0x4B000000  |          95MB           |
	 * +--------+--------------+-------------------------+
	 * |  QDSS  |  0x50F00000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * | M3 Dump|  0x51000000  |           1MB           |
	 * +--------+--------------+-------------------------+
	 * |  Pine0 |  0x51100000  |          45MB           |
	 * +--------+--------------+-------------------------+
	 * |  MHI0  |  0x53E00000  |          24MB           |
	 * +--------+--------------+-------------------------+
	 * |                                                 |
	 * |          Rest of the memory for Linux           |
	 * |                                                 |
	 * +=================================================+
	 */
		qcn9000_pcie0@51100000 {
			no-map;
			reg = <0x0 0x51100000 0x0 0x02D00000>;
		};
		/delete-node/ wifi_dump@51100000;
		/delete-node/ wigig_dump@51300000;

		mhi_region0: dma_pool0@53e00000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x53E00000 0x0 0x01800000>;
		};
#endif
#endif
	};
};

&tlmm {
	pinctrl-0 = <&btcoex_pins>;
	pinctrl-names = "default";

	btcoex_pins: btcoex_pins {
		mux_0 {
			pins = "gpio64";
			function = "pta1_1";
			drive-strength = <6>;
			bias-pull-down;
		};
		mux_1 {
			pins = "gpio65";
			function = "pta1_2";
			drive-strength = <6>;
			bias-pull-down;
		};
		mux_2 {
			pins = "gpio66";
			function = "pta1_0";
			drive-strength = <6>;
			bias-pull-down;
		};
	};

	mdio_pins: mdio_pinmux {
		mux_0 {
			pins = "gpio68";
			function = "mdc";
			drive-strength = <8>;
			bias-pull-up;
		};
		mux_1 {
			pins = "gpio69";
			function = "mdio";
			drive-strength = <8>;
			bias-pull-up;
		};
		mux_3 {
			pins = "gpio44";
			function = "gpio";
			bias-pull-up;
		};
	};

	uart_pins: uart_pins {
		mux {
			pins = "gpio23", "gpio24";
			function = "blsp4_uart1";
			drive-strength = <8>;
			bias-disable;
		};
	};
	i2c_5_pins: i2c_5_pinmux {
                mux {
                        pins = "gpio0", "gpio2";
                        function = "blsp5_i2c";
                        drive-strength = <8>;
                        bias-disable;
                };
        };

	spi_0_pins: spi_0_pins {
		mux {
			pins = "gpio38", "gpio39", "gpio40", "gpio41";
			function = "blsp0_spi";
			drive-strength = <8>;
			bias-disable;
		};
	};

	spi_3_pins: spi_3_pins {
		mux {
			pins = "gpio50", "gpio52", "gpio53";
			function = "blsp3_spi";
			drive-strength = <8>;
			bias-disable;
		};
		spi_cs {
			pins = "gpio22";
			function = "blsp3_spi2";
			drive-strength = <8>;
			bias-disable;
		};
		quartz_interrupt {
			pins = "gpio47";
			function = "gpio";
			input;
			bias-disable;
		};
		quartz_reset {
			pins = "gpio21";
			function = "gpio";
			output-low;
			bias-disable;
		};
	};

	qpic_pins: qpic_pins {
		data_0 {
			pins = "gpio15";
			function = "qpic_pad0";
			drive-strength = <8>;
			bias-disable;
		};
		data_1 {
			pins = "gpio12";
			function = "qpic_pad1";
			drive-strength = <8>;
			bias-disable;
		};
		data_2 {
			pins = "gpio13";
			function = "qpic_pad2";
			drive-strength = <8>;
			bias-disable;
		};
		data_3 {
			pins = "gpio14";
			function = "qpic_pad3";
			drive-strength = <8>;
			bias-disable;
		};
		data_4 {
			pins = "gpio5";
			function = "qpic_pad4";
			drive-strength = <8>;
			bias-disable;
		};
		data_5 {
			pins = "gpio6";
			function = "qpic_pad5";
			drive-strength = <8>;
			bias-disable;
		};
		data_6 {
			pins = "gpio7";
			function = "qpic_pad6";
			drive-strength = <8>;
			bias-disable;
		};
		data_7 {
			pins = "gpio8";
			function = "qpic_pad7";
			drive-strength = <8>;
			bias-disable;
		};
		qpic_pad {
			pins = "gpio1", "gpio3", "gpio4",
			       "gpio10", "gpio11", "gpio17";
			function = "qpic_pad";
			drive-strength = <8>;
			bias-disable;
		};
	};

	hsuart_pins: hsuart_pins {
		mux {
			pins = "gpio46", "gpio47", "gpio48", "gpio49";
			function = "blsp2_uart";
			drive-strength = <8>;
			bias-disable;
		};
	};

	button_pins: button_pins {

		wps_button {
			pins = "gpio67";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-up;
		};
	};

	led_pins: led_pins {
		led_red {
			pins = "gpio25";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
		};

		led_green {
			pins = "gpio26";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
		};

		led_blue {
			pins = "gpio27";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
		};
	};

	pcie0_pins: pcie_pins {
		pcie0_rst {
			pins = "gpio58";
			function = "pcie0_rst";
			drive-strength = <8>;
			bias-pull-down;
		};
		pcie0_wake {
			pins = "gpio59";
			function = "pcie0_wake";
			drive-strength = <8>;
			bias-pull-down;
		};
	};
	pwm_pins: pwm_pinmux {
                mux_1 {
                        pins = "gpio25";
                        function = "pwm02";
                        drive-strength = <8>;
                };
		mux_2 {
                        pins = "gpio26";
                        function = "pwm12";
                        drive-strength = <8>;
                };
		mux_3 {
                        pins = "gpio27";
                        function = "pwm22";
                        drive-strength = <8>;
                };
	};

};

&soc {
	 pwm {
                pinctrl-0 = <&pwm_pins>;
                pinctrl-names = "default";
                used-pwm-indices = <1>, <1>, <1>, <0>;
         //       status = "ok";
        };
	gpio_keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&button_pins>;
		pinctrl-names = "default";

		button@1 {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
			linux,input-type = <1>;
			debounce-interval = <60>;
		};
	};

	mdio: mdio@90000 {
		pinctrl-0 = <&mdio_pins>;
		pinctrl-names = "default";
		phy-reset-gpio = <&tlmm 64 0 &tlmm 66 0>;
		compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
		phy0: ethernet-phy@0 {
			reg = <16>;
		};
		phy1: ethernet-phy@1 {
			reg = <17>;
		};
		phy2: ethernet-phy@2 {
			reg = <18>;
		};
		phy3: ethernet-phy@3 {
			reg = <19>;
		};
		phy4: ethernet-phy@4 {
			compatible ="ethernet-phy-ieee802.3-c45";
			reg = <0>;
		};
		phy5: ethernet-phy@5 {
			reg = <28>;
		};
	};

	ess-switch@3a000000 {
		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
		switch_lan_bmp = <0x3e>; /* lan port bitmap */
		switch_wan_bmp = <0xc0>; /* wan port bitmap */
		switch_mac_mode = <0xff>; /* mac mode for uniphy instance0*/
		switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
		switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
		bm_tick_mode = <0>; /* bm tick mode */
		tm_tick_mode = <0>; /* tm tick mode */
		qcom,port_phyinfo {
			port@0 {
				port_id = <1>;
				phy_address = <16>;
			};
			port@1 {
				port_id = <2>;
				phy_address = <17>;
			};
			port@2 {
				port_id = <3>;
				phy_address = <18>;
			};
			port@3 {
				port_id = <4>;
				phy_address = <19>;
			};
			port@4 {
				port_id = <5>;
				phy_address = <0>;
				port_mac_sel = "QGMAC_PORT";
				ethernet-phy-ieee802.3-c45;
			};
			port@5 {
				port_id = <6>;
				phy_address = <28>;
				port_mac_sel = "QGMAC_PORT";
			};
		};
		port_scheduler_resource {
			port@0 {
				port_id = <0>;
				ucast_queue = <0 143>;
				mcast_queue = <256 271>;
				l0sp = <0 35>;
				l0cdrr = <0 47>;
				l0edrr = <0 47>;
				l1cdrr = <0 7>;
				l1edrr = <0 7>;
			};
			port@1 {
				port_id = <1>;
				ucast_queue = <144 159>;
				mcast_queue = <272 275>;
				l0sp = <36 39>;
				l0cdrr = <48 63>;
				l0edrr = <48 63>;
				l1cdrr = <8 11>;
				l1edrr = <8 11>;
			};
			port@2 {
				port_id = <2>;
				ucast_queue = <160 175>;
				mcast_queue = <276 279>;
				l0sp = <40 43>;
				l0cdrr = <64 79>;
				l0edrr = <64 79>;
				l1cdrr = <12 15>;
				l1edrr = <12 15>;
			};
			port@3 {
				port_id = <3>;
				ucast_queue = <176 191>;
				mcast_queue = <280 283>;
				l0sp = <44 47>;
				l0cdrr = <80 95>;
				l0edrr = <80 95>;
				l1cdrr = <16 19>;
				l1edrr = <16 19>;
			};
			port@4 {
				port_id = <4>;
				ucast_queue = <192 207>;
				mcast_queue = <284 287>;
				l0sp = <48 51>;
				l0cdrr = <96 111>;
				l0edrr = <96 111>;
				l1cdrr = <20 23>;
				l1edrr = <20 23>;
			};
			port@5 {
				port_id = <5>;
				ucast_queue = <208 223>;
				mcast_queue = <288 291>;
				l0sp = <52 55>;
				l0cdrr = <112 127>;
				l0edrr = <112 127>;
				l1cdrr = <24 27>;
				l1edrr = <24 27>;
			};
			port@6 {
				port_id = <6>;
				ucast_queue = <224 239>;
				mcast_queue = <292 295>;
				l0sp = <56 59>;
				l0cdrr = <128 143>;
				l0edrr = <128 143>;
				l1cdrr = <28 31>;
				l1edrr = <28 31>;
			};
			port@7 {
				port_id = <7>;
				ucast_queue = <240 255>;
				mcast_queue = <296 299>;
				l0sp = <60 63>;
				l0cdrr = <144 159>;
				l0edrr = <144 159>;
				l1cdrr = <32 35>;
				l1edrr = <32 35>;
			};
		};
		port_scheduler_config {
			port@0 {
				port_id = <0>;
				l1scheduler {
					group@0 {
						sp = <0 1>; /*L0 SPs*/
						/*cpri cdrr epri edrr*/
						cfg = <0 0 0 0>;
					};
				};
				l0scheduler {
					group@0 {
						/*unicast queues*/
						ucast_queue = <0 4 8>;
						/*multicast queues*/
						mcast_queue = <256 260>;
						/*sp cpri cdrr epri edrr*/
						cfg = <0 0 0 0 0>;
					};
					group@1 {
						ucast_queue = <1 5 9>;
						mcast_queue = <257 261>;
						cfg = <0 1 1 1 1>;
					};
					group@2 {
						ucast_queue = <2 6 10>;
						mcast_queue = <258 262>;
						cfg = <0 2 2 2 2>;
					};
					group@3 {
						ucast_queue = <3 7 11>;
						mcast_queue = <259 263>;
						cfg = <0 3 3 3 3>;
					};
				};
			};
			port@1 {
				port_id = <1>;
				l1scheduler {
					group@0 {
						sp = <36>;
						cfg = <0 8 0 8>;
					};
					group@1 {
						sp = <37>;
						cfg = <1 9 1 9>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <144>;
						ucast_loop_pri = <16>;
						mcast_queue = <272>;
						mcast_loop_pri = <4>;
						cfg = <36 0 48 0 48>;
					};
				};
			};
			port@2 {
				port_id = <2>;
				l1scheduler {
					group@0 {
						sp = <40>;
						cfg = <0 12 0 12>;
					};
					group@1 {
						sp = <41>;
						cfg = <1 13 1 13>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <160>;
						ucast_loop_pri = <16>;
						mcast_queue = <276>;
						mcast_loop_pri = <4>;
						cfg = <40 0 64 0 64>;
					};
				};
			};
			port@3 {
				port_id = <3>;
				l1scheduler {
					group@0 {
						sp = <44>;
						cfg = <0 16 0 16>;
					};
					group@1 {
						sp = <45>;
						cfg = <1 17 1 17>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <176>;
						ucast_loop_pri = <16>;
						mcast_queue = <280>;
						mcast_loop_pri = <4>;
						cfg = <44 0 80 0 80>;
					};
				};
			};
			port@4 {
				port_id = <4>;
				l1scheduler {
					group@0 {
						sp = <48>;
						cfg = <0 20 0 20>;
					};
					group@1 {
						sp = <49>;
						cfg = <1 21 1 21>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <192>;
						ucast_loop_pri = <16>;
						mcast_queue = <284>;
						mcast_loop_pri = <4>;
						cfg = <48 0 96 0 96>;
					};
				};
			};
			port@5 {
				port_id = <5>;
				l1scheduler {
					group@0 {
						sp = <52>;
						cfg = <0 24 0 24>;
					};
					group@1 {
						sp = <53>;
						cfg = <1 25 1 25>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <208>;
						ucast_loop_pri = <16>;
						mcast_queue = <288>;
						mcast_loop_pri = <4>;
						cfg = <52 0 112 0 112>;
					};
				};
			};
			port@6 {
				port_id = <6>;
				l1scheduler {
					group@0 {
						sp = <56>;
						cfg = <0 28 0 28>;
					};
					group@1 {
						sp = <57>;
						cfg = <1 29 1 29>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <224>;
						ucast_loop_pri = <16>;
						mcast_queue = <292>;
						mcast_loop_pri = <4>;
						cfg = <56 0 128 0 128>;
					};
				};
			};
			port@7 {
				port_id = <7>;
				l1scheduler {
					group@0 {
						sp = <60>;
						cfg = <0 32 0 32>;
					};
					group@1 {
						sp = <61>;
						cfg = <1 33 1 33>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <240>;
						ucast_loop_pri = <16>;
						mcast_queue = <296>;
						cfg = <60 0 144 0 144>;
					};
				};
			};
		};
	};

	dp1 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <1>;
		reg = <0x3a001000 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <16>;
		phy-mode = "sgmii";
	};

	dp2 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <2>;
		reg = <0x3a001200 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <17>;
		phy-mode = "sgmii";
	};

	dp3 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <3>;
		reg = <0x3a001400 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <18>;
		phy-mode = "sgmii";
	};

	dp4 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <4>;
		reg = <0x3a001600 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <19>;
		phy-mode = "sgmii";
	};

	dp5 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <5>;
		reg = <0x3a001800 0x200>;
		qcom,mactype = <1>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <0>;
		phy-mode = "sgmii";
	};

	dp6 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <6>;
		reg = <0x3a001a00 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
		qcom,link-poll = <1>;
		qcom,phy-mdio-addr = <28>;
		phy-mode = "sgmii";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&led_pins>;
		pinctrl-names = "default";

		led_red {
			label = "red:status";
			gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led_power: led_green {
			label = "green:status";
			gpio = <&tlmm 26 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		led_blue {
			label = "blue:status";
			gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};
	nss-macsec0 {
		compatible = "qcom,nss-macsec";
		phy_addr = <0>;
		phy_access_mode = <0>;
		mdiobus = <&mdio>;
	};
	nss-macsec1 {
		compatible = "qcom,nss-macsec";
		phy_addr = <0x1c>;
		phy_access_mode = <0>;
		mdiobus = <&mdio>;
	};
	i2c_5: i2c@78ba000 {
		compatible = "qcom,i2c-qup-v2.2.1";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x78ba000 0x600>;
		interrupts = <GIC_SPI 300 0x4>;
		clocks = <&gcc GCC_BLSP1_AHB_CLK>,
			<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
		clock-names = "iface", "core";
		clock-frequency  = <100000>;
		dmas = <&blsp_dma 23>, <&blsp_dma 22>;
		dma-names = "rx", "tx";
	};
};

&serial_blsp4 {
	pinctrl-0 = <&uart_pins>;
	pinctrl-names = "default";
	status = "ok";
};

&spi_0 { /* BLSP1 QUP1 */
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	cs-select = <0>;
	status = "ok";

	m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		compatible = "n25q128a11";
		linux,modalias = "m25p80", "n25q128a11";
		spi-max-frequency = <50000000>;
		use-default-sizes;
	};
};

&serial_blsp2 {
	pinctrl-0 = <&hsuart_pins>;
	pinctrl-names = "default";
	status = "ok";
};

&msm_imem {
	status = "disabled";
};

&ssphy_0 {
	status = "ok";
};

&qusb_phy_0 {
	status = "ok";
};

&usb3_0 {
	status = "ok";
};

&cryptobam {
	status = "ok";
};

&crypto {
	status = "ok";
};

&i2c_0 {
	status = "disabled";
};

&i2c_1 {
	status = "disabled";
};

&i2c_5 {
	pinctrl-0 = <&i2c_5_pins>;
        pinctrl-names = "default";
        status = "ok";
};

&qpic_bam {
	status = "ok";
};

&nand {
	pinctrl-0 = <&qpic_pins>;
	pinctrl-names = "default";
	status = "ok";
};

&qpic_lcd {
	status = "disabled";
};

&qpic_lcd_panel {
	status = "disabled";
};

&pcie0 {
	status = "ok";
};


&pcie0_rp {
	status = "ok";

	mhi_0: qcom,mhi@0 {
		reg = <0 0 0 0 0 >;
		qrtr_instance_id = <0x20>;
		#address-cells = <0x2>;
		#size-cells = <0x2>;
#if !defined(__IPQ_MEM_PROFILE_256_MB__)
		memory-region = <&mhi_region0>;
#endif

#if !defined(__CNSS2__)
		base-addr = <0x51100000>;
		m3-dump-addr = <0x53400000>;
		etr-addr = <0x53500000>;
		qcom,caldb-addr = <0x53600000>;
		mhi,max-channels = <30>;
		mhi,timeout = <10000>;
		qcom,board_id= <0xa4>;

		pcie0_mhi: pcie0_mhi {
			status = "ok";
		};
#endif
	};
};

&pcie1_rp {
	status = "disabled";

	mhi_1: qcom,mhi@1 {
		pcie1_mhi: pcie1_mhi {
			status = "disabled";
		};
	};
};

&npu_cpr {
	status = "disabled";
};

&nss0 {
	npu-supply = <&dummy_reg>;
	mx-supply = <&dummy_reg>;
};

#ifndef __IPQ_MEM_PROFILE_256_MB__
&nss1 {
	npu-supply = <&dummy_reg>;
	mx-supply = <&dummy_reg>;
};
#endif

&wifi1 {
	qcom,board_id = <0x294>;
	status = "ok";
};

/* No support for QCN9000 in 256M profile */
#if !defined(__IPQ_MEM_PROFILE_256_MB__)
&wifi2 {
#ifdef __IPQ_MEM_PROFILE_512_MB__
      /* QCN9000 tgt-mem-mode=1 layout - 30MB
       * +=========+==============+=========+
       * |  Region | Start Offset |   Size  |
       * +---------+--------------+---------+
       * | HREMOTE |  0x4E900000  |   20MB  |
       * +---------+--------------+---------+
       * | M3 Dump |  0x4FD00000  |   1MB   |
       * +---------+--------------+---------+
       * |   ETR   |  0x4FE00000  |   1MB   |
       * +---------+--------------+---------+
       * |  Caldb  |  0x4FF00000  |   8MB   |
       * +==================================+
       */
	base-addr = <0x4E900000>;
	m3-dump-addr = <0x4FD00000>;
	etr-addr = <0x4FE00000>;
	caldb-addr = <0x4FF00000>;
	hremote-size = <0x1400000>;
	tgt-mem-mode = <0x1>;
#else
      /* QCN9000 tgt-mem-mode=0 layout - 45MB
       * +=========+==============+=========+
       * |  Region | Start Offset |   Size  |
       * +---------+--------------+---------+
       * | HREMOTE |  0x51100000  |   35MB  |
       * +---------+--------------+---------+
       * | M3 Dump |  0x53400000  |   1MB   |
       * +---------+--------------+---------+
       * |   ETR   |  0x53500000  |   1MB   |
       * +---------+--------------+---------+
       * |  Caldb  |  0x53600000  |   8MB   |
       * +==================================+
       */
	base-addr = <0x51100000>;
	m3-dump-addr = <0x53400000>;
	etr-addr = <0x53500000>;
	caldb-addr = <0x53600000>;
	hremote-size = <0x2300000>;
	tgt-mem-mode = <0x0>;
#endif
	caldb-size = <0x800000>;
	board_id = <0xa4>;
	status = "ok";
#if defined(__CNSS2__)
	pcie0_mhi: pcie0_mhi {
		status = "ok";
	};
#endif
};
&wifi3 {
	status = "disabled";
};

#include "qcom-ipq807x-mhi.dtsi"
#endif
