mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-31 02:17:58 +00:00
mediatek: Update ethernet driver to support PHY AN8801 on Edgecore EAP111
Signed-off-by: Sebastian Huang <sebastian_huang@accton.com>
This commit is contained in:
Sebastian Huang
@@ -173,6 +173,16 @@
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compatible = "ethernet-phy-id03a2.9471";
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phy-mode = "sgmii";
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};
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an8801sb: ethernet-phy@30 {
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reg = <30>;
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compatible = "ethernet-phy-idc0ff.0421";
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phy-mode = "sgmii";
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full-duplex;
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pause;
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airoha,surge = <0>;
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airoha,polarity = <2>;
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};
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};
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ð {
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@@ -184,7 +194,8 @@
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "sgmii";
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phy-handle = <&en8801sc>;
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phy-handle = <&an8801sb>;
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phy-handle2 = <&en8801sc>;
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managed = "in-band-status";
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nvmem-cells = <&macaddr_lan>;
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nvmem-cell-names = "mac-address";
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1534
feeds/mediatek/mediatek/files-6.6/drivers/net/phy/an8801.c
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1534
feeds/mediatek/mediatek/files-6.6/drivers/net/phy/an8801.c
Normal file
File diff suppressed because it is too large
Load Diff
233
feeds/mediatek/mediatek/files-6.6/drivers/net/phy/an8801.h
Normal file
233
feeds/mediatek/mediatek/files-6.6/drivers/net/phy/an8801.h
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@@ -0,0 +1,233 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*PURPOSE:
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*Define Airoha phy driver function
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*
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*NOTES:
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*
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*/
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#ifndef __AN8801_H
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#define __AN8801_H
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/* NAMING DECLARATIONS
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*/
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#define AN8801_DRIVER_VERSION "1.1.7"
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#define DEBUGFS_COUNTER "counter"
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#define DEBUGFS_INFO "driver_info"
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#define DEBUGFS_PBUS_OP "pbus_op"
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#define DEBUGFS_POLARITY "polarity"
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#define DEBUGFS_MDIO "mdio"
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#define AN8801_MDIO_PHY_ID 0x1
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#define AN8801_PHY_ID1 0xc0ff
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#define AN8801_PHY_ID2 0x0421
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#define AN8801_PHY_ID ((u32)((AN8801_PHY_ID1 << 16) | AN8801_PHY_ID2))
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#define TRUE 1
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#define FALSE 0
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#define LINK_UP 1
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#define LINK_DOWN 0
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#define MAX_LED_SIZE 3
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#define MAX_RETRY 5
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#define AN8801_EPHY_ADDR 0x11000000
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#define AN8801_CL22 0x00800000
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#define LED_ENABLE 1
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#define LED_DISABLE 0
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#define AN8801SB_DEBUGFS
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#ifndef GET_BIT
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#define GET_BIT(val, bit) ((val & BIT(bit)) >> bit)
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#endif
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#define LED_BCR (0x021)
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#define LED_BCR_EXT_CTRL BIT(15)
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#define LED_BCR_EVT_ALL BIT(4)
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#define LED_BCR_CLK_EN BIT(3)
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#define LED_BCR_TIME_TEST BIT(2)
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#define LED_BCR_MODE_MASK (3)
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#define LED_BCR_MODE_DISABLE (0)
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#define LED_BCR_MODE_2LED (1)
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#define LED_BCR_MODE_3LED_1 (2)
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#define LED_BCR_MODE_3LED_2 (3)
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#define LED_ON_DUR (0x022)
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#define LED_ON_DUR_MASK (0xffff)
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#define LED_BLK_DUR (0x023)
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#define LED_BLK_DUR_MASK (0xffff)
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#define LED_ON_CTRL(i) (0x024 + ((i) * 2))
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#define LED_ON_EN BIT(15)
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#define LED_ON_POL BIT(14)
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#define LED_ON_EVT_MASK (0x7f)
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#define LED_ON_EVT_FORCE BIT(6)
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#define LED_ON_EVT_HDX BIT(5)
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#define LED_ON_EVT_FDX BIT(4)
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#define LED_ON_EVT_LINK_DN BIT(3)
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#define LED_ON_EVT_LINK_10M BIT(2)
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#define LED_ON_EVT_LINK_100M BIT(1)
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#define LED_ON_EVT_LINK_1000M BIT(0)
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#define LED_BLK_CTRL(i) (0x025 + ((i) * 2))
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#define LED_BLK_EVT_MASK (0x3ff)
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#define LED_BLK_EVT_FORCE BIT(9)
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#define LED_BLK_EVT_10M_RX BIT(5)
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#define LED_BLK_EVT_10M_TX BIT(4)
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#define LED_BLK_EVT_100M_RX BIT(3)
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#define LED_BLK_EVT_100M_TX BIT(2)
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#define LED_BLK_EVT_1000M_RX BIT(1)
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#define LED_BLK_EVT_1000M_TX BIT(0)
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#define UNIT_LED_BLINK_DURATION 780
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/* Serdes auto negotiation restart */
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#define AN8801SB_SGMII_AN0_ANRESTART (0x0200)
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#define AN8801SB_SGMII_AN0_AN_DONE (0x0001)
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#define AN8801SB_SGMII_AN0_RESET (0x8000)
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#define PHY_PRE_SPEED_REG (0x2b)
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#define MMD_DEV_VSPEC1 (0x1E)
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#define MMD_DEV_VSPEC2 (0x1F)
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#define RGMII_DELAY_STEP_MASK 0x7
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#define RGMII_RXDELAY_ALIGN BIT(4)
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#define RGMII_RXDELAY_FORCE_MODE BIT(24)
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#define RGMII_TXDELAY_FORCE_MODE BIT(24)
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#define AN8801_RG_PKG_SEL_LSB BIT(4)
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#define AN8801_RG_PKG_SEL_MSB BIT(5)
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/*
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*For reference only
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*/
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/* User-defined.B */
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/* Link on(1G/100M/10M), no activity */
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#define AIR_LED0_ON \
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(LED_ON_EVT_LINK_1000M | LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M)
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#define AIR_LED0_BLK (0x0)
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/* No link on, activity(1G/100M/10M TX/RX) */
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#define AIR_LED1_ON (0x0)
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#define AIR_LED1_BLK \
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(LED_BLK_EVT_1000M_TX | LED_BLK_EVT_1000M_RX | \
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LED_BLK_EVT_100M_TX | LED_BLK_EVT_100M_RX | \
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LED_BLK_EVT_10M_TX | LED_BLK_EVT_10M_RX)
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/* Link on(100M/10M), activity(100M/10M TX/RX) */
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#define AIR_LED2_ON (LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M)
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#define AIR_LED2_BLK \
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(LED_BLK_EVT_100M_TX | LED_BLK_EVT_100M_RX | \
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LED_BLK_EVT_10M_TX | LED_BLK_EVT_10M_RX)
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/* User-defined.E */
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/* Invalid data */
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#define INVALID_DATA 0xffffffff
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#define LED_BLINK_DURATION(f) (UNIT_LED_BLINK_DURATION << (f))
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#define LED_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3))
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/* Interrupt GPIO number, should not conflict with LED */
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#define AIR_INTERRUPT_GPIO 3
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/* DATA TYPE DECLARATIONS
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*/
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enum AIR_LED_GPIO_PIN_T {
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AIR_LED_GPIO1 = 1,
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AIR_LED_GPIO2 = 2,
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AIR_LED_GPIO3 = 3,
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AIR_LED_GPIO5 = 5,
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AIR_LED_GPIO8 = 8,
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AIR_LED_GPIO9 = 9,
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};
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enum AIR_LED_T {
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AIR_LED0 = 0,
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AIR_LED1,
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AIR_LED2,
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AIR_LED3
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};
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enum AIR_LED_BLK_DUT_T {
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AIR_LED_BLK_DUR_32M = 0,
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AIR_LED_BLK_DUR_64M,
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AIR_LED_BLK_DUR_128M,
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AIR_LED_BLK_DUR_256M,
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AIR_LED_BLK_DUR_512M,
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AIR_LED_BLK_DUR_1024M,
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AIR_LED_BLK_DUR_LAST
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};
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enum AIR_LED_POLARITY {
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AIR_ACTIVE_LOW = 0,
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AIR_ACTIVE_HIGH,
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};
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enum AIR_LED_MODE_T {
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AIR_LED_MODE_DISABLE = 0,
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AIR_LED_MODE_USER_DEFINE,
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AIR_LED_MODE_LAST
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};
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enum AIR_RGMII_DELAY_STEP_T {
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AIR_RGMII_DELAY_NOSTEP = 0,
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AIR_RGMII_DELAY_STEP_1 = 1,
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AIR_RGMII_DELAY_STEP_2 = 2,
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AIR_RGMII_DELAY_STEP_3 = 3,
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AIR_RGMII_DELAY_STEP_4 = 4,
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AIR_RGMII_DELAY_STEP_5 = 5,
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AIR_RGMII_DELAY_STEP_6 = 6,
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AIR_RGMII_DELAY_STEP_7 = 7,
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};
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struct AIR_LED_CFG_T {
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u16 en;
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u16 gpio;
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u16 pol;
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u16 on_cfg;
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u16 blk_cfg;
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};
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struct an8801_priv {
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struct AIR_LED_CFG_T led_cfg[MAX_LED_SIZE];
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u32 led_blink_cfg;
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u8 rxdelay_force;
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u8 txdelay_force;
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u16 rxdelay_step;
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u8 rxdelay_align;
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u16 txdelay_step;
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#ifdef AN8801SB_DEBUGFS
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struct dentry *debugfs_root;
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#endif
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int pol;
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int surge;
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int sgmii_mode;
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};
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enum an8801_polarity {
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AIR_POL_TX_NOR_RX_REV,
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AIR_POL_TX_REV_RX_REV,
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AIR_POL_TX_NOR_RX_NOR,
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AIR_POL_TX_REV_RX_NOR,
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};
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enum air_surge {
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AIR_SURGE_0R,
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AIR_SURGE_5R,
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AIR_SURGE_LAST = 0xff
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};
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enum air_sgmii_mode {
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AIR_SGMII_AN,
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AIR_SGMII_FORCE,
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AIR_SGMII_LAST = 0xff
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};
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#endif /* End of __AN8801_H */
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@@ -1,6 +1,7 @@
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CONFIG_64BIT=y
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# CONFIG_AHCI_MTK is not set
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CONFIG_AIROHA_EN8801SC_PHY=y
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CONFIG_AIROHA_AN8801_PHY=y
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CONFIG_AIR_AN8855_PHY=y
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CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
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CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
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@@ -0,0 +1,92 @@
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diff -upr linux-6.6.89/drivers/net/mdio/of_mdio.c /home/build9/seb_working/linux-6.6.89/drivers/net/mdio/of_mdio.c
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--- a/drivers/net/mdio/of_mdio.c 2025-08-22 14:44:34.467093772 +0800
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+++ b/drivers/net/mdio/of_mdio.c 2025-08-22 14:39:10.212748831 +0800
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@@ -145,7 +145,10 @@ static int __of_mdiobus_parse_phys(struc
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int addr, rc = 0;
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/* Loop over the child nodes and register a phy_device for each phy */
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+ int an8801=0;
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for_each_available_child_of_node(np, child) {
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+ if(an8801==1)break;
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+
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if (of_node_name_eq(child, "ethernet-phy-package")) {
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/* Ignore invalid ethernet-phy-package node */
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if (!of_find_property(child, "reg", NULL))
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@@ -166,8 +169,25 @@ static int __of_mdiobus_parse_phys(struc
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continue;
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}
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- if (of_mdiobus_child_is_phy(child))
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+ if (of_mdiobus_child_is_phy(child)) {
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+ if(addr==30)
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+ {
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+ int phy_id ;
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+
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+ phy_id = mdiobus_read(mdio, addr, MII_PHYSID1) << 16 ;
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+ phy_id = phy_id + mdiobus_read(mdio, addr, MII_PHYSID2);
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+ dev_info(&mdio->dev, "[of_mdio] %s %d addr:%d phy_id:0x%x \n",__func__, __LINE__, addr, phy_id);
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+
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+ if (phy_id==0 || phy_id==0x1a750000)
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+ {
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+ dev_info(&mdio->dev, "[of_mdio] %s %d continue \n",__func__, __LINE__);
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+ continue;
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+ }
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+ else
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+ an8801=1;
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+ }
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rc = of_mdiobus_register_phy(mdio, child, addr);
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+ }
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else
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rc = of_mdiobus_register_device(mdio, child, addr);
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diff -upr linux-6.6.89/drivers/net/phy/Kconfig /home/build9/seb_working/linux-6.6.89/drivers/net/phy/Kconfig
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--- a/drivers/net/phy/Kconfig 2025-08-08 17:02:38.023751484 +0800
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+++ b/drivers/net/phy/Kconfig 2025-08-22 15:01:27.708103066 +0800
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@@ -142,6 +142,11 @@ endif # RTL8366_SMI
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comment "MII PHY device drivers"
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+config AIROHA_AN8801_PHY
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+ tristate "Drivers for Airoha AN8801 Gigabit PHYs"
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+ help
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+ Currently supports the Airoha AN8801 PHY.
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+
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config AIROHA_EN8801SC_PHY
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tristate "Airoha EN8801SC Gigabit PHY"
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help
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diff -upr linux-6.6.89/drivers/net/phy/Makefile /home/build9/seb_working/linux-6.6.89/drivers/net/phy/Makefile
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--- a/drivers/net/phy/Makefile 2025-08-08 17:02:38.023751484 +0800
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+++ b/drivers/net/phy/Makefile 2025-08-22 15:02:07.464601732 +0800
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@@ -49,6 +49,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
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obj-$(CONFIG_ADIN_PHY) += adin.o
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obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
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+obj-$(CONFIG_AIROHA_AN8801_PHY) += an8801.o
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obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
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obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o
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obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
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diff -upr linux-6.6.89/drivers/net/phy/phylink.c /home/build9/seb_working/linux-6.6.89/drivers/net/phy/phylink.c
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--- a/drivers/net/phy/phylink.c 2025-08-22 14:43:00.994406615 +0800
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+++ b/drivers/net/phy/phylink.c 2025-08-22 14:39:10.280749309 +0800
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@@ -2290,7 +2290,20 @@ int phylink_fwnode_phy_connect(struct ph
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/* We're done with the phy_node handle */
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fwnode_handle_put(phy_fwnode);
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if (!phy_dev)
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- return -ENODEV;
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+ {
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+ phylink_info(pl, "[phylink] reload phy-handle2. %s %d\n",__func__, __LINE__);
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+ phy_fwnode = fwnode_find_reference(fwnode, "phy-handle2", 0);
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+ if (IS_ERR(phy_fwnode)) {
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+ if (pl->cfg_link_an_mode == MLO_AN_PHY)
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+ return -ENODEV;
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+ return 0;
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+ }
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+ phy_dev = fwnode_phy_find_device(phy_fwnode);
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+ fwnode_handle_put(phy_fwnode);
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+
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+ if (!phy_dev)
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+ return -ENODEV;
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+ }
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/* Use PHY device/driver interface */
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if (pl->link_interface == PHY_INTERFACE_MODE_NA) {
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