From 753967bf6b686d7630f2d7c070fe77f5be9311fb Mon Sep 17 00:00:00 2001 From: OutBack Dingo Date: Wed, 6 Dec 2023 09:17:28 -0500 Subject: [PATCH] ipq807x: remove all Xu related and add OptimCloud support Signed-off-by: OutBack Dingo --- .../ipq807x/base-files/etc/board.d/02_network | 7 + .../etc/hotplug.d/firmware/10-ath11k-caldata | 12 + .../base-files/lib/upgrade/platform.sh | 10 +- .../dts/qcom/qcom-ipq5018-xunison-d50-5g.dtsi | 1442 ----------------- .../dts/qcom/qcom-ipq5018-xunison-d50.dtsi | 1442 ----------------- feeds/ipq807x/ipq807x/image/ipq50xx.mk | 53 + feeds/wifi-ax/ath11k-wifi/Makefile | 26 + .../board-optimcloud-d50.bin.IPQ5018 | Bin 0 -> 131072 bytes .../board-optimcloud-d50.bin.QCN9074 | Bin 0 -> 131072 bytes .../board-optimcloud-d60.bin.IPQ5018 | Bin 0 -> 131072 bytes .../board-optimcloud-d60.bin.QCN9074 | Bin 0 -> 131072 bytes profiles/optimcloud_d50-5g.yml | 17 +- profiles/optimcloud_d50.yml | 17 +- profiles/optimcloud_d60-5g.yml | 17 +- profiles/optimcloud_d60.yml | 17 +- 15 files changed, 151 insertions(+), 2909 deletions(-) delete mode 100755 feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50-5g.dtsi delete mode 100755 feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50.dtsi create mode 100644 feeds/wifi-ax/ath11k-wifi/board-optimcloud-d50.bin.IPQ5018 create mode 100644 feeds/wifi-ax/ath11k-wifi/board-optimcloud-d50.bin.QCN9074 create mode 100644 feeds/wifi-ax/ath11k-wifi/board-optimcloud-d60.bin.IPQ5018 create mode 100644 feeds/wifi-ax/ath11k-wifi/board-optimcloud-d60.bin.QCN9074 diff --git a/feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network b/feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network index 68f1a5d24..2f762efa0 100755 --- a/feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network +++ b/feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network @@ -102,6 +102,13 @@ qcom_setup_interfaces() ucidef_add_switch "switch1" \ "6@eth1" "1:lan" "2:lan" "3:lan" "4:lan" ;; + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g) + ucidef_set_interface_wan "eth0" + ucidef_set_interface_lan "eth1" + ;; qcom,ipq5018-mp03.1) ucidef_set_interface_lan "eth1" ucidef_set_interface_wan "eth0" diff --git a/feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata b/feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata index 678ac332f..27dae3e67 100755 --- a/feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata +++ b/feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata @@ -208,6 +208,10 @@ ath11k/IPQ5018/hw1.0/caldata.bin) liteon,wpx8324|\ motorola,q14|\ muxi,ap3220l|\ + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g|\ qcom,ipq5018-mp03.1) caldata_extract "0:ART" 0x1000 0x20000 ;; @@ -249,6 +253,10 @@ ath11k/QCN9074/hw1.0/caldata_1.bin) cig,wf196|\ wallys,dr6018-v4|\ cybertan,eww622-a1|\ + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g|\ qcom,ipq5018-mp03.1|\ qcom,ipq807x-hk14) caldata_extract "0:ART" 0x26800 0x20000 @@ -287,6 +295,10 @@ ath11k-macs) indio,um-310ax-v1|\ indio,um-510axp-v1|\ indio,um-510axm-v1|\ + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g|\ cig,wf188n) ath11k_generate_macs ;; diff --git a/feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh b/feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh index 30d4e23ff..ca17d3382 100755 --- a/feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh +++ b/feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh @@ -38,7 +38,7 @@ do_flash_emmc() { local emmcblock=$(find_mmc_part $2) local board_dir=$3 local part=$4 - + [ -b "$emmcblock" ] || emmcblock=$(find_mmc_part $2) [ -z "$emmcblock" ] && { @@ -162,6 +162,10 @@ platform_check_image() { qcom,ipq6018-cp01|\ qcom,ipq807x-hk01|\ qcom,ipq807x-hk14|\ + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g|\ qcom,ipq5018-mp03.3) [ "$magic_long" = "73797375" ] && return 0 ;; @@ -200,6 +204,10 @@ platform_do_upgrade() { qcom,ipq6018-cp01|\ qcom,ipq807x-hk01|\ qcom,ipq807x-hk14|\ + optimcloud,d60|\ + optimcloud,d60-5g|\ + optimcloud,d50|\ + optimcloud,d50-5g|\ qcom,ipq5018-mp03.3|\ wallys,dr5018|\ wallys,dr6018|\ diff --git a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50-5g.dtsi b/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50-5g.dtsi deleted file mode 100755 index 5778a4c41..000000000 --- a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50-5g.dtsi +++ /dev/null @@ -1,1442 +0,0 @@ -/* - * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "qcom-ipq5018-memory.dtsi" -#include "qcom-ipq5018-mhi.dtsi" -#include "ipq5018_clocks.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ5018"; - compatible = "qcom,ipq5018"; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - status = "ok"; - }; - -#ifdef ENABLE_QSEECOM - qseecom { - compatible = "ipq5018-qseecom"; - mem-start = <0x4a400000>; - mem-size = <0x200000>; - }; -#endif - - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0xb000000 0x1000>, <0xb002000 0x1000>; - ranges = <0x0 0xb00a000 0x1ffa>; - - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xffd>; - }; - - v2m1: v2m@1000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x1000 0xffd>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq5018"; - reg = <0x1800000 0x80000>; - #clock-cells = <0x1>; - #reset-cells = <0x1>; - }; - - apss_clk: qcom,apss_clk@b111000 { - compatible = "qcom,apss-ipq5018"; - reg = <0xb111000 0x6000>; - #clock-cells = <0x1>; - #reset-cells = <1>; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x1d000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - spi_0: spi@78b5000 { /* BLSP1 QUP0 */ - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b5000 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - pwm { - compatible = "qca,ipq6018-pwm"; - reg = <0x1941010 0x20>; - clocks = <&gcc GCC_ADSS_PWM_CLK>; - clock-names = "core"; - src-freq = <100000000>; - pwm-base-index = <0>; - used-pwm-indices = <1>, <1>, <1>, <1>; - status = "disabled"; - }; - - mdio0: mdio@88000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio"; - reg = <0x88000 0x64>; - status = "disabled"; - resets = <&gcc GCC_GEPHY_MDC_SW_ARES>; - reset-names = "gephy_mdc_rst"; - }; - - mdio1: mdio@90000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qca-mdio"; - reg = <0x90000 0x64>; - status = "disabled"; - }; - ess-instance { - ess-switch@0x39c00000 { - compatible = "qcom,ess-switch-ipq50xx"; - reg = <0x39c00000 0x200000>; - switch_access_mode = "local bus"; - clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, - <&gcc GCC_CMN_BLK_SYS_CLK>, - <&gcc GCC_UNIPHY_AHB_CLK>, - <&gcc GCC_UNIPHY_SYS_CLK>, - <&gcc GCC_MDIO0_AHB_CLK>, - <&gcc GCC_MDIO1_AHB_CLK>, - <&gcc GCC_GMAC0_CFG_CLK>, - <&gcc GCC_GMAC0_SYS_CLK>, - <&gcc GCC_GMAC1_CFG_CLK>, - <&gcc GCC_GMAC1_SYS_CLK>, - <&gcc GCC_GEPHY_RX_CLK>, - <&gcc GCC_GEPHY_TX_CLK>, - <&gcc GCC_UNIPHY_RX_CLK>, - <&gcc GCC_UNIPHY_TX_CLK>, - <&gcc GCC_GMAC0_RX_CLK>, - <&gcc GCC_GMAC0_TX_CLK>, - <&gcc GCC_GMAC1_RX_CLK>, - <&gcc GCC_GMAC1_TX_CLK>, - <&gcc GCC_SNOC_GMAC0_AHB_CLK>, - <&gcc GCC_SNOC_GMAC1_AHB_CLK>, - <&gcc GCC_GMAC0_PTP_CLK>, - <&gcc GCC_GMAC1_PTP_CLK>; - clock-names = "cmn_ahb_clk", "cmn_sys_clk", - "uniphy_ahb_clk", "uniphy_sys_clk", - "gcc_mdio0_ahb_clk", - "gcc_mdio1_ahb_clk", - "gcc_gmac0_cfg_clk", - "gcc_gmac0_sys_clk", - "gcc_gmac1_cfg_clk", - "gcc_gmac1_sys_clk", - "uniphy0_port1_rx_clk", - "uniphy0_port1_tx_clk", - "uniphy1_port5_rx_clk", - "uniphy1_port5_tx_clk", - "nss_port1_rx_clk", "nss_port1_tx_clk", - "nss_port2_rx_clk", "nss_port2_tx_clk", - "gcc_snoc_gmac0_ahb_clk", - "gcc_snoc_gmac1_ahb_clk", - "gcc_gmac0_ptp_clk", - "gcc_gmac1_ptp_clk"; - resets = <&gcc GCC_GEPHY_BCR>, <&gcc GCC_UNIPHY_BCR>, - <&gcc GCC_GMAC0_BCR>, <&gcc GCC_GMAC1_BCR>, - <&gcc GCC_UNIPHY_SOFT_RESET>, - <&gcc GCC_GEPHY_MISC_ARES>; - reset-names = "gephy_bcr_rst", "uniphy_bcr_rst", - "gmac0_bcr_rst", "gmac1_bcr_rst", - "uniphy1_soft_rst", - "gephy_misc_rst"; - }; - }; - - ess-uniphy@98000 { - compatible = "qcom,ess-uniphy"; - reg = <0x98000 0x800>; - uniphy_access_mode = "local bus"; - }; - - msm_imem: qcom,msm-imem@8600000 { - compatible = "qcom,msm-imem"; - reg = <0x08600000 0x1000>; - ranges = <0x0 0x08600000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - mem_dump_table@10 { - compatible = "qcom,msm-imem-mem_dump_table"; - reg = <0x10 8>; - }; - }; - - cryptobam: dma@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x00704000 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely = <1>; - }; - - crypto: crypto@73a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x0073a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - qce,cmd_desc_support; - }; - - qpic_bam: dma@7984000{ - compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1c000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - qcom,sps { - compatible = "qcom,msm_sps_4k"; - qcom,pipe-attr-ee; - }; - - nand: qpic-nand@79b0000 { - compatible = "qcom,ebi2-nandc-bam-v2.1.1"; - reg = <0x79b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>, - <&gcc GCC_QPIC_IO_MACRO_CLK>; - clock-names = "core", "aon", "io_macro"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>, - <&qpic_bam 3>; - dma-names = "tx", "rx", "cmd", "status"; - - qpic,io_macro_clk_rates = <24000000 100000000 200000000 320000000>; - status = "disabled"; - - nandcs@0 { - compatible = "qcom,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - sdhc_1: sdhci@7804000 { - compatible = "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; - reg-names = "hc_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - qcom,bus-width = <4>; - qcom,max_clk = <192000000>; - - qcom,dedicated-io = <1>; - - /* device core power supply */ - qcom,vdd-voltage-level = <2900000 2900000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - qcom,vdd-io-always-on; - - qcom,cpu-dma-latency-us = <701>; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ - <78 512 1046 3200>, /* 400 KB/s*/ - <78 512 52286 160000>, /* 20 MB/s */ - <78 512 65360 200000>, /* 25 MB/s */ - <78 512 130718 400000>, /* 50 MB/s */ - <78 512 261438 800000>, /* 100 MB/s */ - <78 512 261438 800000>, /* 200 MB/s */ - <78 512 261438 800000>, /* 400 MB/s */ - <78 512 1338562 4096000>; /* Max. bandwidth */ - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 \ - 50000000 100000000 200000000 \ - 400000000 4294967295>; - - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "iface_clk", "core_clk"; - qcom,large-address-bus; - qcom,disable-aggressive-pm; - status = "disabled"; - }; - - nss-common { - compatible = "qcom,nss-common"; - reg = <0x01868010 0x01>; - reg-names = "nss-misc-reset"; - }; - - nss0: nss@40000000 { - compatible = "qcom,nss"; - interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>, - <0 399 0x1>, <0 398 0x1>, <0 397 0x1>, - <0 396 0x1>, <0 395 0x1>; - reg = <0x07a00000 0x100>, <0x0b111000 0x1000>; - reg-names = "nphys", "qgic-phys"; - clocks = <&gcc GCC_UBI0_CFG_CLK>, - <&gcc GCC_UBI0_DBG_CLK>, - <&gcc GCC_UBI0_CORE_CLK>, - <&gcc GCC_UBI0_UTCM_CLK>, - <&gcc GCC_UBI0_AXI_CLK>, - <&gcc GCC_SNOC_UBI0_AXI_CLK>, - <&gcc GCC_UBI0_NC_AXI_CLK>; - clock-names = "nss-cfg-clk", "nss-dbg-clk", - "nss-core-clk", "nss-utcm-clk", - "nss-axi-clk", - "nss-snoc-axi-clk", - "nss-nc-axi-clk"; - qcom,id = <0>; - qcom,num-queue = <4>; - qcom,num-irq = <8>; - qcom,num-pri = <4>; - qcom,load-addr = <0x40000000>; - qcom,low-frequency = <850000000>; - qcom,mid-frequency = <850000000>; - qcom,max-frequency = <1000000000>; - qcom,ipv4-enabled; - qcom,ipv4-reasm-enabled; - qcom,ipv6-enabled; - qcom,ipv6-reasm-enabled; - qcom,wlanredirect-enabled; - qcom,tun6rd-enabled; - qcom,l2tpv2-enabled; - qcom,gre-enabled; - qcom,gre-redir-enabled; - qcom,gre-redir-mark-enabled; - qcom,map-t-enabled; - qcom,portid-enabled; - qcom,pppoe-enabled; - qcom,pptp-enabled; - qcom,tunipip6-enabled; - qcom,shaping-enabled; - qcom,wlan-dataplane-offload-enabled; - qcom,pvxlan-enabled; - qcom,clmap-enabled; - qcom,vxlan-enabled; - qcom,match-enabled; - qcom,mirror-enabled; - qcom,crypto-enabled; - qcom,ipsec-enabled; - qcom,rmnet_rx-enabled; - qcom,udp-st-enabled; - }; - - nss-dp-common { - compatible = "qcom,nss-dp-common"; - qcom,tcsr-base = <0x01937000>; - }; - - nss_crypto: qcom,nss_crypto { - compatible = "qcom,nss-crypto"; - #address-cells = <1>; - #size-cells = <1>; - qcom,max-contexts = <64>; - qcom,max-context-size = <144>; - ranges; - ce5_node { - compatible = "qcom,ce5"; - reg-names = "crypto_pbase", "bam_base"; - reg = <0x0073a000 0x6000>, - <0x00704000 0x20000>; - qcom,dma-mask = <0x0c>; - qcom,transform-enabled; - qcom,aes128-cbc; - qcom,aes256-cbc; - qcom,aes128-ctr; - qcom,aes256-ctr; - qcom,aes128-ecb; - qcom,aes256-ecb; - qcom,3des-cbc; - qcom,sha160-hash; - qcom,sha256-hash; - qcom,sha160-hmac; - qcom,sha256-hmac; - qcom,aes128-cbc-sha160-hmac; - qcom,aes256-cbc-sha160-hmac; - qcom,aes128-ctr-sha160-hmac; - qcom,aes256-ctr-sha160-hmac; - qcom,3des-cbc-sha160-hmac; - qcom,3des-cbc-sha256-hmac; - qcom,aes128-cbc-sha256-hmac; - qcom,aes256-cbc-sha256-hmac; - qcom,aes128-ctr-sha256-hmac; - qcom,aes256-ctr-sha256-hmac; - engine0 { - qcom,ee = <2 3>; - }; - }; - }; - - acc0:clock-controller@b188000 { - compatible = "qcom,arm-cortex-acc"; - reg = <0x0b188000 0x1000>; - }; - - acc1:clock-controller@b198000 { - compatible = "qcom,arm-cortex-acc"; - reg = <0x0b198000 0x1000>; - }; - - qcom_rng: qrng@e1000 { - compatible = "qcom,prng-ipq807x"; - reg = <0xe3000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - status = "ok"; - }; - - qca,scm_restart_reason { - compatible = "qca,scm_restart_reason"; - dload_status = <0>; - dload_warm_reset = <0>; - }; - - watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt-ipq5018"; - reg = <0xb017000 0x1000>; - reg-names = "kpss_wdt"; - interrupt-names = "bark_irq"; - interrupts = ; - clocks = <&sleep_clk>; - timeout-sec = <10>; - wdt-max-timeout = <32>; - }; - - apcs: syscon@b111000 { - compatible = "syscon"; - reg = <0x0B111000 0x1000>; - }; - - wcss: smp2p-wcss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = <0 177 1>; - - qcom,ipc = <&apcs 8 9>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - qcom,smp2p-feature-ssr-ack; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - q6v5_wcss: q6v5_wcss@CD00000 { - compatible = "qca,q6v5-wcss-rproc-ipq50xx"; - firmware = "IPQ5018/q6_fw.mdt"; - reg = <0xCD00000 0x10000>, - <0x194f000 0x10>, - <0x1952000 0x10>, - <0x4ab000 0x20>, - <0x1818000 0x10>, - <0x1859000 0x10>, - <0x1945000 0x10>, - <0x193D204 0x4>; - reg-names = "wcss-base", - "tcsr-q6-base", - "tcsr-base", - "mpm-base", - "gcc-wcss-bcr-base", - "gcc-wcss-misc-base", - "tcsr-global", - "tcsr-q6-boot-trig"; - qca,auto-restart; - qca,extended-intc; - qca,dump-q6-reg; - qca,emulation; - interrupts-extended = <&intc 0 291 1>, - <&wcss_smp2p_in 0 0>, - <&wcss_smp2p_in 1 0>, - <&wcss_smp2p_in 3 0>; - interrupt-names = "wdog", - "qcom,gpio-err-fatal", - "qcom,gpio-err-ready", - "qcom,gpio-stop-ack"; - qcom,smem-states = <&wcss_smp2p_out 0>, - <&wcss_smp2p_out 1>; - qcom,smem-state-names = "shutdown", - "stop"; - }; - - q6v5_m3: q6v5_m3 { - compatible = "qca,q6v5-m3-rproc"; - firmware = "IPQ5018/m3_fw.mdt"; - qca,auto-restart; - qcom,restart-group = <&q6v5_m3 &q6v5_wcss>; - }; - - tcsr_mutex_block: syscon@1905000 { - compatible = "syscon"; - reg = <0x1905000 0x8000>; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - #hwlock-cells = <1>; - }; - - smem: qcom,smem@4AB00000 { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 0>; - }; - - apcs_glb: mailbox@b111000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - qcom,ipc = <&apcs 8 8>; - - #mbox-cells = <1>; - }; - - tcsr_q6_block: syscon@1945000 { - compatible = "syscon"; - reg = <0x1945000 0xE000>; - }; - - qcom_q6v5_wcss: qcom_q6v5_wcss@CD00000 { - compatible = "qcom,ipq5018-wcss-pil"; - firmware = "IPQ5018/q6_fw.mdt"; - m3_firmware = "IPQ5018/m3_fw.mdt"; - reg = <0xCD00000 0x4040>, - <0x4ab000 0x20>, - <0x4a1000 0x10>, - <0x1938000 0x8>, - <0x193D204 0x4>; - reg-names = "qdsp6", - "rmb", - "mpm", - "tcsr-msip", - "tcsr-q6-boot-trig"; - clocks = <&gcc GCC_Q6_AXIS_CLK>, - <&gcc GCC_WCSS_AHB_S_CLK>, - <&gcc GCC_WCSS_ECAHB_CLK>, - <&gcc GCC_WCSS_ACMT_CLK>, - <&gcc GCC_WCSS_AXI_M_CLK>, - <&gcc GCC_Q6_AXIM_CLK>, - <&gcc GCC_Q6_AXIM2_CLK>, - <&gcc GCC_Q6_AHB_CLK>, - <&gcc GCC_Q6_AHB_S_CLK>, - <&gcc GCC_WCSS_AXI_S_CLK>; - clock-names = "gcc_q6_axis_clk", - "gcc_wcss_ahb_s_clk", - "gcc_wcss_ecahb_clk", - "gcc_wcss_acmt_clk", - "gcc_wcss_axi_m_clk", - "gcc_q6_axim_clk", - "gcc_q6_axim2_clk", - "gcc_q6_ahb_clk", - "gcc_q6_ahb_s_clk", - "gcc_wcss_axi_s_clk"; - qca,auto-restart; - qca,extended-intc; - qca,wcss-aon-reset-seq; - interrupts-extended = <&intc 0 291 1>, - <&wcss_smp2p_in 0 0>, - <&wcss_smp2p_in 1 0>, - <&wcss_smp2p_in 2 0>, - <&wcss_smp2p_in 3 0>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - resets = <&gcc GCC_WCSSAON_RESET>, - <&gcc GCC_WCSS_BCR>, - <&gcc GCC_WCSS_Q6_BCR>, - <&gcc GCC_CE_BCR>; - - reset-names = "wcss_aon_reset", - "wcss_reset", - "wcss_q6_reset", - "ce_reset"; - - qcom,halt-regs = <&tcsr_q6_block 0xA000 0xD000 0x0>; - - qcom,smem-states = <&wcss_smp2p_out 0>, - <&wcss_smp2p_out 1>; - qcom,smem-state-names = "shutdown", - "stop"; - - qcom,q6v6; - - glink-edge { - interrupts = ; - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 8>; - - rpm_requests { - qcom,glink-channels = "IPCRTR"; - }; - }; - }; - - wifi0: wifi@c000000 { - compatible = "qcom,cnss-qca5018", "qcom,ipq5018-wifi"; - reg = <0xc000000 0x1000000>; - #ifdef __IPQ_MEM_PROFILE_256_MB__ - qcom,tgt-mem-mode = <2>; - #else - qcom,tgt-mem-mode = <1>; - #endif - qcom,rproc = <&qcom_q6v5_wcss>; - interrupts = <0 288 1>, /* o_wcss_apps_intr[0] = */ - <0 289 1>, - <0 290 1>, - <0 292 1>, - <0 293 1>, - <0 294 1>, - <0 295 1>, - <0 296 1>, - <0 297 1>, - <0 298 1>, - <0 299 1>, - <0 300 1>, - <0 301 1>, - <0 302 1>, - <0 303 1>, - <0 304 1>, - <0 305 1>, - <0 306 1>, - <0 307 1>, - <0 308 1>, - <0 309 1>, - <0 310 1>, - <0 311 1>, - <0 312 1>, - <0 313 1>, /* o_wcss_apps_intr[25] */ - - <0 314 1>, - <0 315 1>, - <0 316 1>, - <0 317 1>, - <0 318 1>, - <0 319 1>, - <0 320 1>, - <0 321 1>, - <0 322 1>, - <0 323 1>, - <0 324 1>, - <0 325 1>, - - <0 326 1>, - - <0 327 1>, - <0 328 1>, - <0 329 1>, - <0 330 1>, - <0 331 1>, - <0 332 1>, - - <0 333 1>, - <0 334 1>, - <0 335 1>, - <0 336 1>, - <0 337 1>, - <0 338 1>, - <0 339 1>; /* o_wcss_apps_intr[51] */ - - interrupt-names = "misc-pulse1", - "misc-latch", - "sw-exception", - "ce0", - "ce1", - "ce2", - "ce3", - "ce4", - "ce5", - "ce6", - "ce7", - "ce8", - "ce9", - "ce10", - "ce11", - "host2wbm-desc-feed", - "host2reo-re-injection", - "host2reo-command", - "host2rxdma-monitor-ring3", - "host2rxdma-monitor-ring2", - "host2rxdma-monitor-ring1", - "reo2ost-exception", - "wbm2host-rx-release", - "reo2host-status", - "reo2host-destination-ring4", - "reo2host-destination-ring3", - "reo2host-destination-ring2", - "reo2host-destination-ring1", - "rxdma2host-monitor-destination-mac3", - "rxdma2host-monitor-destination-mac2", - "rxdma2host-monitor-destination-mac1", - "ppdu-end-interrupts-mac3", - "ppdu-end-interrupts-mac2", - "ppdu-end-interrupts-mac1", - "rxdma2host-monitor-status-ring-mac3", - "rxdma2host-monitor-status-ring-mac2", - "rxdma2host-monitor-status-ring-mac1", - "host2rxdma-host-buf-ring-mac3", - "host2rxdma-host-buf-ring-mac2", - "host2rxdma-host-buf-ring-mac1", - "rxdma2host-destination-ring-mac3", - "rxdma2host-destination-ring-mac2", - "rxdma2host-destination-ring-mac1", - "host2tcl-input-ring4", - "host2tcl-input-ring3", - "host2tcl-input-ring2", - "host2tcl-input-ring1", - "wbm2host-tx-completions-ring3", - "wbm2host-tx-completions-ring2", - "wbm2host-tx-completions-ring1", - "tcl2host-status-ring"; - status = "disabled"; - qcom,pta-num = <0>; - qcom,coex-mode = <0x3>; - qcom,bt-active-time = <0>; - qcom,bt-priority-time = <0>; - qcom,coex-algo = <0x2>; - qcom,pta-priority = <0>; - }; - - wifi1: wifi1@c000000 { - compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; - qcom,rproc = <&qcom_q6v5_wcss>; - status = "disabled"; - }; - - wifi2: wifi2@c000000 { - compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; - qcom,rproc = <&qcom_q6v5_wcss>; - status = "disabled"; - }; - - i2c_0: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - qup-clock-frequency = <9600000>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = <0x0 0xd0 0x0>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - dbm_1p5: dbm@0x8AF8000 { - compatible = "qcom,usb-dbm-1p5"; - reg = <0x8AF8000 0x300>; - qcom,reset-ep-after-lpm-resume; - }; - - hs_m31phy_0: hs_m31phy@5b000 { - compatible = "qca,m31-usb-hsphy"; - reg = <0x05b000 0x120>, - <0x08af8800 0x400>; - reg-names = "m31usb_phy_base", - "qscratch_base"; - phy_type= "utmi"; - - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - reset-names = "usb2_phy_reset"; - - status = "disabled"; - }; - - ssuniphy_0: ssuniphy@5d000 { - compatible = "qca,ipq5018-uni-ssphy"; - reg = <0x5d000 0x800>; - clocks = <&gcc GCC_USB0_PIPE_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; - - clock-names = "pipe_clk", "phy_cfg_ahb_clk"; - - resets = <&gcc GCC_USB0_PHY_BCR>; - reset-names = "por_rst"; - #phy-cells = <0>; - status = "disabled"; - }; - - usb3: usb3@8A00000 { - compatible = "qcom,ipq5018-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x8AF8800 0x100>, - <0x8A00000 0xe000>; - reg-names = "qscratch_base", "dwc3_base"; - clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_LFPS_CLK>, - <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "sys_noc_axi", - "master", - "sleep", - "mock_utmi", - "cfg_ahb_clk", - "aux_clk", - "lfps_clk", - "pipe_clk"; - assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <60000000>; - resets = <&gcc GCC_USB0_BCR>; - reset-names = "usb30_mstr_rst"; - qca,host = <1>; - qcom,usb-dbm = <&dbm_1p5>; - status = "disabled"; - - dwc_0: dwc3@8A00000 { - compatible = "snps,dwc3"; - reg = <0x8A00000 0xe000>; - interrupts = ; - usb-phy = <&hs_m31phy_0>; - #phy-cells = <0>; - phys = <&ssuniphy_0>; - phy-names = "usb3-phy"; - snps,dis_ep_cache_eviction; - tx-fifo-resize; - snps,usb3-u1u2-disable; - snps,nominal-elastic-buffer; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,quirk-ref-clock-adjustment = <0x49459>; - snps,quirk-ref-clock-period = <0x10>; - snps,quirk-30m-sb-sel = <0x0>; - dr_mode = "host"; - }; - }; - - qcom,usbbam@8B04000 { - compatible = "qcom,usb-bam-msm"; - reg = <0x8B04000 0x17000>; - interrupt-parent = <&intc>; - interrupts = <0 135 0>; - - qcom,bam-type = <0>; - qcom,usb-bam-fifo-baseaddr = <0x4A600000>; - qcom,usb-bam-num-pipes = <4>; - qcom,ignore-core-reset-ack; - qcom,disable-clk-gating; - qcom,usb-bam-override-threshold = <0x4001>; - qcom,usb-bam-max-mbps-highspeed = <400>; - qcom,usb-bam-max-mbps-superspeed = <3600>; - qcom,reset-bam-on-connect; - - qcom,pipe0 { - label = "ssusb-qdss-in-0"; - qcom,usb-bam-mem-type = <2>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <0>; - qcom,peer-bam-physical-address = <0x6064000>; - qcom,src-bam-pipe-index = <0>; - qcom,dst-bam-pipe-index = <0>; - qcom,data-fifo-offset = <0x0>; - qcom,data-fifo-size = <0xe00>; - qcom,descriptor-fifo-offset = <0xe00>; - qcom,descriptor-fifo-size = <0x200>; - }; - }; - - qcom,diag@0 { - compatible = "qcom,diag"; - status = "ok"; - }; - - pcie_x1phy: phy@7e000{ - compatible = "qca,uni-pcie-phy-gen2"; - reg = <0x7e000 0x800>; - phy-type = "gen2"; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "phy_phy"; - mode_fixed = <2>; - status = "disabled"; - }; - - pcie_x1: pci@80000000 { - compatible = "qcom,pcie-ipq5018"; - reg = <0x80000000 0xf1d - 0x80000F20 0xa8 - 0x80001000 0x1000 - 0x78000 0x3000 - 0x80100000 0x1000>; - reg-names = "dbi", "elbi", "dm_iatu", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_x1phy>; - phy-names ="pciephy"; - force_gen2 = <1>; - - ranges = <0x81000000 0 0x80200000 0x80200000 - 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x80300000 0x80300000 - 0 0x10000000>; /* non-prefetchable memory */ - - interrupts = , - <0 416 IRQ_TYPE_NONE>, <0 417 IRQ_TYPE_NONE>, - <0 418 IRQ_TYPE_NONE>, <0 419 IRQ_TYPE_NONE>, - <0 420 IRQ_TYPE_NONE>, <0 421 IRQ_TYPE_NONE>, - <0 422 IRQ_TYPE_NONE>, <0 423 IRQ_TYPE_NONE>, - <0 424 IRQ_TYPE_NONE>, <0 425 IRQ_TYPE_NONE>, - <0 426 IRQ_TYPE_NONE>, <0 427 IRQ_TYPE_NONE>, - <0 428 IRQ_TYPE_NONE>, <0 429 IRQ_TYPE_NONE>, - <0 430 IRQ_TYPE_NONE>, <0 431 IRQ_TYPE_NONE>, - <0 432 IRQ_TYPE_NONE>, <0 433 IRQ_TYPE_NONE>, - <0 434 IRQ_TYPE_NONE>, <0 435 IRQ_TYPE_NONE>, - <0 436 IRQ_TYPE_NONE>, <0 437 IRQ_TYPE_NONE>, - <0 438 IRQ_TYPE_NONE>, <0 439 IRQ_TYPE_NONE>, - <0 440 IRQ_TYPE_NONE>, <0 441 IRQ_TYPE_NONE>, - <0 442 IRQ_TYPE_NONE>, <0 443 IRQ_TYPE_NONE>, - <0 444 IRQ_TYPE_NONE>, <0 445 IRQ_TYPE_NONE>, - <0 446 IRQ_TYPE_NONE>, <0 447 IRQ_TYPE_NONE>; - interrupt-names = "msi", "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, - <&gcc GCC_PCIE1_AXI_M_CLK>, - <&gcc GCC_PCIE1_AXI_S_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, - <&gcc GCC_PCIE1_AUX_CLK>, - <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; - - clock-names = "sys_noc", - "axi_m", - "axi_s", - "ahb", - "aux", - "axi_bridge"; - - resets = <&gcc GCC_PCIE1_PIPE_ARES>, - <&gcc GCC_PCIE1_SLEEP_ARES>, - <&gcc GCC_PCIE1_CORE_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE1_AHB_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; - - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - qcom,msi-gicm-addr = <0x0B00A040>; - qcom,msi-gicm-base = <0x1c0>; - - status = "disabled"; - - pcie_x1_rp: pcie_x1_rp { - reg = <0 0 0 0 0>; - }; - }; - - pcie_x2phy: phy@86000{ - compatible = "qca,uni-pcie-phy-gen2"; - reg = <0x86000 0x800 0x86800 0x800>; - phy-type = "gen2"; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "phy_phy"; - mode_fixed = <2>; - x2 = <1>; - status = "disabled"; - }; - - pcie_x2: pci@a0000000 { - compatible = "qcom,pcie-ipq5018"; - reg = <0xa0000000 0xf1d - 0xa0000F20 0xa8 - 0xa0001000 0x1000 - 0x80000 0x3000 - 0xa0100000 0x1000>; - reg-names = "dbi", "elbi", "dm_iatu", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_x2phy>; - phy-names ="pciephy"; - force_gen2 = <1>; - - ranges = <0x81000000 0 0xa0200000 0xa0200000 - 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0xa0300000 0xa0300000 - 0 0x10000000>; /* non-prefetchable memory */ - - interrupts = , - <0 448 IRQ_TYPE_NONE>, <0 449 IRQ_TYPE_NONE>, - <0 450 IRQ_TYPE_NONE>, <0 451 IRQ_TYPE_NONE>, - <0 452 IRQ_TYPE_NONE>, <0 453 IRQ_TYPE_NONE>, - <0 454 IRQ_TYPE_NONE>, <0 455 IRQ_TYPE_NONE>, - <0 456 IRQ_TYPE_NONE>, <0 457 IRQ_TYPE_NONE>, - <0 458 IRQ_TYPE_NONE>, <0 459 IRQ_TYPE_NONE>, - <0 460 IRQ_TYPE_NONE>, <0 461 IRQ_TYPE_NONE>, - <0 462 IRQ_TYPE_NONE>, <0 463 IRQ_TYPE_NONE>, - <0 464 IRQ_TYPE_NONE>, <0 465 IRQ_TYPE_NONE>, - <0 466 IRQ_TYPE_NONE>, <0 467 IRQ_TYPE_NONE>, - <0 468 IRQ_TYPE_NONE>, <0 469 IRQ_TYPE_NONE>, - <0 470 IRQ_TYPE_NONE>, <0 471 IRQ_TYPE_NONE>, - <0 472 IRQ_TYPE_NONE>, <0 473 IRQ_TYPE_NONE>, - <0 474 IRQ_TYPE_NONE>, <0 475 IRQ_TYPE_NONE>, - <0 476 IRQ_TYPE_NONE>, <0 477 IRQ_TYPE_NONE>, - <0 478 IRQ_TYPE_NONE>, <0 479 IRQ_TYPE_NONE>; - interrupt-names = "msi", "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; - - clock-names = "sys_noc", - "axi_m", - "axi_s", - "ahb", - "aux", - "axi_bridge"; - - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; - - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - qcom,msi-gicm-addr = <0x0B00B040>; - qcom,msi-gicm-base = <0x1e0>; - - status = "disabled"; - - pcie_x2_rp: pcie_x2_rp { - reg = <0 0 0 0 0>; - }; - }; - - qgic_msi_0: qti,qgic2m-msi_0 { - compatible = "qti,qgic2m-msi"; - - interrupts = <0 416 IRQ_TYPE_NONE>, <0 417 IRQ_TYPE_NONE>, - <0 418 IRQ_TYPE_NONE>, <0 419 IRQ_TYPE_NONE>, - <0 420 IRQ_TYPE_NONE>, <0 421 IRQ_TYPE_NONE>, - <0 422 IRQ_TYPE_NONE>, <0 423 IRQ_TYPE_NONE>, - <0 424 IRQ_TYPE_NONE>, <0 425 IRQ_TYPE_NONE>, - <0 426 IRQ_TYPE_NONE>, <0 427 IRQ_TYPE_NONE>, - <0 428 IRQ_TYPE_NONE>, <0 429 IRQ_TYPE_NONE>, - <0 430 IRQ_TYPE_NONE>, <0 431 IRQ_TYPE_NONE>, - <0 432 IRQ_TYPE_NONE>, <0 433 IRQ_TYPE_NONE>, - <0 434 IRQ_TYPE_NONE>, <0 435 IRQ_TYPE_NONE>, - <0 436 IRQ_TYPE_NONE>, <0 437 IRQ_TYPE_NONE>, - <0 438 IRQ_TYPE_NONE>, <0 439 IRQ_TYPE_NONE>, - <0 440 IRQ_TYPE_NONE>, <0 441 IRQ_TYPE_NONE>, - <0 442 IRQ_TYPE_NONE>, <0 443 IRQ_TYPE_NONE>, - <0 444 IRQ_TYPE_NONE>, <0 445 IRQ_TYPE_NONE>, - <0 446 IRQ_TYPE_NONE>, <0 447 IRQ_TYPE_NONE>; - interrupt-names = "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - - qti,msi-gicm-addr = <0x0B00A040>; - qti,msi-gicm-base = <0x1c0>; - - status = "disabled"; - }; - - qgic_msi_1: qti,qgic2m-msi_1 { - compatible = "qti,qgic2m-msi"; - - interrupts = <0 448 IRQ_TYPE_NONE>, <0 449 IRQ_TYPE_NONE>, - <0 450 IRQ_TYPE_NONE>, <0 451 IRQ_TYPE_NONE>, - <0 452 IRQ_TYPE_NONE>, <0 453 IRQ_TYPE_NONE>, - <0 454 IRQ_TYPE_NONE>, <0 455 IRQ_TYPE_NONE>, - <0 456 IRQ_TYPE_NONE>, <0 457 IRQ_TYPE_NONE>, - <0 458 IRQ_TYPE_NONE>, <0 459 IRQ_TYPE_NONE>, - <0 460 IRQ_TYPE_NONE>, <0 461 IRQ_TYPE_NONE>, - <0 462 IRQ_TYPE_NONE>, <0 463 IRQ_TYPE_NONE>, - <0 464 IRQ_TYPE_NONE>, <0 465 IRQ_TYPE_NONE>, - <0 466 IRQ_TYPE_NONE>, <0 467 IRQ_TYPE_NONE>, - <0 468 IRQ_TYPE_NONE>, <0 469 IRQ_TYPE_NONE>, - <0 470 IRQ_TYPE_NONE>, <0 471 IRQ_TYPE_NONE>, - <0 472 IRQ_TYPE_NONE>, <0 473 IRQ_TYPE_NONE>, - <0 474 IRQ_TYPE_NONE>, <0 475 IRQ_TYPE_NONE>, - <0 476 IRQ_TYPE_NONE>, <0 477 IRQ_TYPE_NONE>, - <0 478 IRQ_TYPE_NONE>, <0 479 IRQ_TYPE_NONE>; - interrupt-names = "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - - qti,msi-gicm-addr = <0x0B00B040>; - qti,msi-gicm-base = <0x1e0>; - - status = "disabled"; - }; - - qcom,test@0 { - compatible = "qcom,testmhi"; - status = "ok"; - }; - - tzlog: qca,tzlog { - compatible = "qca,tzlog_ipq50xx"; - interrupts = ; - qca,tzbsp-diag-buf-size = <0x2000>; - }; - - eud: qcom,msm-eud{ - compatible = "qcom,msm-eud"; - reg = <0x58000 0x1000>, - <0x59000 0x2000>, - <0x5a000 0x1000>; - reg-names = "eud_base", - "eud_mode_mgr", - "eud_mode_mgr2"; - interrupts = ; - interrupt-names = "eud_irq"; - status = "disabled"; - }; - - bt: bt@7000000 { - compatible = "qcom,bt"; - firmware = "IPQ5018/bt_fw_patch.mdt"; - - reg = <0x01943008 0x8>; - reg-names = "bt_warm_rst"; - memory-region = <&bt_region>; - - qcom,ipc = <&apcs 8 23>; - interrupts = ; - - resets = <&gcc GCC_BTSS_BCR>; - reset-names = "btss_reset"; - - clocks = <&gcc GCC_BTSS_LPO_CLK>; - clock-names = "lpo_clk"; - }; - lpass: lpass@0xA000000{ - compatible = "qca,lpass-ipq5018"; - reg = <0xA000000 0x3BFFFF>; - clocks = <&gcc GCC_SNOC_LPASS_AXIM_CLK>, - <&gcc GCC_SNOC_LPASS_SWAY_CLK>, - <&gcc GCC_LPASS_CORE_AXIM_CLK>, - <&gcc GCC_LPASS_SWAY_CLK>; - clock-names = "snoc_axim", "snoc_sway", "axim", "sway"; - resets = <&gcc GCC_LPASS_BCR>; - reset-names = "lpass"; - status = "disabled"; - }; - - pcm: pcm@0xA3C0000{ - compatible = "qca,ipq5018-lpass-pcm"; - reg = <0xA3C0000 0x23014>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "out0"; - capture_memory = "lpm"; - playback_memory = "lpm"; - voice_loopback = <0>; - status = "disabled"; - }; - - pcm_lb: pcm_lb@0 { - compatible = "qca,ipq5018-pcm-lb"; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - qcom,acc = <&acc0>; - next-level-cache = <&L2_0>; - clocks = <&apss_clk APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points = < - /* kHz uV (fixed) */ - 800000 1100000 - 1008000 1100000 - >; - clock-latency = <200000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - qcom,acc = <&acc1>; - next-level-cache = <&L2_0>; - clocks = <&apss_clk APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points = < - /* kHz uV (fixed) */ - 800000 1100000 - 1008000 1100000 - >; - clock-latency = <200000>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - }; - - pmuv8: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq5018"; - }; - qfprom_sec { - compatible = "qcom,qfprom-sec"; - img-addr = <0x4A800000>; - img-size = <0x00400000>; - }; - }; - -}; - -#include "qcom-ipq5018-coresight.dtsi" -#include "qcom-ipq5018-thermal.dtsi" diff --git a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50.dtsi b/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50.dtsi deleted file mode 100755 index 5778a4c41..000000000 --- a/feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-xunison-d50.dtsi +++ /dev/null @@ -1,1442 +0,0 @@ -/* - * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include "qcom-ipq5018-memory.dtsi" -#include "qcom-ipq5018-mhi.dtsi" -#include "ipq5018_clocks.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ5018"; - compatible = "qcom,ipq5018"; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - status = "ok"; - }; - -#ifdef ENABLE_QSEECOM - qseecom { - compatible = "ipq5018-qseecom"; - mem-start = <0x4a400000>; - mem-size = <0x200000>; - }; -#endif - - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0xb000000 0x1000>, <0xb002000 0x1000>; - ranges = <0x0 0xb00a000 0x1ffa>; - - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xffd>; - }; - - v2m1: v2m@1000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x1000 0xffd>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq5018"; - reg = <0x1800000 0x80000>; - #clock-cells = <0x1>; - #reset-cells = <0x1>; - }; - - apss_clk: qcom,apss_clk@b111000 { - compatible = "qcom,apss-ipq5018"; - reg = <0xb111000 0x6000>; - #clock-cells = <0x1>; - #reset-cells = <1>; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x1d000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - spi_0: spi@78b5000 { /* BLSP1 QUP0 */ - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b5000 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, <&blsp_dma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - pwm { - compatible = "qca,ipq6018-pwm"; - reg = <0x1941010 0x20>; - clocks = <&gcc GCC_ADSS_PWM_CLK>; - clock-names = "core"; - src-freq = <100000000>; - pwm-base-index = <0>; - used-pwm-indices = <1>, <1>, <1>, <1>; - status = "disabled"; - }; - - mdio0: mdio@88000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio"; - reg = <0x88000 0x64>; - status = "disabled"; - resets = <&gcc GCC_GEPHY_MDC_SW_ARES>; - reset-names = "gephy_mdc_rst"; - }; - - mdio1: mdio@90000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "qcom,qca-mdio"; - reg = <0x90000 0x64>; - status = "disabled"; - }; - ess-instance { - ess-switch@0x39c00000 { - compatible = "qcom,ess-switch-ipq50xx"; - reg = <0x39c00000 0x200000>; - switch_access_mode = "local bus"; - clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, - <&gcc GCC_CMN_BLK_SYS_CLK>, - <&gcc GCC_UNIPHY_AHB_CLK>, - <&gcc GCC_UNIPHY_SYS_CLK>, - <&gcc GCC_MDIO0_AHB_CLK>, - <&gcc GCC_MDIO1_AHB_CLK>, - <&gcc GCC_GMAC0_CFG_CLK>, - <&gcc GCC_GMAC0_SYS_CLK>, - <&gcc GCC_GMAC1_CFG_CLK>, - <&gcc GCC_GMAC1_SYS_CLK>, - <&gcc GCC_GEPHY_RX_CLK>, - <&gcc GCC_GEPHY_TX_CLK>, - <&gcc GCC_UNIPHY_RX_CLK>, - <&gcc GCC_UNIPHY_TX_CLK>, - <&gcc GCC_GMAC0_RX_CLK>, - <&gcc GCC_GMAC0_TX_CLK>, - <&gcc GCC_GMAC1_RX_CLK>, - <&gcc GCC_GMAC1_TX_CLK>, - <&gcc GCC_SNOC_GMAC0_AHB_CLK>, - <&gcc GCC_SNOC_GMAC1_AHB_CLK>, - <&gcc GCC_GMAC0_PTP_CLK>, - <&gcc GCC_GMAC1_PTP_CLK>; - clock-names = "cmn_ahb_clk", "cmn_sys_clk", - "uniphy_ahb_clk", "uniphy_sys_clk", - "gcc_mdio0_ahb_clk", - "gcc_mdio1_ahb_clk", - "gcc_gmac0_cfg_clk", - "gcc_gmac0_sys_clk", - "gcc_gmac1_cfg_clk", - "gcc_gmac1_sys_clk", - "uniphy0_port1_rx_clk", - "uniphy0_port1_tx_clk", - "uniphy1_port5_rx_clk", - "uniphy1_port5_tx_clk", - "nss_port1_rx_clk", "nss_port1_tx_clk", - "nss_port2_rx_clk", "nss_port2_tx_clk", - "gcc_snoc_gmac0_ahb_clk", - "gcc_snoc_gmac1_ahb_clk", - "gcc_gmac0_ptp_clk", - "gcc_gmac1_ptp_clk"; - resets = <&gcc GCC_GEPHY_BCR>, <&gcc GCC_UNIPHY_BCR>, - <&gcc GCC_GMAC0_BCR>, <&gcc GCC_GMAC1_BCR>, - <&gcc GCC_UNIPHY_SOFT_RESET>, - <&gcc GCC_GEPHY_MISC_ARES>; - reset-names = "gephy_bcr_rst", "uniphy_bcr_rst", - "gmac0_bcr_rst", "gmac1_bcr_rst", - "uniphy1_soft_rst", - "gephy_misc_rst"; - }; - }; - - ess-uniphy@98000 { - compatible = "qcom,ess-uniphy"; - reg = <0x98000 0x800>; - uniphy_access_mode = "local bus"; - }; - - msm_imem: qcom,msm-imem@8600000 { - compatible = "qcom,msm-imem"; - reg = <0x08600000 0x1000>; - ranges = <0x0 0x08600000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - mem_dump_table@10 { - compatible = "qcom,msm-imem-mem_dump_table"; - reg = <0x10 8>; - }; - }; - - cryptobam: dma@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x00704000 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely = <1>; - }; - - crypto: crypto@73a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x0073a000 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - qce,cmd_desc_support; - }; - - qpic_bam: dma@7984000{ - compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1c000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - qcom,sps { - compatible = "qcom,msm_sps_4k"; - qcom,pipe-attr-ee; - }; - - nand: qpic-nand@79b0000 { - compatible = "qcom,ebi2-nandc-bam-v2.1.1"; - reg = <0x79b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>, - <&gcc GCC_QPIC_IO_MACRO_CLK>; - clock-names = "core", "aon", "io_macro"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>, - <&qpic_bam 3>; - dma-names = "tx", "rx", "cmd", "status"; - - qpic,io_macro_clk_rates = <24000000 100000000 200000000 320000000>; - status = "disabled"; - - nandcs@0 { - compatible = "qcom,nandcs"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - sdhc_1: sdhci@7804000 { - compatible = "qcom,sdhci-msm-v5"; - reg = <0x7804000 0x1000>; - reg-names = "hc_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - qcom,bus-width = <4>; - qcom,max_clk = <192000000>; - - qcom,dedicated-io = <1>; - - /* device core power supply */ - qcom,vdd-voltage-level = <2900000 2900000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - qcom,vdd-io-always-on; - - qcom,cpu-dma-latency-us = <701>; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ - <78 512 1046 3200>, /* 400 KB/s*/ - <78 512 52286 160000>, /* 20 MB/s */ - <78 512 65360 200000>, /* 25 MB/s */ - <78 512 130718 400000>, /* 50 MB/s */ - <78 512 261438 800000>, /* 100 MB/s */ - <78 512 261438 800000>, /* 200 MB/s */ - <78 512 261438 800000>, /* 400 MB/s */ - <78 512 1338562 4096000>; /* Max. bandwidth */ - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 \ - 50000000 100000000 200000000 \ - 400000000 4294967295>; - - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "iface_clk", "core_clk"; - qcom,large-address-bus; - qcom,disable-aggressive-pm; - status = "disabled"; - }; - - nss-common { - compatible = "qcom,nss-common"; - reg = <0x01868010 0x01>; - reg-names = "nss-misc-reset"; - }; - - nss0: nss@40000000 { - compatible = "qcom,nss"; - interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>, - <0 399 0x1>, <0 398 0x1>, <0 397 0x1>, - <0 396 0x1>, <0 395 0x1>; - reg = <0x07a00000 0x100>, <0x0b111000 0x1000>; - reg-names = "nphys", "qgic-phys"; - clocks = <&gcc GCC_UBI0_CFG_CLK>, - <&gcc GCC_UBI0_DBG_CLK>, - <&gcc GCC_UBI0_CORE_CLK>, - <&gcc GCC_UBI0_UTCM_CLK>, - <&gcc GCC_UBI0_AXI_CLK>, - <&gcc GCC_SNOC_UBI0_AXI_CLK>, - <&gcc GCC_UBI0_NC_AXI_CLK>; - clock-names = "nss-cfg-clk", "nss-dbg-clk", - "nss-core-clk", "nss-utcm-clk", - "nss-axi-clk", - "nss-snoc-axi-clk", - "nss-nc-axi-clk"; - qcom,id = <0>; - qcom,num-queue = <4>; - qcom,num-irq = <8>; - qcom,num-pri = <4>; - qcom,load-addr = <0x40000000>; - qcom,low-frequency = <850000000>; - qcom,mid-frequency = <850000000>; - qcom,max-frequency = <1000000000>; - qcom,ipv4-enabled; - qcom,ipv4-reasm-enabled; - qcom,ipv6-enabled; - qcom,ipv6-reasm-enabled; - qcom,wlanredirect-enabled; - qcom,tun6rd-enabled; - qcom,l2tpv2-enabled; - qcom,gre-enabled; - qcom,gre-redir-enabled; - qcom,gre-redir-mark-enabled; - qcom,map-t-enabled; - qcom,portid-enabled; - qcom,pppoe-enabled; - qcom,pptp-enabled; - qcom,tunipip6-enabled; - qcom,shaping-enabled; - qcom,wlan-dataplane-offload-enabled; - qcom,pvxlan-enabled; - qcom,clmap-enabled; - qcom,vxlan-enabled; - qcom,match-enabled; - qcom,mirror-enabled; - qcom,crypto-enabled; - qcom,ipsec-enabled; - qcom,rmnet_rx-enabled; - qcom,udp-st-enabled; - }; - - nss-dp-common { - compatible = "qcom,nss-dp-common"; - qcom,tcsr-base = <0x01937000>; - }; - - nss_crypto: qcom,nss_crypto { - compatible = "qcom,nss-crypto"; - #address-cells = <1>; - #size-cells = <1>; - qcom,max-contexts = <64>; - qcom,max-context-size = <144>; - ranges; - ce5_node { - compatible = "qcom,ce5"; - reg-names = "crypto_pbase", "bam_base"; - reg = <0x0073a000 0x6000>, - <0x00704000 0x20000>; - qcom,dma-mask = <0x0c>; - qcom,transform-enabled; - qcom,aes128-cbc; - qcom,aes256-cbc; - qcom,aes128-ctr; - qcom,aes256-ctr; - qcom,aes128-ecb; - qcom,aes256-ecb; - qcom,3des-cbc; - qcom,sha160-hash; - qcom,sha256-hash; - qcom,sha160-hmac; - qcom,sha256-hmac; - qcom,aes128-cbc-sha160-hmac; - qcom,aes256-cbc-sha160-hmac; - qcom,aes128-ctr-sha160-hmac; - qcom,aes256-ctr-sha160-hmac; - qcom,3des-cbc-sha160-hmac; - qcom,3des-cbc-sha256-hmac; - qcom,aes128-cbc-sha256-hmac; - qcom,aes256-cbc-sha256-hmac; - qcom,aes128-ctr-sha256-hmac; - qcom,aes256-ctr-sha256-hmac; - engine0 { - qcom,ee = <2 3>; - }; - }; - }; - - acc0:clock-controller@b188000 { - compatible = "qcom,arm-cortex-acc"; - reg = <0x0b188000 0x1000>; - }; - - acc1:clock-controller@b198000 { - compatible = "qcom,arm-cortex-acc"; - reg = <0x0b198000 0x1000>; - }; - - qcom_rng: qrng@e1000 { - compatible = "qcom,prng-ipq807x"; - reg = <0xe3000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - status = "ok"; - }; - - qca,scm_restart_reason { - compatible = "qca,scm_restart_reason"; - dload_status = <0>; - dload_warm_reset = <0>; - }; - - watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt-ipq5018"; - reg = <0xb017000 0x1000>; - reg-names = "kpss_wdt"; - interrupt-names = "bark_irq"; - interrupts = ; - clocks = <&sleep_clk>; - timeout-sec = <10>; - wdt-max-timeout = <32>; - }; - - apcs: syscon@b111000 { - compatible = "syscon"; - reg = <0x0B111000 0x1000>; - }; - - wcss: smp2p-wcss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = <0 177 1>; - - qcom,ipc = <&apcs 8 9>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - qcom,smp2p-feature-ssr-ack; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - q6v5_wcss: q6v5_wcss@CD00000 { - compatible = "qca,q6v5-wcss-rproc-ipq50xx"; - firmware = "IPQ5018/q6_fw.mdt"; - reg = <0xCD00000 0x10000>, - <0x194f000 0x10>, - <0x1952000 0x10>, - <0x4ab000 0x20>, - <0x1818000 0x10>, - <0x1859000 0x10>, - <0x1945000 0x10>, - <0x193D204 0x4>; - reg-names = "wcss-base", - "tcsr-q6-base", - "tcsr-base", - "mpm-base", - "gcc-wcss-bcr-base", - "gcc-wcss-misc-base", - "tcsr-global", - "tcsr-q6-boot-trig"; - qca,auto-restart; - qca,extended-intc; - qca,dump-q6-reg; - qca,emulation; - interrupts-extended = <&intc 0 291 1>, - <&wcss_smp2p_in 0 0>, - <&wcss_smp2p_in 1 0>, - <&wcss_smp2p_in 3 0>; - interrupt-names = "wdog", - "qcom,gpio-err-fatal", - "qcom,gpio-err-ready", - "qcom,gpio-stop-ack"; - qcom,smem-states = <&wcss_smp2p_out 0>, - <&wcss_smp2p_out 1>; - qcom,smem-state-names = "shutdown", - "stop"; - }; - - q6v5_m3: q6v5_m3 { - compatible = "qca,q6v5-m3-rproc"; - firmware = "IPQ5018/m3_fw.mdt"; - qca,auto-restart; - qcom,restart-group = <&q6v5_m3 &q6v5_wcss>; - }; - - tcsr_mutex_block: syscon@1905000 { - compatible = "syscon"; - reg = <0x1905000 0x8000>; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - #hwlock-cells = <1>; - }; - - smem: qcom,smem@4AB00000 { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 0>; - }; - - apcs_glb: mailbox@b111000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - qcom,ipc = <&apcs 8 8>; - - #mbox-cells = <1>; - }; - - tcsr_q6_block: syscon@1945000 { - compatible = "syscon"; - reg = <0x1945000 0xE000>; - }; - - qcom_q6v5_wcss: qcom_q6v5_wcss@CD00000 { - compatible = "qcom,ipq5018-wcss-pil"; - firmware = "IPQ5018/q6_fw.mdt"; - m3_firmware = "IPQ5018/m3_fw.mdt"; - reg = <0xCD00000 0x4040>, - <0x4ab000 0x20>, - <0x4a1000 0x10>, - <0x1938000 0x8>, - <0x193D204 0x4>; - reg-names = "qdsp6", - "rmb", - "mpm", - "tcsr-msip", - "tcsr-q6-boot-trig"; - clocks = <&gcc GCC_Q6_AXIS_CLK>, - <&gcc GCC_WCSS_AHB_S_CLK>, - <&gcc GCC_WCSS_ECAHB_CLK>, - <&gcc GCC_WCSS_ACMT_CLK>, - <&gcc GCC_WCSS_AXI_M_CLK>, - <&gcc GCC_Q6_AXIM_CLK>, - <&gcc GCC_Q6_AXIM2_CLK>, - <&gcc GCC_Q6_AHB_CLK>, - <&gcc GCC_Q6_AHB_S_CLK>, - <&gcc GCC_WCSS_AXI_S_CLK>; - clock-names = "gcc_q6_axis_clk", - "gcc_wcss_ahb_s_clk", - "gcc_wcss_ecahb_clk", - "gcc_wcss_acmt_clk", - "gcc_wcss_axi_m_clk", - "gcc_q6_axim_clk", - "gcc_q6_axim2_clk", - "gcc_q6_ahb_clk", - "gcc_q6_ahb_s_clk", - "gcc_wcss_axi_s_clk"; - qca,auto-restart; - qca,extended-intc; - qca,wcss-aon-reset-seq; - interrupts-extended = <&intc 0 291 1>, - <&wcss_smp2p_in 0 0>, - <&wcss_smp2p_in 1 0>, - <&wcss_smp2p_in 2 0>, - <&wcss_smp2p_in 3 0>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - resets = <&gcc GCC_WCSSAON_RESET>, - <&gcc GCC_WCSS_BCR>, - <&gcc GCC_WCSS_Q6_BCR>, - <&gcc GCC_CE_BCR>; - - reset-names = "wcss_aon_reset", - "wcss_reset", - "wcss_q6_reset", - "ce_reset"; - - qcom,halt-regs = <&tcsr_q6_block 0xA000 0xD000 0x0>; - - qcom,smem-states = <&wcss_smp2p_out 0>, - <&wcss_smp2p_out 1>; - qcom,smem-state-names = "shutdown", - "stop"; - - qcom,q6v6; - - glink-edge { - interrupts = ; - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 8>; - - rpm_requests { - qcom,glink-channels = "IPCRTR"; - }; - }; - }; - - wifi0: wifi@c000000 { - compatible = "qcom,cnss-qca5018", "qcom,ipq5018-wifi"; - reg = <0xc000000 0x1000000>; - #ifdef __IPQ_MEM_PROFILE_256_MB__ - qcom,tgt-mem-mode = <2>; - #else - qcom,tgt-mem-mode = <1>; - #endif - qcom,rproc = <&qcom_q6v5_wcss>; - interrupts = <0 288 1>, /* o_wcss_apps_intr[0] = */ - <0 289 1>, - <0 290 1>, - <0 292 1>, - <0 293 1>, - <0 294 1>, - <0 295 1>, - <0 296 1>, - <0 297 1>, - <0 298 1>, - <0 299 1>, - <0 300 1>, - <0 301 1>, - <0 302 1>, - <0 303 1>, - <0 304 1>, - <0 305 1>, - <0 306 1>, - <0 307 1>, - <0 308 1>, - <0 309 1>, - <0 310 1>, - <0 311 1>, - <0 312 1>, - <0 313 1>, /* o_wcss_apps_intr[25] */ - - <0 314 1>, - <0 315 1>, - <0 316 1>, - <0 317 1>, - <0 318 1>, - <0 319 1>, - <0 320 1>, - <0 321 1>, - <0 322 1>, - <0 323 1>, - <0 324 1>, - <0 325 1>, - - <0 326 1>, - - <0 327 1>, - <0 328 1>, - <0 329 1>, - <0 330 1>, - <0 331 1>, - <0 332 1>, - - <0 333 1>, - <0 334 1>, - <0 335 1>, - <0 336 1>, - <0 337 1>, - <0 338 1>, - <0 339 1>; /* o_wcss_apps_intr[51] */ - - interrupt-names = "misc-pulse1", - "misc-latch", - "sw-exception", - "ce0", - "ce1", - "ce2", - "ce3", - "ce4", - "ce5", - "ce6", - "ce7", - "ce8", - "ce9", - "ce10", - "ce11", - "host2wbm-desc-feed", - "host2reo-re-injection", - "host2reo-command", - "host2rxdma-monitor-ring3", - "host2rxdma-monitor-ring2", - "host2rxdma-monitor-ring1", - "reo2ost-exception", - "wbm2host-rx-release", - "reo2host-status", - "reo2host-destination-ring4", - "reo2host-destination-ring3", - "reo2host-destination-ring2", - "reo2host-destination-ring1", - "rxdma2host-monitor-destination-mac3", - "rxdma2host-monitor-destination-mac2", - "rxdma2host-monitor-destination-mac1", - "ppdu-end-interrupts-mac3", - "ppdu-end-interrupts-mac2", - "ppdu-end-interrupts-mac1", - "rxdma2host-monitor-status-ring-mac3", - "rxdma2host-monitor-status-ring-mac2", - "rxdma2host-monitor-status-ring-mac1", - "host2rxdma-host-buf-ring-mac3", - "host2rxdma-host-buf-ring-mac2", - "host2rxdma-host-buf-ring-mac1", - "rxdma2host-destination-ring-mac3", - "rxdma2host-destination-ring-mac2", - "rxdma2host-destination-ring-mac1", - "host2tcl-input-ring4", - "host2tcl-input-ring3", - "host2tcl-input-ring2", - "host2tcl-input-ring1", - "wbm2host-tx-completions-ring3", - "wbm2host-tx-completions-ring2", - "wbm2host-tx-completions-ring1", - "tcl2host-status-ring"; - status = "disabled"; - qcom,pta-num = <0>; - qcom,coex-mode = <0x3>; - qcom,bt-active-time = <0>; - qcom,bt-priority-time = <0>; - qcom,coex-algo = <0x2>; - qcom,pta-priority = <0>; - }; - - wifi1: wifi1@c000000 { - compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; - qcom,rproc = <&qcom_q6v5_wcss>; - status = "disabled"; - }; - - wifi2: wifi2@c000000 { - compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; - qcom,rproc = <&qcom_q6v5_wcss>; - status = "disabled"; - }; - - i2c_0: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x78b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - qup-clock-frequency = <9600000>; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq5018-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = <0x0 0xd0 0x0>; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - dbm_1p5: dbm@0x8AF8000 { - compatible = "qcom,usb-dbm-1p5"; - reg = <0x8AF8000 0x300>; - qcom,reset-ep-after-lpm-resume; - }; - - hs_m31phy_0: hs_m31phy@5b000 { - compatible = "qca,m31-usb-hsphy"; - reg = <0x05b000 0x120>, - <0x08af8800 0x400>; - reg-names = "m31usb_phy_base", - "qscratch_base"; - phy_type= "utmi"; - - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - reset-names = "usb2_phy_reset"; - - status = "disabled"; - }; - - ssuniphy_0: ssuniphy@5d000 { - compatible = "qca,ipq5018-uni-ssphy"; - reg = <0x5d000 0x800>; - clocks = <&gcc GCC_USB0_PIPE_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; - - clock-names = "pipe_clk", "phy_cfg_ahb_clk"; - - resets = <&gcc GCC_USB0_PHY_BCR>; - reset-names = "por_rst"; - #phy-cells = <0>; - status = "disabled"; - }; - - usb3: usb3@8A00000 { - compatible = "qcom,ipq5018-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x8AF8800 0x100>, - <0x8A00000 0xe000>; - reg-names = "qscratch_base", "dwc3_base"; - clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_LFPS_CLK>, - <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "sys_noc_axi", - "master", - "sleep", - "mock_utmi", - "cfg_ahb_clk", - "aux_clk", - "lfps_clk", - "pipe_clk"; - assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <60000000>; - resets = <&gcc GCC_USB0_BCR>; - reset-names = "usb30_mstr_rst"; - qca,host = <1>; - qcom,usb-dbm = <&dbm_1p5>; - status = "disabled"; - - dwc_0: dwc3@8A00000 { - compatible = "snps,dwc3"; - reg = <0x8A00000 0xe000>; - interrupts = ; - usb-phy = <&hs_m31phy_0>; - #phy-cells = <0>; - phys = <&ssuniphy_0>; - phy-names = "usb3-phy"; - snps,dis_ep_cache_eviction; - tx-fifo-resize; - snps,usb3-u1u2-disable; - snps,nominal-elastic-buffer; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,quirk-ref-clock-adjustment = <0x49459>; - snps,quirk-ref-clock-period = <0x10>; - snps,quirk-30m-sb-sel = <0x0>; - dr_mode = "host"; - }; - }; - - qcom,usbbam@8B04000 { - compatible = "qcom,usb-bam-msm"; - reg = <0x8B04000 0x17000>; - interrupt-parent = <&intc>; - interrupts = <0 135 0>; - - qcom,bam-type = <0>; - qcom,usb-bam-fifo-baseaddr = <0x4A600000>; - qcom,usb-bam-num-pipes = <4>; - qcom,ignore-core-reset-ack; - qcom,disable-clk-gating; - qcom,usb-bam-override-threshold = <0x4001>; - qcom,usb-bam-max-mbps-highspeed = <400>; - qcom,usb-bam-max-mbps-superspeed = <3600>; - qcom,reset-bam-on-connect; - - qcom,pipe0 { - label = "ssusb-qdss-in-0"; - qcom,usb-bam-mem-type = <2>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <0>; - qcom,peer-bam-physical-address = <0x6064000>; - qcom,src-bam-pipe-index = <0>; - qcom,dst-bam-pipe-index = <0>; - qcom,data-fifo-offset = <0x0>; - qcom,data-fifo-size = <0xe00>; - qcom,descriptor-fifo-offset = <0xe00>; - qcom,descriptor-fifo-size = <0x200>; - }; - }; - - qcom,diag@0 { - compatible = "qcom,diag"; - status = "ok"; - }; - - pcie_x1phy: phy@7e000{ - compatible = "qca,uni-pcie-phy-gen2"; - reg = <0x7e000 0x800>; - phy-type = "gen2"; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "phy_phy"; - mode_fixed = <2>; - status = "disabled"; - }; - - pcie_x1: pci@80000000 { - compatible = "qcom,pcie-ipq5018"; - reg = <0x80000000 0xf1d - 0x80000F20 0xa8 - 0x80001000 0x1000 - 0x78000 0x3000 - 0x80100000 0x1000>; - reg-names = "dbi", "elbi", "dm_iatu", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_x1phy>; - phy-names ="pciephy"; - force_gen2 = <1>; - - ranges = <0x81000000 0 0x80200000 0x80200000 - 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0x80300000 0x80300000 - 0 0x10000000>; /* non-prefetchable memory */ - - interrupts = , - <0 416 IRQ_TYPE_NONE>, <0 417 IRQ_TYPE_NONE>, - <0 418 IRQ_TYPE_NONE>, <0 419 IRQ_TYPE_NONE>, - <0 420 IRQ_TYPE_NONE>, <0 421 IRQ_TYPE_NONE>, - <0 422 IRQ_TYPE_NONE>, <0 423 IRQ_TYPE_NONE>, - <0 424 IRQ_TYPE_NONE>, <0 425 IRQ_TYPE_NONE>, - <0 426 IRQ_TYPE_NONE>, <0 427 IRQ_TYPE_NONE>, - <0 428 IRQ_TYPE_NONE>, <0 429 IRQ_TYPE_NONE>, - <0 430 IRQ_TYPE_NONE>, <0 431 IRQ_TYPE_NONE>, - <0 432 IRQ_TYPE_NONE>, <0 433 IRQ_TYPE_NONE>, - <0 434 IRQ_TYPE_NONE>, <0 435 IRQ_TYPE_NONE>, - <0 436 IRQ_TYPE_NONE>, <0 437 IRQ_TYPE_NONE>, - <0 438 IRQ_TYPE_NONE>, <0 439 IRQ_TYPE_NONE>, - <0 440 IRQ_TYPE_NONE>, <0 441 IRQ_TYPE_NONE>, - <0 442 IRQ_TYPE_NONE>, <0 443 IRQ_TYPE_NONE>, - <0 444 IRQ_TYPE_NONE>, <0 445 IRQ_TYPE_NONE>, - <0 446 IRQ_TYPE_NONE>, <0 447 IRQ_TYPE_NONE>; - interrupt-names = "msi", "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, - <&gcc GCC_PCIE1_AXI_M_CLK>, - <&gcc GCC_PCIE1_AXI_S_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, - <&gcc GCC_PCIE1_AUX_CLK>, - <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; - - clock-names = "sys_noc", - "axi_m", - "axi_s", - "ahb", - "aux", - "axi_bridge"; - - resets = <&gcc GCC_PCIE1_PIPE_ARES>, - <&gcc GCC_PCIE1_SLEEP_ARES>, - <&gcc GCC_PCIE1_CORE_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE1_AHB_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; - - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - qcom,msi-gicm-addr = <0x0B00A040>; - qcom,msi-gicm-base = <0x1c0>; - - status = "disabled"; - - pcie_x1_rp: pcie_x1_rp { - reg = <0 0 0 0 0>; - }; - }; - - pcie_x2phy: phy@86000{ - compatible = "qca,uni-pcie-phy-gen2"; - reg = <0x86000 0x800 0x86800 0x800>; - phy-type = "gen2"; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "phy_phy"; - mode_fixed = <2>; - x2 = <1>; - status = "disabled"; - }; - - pcie_x2: pci@a0000000 { - compatible = "qcom,pcie-ipq5018"; - reg = <0xa0000000 0xf1d - 0xa0000F20 0xa8 - 0xa0001000 0x1000 - 0x80000 0x3000 - 0xa0100000 0x1000>; - reg-names = "dbi", "elbi", "dm_iatu", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_x2phy>; - phy-names ="pciephy"; - force_gen2 = <1>; - - ranges = <0x81000000 0 0xa0200000 0xa0200000 - 0 0x00100000 /* downstream I/O */ - 0x82000000 0 0xa0300000 0xa0300000 - 0 0x10000000>; /* non-prefetchable memory */ - - interrupts = , - <0 448 IRQ_TYPE_NONE>, <0 449 IRQ_TYPE_NONE>, - <0 450 IRQ_TYPE_NONE>, <0 451 IRQ_TYPE_NONE>, - <0 452 IRQ_TYPE_NONE>, <0 453 IRQ_TYPE_NONE>, - <0 454 IRQ_TYPE_NONE>, <0 455 IRQ_TYPE_NONE>, - <0 456 IRQ_TYPE_NONE>, <0 457 IRQ_TYPE_NONE>, - <0 458 IRQ_TYPE_NONE>, <0 459 IRQ_TYPE_NONE>, - <0 460 IRQ_TYPE_NONE>, <0 461 IRQ_TYPE_NONE>, - <0 462 IRQ_TYPE_NONE>, <0 463 IRQ_TYPE_NONE>, - <0 464 IRQ_TYPE_NONE>, <0 465 IRQ_TYPE_NONE>, - <0 466 IRQ_TYPE_NONE>, <0 467 IRQ_TYPE_NONE>, - <0 468 IRQ_TYPE_NONE>, <0 469 IRQ_TYPE_NONE>, - <0 470 IRQ_TYPE_NONE>, <0 471 IRQ_TYPE_NONE>, - <0 472 IRQ_TYPE_NONE>, <0 473 IRQ_TYPE_NONE>, - <0 474 IRQ_TYPE_NONE>, <0 475 IRQ_TYPE_NONE>, - <0 476 IRQ_TYPE_NONE>, <0 477 IRQ_TYPE_NONE>, - <0 478 IRQ_TYPE_NONE>, <0 479 IRQ_TYPE_NONE>; - interrupt-names = "msi", "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; - - clock-names = "sys_noc", - "axi_m", - "axi_s", - "ahb", - "aux", - "axi_bridge"; - - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; - - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - qcom,msi-gicm-addr = <0x0B00B040>; - qcom,msi-gicm-base = <0x1e0>; - - status = "disabled"; - - pcie_x2_rp: pcie_x2_rp { - reg = <0 0 0 0 0>; - }; - }; - - qgic_msi_0: qti,qgic2m-msi_0 { - compatible = "qti,qgic2m-msi"; - - interrupts = <0 416 IRQ_TYPE_NONE>, <0 417 IRQ_TYPE_NONE>, - <0 418 IRQ_TYPE_NONE>, <0 419 IRQ_TYPE_NONE>, - <0 420 IRQ_TYPE_NONE>, <0 421 IRQ_TYPE_NONE>, - <0 422 IRQ_TYPE_NONE>, <0 423 IRQ_TYPE_NONE>, - <0 424 IRQ_TYPE_NONE>, <0 425 IRQ_TYPE_NONE>, - <0 426 IRQ_TYPE_NONE>, <0 427 IRQ_TYPE_NONE>, - <0 428 IRQ_TYPE_NONE>, <0 429 IRQ_TYPE_NONE>, - <0 430 IRQ_TYPE_NONE>, <0 431 IRQ_TYPE_NONE>, - <0 432 IRQ_TYPE_NONE>, <0 433 IRQ_TYPE_NONE>, - <0 434 IRQ_TYPE_NONE>, <0 435 IRQ_TYPE_NONE>, - <0 436 IRQ_TYPE_NONE>, <0 437 IRQ_TYPE_NONE>, - <0 438 IRQ_TYPE_NONE>, <0 439 IRQ_TYPE_NONE>, - <0 440 IRQ_TYPE_NONE>, <0 441 IRQ_TYPE_NONE>, - <0 442 IRQ_TYPE_NONE>, <0 443 IRQ_TYPE_NONE>, - <0 444 IRQ_TYPE_NONE>, <0 445 IRQ_TYPE_NONE>, - <0 446 IRQ_TYPE_NONE>, <0 447 IRQ_TYPE_NONE>; - interrupt-names = "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - - qti,msi-gicm-addr = <0x0B00A040>; - qti,msi-gicm-base = <0x1c0>; - - status = "disabled"; - }; - - qgic_msi_1: qti,qgic2m-msi_1 { - compatible = "qti,qgic2m-msi"; - - interrupts = <0 448 IRQ_TYPE_NONE>, <0 449 IRQ_TYPE_NONE>, - <0 450 IRQ_TYPE_NONE>, <0 451 IRQ_TYPE_NONE>, - <0 452 IRQ_TYPE_NONE>, <0 453 IRQ_TYPE_NONE>, - <0 454 IRQ_TYPE_NONE>, <0 455 IRQ_TYPE_NONE>, - <0 456 IRQ_TYPE_NONE>, <0 457 IRQ_TYPE_NONE>, - <0 458 IRQ_TYPE_NONE>, <0 459 IRQ_TYPE_NONE>, - <0 460 IRQ_TYPE_NONE>, <0 461 IRQ_TYPE_NONE>, - <0 462 IRQ_TYPE_NONE>, <0 463 IRQ_TYPE_NONE>, - <0 464 IRQ_TYPE_NONE>, <0 465 IRQ_TYPE_NONE>, - <0 466 IRQ_TYPE_NONE>, <0 467 IRQ_TYPE_NONE>, - <0 468 IRQ_TYPE_NONE>, <0 469 IRQ_TYPE_NONE>, - <0 470 IRQ_TYPE_NONE>, <0 471 IRQ_TYPE_NONE>, - <0 472 IRQ_TYPE_NONE>, <0 473 IRQ_TYPE_NONE>, - <0 474 IRQ_TYPE_NONE>, <0 475 IRQ_TYPE_NONE>, - <0 476 IRQ_TYPE_NONE>, <0 477 IRQ_TYPE_NONE>, - <0 478 IRQ_TYPE_NONE>, <0 479 IRQ_TYPE_NONE>; - interrupt-names = "msi_0", "msi_1", - "msi_2", "msi_3", "msi_4", - "msi_5", "msi_6", "msi_7", - "msi_8", "msi_9", "msi_10", - "msi_11", "msi_12", "msi_13", - "msi_14", "msi_15", "msi_16", - "msi_17", "msi_18", "msi_19", - "msi_20", "msi_21", - "msi_23", "msi_24", "msi_25", - "msi_26", "msi_27", "msi_28", - "msi_29", "msi_30", "msi_31"; - - qti,msi-gicm-addr = <0x0B00B040>; - qti,msi-gicm-base = <0x1e0>; - - status = "disabled"; - }; - - qcom,test@0 { - compatible = "qcom,testmhi"; - status = "ok"; - }; - - tzlog: qca,tzlog { - compatible = "qca,tzlog_ipq50xx"; - interrupts = ; - qca,tzbsp-diag-buf-size = <0x2000>; - }; - - eud: qcom,msm-eud{ - compatible = "qcom,msm-eud"; - reg = <0x58000 0x1000>, - <0x59000 0x2000>, - <0x5a000 0x1000>; - reg-names = "eud_base", - "eud_mode_mgr", - "eud_mode_mgr2"; - interrupts = ; - interrupt-names = "eud_irq"; - status = "disabled"; - }; - - bt: bt@7000000 { - compatible = "qcom,bt"; - firmware = "IPQ5018/bt_fw_patch.mdt"; - - reg = <0x01943008 0x8>; - reg-names = "bt_warm_rst"; - memory-region = <&bt_region>; - - qcom,ipc = <&apcs 8 23>; - interrupts = ; - - resets = <&gcc GCC_BTSS_BCR>; - reset-names = "btss_reset"; - - clocks = <&gcc GCC_BTSS_LPO_CLK>; - clock-names = "lpo_clk"; - }; - lpass: lpass@0xA000000{ - compatible = "qca,lpass-ipq5018"; - reg = <0xA000000 0x3BFFFF>; - clocks = <&gcc GCC_SNOC_LPASS_AXIM_CLK>, - <&gcc GCC_SNOC_LPASS_SWAY_CLK>, - <&gcc GCC_LPASS_CORE_AXIM_CLK>, - <&gcc GCC_LPASS_SWAY_CLK>; - clock-names = "snoc_axim", "snoc_sway", "axim", "sway"; - resets = <&gcc GCC_LPASS_BCR>; - reset-names = "lpass"; - status = "disabled"; - }; - - pcm: pcm@0xA3C0000{ - compatible = "qca,ipq5018-lpass-pcm"; - reg = <0xA3C0000 0x23014>; - interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "out0"; - capture_memory = "lpm"; - playback_memory = "lpm"; - voice_loopback = <0>; - status = "disabled"; - }; - - pcm_lb: pcm_lb@0 { - compatible = "qca,ipq5018-pcm-lb"; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - qcom,acc = <&acc0>; - next-level-cache = <&L2_0>; - clocks = <&apss_clk APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points = < - /* kHz uV (fixed) */ - 800000 1100000 - 1008000 1100000 - >; - clock-latency = <200000>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - qcom,acc = <&acc1>; - next-level-cache = <&L2_0>; - clocks = <&apss_clk APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points = < - /* kHz uV (fixed) */ - 800000 1100000 - 1008000 1100000 - >; - clock-latency = <200000>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - }; - - pmuv8: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - firmware { - scm { - compatible = "qcom,scm-ipq5018"; - }; - qfprom_sec { - compatible = "qcom,qfprom-sec"; - img-addr = <0x4A800000>; - img-size = <0x00400000>; - }; - }; - -}; - -#include "qcom-ipq5018-coresight.dtsi" -#include "qcom-ipq5018-thermal.dtsi" diff --git a/feeds/ipq807x/ipq807x/image/ipq50xx.mk b/feeds/ipq807x/ipq807x/image/ipq50xx.mk index 9975a1254..572c035b2 100644 --- a/feeds/ipq807x/ipq807x/image/ipq50xx.mk +++ b/feeds/ipq807x/ipq807x/image/ipq50xx.mk @@ -165,3 +165,56 @@ define Device/yuncore_fap655 endef TARGET_DEVICES += yuncore_fap655 +define Device/optimcloud_d50-5g + DEVICE_TITLE := OptimCloud D50-5G + DEVICE_DTS := qcom-ipq5018-optimcloud-d50-5g + SUPPORTED_DEVICES := optimcloud,d50-5g + DEVICE_PACKAGES := ath11k-wifi-optimcloud-d50 ath11k-firmware-ipq50xx ath11k-firmware-qcn9000 + DEVICE_DTS_CONFIG := config@mp03.1 + IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata + IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand + IMAGE/nand-factory.ubi := append-ubi +endef +TARGET_DEVICES += optimcloud_d50-5g + +define Device/optimcloud_d50 + DEVICE_TITLE := OptimCloud D50 + DEVICE_DTS := qcom-ipq5018-optimcloud-d50 + SUPPORTED_DEVICES := optimcloud,d50 + DEVICE_PACKAGES := ath11k-wifi-optimcloud-d50 ath11k-firmware-ipq50xx ath11k-firmware-qcn9000 ath11k-firmware-qcn6122 + DEVICE_DTS_CONFIG := config@mp03.1 + IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata + IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand + IMAGE/factory.ubi := append-ubi | qsdk-ipq-factory-nand + IMAGE/nand-factory.ubi := append-ubi | qsdk-ipq-factory-nand +endef +TARGET_DEVICES += optimcloud_d50 + +define Device/optimcloud_d60-5g + DEVICE_TITLE := OptimCloud D60-5G + DEVICE_DTS := qcom-ipq5018-optimcloud-d60-5g + SUPPORTED_DEVICES := optimcloud,d60-5g + DEVICE_PACKAGES := ath11k-wifi-optimcloud-d60 ath11k-firmware-ipq50xx ath11k-firmware-qcn9000 + DEVICE_DTS_CONFIG := config@mp03.1 + IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata + IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand + IMAGE/nand-factory.ubi := append-ubi +endef +TARGET_DEVICES += optimcloud_d60-5g + +define Device/optimcloud_d60 + DEVICE_TITLE := OptimCloud D60 + DEVICE_DTS := qcom-ipq5018-optimcloud-d60 + SUPPORTED_DEVICES := optimcloud,d60 + DEVICE_PACKAGES := ath11k-wifi-optimcloud-d60 ath11k-firmware-ipq50xx ath11k-firmware-qcn9000 ath11k-firmware-qcn6122 + DEVICE_DTS_CONFIG := config@mp03.1 + IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata + IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand + IMAGE/factory.ubi := append-ubi | qsdk-ipq-factory-nand + IMAGE/nand-factory.ubi := append-ubi | qsdk-ipq-factory-nand + endef + TARGET_DEVICES += optimcloud_d60 diff --git a/feeds/wifi-ax/ath11k-wifi/Makefile b/feeds/wifi-ax/ath11k-wifi/Makefile index 1a4a9d247..29ffb4394 100644 --- a/feeds/wifi-ax/ath11k-wifi/Makefile +++ b/feeds/wifi-ax/ath11k-wifi/Makefile @@ -128,6 +128,16 @@ $(call Package/ath11k-wifi-default) TITLE:=motorola q14 bdf endef +define Package/ath11k-wifi-optimcloud-d50 +$(call Package/ath11k-wifi-default) + TITLE:=optimcloud d50 bdf +endef + +define Package/ath11k-wifi-optimcloud-d60 +$(call Package/ath11k-wifi-default) + TITLE:=optimcloud d60 bdf +endef + define Package/ath11k-wifi-plasmacloud-pax1800 $(call Package/ath11k-wifi-default) TITLE:=plasmacloud-pax1800(-v2) bdf @@ -274,6 +284,20 @@ define Package/ath11k-wifi-cig-wf196_6g-us/install echo -n 'US' > $(1)/lib/firmware/country endef +define Package/ath11k-wifi-optimcloud-d50/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/ + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ + $(INSTALL_DATA) ./board-optimcloud-d50.bin.IPQ5018 $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/board.bin + $(INSTALL_DATA) ./board-optimcloud-d50.bin.QCN9074 $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board.bin +endef + +define Package/ath11k-wifi-optimcloud-d60/install + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ5018/hw1.0/ + $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ + $(INSTALL_DATA) ./board-optimcloud-d60.bin.QCN9074 $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board.bin + $(INSTALL_DATA) ./board-optimcloud-d60.bin.QCN9074 $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board.bin +endef + define Package/ath11k-wifi-gl-ax1800/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/ $(INSTALL_DATA) ./board-gl-ax1800.bin.IPQ6018 $(1)/lib/firmware/ath11k/IPQ6018/hw1.0/board-2.bin @@ -388,6 +412,8 @@ $(eval $(call BuildPackage,ath11k-wifi-cig-wf188n-us)) $(eval $(call BuildPackage,ath11k-wifi-cig-wf196_6g-ca)) $(eval $(call BuildPackage,ath11k-wifi-cig-wf196_6g-us)) $(eval $(call BuildPackage,ath11k-wifi-motorola-q14)) +$(eval $(call BuildPackage,ath11k-wifi-optimcloud-d50)) +$(eval $(call BuildPackage,ath11k-wifi-optimcloud-d60)) $(eval $(call BuildPackage,ath11k-wifi-hfcl-ion4xi)) $(eval $(call BuildPackage,ath11k-wifi-hfcl-ion4xi_wp)) $(eval $(call BuildPackage,ath11k-wifi-hfcl-ion4xi_w)) diff --git a/feeds/wifi-ax/ath11k-wifi/board-optimcloud-d50.bin.IPQ5018 b/feeds/wifi-ax/ath11k-wifi/board-optimcloud-d50.bin.IPQ5018 new file mode 100644 index 0000000000000000000000000000000000000000..b65d6bc71e4eb57285c91e4632e3229cad14b1ab GIT binary patch literal 131072 zcmeHQ33OcLb-wS-(`ZH>OEa=Gl5APlF4-nT81FV%`(kNiS-XU>Rd9+EOhO1XCNZ(X z5)3sCNg#xb5Or~-+QyjmS-e+ z1h((f{b&CBFZaLy_uu<3Z=PlhvMl0j{LnRp7I_Zmt{s%uA$c8^*AaOgmDkIpG+rvV zaO`=6QiEgebvHPZQxa0$-01sQGCw7Gc;QvqiTfr&k5Ow@u3G79~k(}jgn#-d_-JwB;HBRc<|lod-b zjn}dG+MZVuOFl1SmT`hO=%ompGYDi*-Hh{q0oTVY!GC(iA>gHbx>tz9L!;?KAd?Dh z?=y_T!&6gJhl}LOdClYTm>l*J<>XXUum;8qD}DO3dvhiGC{WEB?Drq=-{!x^|FHja z{wYfQTmG*^OaGCm@NbCnZzc*|Nwm0?$PdIaQoyU^8KPxhLj8w{!ndLR6{z1#lvRfM zDb9;g9VQ$dFlMvX;h$_Bqz`k|;Yr9~9d1EC;&t#ail@Iy{v9~P>%cfR%>jo~=}-tbCMsrKP7qhAO@sxg;(PA@3 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