mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-31 18:38:10 +00:00
ipq53xx: add Edgecore EAP105 support
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
@@ -38,6 +38,11 @@ $(call Package/ath12k-wifi-default)
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TITLE:=board.bin for CIG WF189
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endef
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define Package/ath12k-wifi-edgecore-eap105
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$(call Package/ath12k-wifi-default)
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TITLE:=board.bin for Edgecore EAP105
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endef
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define Package/ath12k-wifi-sercomm-ap72tip
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$(call Package/ath12k-wifi-default)
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TITLE:=board.bin for Sercomm WIFI-7
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@@ -51,6 +56,14 @@ define Package/ath12k-wifi-cig-wf189/install
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$(INSTALL_DATA) ./board-cig-wf189.bin.ipq53xx $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board.bin
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endef
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define Package/ath12k-wifi-edgecore-eap105/install
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$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0
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$(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/
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$(INSTALL_DATA) ./board-edgecore-eap105.bin.qcn9224 $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/board.bin
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$(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/
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$(INSTALL_DATA) ./board-edgecore-eap105.bin.ipq53xx $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board.bin
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endef
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define Package/ath12k-wifi-sercomm-ap72tip/install
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$(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0
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$(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/
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@@ -61,4 +74,5 @@ endef
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$(eval $(call BuildPackage,ath12k-wifi-qcom-qcn9274))
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$(eval $(call BuildPackage,ath12k-wifi-cig-wf189))
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$(eval $(call BuildPackage,ath12k-wifi-edgecore-eap105))
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$(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip))
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BIN
feeds/ipq95xx/ath12k-wifi/board-edgecore-eap105.bin.ipq53xx
Normal file
BIN
feeds/ipq95xx/ath12k-wifi/board-edgecore-eap105.bin.ipq53xx
Normal file
Binary file not shown.
BIN
feeds/ipq95xx/ath12k-wifi/board-edgecore-eap105.bin.qcn9224
Normal file
BIN
feeds/ipq95xx/ath12k-wifi/board-edgecore-eap105.bin.qcn9224
Normal file
Binary file not shown.
@@ -10,6 +10,8 @@ ipq53xx_setup_interfaces()
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qcom,ipq9574-ap-al02-c4)
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ucidef_set_interfaces_lan_wan "eth1 eth2 eth3 eth4 eth5" "eth0"
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;;
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cig,wf189|\
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edgecore,eap105|\
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sercomm,ap72tip)
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ucidef_set_interfaces_lan_wan "eth1" "eth0"
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;;
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@@ -31,6 +31,7 @@ case "$FIRMWARE" in
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ath12k/IPQ5332/hw1.0/caldata.bin)
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case "$board" in
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cig,wf189|\
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edgecore,eap105|\
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sercomm,ap72tip)
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caldata_extract "0:ART" 0x1000 0x20000
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;;
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@@ -38,12 +39,10 @@ ath12k/IPQ5332/hw1.0/caldata.bin)
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;;
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ath12k/QCN92XX/hw1.0/cal-pci-0001:01:00.0.bin)
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case "$board" in
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cig,wf189)
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caldata_extract "0:ART" 0x58800 0x2d000
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;;
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cig,wf189|\
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edgecore,eap105|\
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sercomm,ap72tip)
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caldata_extract "0:ART" 0x58800 0x2d000
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#caldata_extract "0:ART" 0x26800 0x2d000
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;;
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esac
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;;
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@@ -17,6 +17,7 @@ platform_do_upgrade() {
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board=$(board_name)
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case $board in
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cig,wf189|\
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edgecore,eap105|\
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sercomm,ap72tip|\
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qcom,ipq9574-ap-al02-c4|\
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qcom,ipq9574-ap-al02-c15)
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@@ -1000,6 +1000,7 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21
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# CONFIG_RCU_EXPERT is not set
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CONFIG_RCU_STALL_COMMON=y
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CONFIG_RD_GZIP=y
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CONFIG_REALTEK_PHY=y
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# CONFIG_REED_SOLOMON_TEST is not set
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CONFIG_REGMAP=y
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CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
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@@ -1035,6 +1036,7 @@ CONFIG_RPS=y
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CONFIG_RTC_CLASS=y
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# CONFIG_RTC_DRV_CMOS is not set
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# CONFIG_RTC_DRV_PM8XXX is not set
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CONFIG_RTK_MSSDK_PHY=y
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CONFIG_RWSEM_SPIN_ON_OWNER=y
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CONFIG_RWSEM_XCHGADD_ALGORITHM=y
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CONFIG_SAMPLES=y
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@@ -0,0 +1,454 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ5332 AP-MI01.6 board device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "ipq5332.dtsi"
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#ifdef __IPQ_MEM_PROFILE_512_MB__
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#include "ipq5332-512MB-memory.dtsi"
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#else
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#include "ipq5332-default-memory.dtsi"
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#endif
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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model = "EdgeCore eap105";
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compatible = "edgecore,eap105", "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &blsp1_uart0;
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serial1 = &blsp1_uart1;
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ethernet0 = "/soc/dp1";
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ethernet1 = "/soc/dp2";
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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chosen {
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stdout-path = "serial0";
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};
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soc {
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pinctrl@1000000 {
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spi_0_pins: spi0-pinmux {
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spi_clock {
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pins = "gpio14";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-down;
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};
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spi_mosi {
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pins = "gpio15";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-down;
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};
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spi_miso {
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pins = "gpio16";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-down;
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};
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spi_cs {
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pins = "gpio17";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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serial_0_pins: serial0-pinmux {
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pins = "gpio18", "gpio19";
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function = "blsp0_uart0";
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drive-strength = <8>;
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bias-pull-up;
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};
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serial_1_pins: serial1-pinmux {
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pins = "gpio33", "gpio34", "gpio35", "gpio36";
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function = "blsp1_uart2";
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drive-strength = <8>;
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bias-pull-up;
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};
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i2c_1_pins: i2c-1-pinmux {
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pins = "gpio29", "gpio30";
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function = "blsp1_i2c0";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio1_pins: mdio1_pinmux {
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mux_0 {
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pins = "gpio27";
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function = "mdc1";
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drive-strength = <8>;
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bias-disable;
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};
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mux_1 {
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pins = "gpio28";
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function = "mdio1";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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pwm_pins: pwm_pinmux {
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mux_1 {
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pins = "gpio26";
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function = "pwm2";
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drive-strength = <8>;
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};
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mux_2 {
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pins = "gpio30";
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function = "pwm1";
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drive-strength = <8>;
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};
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mux_3 {
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pins = "gpio45";
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function = "pwm0";
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drive-strength = <8>;
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};
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};
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/*audio_pins_pri: audio_pinmux_pri {
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mux_1 {
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pins = "gpio29";
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function = "audio_pri";
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drive-strength = <8>;
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bias-pull-down;
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};
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mux_2 {
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pins = "gpio30";
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function = "audio_pri";
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drive-strength = <8>;
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bias-pull-down;
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};
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mux_3 {
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pins = "gpio31";
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function = "audio_pri";
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drive-strength = <4>;
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bias-pull-down;
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};
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mux_4 {
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pins = "gpio32";
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function = "audio_pri";
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drive-strength = <4>;
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bias-pull-down;
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};
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};*/
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spi_2_pins: spi-2-pins {
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pins = "gpio33", "gpio34", "gpio35", "gpio36";
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function = "blsp2_spi0";
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drive-strength = <8>;
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bias-pull-down;
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};
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button_pins: button_pins {
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rst_button {
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pins = "gpio25";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led@37 {
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label = "red:status";
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gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led_power: led@38 {
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label = "blue:status";
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gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led@39 {
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label = "green:status";
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gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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dp1 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <2>;
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reg = <0x3a504000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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mdio-bus = <&mdio>;
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qcom,phy-mdio-addr = <1>;
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qcom,link-poll = <1>;
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phy-mode = "sgmii";
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};
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dp2 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <1>;
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reg = <0x3a500000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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mdio-bus = <&mdio>;
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qcom,phy-mdio-addr = <2>;
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qcom,link-poll = <1>;
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phy-mode = "sgmii";
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};
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mdio:mdio@90000 {
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status = "ok";
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pinctrl-0 = <&mdio1_pins>;
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pinctrl-names = "default";
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/*gpio24 for rtl8251 reset gpio 22 for rtl8211f */
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phy-reset-gpio = <&tlmm 24 GPIO_ACTIVE_LOW &tlmm 22 GPIO_ACTIVE_LOW>;
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phyaddr_fixup = <0xC90F018>;
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uniphyaddr_fixup = <0xC90F014>;
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mdio_clk_fixup; /* MDIO clock sequence fix up flag */
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phy0: ethernet-phy@0 {
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reg = <2>;
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compatible = "ethernet-phy-id001c.c916";
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-id001c.c86a";
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};
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};
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ess-instance {
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num_devices = <0x1>;
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ess-switch@3a000000 {
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switch_cpu_bmp = <0x1>; /* cpu port bitmap */
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switch_lan_bmp = <0x2>; /* lan port bitmap */
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switch_wan_bmp = <0x4>; /* wan port bitmap */
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switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/
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switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
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switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
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qcom,port_phyinfo {
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port@0 {
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port_id = <1>;
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phy_address = <2>;
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};
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port@1 {
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port_id = <2>;
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phy_address = <1>;
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};
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};
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};
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};
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/* EDMA host driver configuration for the board */
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edma@3ab00000 {
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qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */
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qcom,txdesc-rings = <12>; /* Total number of Tx desc rings to be provisioned */
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qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */
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qcom,txcmpl-rings = <12>; /* Total number of Tx complete rings to be provisioned */
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qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */
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qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */
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qcom,rxdesc-ring-start = <12>; /* Rx desc ring start ID */
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qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */
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qcom,rx-page-mode = <0>; /* Rx fill ring page mode */
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qcom,tx-map-priority-level = <1>; /* Tx priority level per port */
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qcom,rx-map-priority-level = <1>; /* Rx priority level per core */
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qcom,ppeds-num = <2>; /* Number of PPEDS nodes */
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/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
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qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node#0 ring and queue map */
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<2 2 2 2 40 8>; /* PPEDS Node#1 ring and queue map */
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qcom,txdesc-map = <8 9 10 11>, /* Port0 per-core Tx ring map */
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<12 13 14 15>, /* Port1 per-core Tx ring map */
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<4 5 6 7>; /* used only for packets from vp*/
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qcom,txdesc-fc-grp-map = <1 2>; /* Per GMAC flow control group map */
|
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qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */
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qcom,rxdesc-map = <12 13 14 15>; /* Per-core Rx desc ring map */
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qcom,rx-queue-start = <0>; /* Rx queue start */
|
||||
qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */
|
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<1 9 17 25>, /* Priority 1 queues per-core Rx ring map */
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<2 10 18 26>, /* Priority 2 queues per-core Rx ring map */
|
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<3 11 19 27>, /* Priority 3 queues per-core Rx ring map */
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<4 12 20 28>, /* Priority 4 queues per-core Rx ring map */
|
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<5 13 21 29>, /* Priority 5 queues per-core Rx ring map */
|
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<6 14 22 30>, /* Priority 6 queues per-core Rx ring map */
|
||||
<7 15 23 31>; /* Priority 7 queues per-core Rx ring map */
|
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interrupts = <0 163 4>, /* Tx complete ring id #4 IRQ info */
|
||||
<0 164 4>, /* Tx complete ring id #5 IRQ info */
|
||||
<0 165 4>, /* Tx complete ring id #6 IRQ info */
|
||||
<0 166 4>, /* Tx complete ring id #7 IRQ info */
|
||||
<0 167 4>, /* Tx complete ring id #8 IRQ info */
|
||||
<0 168 4>, /* Tx complete ring id #9 IRQ info */
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||||
<0 169 4>, /* Tx complete ring id #10 IRQ info */
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||||
<0 170 4>, /* Tx complete ring id #11 IRQ info */
|
||||
<0 171 4>, /* Tx complete ring id #12 IRQ info */
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||||
<0 172 4>, /* Tx complete ring id #13 IRQ info */
|
||||
<0 173 4>, /* Tx complete ring id #14 IRQ info */
|
||||
<0 174 4>, /* Tx complete ring id #15 IRQ info */
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<0 139 4>, /* Rx desc ring id #12 IRQ info */
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<0 140 4>, /* Rx desc ring id #13 IRQ info */
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<0 141 4>, /* Rx desc ring id #14 IRQ info */
|
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<0 142 4>, /* Rx desc ring id #15 IRQ info */
|
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<0 191 4>, /* Misc error IRQ info */
|
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<0 160 4>, /* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
|
||||
<0 128 4>, /* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
|
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<0 152 4>, /* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
|
||||
<0 161 4>, /* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
|
||||
<0 129 4>, /* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
|
||||
<0 153 4>; /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
|
||||
};
|
||||
|
||||
serial@78af000 {
|
||||
pinctrl-0 = <&serial_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
serial@78b0000 {
|
||||
pinctrl-0 = <&serial_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
spi_2: spi@78b7000 {
|
||||
pinctrl-0 = <&spi_2_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-select = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c_1: i2c@78b6000 {
|
||||
pinctrl-0 = <&i2c_1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
dma@7984000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand: nand@79b0000 {
|
||||
pinctrl-0 = <&qspi_nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
spi@78b5000 {
|
||||
pinctrl-0 = <&spi_0_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-select = <0>;
|
||||
status = "ok";
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "mx25u12835f";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3@8A00000 {
|
||||
status = "ok";
|
||||
qcom,multiplexed-phy;
|
||||
};
|
||||
|
||||
ssuniphy_0: ssuniphy@4b0000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
hs_m31phy_0: hs_m31phy@7b000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
pcie1_phy_x2: phy_x2@4b1000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
button@1 {
|
||||
label = "rst";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
|
||||
linux,input-type = <1>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
};
|
||||
|
||||
wsi: wsi {
|
||||
id = <0>;
|
||||
num_chip = <2>;
|
||||
};
|
||||
|
||||
pcie1: pcie@18000000 {
|
||||
status = "ok";
|
||||
pcie1_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
|
||||
qcom,mhi@1 {
|
||||
reg = <0 0 0 0 0>;
|
||||
qti,disable-rddm-prealloc;
|
||||
qti,rddm-seg-len = <0x1000>;
|
||||
#if defined(__CNSS2__)
|
||||
qrtr_node_id = <0x31>;
|
||||
memory-region = <0>, <&mhi_region1>;
|
||||
#else
|
||||
memory-region = <&qcn9224_pcie1>;
|
||||
qcom,board_id = <0x1019>;
|
||||
qcom,wsi = <&wsi>;
|
||||
#endif
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
qcom,rproc = <&q6_wcss_pd1>;
|
||||
qcom,rproc_rpd = <&q6v5_wcss>;
|
||||
qcom,multipd_arch;
|
||||
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
|
||||
#if defined(__CNSS2__)
|
||||
mem-region = <&q6_region>;
|
||||
#else
|
||||
memory-region = <&q6_region>;
|
||||
qcom,wsi = <&wsi>;
|
||||
#endif
|
||||
qcom,board_id = <0x16>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&mhi_region1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&qcn9224_pcie1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QCN9224 5G+6G */
|
||||
&wifi2 {
|
||||
hremote_node = <&qcn9224_pcie1>;
|
||||
board_id = <0x1019>;
|
||||
status = "ok";
|
||||
};
|
||||
569
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/realtek.c
Executable file
569
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/realtek.c
Executable file
@@ -0,0 +1,569 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* drivers/net/phy/realtek.c
|
||||
*
|
||||
* Driver for Realtek PHYs
|
||||
*
|
||||
* Author: Johnson Leung <r58129@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2004 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#define RTL821x_PHYSR 0x11
|
||||
#define RTL821x_PHYSR_DUPLEX BIT(13)
|
||||
#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
|
||||
|
||||
#define RTL821x_INER 0x12
|
||||
#define RTL8211B_INER_INIT 0x6400
|
||||
#define RTL8211E_INER_LINK_STATUS BIT(10)
|
||||
#define RTL8211F_INER_LINK_STATUS BIT(4)
|
||||
|
||||
#define RTL821x_INSR 0x13
|
||||
|
||||
#define RTL821x_EXT_PAGE_SELECT 0x1e
|
||||
#define RTL821x_PAGE_SELECT 0x1f
|
||||
|
||||
#define RTL8211F_INSR 0x1d
|
||||
|
||||
#define RTL8211F_TX_DELAY BIT(8)
|
||||
#define RTL8211E_TX_DELAY BIT(1)
|
||||
#define RTL8211E_RX_DELAY BIT(2)
|
||||
#define RTL8211E_MODE_MII_GMII BIT(3)
|
||||
|
||||
#define RTL8201F_ISR 0x1e
|
||||
#define RTL8201F_IER 0x13
|
||||
|
||||
#define RTL8366RB_POWER_SAVE 0x15
|
||||
#define RTL8366RB_POWER_SAVE_ON BIT(12)
|
||||
|
||||
#define RTL_SUPPORTS_5000FULL BIT(14)
|
||||
#define RTL_SUPPORTS_2500FULL BIT(13)
|
||||
#define RTL_SUPPORTS_10000FULL BIT(0)
|
||||
#define RTL_ADV_2500FULL BIT(7)
|
||||
#define RTL_LPADV_10000FULL BIT(11)
|
||||
#define RTL_LPADV_5000FULL BIT(6)
|
||||
#define RTL_LPADV_2500FULL BIT(5)
|
||||
|
||||
#define RTL_GENERIC_PHYID 0x001cc800
|
||||
|
||||
MODULE_DESCRIPTION("Realtek PHY driver");
|
||||
MODULE_AUTHOR("Johnson Leung");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
static int rtl821x_read_page(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_read(phydev, RTL821x_PAGE_SELECT);
|
||||
}
|
||||
|
||||
static int rtl821x_write_page(struct phy_device *phydev, int page)
|
||||
{
|
||||
return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
|
||||
}
|
||||
|
||||
static int rtl8201_ack_interrupt(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = phy_read(phydev, RTL8201F_ISR);
|
||||
|
||||
return (err < 0) ? err : 0;
|
||||
}
|
||||
|
||||
static int rtl821x_ack_interrupt(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = phy_read(phydev, RTL821x_INSR);
|
||||
|
||||
return (err < 0) ? err : 0;
|
||||
}
|
||||
|
||||
static int rtl8211f_ack_interrupt(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
|
||||
|
||||
return (err < 0) ? err : 0;
|
||||
}
|
||||
|
||||
static int rtl8201_config_intr(struct phy_device *phydev)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
val = BIT(13) | BIT(12) | BIT(11);
|
||||
else
|
||||
val = 0;
|
||||
|
||||
return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
|
||||
}
|
||||
|
||||
static int rtl8211b_config_intr(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
err = phy_write(phydev, RTL821x_INER,
|
||||
RTL8211B_INER_INIT);
|
||||
else
|
||||
err = phy_write(phydev, RTL821x_INER, 0);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rtl8211e_config_intr(struct phy_device *phydev)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
err = phy_write(phydev, RTL821x_INER,
|
||||
RTL8211E_INER_LINK_STATUS);
|
||||
else
|
||||
err = phy_write(phydev, RTL821x_INER, 0);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rtl8211f_config_intr(struct phy_device *phydev)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
||||
val = RTL8211F_INER_LINK_STATUS;
|
||||
else
|
||||
val = 0;
|
||||
|
||||
return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
|
||||
}
|
||||
|
||||
static int rtl8211_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = genphy_config_aneg(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Quirk was copied from vendor driver. Unfortunately it includes no
|
||||
* description of the magic numbers.
|
||||
*/
|
||||
if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
|
||||
phy_write(phydev, 0x17, 0x2138);
|
||||
phy_write(phydev, 0x0e, 0x0260);
|
||||
} else {
|
||||
phy_write(phydev, 0x17, 0x2108);
|
||||
phy_write(phydev, 0x0e, 0x0000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8211c_config_init(struct phy_device *phydev)
|
||||
{
|
||||
/* RTL8211C has an issue when operating in Gigabit slave mode */
|
||||
return phy_set_bits(phydev, MII_CTRL1000,
|
||||
CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
|
||||
}
|
||||
|
||||
static int rtl8211f_config_init(struct phy_device *phydev)
|
||||
{
|
||||
struct device *dev = &phydev->mdio.dev;
|
||||
u16 val;
|
||||
int ret;
|
||||
|
||||
printk(" RTL8211F Init !!! \n");
|
||||
/* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and
|
||||
* rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin.
|
||||
*/
|
||||
switch (phydev->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
val = 0;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
val = RTL8211F_TX_DELAY;
|
||||
break;
|
||||
default: /* the rest of the modes imply leaving delay as is. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
|
||||
val);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to update the TX delay register\n");
|
||||
return ret;
|
||||
} else if (ret) {
|
||||
dev_dbg(dev,
|
||||
"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
|
||||
val ? "Enabling" : "Disabling");
|
||||
} else {
|
||||
dev_dbg(dev,
|
||||
"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
|
||||
val ? "enabled" : "disabled");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8211e_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret = 0, oldpage;
|
||||
u16 val;
|
||||
|
||||
/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
|
||||
switch (phydev->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val = 0;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
val = RTL8211E_RX_DELAY;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
val = RTL8211E_TX_DELAY;
|
||||
break;
|
||||
default: /* the rest of the modes imply leaving delays as is. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* According to a sample driver there is a 0x1c config register on the
|
||||
* 0xa4 extension page (0x7) layout. It can be used to disable/enable
|
||||
* the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
|
||||
* also be used to customize the whole configuration register:
|
||||
* 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
|
||||
* 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
|
||||
* for details).
|
||||
*/
|
||||
oldpage = phy_select_page(phydev, 0x7);
|
||||
if (oldpage < 0)
|
||||
goto err_restore_page;
|
||||
|
||||
ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
|
||||
if (ret)
|
||||
goto err_restore_page;
|
||||
|
||||
ret = __phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
|
||||
val);
|
||||
|
||||
err_restore_page:
|
||||
return phy_restore_page(phydev, oldpage, ret);
|
||||
}
|
||||
|
||||
static int rtl8211b_suspend(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MII_MMD_DATA, BIT(9));
|
||||
|
||||
return genphy_suspend(phydev);
|
||||
}
|
||||
|
||||
static int rtl8211b_resume(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MII_MMD_DATA, 0);
|
||||
|
||||
return genphy_resume(phydev);
|
||||
}
|
||||
|
||||
static int rtl8366rb_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
|
||||
RTL8366RB_POWER_SAVE_ON);
|
||||
if (ret) {
|
||||
dev_err(&phydev->mdio.dev,
|
||||
"error enabling power management\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
|
||||
rtl821x_write_page(phydev, 0xa5c);
|
||||
ret = __phy_read(phydev, 0x12);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
|
||||
rtl821x_write_page(phydev, 0xa5d);
|
||||
ret = __phy_read(phydev, 0x10);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
|
||||
rtl821x_write_page(phydev, 0xa5d);
|
||||
ret = __phy_read(phydev, 0x11);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else {
|
||||
ret = -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
|
||||
u16 val)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
|
||||
rtl821x_write_page(phydev, 0xa5d);
|
||||
ret = __phy_write(phydev, 0x10, val);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else {
|
||||
ret = -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl8125_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
|
||||
{
|
||||
int ret = rtlgen_read_mmd(phydev, devnum, regnum);
|
||||
|
||||
if (ret != -EOPNOTSUPP)
|
||||
return ret;
|
||||
|
||||
if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
|
||||
rtl821x_write_page(phydev, 0xa6e);
|
||||
ret = __phy_read(phydev, 0x16);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
|
||||
rtl821x_write_page(phydev, 0xa6d);
|
||||
ret = __phy_read(phydev, 0x12);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
|
||||
rtl821x_write_page(phydev, 0xa6d);
|
||||
ret = __phy_read(phydev, 0x10);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl8125_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
|
||||
u16 val)
|
||||
{
|
||||
int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
|
||||
|
||||
if (ret != -EOPNOTSUPP)
|
||||
return ret;
|
||||
|
||||
if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
|
||||
rtl821x_write_page(phydev, 0xa6d);
|
||||
ret = __phy_write(phydev, 0x12, val);
|
||||
rtl821x_write_page(phydev, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl8125_get_features(struct phy_device *phydev)
|
||||
{
|
||||
int val;
|
||||
|
||||
val = phy_read_paged(phydev, 0xa61, 0x13);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||
phydev->supported, val & RTL_SUPPORTS_2500FULL);
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
|
||||
phydev->supported, val & RTL_SUPPORTS_5000FULL);
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
|
||||
phydev->supported, val & RTL_SUPPORTS_10000FULL);
|
||||
|
||||
return genphy_read_abilities(phydev);
|
||||
}
|
||||
|
||||
static int rtl8125_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (phydev->autoneg == AUTONEG_ENABLE) {
|
||||
u16 adv2500 = 0;
|
||||
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||
phydev->advertising))
|
||||
adv2500 = RTL_ADV_2500FULL;
|
||||
|
||||
ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
|
||||
RTL_ADV_2500FULL, adv2500);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return __genphy_config_aneg(phydev, ret);
|
||||
}
|
||||
|
||||
static int rtl8125_read_status(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->autoneg == AUTONEG_ENABLE) {
|
||||
int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
|
||||
|
||||
if (lpadv < 0)
|
||||
return lpadv;
|
||||
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
|
||||
phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
|
||||
phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||
phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
|
||||
}
|
||||
|
||||
return genphy_read_status(phydev);
|
||||
}
|
||||
|
||||
static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
|
||||
{
|
||||
int val;
|
||||
|
||||
phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
|
||||
val = phy_read(phydev, 0x13);
|
||||
phy_write(phydev, RTL821x_PAGE_SELECT, 0);
|
||||
|
||||
return val >= 0 && val & RTL_SUPPORTS_2500FULL;
|
||||
}
|
||||
|
||||
static int rtlgen_match_phy_device(struct phy_device *phydev)
|
||||
{
|
||||
return phydev->phy_id == RTL_GENERIC_PHYID &&
|
||||
!rtlgen_supports_2_5gbps(phydev);
|
||||
}
|
||||
|
||||
static int rtl8125_match_phy_device(struct phy_device *phydev)
|
||||
{
|
||||
return phydev->phy_id == RTL_GENERIC_PHYID &&
|
||||
rtlgen_supports_2_5gbps(phydev);
|
||||
}
|
||||
|
||||
static struct phy_driver realtek_drvs[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(0x00008201),
|
||||
.name = "RTL8201CP Ethernet",
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc816),
|
||||
.name = "RTL8201F Fast Ethernet",
|
||||
.ack_interrupt = &rtl8201_ack_interrupt,
|
||||
.config_intr = &rtl8201_config_intr,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_MODEL(0x001cc880),
|
||||
.name = "RTL8208 Fast Ethernet",
|
||||
.read_mmd = genphy_read_mmd_unsupported,
|
||||
.write_mmd = genphy_write_mmd_unsupported,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc910),
|
||||
.name = "RTL8211 Gigabit Ethernet",
|
||||
.config_aneg = rtl8211_config_aneg,
|
||||
.read_mmd = &genphy_read_mmd_unsupported,
|
||||
.write_mmd = &genphy_write_mmd_unsupported,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc912),
|
||||
.name = "RTL8211B Gigabit Ethernet",
|
||||
.ack_interrupt = &rtl821x_ack_interrupt,
|
||||
.config_intr = &rtl8211b_config_intr,
|
||||
.read_mmd = &genphy_read_mmd_unsupported,
|
||||
.write_mmd = &genphy_write_mmd_unsupported,
|
||||
.suspend = rtl8211b_suspend,
|
||||
.resume = rtl8211b_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc913),
|
||||
.name = "RTL8211C Gigabit Ethernet",
|
||||
.config_init = rtl8211c_config_init,
|
||||
.read_mmd = &genphy_read_mmd_unsupported,
|
||||
.write_mmd = &genphy_write_mmd_unsupported,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc914),
|
||||
.name = "RTL8211DN Gigabit Ethernet",
|
||||
.ack_interrupt = rtl821x_ack_interrupt,
|
||||
.config_intr = rtl8211e_config_intr,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc915),
|
||||
.name = "RTL8211E Gigabit Ethernet",
|
||||
.config_init = &rtl8211e_config_init,
|
||||
.ack_interrupt = &rtl821x_ack_interrupt,
|
||||
.config_intr = &rtl8211e_config_intr,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc916),
|
||||
.name = "RTL8211F Gigabit Ethernet",
|
||||
.config_init = &rtl8211f_config_init,
|
||||
.ack_interrupt = &rtl8211f_ack_interrupt,
|
||||
.config_intr = &rtl8211f_config_intr,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
}, {
|
||||
.name = "Generic FE-GE Realtek PHY",
|
||||
.match_phy_device = rtlgen_match_phy_device,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
.read_mmd = rtlgen_read_mmd,
|
||||
.write_mmd = rtlgen_write_mmd,
|
||||
}, {
|
||||
.name = "RTL8125 2.5Gbps internal",
|
||||
.match_phy_device = rtl8125_match_phy_device,
|
||||
.get_features = rtl8125_get_features,
|
||||
.config_aneg = rtl8125_config_aneg,
|
||||
.read_status = rtl8125_read_status,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = rtl821x_read_page,
|
||||
.write_page = rtl821x_write_page,
|
||||
.read_mmd = rtl8125_read_mmd,
|
||||
.write_mmd = rtl8125_write_mmd,
|
||||
}, {
|
||||
PHY_ID_MATCH_EXACT(0x001cc961),
|
||||
.name = "RTL8366RB Gigabit Ethernet",
|
||||
.config_init = &rtl8366rb_config_init,
|
||||
/* These interrupts are handled by the irq controller
|
||||
* embedded inside the RTL8366RB, they get unmasked when the
|
||||
* irq is requested and ACKed by reading the status register,
|
||||
* which is done by the irqchip code.
|
||||
*/
|
||||
.ack_interrupt = genphy_no_ack_interrupt,
|
||||
.config_intr = genphy_no_config_intr,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
},
|
||||
};
|
||||
|
||||
module_phy_driver(realtek_drvs);
|
||||
|
||||
static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
|
||||
{ PHY_ID_MATCH_VENDOR(0x001cc800) },
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(mdio, realtek_tbl);
|
||||
10
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/Kconfig
Executable file
10
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/Kconfig
Executable file
@@ -0,0 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
#
|
||||
|
||||
config RTK_MSSDK_PHY
|
||||
tristate "Realtek MSSDK PHYs"
|
||||
help
|
||||
Currently supports the RTL8261N,RTL8264B,RTL8251B PHYs.
|
||||
|
||||
19
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/Makefile
Executable file
19
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/Makefile
Executable file
@@ -0,0 +1,19 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
#
|
||||
|
||||
ccflags-y := -DRTK_PHYDRV_IN_LINUX
|
||||
obj-$(CONFIG_RTK_MSSDK_PHY) += rtk-ms-phy.o
|
||||
|
||||
rtk-ms-phy-objs := rtk_phy.o
|
||||
rtk-ms-phy-objs += rtk_osal.o
|
||||
|
||||
# files from SDK
|
||||
rtk-ms-phy-objs += phy_patch.o
|
||||
rtk-ms-phy-objs += phy_rtl826xb_patch.o
|
||||
rtk-ms-phy-objs += phy_rtl8251b_patch.o
|
||||
|
||||
# rtk phylib
|
||||
rtk-ms-phy-objs += rtk_phylib.o
|
||||
rtk-ms-phy-objs += rtk_phylib_rtl826xb.o
|
||||
1465
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/construct/conf_rtl8261n_c.c
Executable file
1465
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/construct/conf_rtl8261n_c.c
Executable file
File diff suppressed because it is too large
Load Diff
2177
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/construct/conf_rtl8264b.c
Executable file
2177
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/construct/conf_rtl8264b.c
Executable file
File diff suppressed because it is too large
Load Diff
165
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/error.h
Executable file
165
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/error.h
Executable file
@@ -0,0 +1,165 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ERROR_H__
|
||||
#define __COMMON_ERROR_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "type.h"
|
||||
#else
|
||||
#include <common/type.h>
|
||||
#endif
|
||||
/*
|
||||
* Data Type Declaration
|
||||
*/
|
||||
typedef enum rt_error_common_e
|
||||
{
|
||||
RT_ERR_FAILED = -1, /* General Error */
|
||||
|
||||
/* 0x0000xxxx for common error code */
|
||||
RT_ERR_OK = 0, /* 0x00000000, OK */
|
||||
RT_ERR_INPUT = 0xF001, /* 0x0000F001, invalid input parameter */
|
||||
RT_ERR_UNIT_ID, /* 0x0000F002, invalid unit id */
|
||||
RT_ERR_PORT_ID, /* 0x0000F003, invalid port id */
|
||||
RT_ERR_PORT_MASK, /* 0x0000F004, invalid port mask */
|
||||
RT_ERR_PORT_LINKDOWN, /* 0x0000F005, link down port status */
|
||||
RT_ERR_ENTRY_INDEX, /* 0x0000F006, invalid entry index */
|
||||
RT_ERR_NULL_POINTER, /* 0x0000F007, input parameter is null pointer */
|
||||
RT_ERR_QUEUE_ID, /* 0x0000F008, invalid queue id */
|
||||
RT_ERR_QUEUE_NUM, /* 0x0000F009, invalid queue number */
|
||||
RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000F00a, busy watting time out */
|
||||
RT_ERR_MAC, /* 0x0000F00b, invalid mac address */
|
||||
RT_ERR_OUT_OF_RANGE, /* 0x0000F00c, input parameter out of range */
|
||||
RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000F00d, functions not supported by this chip model */
|
||||
RT_ERR_SMI, /* 0x0000F00e, SMI error */
|
||||
RT_ERR_NOT_INIT, /* 0x0000F00f, The module is not initial */
|
||||
RT_ERR_CHIP_NOT_FOUND, /* 0x0000F010, The chip can not found */
|
||||
RT_ERR_NOT_ALLOWED, /* 0x0000F011, actions not allowed by the function */
|
||||
RT_ERR_DRIVER_NOT_FOUND, /* 0x0000F012, The driver can not found */
|
||||
RT_ERR_SEM_LOCK_FAILED, /* 0x0000F013, Failed to lock semaphore */
|
||||
RT_ERR_SEM_UNLOCK_FAILED, /* 0x0000F014, Failed to unlock semaphore */
|
||||
RT_ERR_THREAD_EXIST, /* 0x0000F015, Thread exist */
|
||||
RT_ERR_THREAD_CREATE_FAILED, /* 0x0000F016, Thread create fail */
|
||||
RT_ERR_FWD_ACTION, /* 0x0000F017, Invalid forwarding Action */
|
||||
RT_ERR_IPV4_ADDRESS, /* 0x0000F018, Invalid IPv4 address */
|
||||
RT_ERR_IPV6_ADDRESS, /* 0x0000F019, Invalid IPv6 address */
|
||||
RT_ERR_PRIORITY, /* 0x0000F01a, Invalid Priority value */
|
||||
RT_ERR_FID, /* 0x0000F01b, invalid fid */
|
||||
RT_ERR_ENTRY_NOTFOUND, /* 0x0000F01c, specified entry not found */
|
||||
RT_ERR_DROP_PRECEDENCE, /* 0x0000F01d, invalid drop precedence */
|
||||
RT_ERR_NOT_FINISH, /* 0x0000F01e, Action not finish, still need to wait */
|
||||
RT_ERR_TIMEOUT, /* 0x0000F01f, Time out */
|
||||
RT_ERR_REG_ARRAY_INDEX_1, /* 0x0000F020, invalid index 1 of register array */
|
||||
RT_ERR_REG_ARRAY_INDEX_2, /* 0x0000F021, invalid index 2 of register array */
|
||||
RT_ERR_ETHER_TYPE, /* 0x0000F022, invalid ether type */
|
||||
RT_ERR_MBUF_PKT_NOT_AVAILABLE, /* 0x0000F023, mbuf->packet is not available */
|
||||
RT_ERR_QOS_INVLD_RSN, /* 0x0000F024, invalid pkt to CPU reason */
|
||||
RT_ERR_CB_FUNCTION_EXIST, /* 0x0000F025, Callback function exist */
|
||||
RT_ERR_CB_FUNCTION_FULL, /* 0x0000F026, Callback function number is full */
|
||||
RT_ERR_CB_FUNCTION_NOT_FOUND, /* 0x0000F027, Callback function can not found */
|
||||
RT_ERR_TBL_FULL, /* 0x0000F028, The table is full */
|
||||
RT_ERR_TRUNK_ID, /* 0x0000F029, invalid trunk id */
|
||||
RT_ERR_TYPE, /* 0x0000F02a, invalid type */
|
||||
RT_ERR_ENTRY_EXIST, /* 0x0000F02b, entry exists */
|
||||
RT_ERR_CHIP_UNDEFINED_VALUE, /* 0x0000F02c, chip returned an undefined value */
|
||||
RT_ERR_EXCEEDS_CAPACITY, /* 0x0000F02d, exceeds the capacity of hardware */
|
||||
RT_ERR_ENTRY_REFERRED, /* 0x0000F02e, entry is still being referred */
|
||||
RT_ERR_OPER_DENIED, /* 0x0000F02f, operation denied */
|
||||
RT_ERR_PORT_NOT_SUPPORTED, /* 0x0000F030, functions not supported by this port */
|
||||
RT_ERR_SOCKET, /* 0x0000F031, socket error */
|
||||
RT_ERR_MEM_ALLOC, /* 0x0000F032, insufficient memory resource */
|
||||
RT_ERR_ABORT, /* 0x0000F033, operation aborted */
|
||||
RT_ERR_DEV_ID, /* 0x0000F034, invalid device id */
|
||||
RT_ERR_DRIVER_NOT_SUPPORTED, /* 0x0000F035, functions not supported by this driver */
|
||||
RT_ERR_NOT_SUPPORTED, /* 0x0000F036, functions not supported */
|
||||
RT_ERR_SER, /* 0x0000F037, ECC or parity error */
|
||||
RT_ERR_MEM_NOT_ALIGN, /* 0x0000F038, memory address is not aligned */
|
||||
RT_ERR_SEM_FAKELOCK_OK, /* 0x0000F039, attach thread lock a semaphore which was already locked */
|
||||
RT_ERR_CHECK_FAILED, /* 0x0000F03a, check result is failed */
|
||||
|
||||
RT_ERR_COMMON_END = 0xFFFF /* The symbol is the latest symbol of common error */
|
||||
} rt_error_common_t;
|
||||
|
||||
/*
|
||||
* Macro Definition
|
||||
*/
|
||||
#define RT_PARAM_CHK(expr, errCode)\
|
||||
do {\
|
||||
if ((int32)(expr)) {\
|
||||
return errCode; \
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_PARAM_CHK_EHDL(expr, errCode, err_hdl)\
|
||||
do {\
|
||||
if ((int32)(expr)) {\
|
||||
{err_hdl}\
|
||||
return errCode; \
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_INIT_CHK(state)\
|
||||
do {\
|
||||
if (INIT_COMPLETED != (state)) {\
|
||||
return RT_ERR_NOT_INIT;\
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_INIT_REENTRY_CHK(state)\
|
||||
do {\
|
||||
if (INIT_COMPLETED == (state)) {\
|
||||
osal_printf(" %s had already been initialized!\n", __FUNCTION__);\
|
||||
return RT_ERR_OK;\
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_INIT_REENTRY_CHK_NO_WARNING(state)\
|
||||
do {\
|
||||
if (INIT_COMPLETED == (state)) {\
|
||||
return RT_ERR_OK;\
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_ERR_CHK(op, ret)\
|
||||
do {\
|
||||
if ((ret = (op)) != RT_ERR_OK)\
|
||||
return ret;\
|
||||
} while(0)
|
||||
|
||||
#define RT_ERR_HDL(op, errHandle, ret)\
|
||||
do {\
|
||||
if ((ret = (op)) != RT_ERR_OK)\
|
||||
goto errHandle;\
|
||||
} while(0)
|
||||
|
||||
#define RT_ERR_CHK_EHDL(op, ret, err_hdl)\
|
||||
do {\
|
||||
if ((ret = (op)) != RT_ERR_OK)\
|
||||
{\
|
||||
{err_hdl}\
|
||||
return ret;\
|
||||
}\
|
||||
} while(0)
|
||||
|
||||
#define RT_NULL_HDL(pointer, err_label)\
|
||||
do {\
|
||||
if (NULL == (pointer)) {\
|
||||
goto err_label;\
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
#define RT_ERR_VOID_CHK(op, ret)\
|
||||
do {\
|
||||
if ((ret = (op)) != RT_ERR_OK) {\
|
||||
osal_printf("Fail in %s %d, ret %x!\n", __FUNCTION__, __LINE__, ret);\
|
||||
return ;}\
|
||||
} while(0)
|
||||
|
||||
#endif /* __COMMON_ERROR_H__ */
|
||||
|
||||
179
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_patch.c
Executable file
179
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_patch.c
Executable file
@@ -0,0 +1,179 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "rtk_osal.h"
|
||||
#else
|
||||
#include <common/rt_type.h>
|
||||
#include <common/rt_error.h>
|
||||
#include <common/debug/rt_log.h>
|
||||
#include <hal/common/halctrl.h>
|
||||
#include <hal/phy/phy_patch.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Function Declaration
|
||||
*/
|
||||
uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op)
|
||||
{
|
||||
if (patch_mode != PHY_PATCH_MODE_CMP)
|
||||
{
|
||||
return patch_op;
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (compare_op)
|
||||
{
|
||||
case RTK_PATCH_CMP_WS:
|
||||
return RTK_PATCH_OP_SKIP;
|
||||
case RTK_PATCH_CMP_W:
|
||||
case RTK_PATCH_CMP_WC:
|
||||
case RTK_PATCH_CMP_SWC:
|
||||
default:
|
||||
return RTK_PATCH_OP_TO_CMP(patch_op, compare_op);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data, uint8 patch_mode)
|
||||
{
|
||||
rtk_hwpatch_t op;
|
||||
|
||||
op.patch_op = patch_op;
|
||||
op.portmask = portmask;
|
||||
op.pagemmd = pagemmd;
|
||||
op.addr = addr;
|
||||
op.msb = msb;
|
||||
op.lsb = lsb;
|
||||
op.data = data;
|
||||
op.compare_op = RTK_PATCH_CMP_W;
|
||||
|
||||
return pPhy_patchDb->fPatch_op(unit, port, portOffset, &op, patch_mode);
|
||||
}
|
||||
|
||||
static int32 _phy_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch, int32 size, uint8 patch_mode)
|
||||
{
|
||||
int32 i = 0;
|
||||
int32 ret = 0;
|
||||
int32 chk_ret = RT_ERR_OK;
|
||||
int32 n;
|
||||
rtk_hwpatch_t *patch = pPatch;
|
||||
rt_phy_patch_db_t *pPatchDb = NULL;
|
||||
|
||||
PHYPATCH_DB_GET(unit, port, pPatchDb);
|
||||
|
||||
if (size <= 0)
|
||||
{
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
n = size / sizeof(rtk_hwpatch_t);
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
{
|
||||
ret = pPatchDb->fPatch_op(unit, port, portOffset, &patch[i], patch_mode);
|
||||
if ((ret != RT_ERR_ABORT) && (ret != RT_ERR_OK))
|
||||
{
|
||||
if ((ret == RT_ERR_CHECK_FAILED) && (patch_mode == PHY_PATCH_MODE_CMP))
|
||||
{
|
||||
osal_printf("PATCH CHECK: Failed entry:%u|%u|0x%X|0x%X|%u|%u|0x%X\n",
|
||||
i + 1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].msb, patch[i].lsb, patch[i].data);
|
||||
chk_ret = RT_ERR_CHECK_FAILED;
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u %s failed! %u[%u][0x%X][0x%X][0x%X] ret=0x%X\n", unit, port, __FUNCTION__,
|
||||
i+1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].data, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
|
||||
}
|
||||
|
||||
/* Function Name:
|
||||
* phy_patch
|
||||
* Description:
|
||||
* apply initial patch data to PHY
|
||||
* Input:
|
||||
* unit - unit id
|
||||
* port - port id
|
||||
* portOffset - the index offset of port based the base port in the PHY chip
|
||||
* Output:
|
||||
* None
|
||||
* Return:
|
||||
* RT_ERR_OK
|
||||
* RT_ERR_FAILED
|
||||
* RT_ERR_CHECK_FAILED
|
||||
* RT_ERR_NOT_SUPPORTED
|
||||
* Note:
|
||||
* None
|
||||
*/
|
||||
int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
|
||||
{
|
||||
int32 ret = RT_ERR_OK;
|
||||
int32 chk_ret = RT_ERR_OK;
|
||||
uint32 i = 0;
|
||||
uint8 patch_type = 0;
|
||||
rt_phy_patch_db_t *pPatchDb = NULL;
|
||||
rtk_hwpatch_seq_t *table = NULL;
|
||||
|
||||
PHYPATCH_DB_GET(unit, port, pPatchDb);
|
||||
|
||||
if ((pPatchDb == NULL) || (pPatchDb->fPatch_op == NULL) || (pPatchDb->fPatch_flow == NULL))
|
||||
{
|
||||
RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u phy_patch, db is NULL\n", unit, port);
|
||||
return RT_ERR_DRIVER_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if (patch_mode == PHY_PATCH_MODE_CMP)
|
||||
{
|
||||
table = pPatchDb->cmp_table;
|
||||
}
|
||||
else
|
||||
{
|
||||
table = pPatchDb->seq_table;
|
||||
}
|
||||
RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: U%u P%u portOffset:%u patch_mode:%u\n", unit, port, portOffset, patch_mode);
|
||||
|
||||
for (i = 0; i < RTK_PATCH_SEQ_MAX; i++)
|
||||
{
|
||||
patch_type = table[i].patch_type;
|
||||
RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: table[%u] patch_type:%u\n", i, patch_type);
|
||||
|
||||
if (RTK_PATCH_TYPE_IS_DATA(patch_type))
|
||||
{
|
||||
ret = _phy_patch_process(unit, port, portOffset, table[i].patch.data.conf, table[i].patch.data.size, patch_mode);
|
||||
|
||||
if (ret == RT_ERR_CHECK_FAILED)
|
||||
chk_ret = ret;
|
||||
else if (ret != RT_ERR_OK)
|
||||
{
|
||||
RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
else if (RTK_PATCH_TYPE_IS_FLOW(patch_type))
|
||||
{
|
||||
RT_ERR_CHK_EHDL(pPatchDb->fPatch_flow(unit, port, portOffset, table[i].patch.flow_id, patch_mode),
|
||||
ret, RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret););
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
174
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_patch.h
Executable file
174
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_patch.h
Executable file
@@ -0,0 +1,174 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __HAL_PHY_PATCH_H__
|
||||
#define __HAL_PHY_PATCH_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "rtk_phylib_def.h"
|
||||
#else
|
||||
#include <common/rt_type.h>
|
||||
#include <common/rt_autoconf.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Symbol Definition
|
||||
*/
|
||||
#define PHYPATCH_PHYCTRL_IN_HALCTRL 0 /* 3.6.x: 1 ,4.0.x: 1, 4.1.x+: 0 */
|
||||
#define PHYPATCH_FMAILY_IN_HWP 0 /* 3.6.x: 1 ,4.0.x: 0, 4.1.x+: 0 */
|
||||
#define PHY_PATCH_MODE_BCAST_DEFAULT PHY_PATCH_MODE_BCAST /* 3.6.x: PHY_PATCH_MODE_BCAST_BUS ,4.0.x+: PHY_PATCH_MODE_BCAST */
|
||||
|
||||
#define PHY_PATCH_MODE_NORMAL 0
|
||||
#define PHY_PATCH_MODE_CMP 1
|
||||
#define PHY_PATCH_MODE_BCAST 2
|
||||
#define PHY_PATCH_MODE_BCAST_BUS 3
|
||||
|
||||
#define RTK_PATCH_CMP_W 0 /* write */
|
||||
#define RTK_PATCH_CMP_WC 1 /* compare */
|
||||
#define RTK_PATCH_CMP_SWC 2 /* sram compare */
|
||||
#define RTK_PATCH_CMP_WS 3 /* skip */
|
||||
|
||||
#define RTK_PATCH_OP_SECTION_SIZE 50
|
||||
#define RTK_PATCH_OP_TO_CMP(_op, _cmp) (_op + (RTK_PATCH_OP_SECTION_SIZE * _cmp))
|
||||
/* 0~49 normal op */
|
||||
#define RTK_PATCH_OP_PHY 0
|
||||
#define RTK_PATCH_OP_PHYOCP 1
|
||||
#define RTK_PATCH_OP_TOP 2
|
||||
#define RTK_PATCH_OP_TOPOCP 3
|
||||
#define RTK_PATCH_OP_PSDS0 4
|
||||
#define RTK_PATCH_OP_PSDS1 5
|
||||
#define RTK_PATCH_OP_MSDS 6
|
||||
#define RTK_PATCH_OP_MAC 7
|
||||
|
||||
/* 50~99 normal op for compare */
|
||||
#define RTK_PATCH_OP_CMP_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_WC)
|
||||
#define RTK_PATCH_OP_CMP_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_WC)
|
||||
|
||||
/* 100~149 normal op for sram compare */
|
||||
#define RTK_PATCH_OP_CMP_SRAM_PHY RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_PHYOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_TOP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_TOPOCP RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_PSDS0 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0 , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_PSDS1 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1 , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_MSDS RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS , RTK_PATCH_CMP_SWC)
|
||||
#define RTK_PATCH_OP_CMP_SRAM_MAC RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC , RTK_PATCH_CMP_SWC)
|
||||
|
||||
/* 200~255 control op */
|
||||
#define RTK_PATCH_OP_DELAY_MS 200
|
||||
#define RTK_PATCH_OP_SKIP 255
|
||||
|
||||
|
||||
/*
|
||||
patch type PHY_PATCH_TYPE_NONE => empty
|
||||
patch type: PHY_PATCH_TYPE_TOP ~ (PHY_PATCH_TYPE_END-1) => data array
|
||||
patch type: PHY_PATCH_TYPE_END ~ (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOW_MAX) => flow
|
||||
*/
|
||||
#define RTK_PATCH_TYPE_IS_DATA(_patch_type) (_patch_type > PHY_PATCH_TYPE_NONE && _patch_type < PHY_PATCH_TYPE_END)
|
||||
#define RTK_PATCH_TYPE_IS_FLOW(_patch_type) (_patch_type >= PHY_PATCH_TYPE_END && _patch_type <= (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX))
|
||||
|
||||
|
||||
/*
|
||||
* Macro Definition
|
||||
*/
|
||||
#if PHYPATCH_PHYCTRL_IN_HALCTRL
|
||||
#define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \
|
||||
do {\
|
||||
hal_control_t *pHalCtrl = NULL;\
|
||||
if ((pHalCtrl = hal_ctrlInfo_get(_unit)) == NULL)\
|
||||
return RT_ERR_FAILED;\
|
||||
_pPatchDb = (pHalCtrl->pPhy_ctrl[_port]->pPhy_patchDb);\
|
||||
} while(0)
|
||||
#else
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#else
|
||||
#include <hal/phy/phydef.h>
|
||||
#include <hal/phy/phy_probe.h>
|
||||
#endif
|
||||
#define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \
|
||||
do {\
|
||||
rt_phyctrl_t *pPhyCtrl = NULL;\
|
||||
if ((pPhyCtrl = phy_phyctrl_get(_unit, _port)) == NULL)\
|
||||
return RT_ERR_FAILED;\
|
||||
_pPatchDb = (pPhyCtrl->pPhy_patchDb);\
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
#if PHYPATCH_FMAILY_IN_HWP
|
||||
#define PHYPATCH_IS_RTKSDS(_unit) (HWP_9300_FAMILY_ID(_unit) || HWP_9310_FAMILY_ID(_unit))
|
||||
#else
|
||||
#define PHYPATCH_IS_RTKSDS(_unit) (RTK_9300_FAMILY_ID(_unit) || RTK_9310_FAMILY_ID(_unit) || RTK_9311B_FAMILY_ID(_unit) || RTK_9330_FAMILY_ID(_unit))
|
||||
#endif
|
||||
|
||||
#define PHYPATCH_TABLE_ASSIGN(_pPatchDb, _table, _idx, _patch_type, _para) \
|
||||
do {\
|
||||
if (RTK_PATCH_TYPE_IS_DATA(_patch_type)) {\
|
||||
_pPatchDb->_table[_idx].patch_type = _patch_type;\
|
||||
_pPatchDb->_table[_idx].patch.data.conf = _para;\
|
||||
_pPatchDb->_table[_idx].patch.data.size = sizeof(_para);\
|
||||
}\
|
||||
else if (RTK_PATCH_TYPE_IS_FLOW(_patch_type)) {\
|
||||
_pPatchDb->_table[_idx].patch_type = _patch_type;\
|
||||
_pPatchDb->_table[_idx].patch.flow_id = _patch_type;\
|
||||
}\
|
||||
else {\
|
||||
_pPatchDb->_table[_idx].patch_type = PHY_PATCH_TYPE_NONE;\
|
||||
}\
|
||||
} while(0)
|
||||
#define PHYPATCH_SEQ_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, seq_table, _idx, _patch_type, _para)
|
||||
#define PHYPATCH_CMP_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, cmp_table, _idx, _patch_type, _para)
|
||||
|
||||
#define PHYPATCH_COMPARE(_mmdpage, _reg, _msb, _lsb, _exp, _real, _mask) \
|
||||
do {\
|
||||
uint32 _rData = REG32_FIELD_GET(_real, _lsb, _mask);\
|
||||
if (_exp != _rData) {\
|
||||
osal_printf("PATCH CHECK: %u(0x%X).%u(0x%X)[%u:%u] = 0x%X (!= 0x%X)\n", _mmdpage, _mmdpage, _reg, _reg, _msb, _lsb, _rData, _exp);\
|
||||
return RT_ERR_CHECK_FAILED;\
|
||||
}\
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Function Declaration
|
||||
*/
|
||||
|
||||
extern uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op);
|
||||
extern int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset,
|
||||
uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data,
|
||||
uint8 patch_mode);
|
||||
|
||||
|
||||
/* Function Name:
|
||||
* phy_patch
|
||||
* Description:
|
||||
* apply initial patch data to PHY
|
||||
* Input:
|
||||
* unit - unit id
|
||||
* port - port id
|
||||
* portOffset - the index offset of port based the base port in the PHY chip
|
||||
* Output:
|
||||
* None
|
||||
* Return:
|
||||
* RT_ERR_OK
|
||||
* RT_ERR_FAILED
|
||||
* RT_ERR_CHECK_FAILED
|
||||
* RT_ERR_NOT_SUPPORTED
|
||||
* Note:
|
||||
* None
|
||||
*/
|
||||
extern int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode);
|
||||
|
||||
|
||||
|
||||
#endif /* __HAL_PHY_PATCH_H__ */
|
||||
3757
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl8251b_patch.c
Executable file
3757
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl8251b_patch.c
Executable file
File diff suppressed because it is too large
Load Diff
56
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl8251b_patch.h
Executable file
56
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl8251b_patch.h
Executable file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy.h>
|
||||
#include "type.h"
|
||||
|
||||
#ifndef __PHY_RTL8251B_PATCH_H__
|
||||
#define __PHY_RTL8251B_PATCH_H__
|
||||
|
||||
#ifndef SUCCESS
|
||||
#define SUCCESS 1
|
||||
#endif
|
||||
#ifndef FAILURE
|
||||
#define FAILURE 0
|
||||
#endif
|
||||
|
||||
#ifndef BOOL
|
||||
#define BOOL uint32
|
||||
#endif
|
||||
#ifndef UINT32
|
||||
#define UINT32 uint32
|
||||
#endif
|
||||
#ifndef UINT16
|
||||
#define UINT16 uint16
|
||||
#endif
|
||||
#ifndef UINT8
|
||||
#define UINT8 uint8
|
||||
#endif
|
||||
|
||||
#define MMD_PMAPMD 1
|
||||
#define MMD_PCS 3
|
||||
#define MMD_AN 7
|
||||
#define MMD_VEND1 30 /* Vendor specific 2 */
|
||||
#define MMD_VEND2 31 /* Vendor specific 2 */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 dev;
|
||||
UINT16 addr;
|
||||
UINT16 value;
|
||||
} MMD_REG;
|
||||
|
||||
int32 MmdPhyRead(struct phy_device *phydev,UINT16 dev,UINT16 addr,UINT16 *data);
|
||||
int32 MmdPhyWrite(struct phy_device *phydev,UINT16 dev,UINT16 addr,UINT16 data);
|
||||
|
||||
extern int32 rtl8251b_phy_init(struct phy_device *phydev);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
1032
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl826xb_patch.c
Executable file
1032
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl826xb_patch.c
Executable file
File diff suppressed because it is too large
Load Diff
63
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl826xb_patch.h
Executable file
63
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/phy_rtl826xb_patch.h
Executable file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __HAL_PHY_PHY_RTL826XB_PATCH_H__
|
||||
#define __HAL_PHY_PHY_RTL826XB_PATCH_H__
|
||||
|
||||
/*
|
||||
* Include Files
|
||||
*/
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "rtk_osal.h"
|
||||
#include "rtk_phylib_def.h"
|
||||
#else
|
||||
#include <common/rt_type.h>
|
||||
#include <rtk/port.h>
|
||||
#endif
|
||||
|
||||
/* Function Name:
|
||||
* phy_rtl826xb_patch
|
||||
* Description:
|
||||
* apply patch data to PHY
|
||||
* Input:
|
||||
* unit - unit id
|
||||
* baseport - base port id on the PHY chip
|
||||
* portOffset - the index offset base on baseport for the port to patch
|
||||
* Output:
|
||||
* None
|
||||
* Return:
|
||||
* RT_ERR_OK
|
||||
* RT_ERR_FAILED
|
||||
* RT_ERR_NOT_SUPPORTED
|
||||
* RT_ERR_ABORT
|
||||
* Note:
|
||||
* None
|
||||
*/
|
||||
extern int32 phy_rtl826xb_patch(uint32 unit, rtk_port_t baseport, uint8 portOffset);
|
||||
|
||||
/* Function Name:
|
||||
* phy_rtl826xb_broadcast_patch
|
||||
* Description:
|
||||
* apply patch data to PHY
|
||||
* Input:
|
||||
* unit - unit id
|
||||
* baseport - base port id on the PHY chip
|
||||
* portOffset - the index offset base on baseport for the port to patch
|
||||
* perChip - 1 for per-chip mode, 0 for per-bus mode
|
||||
* Output:
|
||||
* None
|
||||
* Return:
|
||||
* RT_ERR_OK
|
||||
* RT_ERR_FAILED
|
||||
* RT_ERR_NOT_SUPPORTED
|
||||
* RT_ERR_ABORT
|
||||
* Note:
|
||||
* None
|
||||
*/
|
||||
extern int32 phy_rtl826xb_broadcast_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 perChip);
|
||||
|
||||
extern int32 phy_rtl826xb_patch_db_init(uint32 unit, rtk_port_t port, rt_phy_patch_db_t **pPhy_patchDb);
|
||||
#endif /* __HAL_PHY_PHY_RTL826XB_PATCH_H__ */
|
||||
56
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_osal.c
Executable file
56
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_osal.c
Executable file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "type.h"
|
||||
#include "error.h"
|
||||
#include "rtk_phylib_def.h"
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/sched/signal.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
int32
|
||||
osal_time_usecs_get(osal_usecs_t *pUsec)
|
||||
{
|
||||
struct timespec64 ts;
|
||||
|
||||
RT_PARAM_CHK((NULL == pUsec), RT_ERR_NULL_POINTER);
|
||||
|
||||
ktime_get_ts64(&ts);
|
||||
*pUsec = (osal_usecs_t)((ts.tv_sec * USEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_USEC));
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
void *
|
||||
osal_alloc(uint32 size)
|
||||
{
|
||||
void *p;
|
||||
p = kmalloc((size_t)size, GFP_ATOMIC);
|
||||
return p;
|
||||
}
|
||||
|
||||
int32
|
||||
phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData)
|
||||
{
|
||||
int32 rData = 0;
|
||||
rData = phy_read_mmd(port, mmdAddr, mmdReg);
|
||||
if (rData < 0)
|
||||
return RT_ERR_FAILED;
|
||||
*pData = (uint32)rData;
|
||||
return RT_ERR_OK;
|
||||
}
|
||||
|
||||
int32
|
||||
phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data)
|
||||
{
|
||||
int ret = phy_write_mmd(port, mmdAddr, mmdReg, data);
|
||||
return (ret < 0) ? RT_ERR_FAILED : RT_ERR_OK;
|
||||
}
|
||||
100
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_osal.h
Executable file
100
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_osal.h
Executable file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __RTK_PHY_OSAL_H
|
||||
#define __RTK_PHY_OSAL_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/delay.h>
|
||||
#include "type.h"
|
||||
#include "error.h"
|
||||
#include "phy_patch.h"
|
||||
#include "rtk_phylib.h"
|
||||
|
||||
#ifdef PHYPATCH_DB_GET
|
||||
#undef PHYPATCH_DB_GET
|
||||
#endif
|
||||
|
||||
#define PHYPATCH_DB_GET(_unit, _pPhy_device, _pPatchDb) \
|
||||
do { \
|
||||
struct rtk_phy_priv *_pPriv = (_pPhy_device)->priv; \
|
||||
rt_phy_patch_db_t *_pDb = _pPriv->patch; _pPatchDb = _pDb; \
|
||||
/*printk("[PHYPATCH_DB_GET] ? [%s]\n", (_pDb != NULL) ? "E":"N");*/ \
|
||||
} while(0)
|
||||
|
||||
#define HWP_9300_FAMILY_ID(_unit) 0
|
||||
#define HWP_9310_FAMILY_ID(_unit) 0
|
||||
#define RTK_9300_FAMILY_ID(_unit) 0
|
||||
#define RTK_9310_FAMILY_ID(_unit) 0
|
||||
#define RTK_9311B_FAMILY_ID(_unit) 0
|
||||
#define RTK_9330_FAMILY_ID(_unit) 0
|
||||
|
||||
#ifndef WAIT_COMPLETE_VAR
|
||||
#define WAIT_COMPLETE_VAR() \
|
||||
osal_usecs_t _t, _now, _t_wait=0, _timeout; \
|
||||
int32 _chkCnt=0;
|
||||
|
||||
#define WAIT_COMPLETE(_timeout_us) \
|
||||
_timeout = _timeout_us; \
|
||||
for(osal_time_usecs_get(&_t),osal_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \
|
||||
(_t_wait <= _timeout); \
|
||||
osal_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \
|
||||
)
|
||||
|
||||
#define WAIT_COMPLETE_IS_TIMEOUT() (_t_wait > _timeout)
|
||||
#endif
|
||||
|
||||
/* OSAL */
|
||||
#include <linux/slab.h>
|
||||
int32 osal_time_usecs_get(osal_usecs_t *pUsec);
|
||||
void *osal_alloc(uint32 size);
|
||||
#define osal_time_mdelay mdelay
|
||||
|
||||
#include <linux/ctype.h> /* for Kernel Space */
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#define osal_strlen strlen
|
||||
#define osal_strcmp strcmp
|
||||
#define osal_strcpy strcpy
|
||||
#define osal_strncpy strncpy
|
||||
#define osal_strcat strcat
|
||||
#define osal_strchr strchr
|
||||
#define osal_memset memset
|
||||
#define osal_memcpy memcpy
|
||||
#define osal_memcmp memcmp
|
||||
#define osal_strdup strdup
|
||||
#define osal_strncmp strncmp
|
||||
#define osal_strstr strstr
|
||||
#define osal_strtok strtok
|
||||
#define osal_strtok_r strtok_r
|
||||
#define osal_toupper toupper
|
||||
|
||||
#define osal_printf printk
|
||||
|
||||
/* HWP */
|
||||
#define HWP_PORT_SMI(unit, port) 0
|
||||
#define HWP_PHY_MODEL_BY_PORT(unit, port) 0
|
||||
#define HWP_PHY_ADDR(unit, port) 0
|
||||
#define HWP_PHY_BASE_MACID(unit, p) 0
|
||||
#define HWP_PORT_TRAVS_EXCEPT_CPU(unit, p) if (bcast_phyad < 0x1F && p != NULL)
|
||||
|
||||
|
||||
/* RT_LOG */
|
||||
//#define RT_LOG(level, module, fmt, args...) do { printk("RT_LOG:"fmt, ## args); } while(0)
|
||||
#define RT_LOG(level, module, fmt, args...) do {} while(0)
|
||||
#define RT_ERR(error_code, module, fmt, args...) do {} while(0)
|
||||
#define RT_INIT_ERR(error_code, module, fmt, args...) do {} while(0)
|
||||
#define RT_INIT_MSG(fmt, args...) do {} while(0)
|
||||
|
||||
#define phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad) 0
|
||||
|
||||
/* reg access */
|
||||
int32 phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData);
|
||||
int32 phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data);
|
||||
|
||||
|
||||
#endif /* __RTK_PHY_OSAL_H */
|
||||
336
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phy.c
Executable file
336
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phy.c
Executable file
@@ -0,0 +1,336 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "phy_rtl826xb_patch.h"
|
||||
#include "phy_rtl8251b_patch.h"
|
||||
#include "rtk_phylib_rtl826xb.h"
|
||||
#include "rtk_phylib.h"
|
||||
|
||||
#define REALTEK_PHY_ID_RTL8261N 0x001CCAF3
|
||||
#define REALTEK_PHY_ID_RTL8264B 0x001CC813
|
||||
#define REALTEK_PHY_ID_RTL8251B 0x001CC86A
|
||||
#define REALTEK_PHY_ID_RTL8251BE 0x001CC862 //Engineer sample
|
||||
|
||||
static int rtl8251_match_phy_device(struct phy_device *phydev)
|
||||
{
|
||||
return (phydev->phy_id == REALTEK_PHY_ID_RTL8251B) ||
|
||||
(phydev->phy_id == REALTEK_PHY_ID_RTL8251BE);
|
||||
}
|
||||
|
||||
|
||||
static int rtl826xb_get_features(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
ret = genphy_c45_pma_read_abilities(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
linkmode_or(phydev->supported, phydev->supported, PHY_BASIC_FEATURES);
|
||||
|
||||
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
|
||||
/* not support 10M modes */
|
||||
linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
|
||||
phydev->supported);
|
||||
linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl826xb_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct rtk_phy_priv *priv = NULL;
|
||||
|
||||
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct rtk_phy_priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
{
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset(priv, 0, sizeof(struct rtk_phy_priv));
|
||||
|
||||
if (phy_rtl826xb_patch_db_init(0, phydev, &(priv->patch)) != RT_ERR_OK)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->phytype = (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N) ? (RTK_PHYLIB_RTL8261N) : (RTK_PHYLIB_RTL8264B);
|
||||
priv->isBasePort = (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N) ? (1) : (((phydev->mdio.addr % 4) == 0) ? (1) : (0));
|
||||
phydev->priv = priv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtkphy_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret = 0;
|
||||
switch (phydev->drv->phy_id)
|
||||
{
|
||||
case REALTEK_PHY_ID_RTL8261N:
|
||||
case REALTEK_PHY_ID_RTL8264B:
|
||||
phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
|
||||
|
||||
|
||||
#if 1 /* toggle reset */
|
||||
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1);
|
||||
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 0);
|
||||
mdelay(30);
|
||||
#endif
|
||||
|
||||
ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_NORMAL);
|
||||
if (ret)
|
||||
{
|
||||
phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
#if 0 /* Debug: patch check */
|
||||
ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_CMP);
|
||||
if (ret)
|
||||
{
|
||||
phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] phy_patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
printk("[%s,%u] patch chk %s\n", __FUNCTION__, __LINE__, (ret == 0) ? "PASS" : "FAIL");
|
||||
#endif
|
||||
#if 0 /* Debug: USXGMII*/
|
||||
{
|
||||
uint32 data = 0;
|
||||
rtk_phylib_826xb_sds_read(phydev, 0x07, 0x10, 15, 0, &data);
|
||||
printk("[%s,%u] SDS 0x07, 0x10 : 0x%X\n", __FUNCTION__, __LINE__, data);
|
||||
rtk_phylib_826xb_sds_read(phydev, 0x06, 0x12, 15, 0, &data);
|
||||
printk("[%s,%u] SDS 0x06, 0x12 : 0x%X\n", __FUNCTION__, __LINE__, data);
|
||||
}
|
||||
{
|
||||
u16 sdspage = 0x5, sdsreg = 0x0;
|
||||
u16 regData = (sdspage & 0x3f) | ((sdsreg & 0x1f) << 6) | BIT(15);
|
||||
u16 readData = 0;
|
||||
phy_write_mmd(phydev, 30, 323, regData);
|
||||
do
|
||||
{
|
||||
udelay(10);
|
||||
readData = phy_read_mmd(phydev, 30, 323);
|
||||
} while ((readData & BIT(15)) != 0);
|
||||
readData = phy_read_mmd(phydev, 30, 322);
|
||||
printk("[%s,%d] sds link [%s] (0x%X)\n", __FUNCTION__, __LINE__, (readData & BIT(12)) ? "UP" : "DOWN", readData);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
case REALTEK_PHY_ID_RTL8251B:
|
||||
case REALTEK_PHY_ID_RTL8251BE:
|
||||
|
||||
printk(" RTL8251BE Init !!! \n");
|
||||
|
||||
ret = rtl8251b_phy_init(phydev);
|
||||
if (ret != SUCCESS)
|
||||
{
|
||||
phydev_err(phydev, "%s:%u [RTL8251B] patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
|
||||
return ret;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = 0;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
phydev_err(phydev, "%s:%u Unknow phy_id: 0x%X\n", __FUNCTION__, __LINE__, phydev->drv->phy_id);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtkphy_c45_suspend(struct phy_device *phydev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = rtk_phylib_c45_power_low(phydev);
|
||||
|
||||
phydev->speed = SPEED_UNKNOWN;
|
||||
phydev->duplex = DUPLEX_UNKNOWN;
|
||||
phydev->pause = 0;
|
||||
phydev->asym_pause = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtkphy_c45_resume(struct phy_device *phydev)
|
||||
{
|
||||
return rtk_phylib_c45_power_normal(phydev);
|
||||
}
|
||||
|
||||
static int rtkphy_c45_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
bool changed = false;
|
||||
u16 reg = 0;
|
||||
int ret = 0;
|
||||
|
||||
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
|
||||
if (phydev->autoneg == AUTONEG_DISABLE)
|
||||
return genphy_c45_pma_setup_forced(phydev);
|
||||
|
||||
ret = genphy_c45_an_config_aneg(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (ret > 0)
|
||||
changed = true;
|
||||
|
||||
reg = 0;
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
phydev->advertising))
|
||||
reg |= BIT(9);
|
||||
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
|
||||
phydev->advertising))
|
||||
reg |= BIT(8);
|
||||
|
||||
ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xA412,
|
||||
BIT(9) | BIT(8) , reg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (ret > 0)
|
||||
changed = true;
|
||||
|
||||
return genphy_c45_check_and_restart_aneg(phydev, changed);
|
||||
}
|
||||
|
||||
static int rtkphy_c45_aneg_done(struct phy_device *phydev)
|
||||
{
|
||||
return genphy_c45_aneg_done(phydev);
|
||||
}
|
||||
|
||||
static int rtkphy_c45_read_status(struct phy_device *phydev)
|
||||
{
|
||||
int ret = 0, status = 0;
|
||||
phydev->speed = SPEED_UNKNOWN;
|
||||
phydev->duplex = DUPLEX_UNKNOWN;
|
||||
phydev->pause = 0;
|
||||
phydev->asym_pause = 0;
|
||||
|
||||
ret = genphy_c45_read_link(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (phydev->autoneg == AUTONEG_ENABLE)
|
||||
{
|
||||
linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
phydev->lp_advertising);
|
||||
|
||||
ret = genphy_c45_read_lpa(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
status = phy_read_mmd(phydev, 31, 0xA414);
|
||||
if (status < 0)
|
||||
return status;
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
phydev->lp_advertising, status & BIT(11));
|
||||
|
||||
phy_resolve_aneg_linkmode(phydev);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = genphy_c45_read_pma(phydev);
|
||||
}
|
||||
|
||||
/* mdix*/
|
||||
status = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_SWAPPOL);
|
||||
if (status < 0)
|
||||
return status;
|
||||
|
||||
switch (status & 0x3)
|
||||
{
|
||||
case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
|
||||
phydev->mdix = ETH_TP_MDI;
|
||||
break;
|
||||
|
||||
case 0:
|
||||
phydev->mdix = ETH_TP_MDI_X;
|
||||
break;
|
||||
|
||||
default:
|
||||
phydev->mdix = ETH_TP_MDI_INVALID;
|
||||
break;
|
||||
}
|
||||
|
||||
phydev->interface=0x17; // USXGMII Mode
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static struct phy_driver rtk_phy_drivers[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N),
|
||||
.name = "Realtek RTL8261N",
|
||||
.get_features = rtl826xb_get_features,
|
||||
.config_init = rtkphy_config_init,
|
||||
.probe = rtl826xb_probe,
|
||||
.suspend = rtkphy_c45_suspend,
|
||||
.resume = rtkphy_c45_resume,
|
||||
.config_aneg = rtkphy_c45_config_aneg,
|
||||
.aneg_done = rtkphy_c45_aneg_done,
|
||||
.read_status = rtkphy_c45_read_status,
|
||||
},
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B),
|
||||
.name = "Realtek RTL8264B",
|
||||
.get_features = rtl826xb_get_features,
|
||||
.config_init = rtkphy_config_init,
|
||||
.probe = rtl826xb_probe,
|
||||
.suspend = rtkphy_c45_suspend,
|
||||
.resume = rtkphy_c45_resume,
|
||||
.config_aneg = rtkphy_c45_config_aneg,
|
||||
.aneg_done = rtkphy_c45_aneg_done,
|
||||
.read_status = rtkphy_c45_read_status,
|
||||
},
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8251B),
|
||||
.name = "Realtek RTL8251B",
|
||||
.match_phy_device = rtl8251_match_phy_device,
|
||||
.get_features = rtl826xb_get_features,
|
||||
.config_init = rtkphy_config_init,
|
||||
.suspend = rtkphy_c45_suspend,
|
||||
.resume = rtkphy_c45_resume,
|
||||
.config_aneg = rtkphy_c45_config_aneg,
|
||||
.aneg_done = rtkphy_c45_aneg_done,
|
||||
.read_status = rtkphy_c45_read_status,
|
||||
},
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8251BE),
|
||||
.name = "Realtek RTL8251BE",
|
||||
.match_phy_device = rtl8251_match_phy_device,
|
||||
.get_features = rtl826xb_get_features,
|
||||
.config_init = rtkphy_config_init,
|
||||
.suspend = rtkphy_c45_suspend,
|
||||
.resume = rtkphy_c45_resume,
|
||||
.config_aneg = rtkphy_c45_config_aneg,
|
||||
.aneg_done = rtkphy_c45_aneg_done,
|
||||
.read_status = rtkphy_c45_read_status,
|
||||
},
|
||||
};
|
||||
|
||||
module_phy_driver(rtk_phy_drivers);
|
||||
|
||||
|
||||
static struct mdio_device_id __maybe_unused rtk_phy_tbl[] = {
|
||||
{ PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N) },
|
||||
{ PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B) },
|
||||
{ PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8251B) },
|
||||
{ PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8251BE) },
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(mdio, rtk_phy_tbl);
|
||||
|
||||
MODULE_AUTHOR("Realtek");
|
||||
MODULE_DESCRIPTION("Realtek PHY drivers");
|
||||
MODULE_LICENSE("GPL");
|
||||
109
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib.c
Executable file
109
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib.c
Executable file
@@ -0,0 +1,109 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "rtk_phylib.h"
|
||||
#include <linux/phy.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
|
||||
/* OSAL */
|
||||
|
||||
void rtk_phylib_mdelay(uint32 msec)
|
||||
{
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
mdelay(msec);
|
||||
#else
|
||||
osal_time_mdelay(msec);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void rtk_phylib_udelay(uint32 usec)
|
||||
{
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
if (1000 <= usec)
|
||||
{
|
||||
mdelay(usec/1000);
|
||||
usec = usec % 1000;
|
||||
}
|
||||
udelay(usec);
|
||||
#else
|
||||
osal_time_udelay(usec);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* Register Access APIs */
|
||||
int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data)
|
||||
{
|
||||
int32 ret = 0;
|
||||
uint32 mask = 0;
|
||||
mask = UINT32_BITS_MASK(msb,lsb);
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
ret = phy_modify_mmd(phydev, mmd, reg, mask, data);
|
||||
#else
|
||||
{
|
||||
uint32 rData = 0, wData = 0;
|
||||
if ((msb != 15) || (lsb != 0))
|
||||
{
|
||||
if ((ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData)) != RT_ERR_OK)
|
||||
return ret;
|
||||
}
|
||||
wData = REG32_FIELD_SET(rData, data, lsb, mask);
|
||||
ret = phy_common_general_reg_mmd_set(phydev->unit, phydev->port, page, reg, wData);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData)
|
||||
{
|
||||
int32 ret = 0;
|
||||
uint32 rData = 0;
|
||||
uint32 mask = 0;
|
||||
mask = UINT32_BITS_MASK(msb,lsb);
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
rData = phy_read_mmd(phydev, mmd, reg);
|
||||
#else
|
||||
{
|
||||
ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData);
|
||||
}
|
||||
#endif
|
||||
|
||||
*pData = REG32_FIELD_GET(rData, lsb, mask);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Function Driver */
|
||||
|
||||
int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev)
|
||||
{
|
||||
int32 ret = 0;
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32 rtk_phylib_c45_power_low(rtk_phydev *phydev)
|
||||
{
|
||||
int32 ret = 0;
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 1));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable)
|
||||
{
|
||||
int32 ret = 0;
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 3, 0, 14, 14, (enable == 0) ? 0 : 1));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
101
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib.h
Executable file
101
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib.h
Executable file
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __RTK_PHYLIB_H
|
||||
#define __RTK_PHYLIB_H
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "type.h"
|
||||
#include "rtk_phylib_def.h"
|
||||
#else
|
||||
//#include SDK headers
|
||||
#endif
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#define PR_INFO(_fmt, _args...) pr_info(_fmt, ##_args)
|
||||
#define PR_DBG(_fmt, _args...) pr_debug(_fmt, ##_args)
|
||||
#define PR_ERR(_fmt, _args...) pr_err("ERROR: "_fmt, ##_args)
|
||||
|
||||
#define RTK_PHYLIB_ERR_FAILED (-EPERM)
|
||||
#define RTK_PHYLIB_ERR_INPUT (-EINVAL)
|
||||
#define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY (-ENOSPC)
|
||||
#define RTK_PHYLIB_ERR_TIMEOUT (-ETIME)
|
||||
#define RTK_PHYLIB_ERR_ENTRY_NOTFOUND (-ENODATA)
|
||||
#else
|
||||
#define PR_INFO(_fmt, _args...) RT_LOG(LOG_INFO, (MOD_HAL|MOD_PHY), _fmt, ##_args)
|
||||
#define PR_DBG(_fmt, _args...) RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PHY), _fmt, ##_args)
|
||||
#define PR_ERR(_fmt, _args...) RT_LOG(LOG_MAJOR_ERR, (MOD_HAL|MOD_PHY), _fmt, ##_args)
|
||||
|
||||
#define RTK_PHYLIB_ERR_FAILED (RT_ERR_FAILED)
|
||||
#define RTK_PHYLIB_ERR_INPUT (RT_ERR_INPUT)
|
||||
#define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY (RT_ERR_EXCEEDS_CAPACITY)
|
||||
#define RTK_PHYLIB_ERR_TIMEOUT (RT_ERR_BUSYWAIT_TIMEOUT)
|
||||
#define RTK_PHYLIB_ERR_ENTRY_NOTFOUND (RT_ERR_ENTRY_NOTFOUND)
|
||||
#endif
|
||||
|
||||
typedef enum rtk_phylib_phy_e
|
||||
{
|
||||
RTK_PHYLIB_NONE,
|
||||
RTK_PHYLIB_RTL8261N,
|
||||
RTK_PHYLIB_RTL8264B,
|
||||
RTK_PHYLIB_END
|
||||
} rtk_phylib_phy_t;
|
||||
|
||||
struct rtk_phy_priv {
|
||||
rtk_phylib_phy_t phytype;
|
||||
uint8 isBasePort;
|
||||
rt_phy_patch_db_t *patch;
|
||||
};
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
typedef struct phy_device rtk_phydev;
|
||||
#else
|
||||
struct rtk_phy_dev_s
|
||||
{
|
||||
uint32 unit;
|
||||
rtk_port_t port;
|
||||
|
||||
struct rtk_phy_priv *priv;
|
||||
};
|
||||
typedef struct rtk_phy_dev_s rtk_phydev;
|
||||
#endif
|
||||
|
||||
#define RTK_PHYLIB_ERR_CHK(op)\
|
||||
do {\
|
||||
if ((ret = (op)) != 0)\
|
||||
return ret;\
|
||||
} while(0)
|
||||
|
||||
#define RTK_PHYLIB_VAL_TO_BYTE_ARRAY(_val, _valbytes, _array, _start, _bytes)\
|
||||
do{\
|
||||
uint32 _i = 0;\
|
||||
for (_i = 0; _i < _bytes; _i++)\
|
||||
_array[_start+_i] = (_val >> (8* (_valbytes - _i - 1)));\
|
||||
}while(0)
|
||||
|
||||
#define RTK_PHYLIB_BYTE_ARRAY_TO_VAL(_val, _array, _start, _bytes)\
|
||||
do{\
|
||||
uint32 _i = 0;\
|
||||
for (_i = 0; _i < _bytes; _i++)\
|
||||
_val = (_val << 8) | _array[_start + _i];\
|
||||
}while(0)
|
||||
|
||||
|
||||
/* OSAL */
|
||||
void rtk_phylib_mdelay(uint32 msec);
|
||||
void rtk_phylib_udelay(uint32 usec);
|
||||
|
||||
/* Register Access APIs */
|
||||
int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
|
||||
int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
|
||||
|
||||
/* Function Driver */
|
||||
int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev);
|
||||
int32 rtk_phylib_c45_power_low(rtk_phydev *phydev);
|
||||
int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable);
|
||||
|
||||
|
||||
#endif /* __RTK_PHYLIB_H */
|
||||
166
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_def.h
Executable file
166
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_def.h
Executable file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
#ifndef __RTK_PHYLIB_DEF_H
|
||||
#define __RTK_PHYLIB_DEF_H
|
||||
|
||||
#include "type.h"
|
||||
|
||||
//#define PHY_C22_MMD_PAGE 0
|
||||
#define PHY_C22_MMD_PAGE 0x0A41
|
||||
#define PHY_C22_MMD_DEV_REG 13
|
||||
#define PHY_C22_MMD_ADD_REG 14
|
||||
|
||||
/* MDIO Manageable Device(MDD) address*/
|
||||
#define PHY_MMD_PMAPMD 1
|
||||
#define PHY_MMD_PCS 3
|
||||
#define PHY_MMD_AN 7
|
||||
#define PHY_MMD_VEND1 30 /* Vendor specific 1 */
|
||||
#define PHY_MMD_VEND2 31 /* Vendor specific 2 */
|
||||
|
||||
#define BIT_0 0x00000001U
|
||||
#define BIT_1 0x00000002U
|
||||
#define BIT_2 0x00000004U
|
||||
#define BIT_3 0x00000008U
|
||||
#define BIT_4 0x00000010U
|
||||
#define BIT_5 0x00000020U
|
||||
#define BIT_6 0x00000040U
|
||||
#define BIT_7 0x00000080U
|
||||
#define BIT_8 0x00000100U
|
||||
#define BIT_9 0x00000200U
|
||||
#define BIT_10 0x00000400U
|
||||
#define BIT_11 0x00000800U
|
||||
#define BIT_12 0x00001000U
|
||||
#define BIT_13 0x00002000U
|
||||
#define BIT_14 0x00004000U
|
||||
#define BIT_15 0x00008000U
|
||||
#define BIT_16 0x00010000U
|
||||
#define BIT_17 0x00020000U
|
||||
#define BIT_18 0x00040000U
|
||||
#define BIT_19 0x00080000U
|
||||
#define BIT_20 0x00100000U
|
||||
#define BIT_21 0x00200000U
|
||||
#define BIT_22 0x00400000U
|
||||
#define BIT_23 0x00800000U
|
||||
#define BIT_24 0x01000000U
|
||||
#define BIT_25 0x02000000U
|
||||
#define BIT_26 0x04000000U
|
||||
#define BIT_27 0x08000000U
|
||||
#define BIT_28 0x10000000U
|
||||
#define BIT_29 0x20000000U
|
||||
#define BIT_30 0x40000000U
|
||||
#define BIT_31 0x80000000U
|
||||
|
||||
#define MASK_1_BITS (BIT_1 - 1)
|
||||
#define MASK_2_BITS (BIT_2 - 1)
|
||||
#define MASK_3_BITS (BIT_3 - 1)
|
||||
#define MASK_4_BITS (BIT_4 - 1)
|
||||
#define MASK_5_BITS (BIT_5 - 1)
|
||||
#define MASK_6_BITS (BIT_6 - 1)
|
||||
#define MASK_7_BITS (BIT_7 - 1)
|
||||
#define MASK_8_BITS (BIT_8 - 1)
|
||||
#define MASK_9_BITS (BIT_9 - 1)
|
||||
#define MASK_10_BITS (BIT_10 - 1)
|
||||
#define MASK_11_BITS (BIT_11 - 1)
|
||||
#define MASK_12_BITS (BIT_12 - 1)
|
||||
#define MASK_13_BITS (BIT_13 - 1)
|
||||
#define MASK_14_BITS (BIT_14 - 1)
|
||||
#define MASK_15_BITS (BIT_15 - 1)
|
||||
#define MASK_16_BITS (BIT_16 - 1)
|
||||
#define MASK_17_BITS (BIT_17 - 1)
|
||||
#define MASK_18_BITS (BIT_18 - 1)
|
||||
#define MASK_19_BITS (BIT_19 - 1)
|
||||
#define MASK_20_BITS (BIT_20 - 1)
|
||||
#define MASK_21_BITS (BIT_21 - 1)
|
||||
#define MASK_22_BITS (BIT_22 - 1)
|
||||
#define MASK_23_BITS (BIT_23 - 1)
|
||||
#define MASK_24_BITS (BIT_24 - 1)
|
||||
#define MASK_25_BITS (BIT_25 - 1)
|
||||
#define MASK_26_BITS (BIT_26 - 1)
|
||||
#define MASK_27_BITS (BIT_27 - 1)
|
||||
#define MASK_28_BITS (BIT_28 - 1)
|
||||
#define MASK_29_BITS (BIT_29 - 1)
|
||||
#define MASK_30_BITS (BIT_30 - 1)
|
||||
#define MASK_31_BITS (BIT_31 - 1)
|
||||
|
||||
#define REG32_FIELD_SET(_data, _val, _fOffset, _fMask) ((_data & ~(_fMask)) | ((_val << (_fOffset)) & (_fMask)))
|
||||
#define REG32_FIELD_GET(_data, _fOffset, _fMask) ((_data & (_fMask)) >> (_fOffset))
|
||||
#define UINT32_BITS_MASK(_mBit, _lBit) ((0xFFFFFFFF >> (31 - _mBit)) ^ ((1 << _lBit) - 1))
|
||||
|
||||
typedef struct phy_device * rtk_port_t;
|
||||
|
||||
#if 1 /* ss\sdk\include\hal\phy\phydef.h */
|
||||
/* unified patch format */
|
||||
typedef enum rtk_phypatch_type_e
|
||||
{
|
||||
PHY_PATCH_TYPE_NONE = 0,
|
||||
PHY_PATCH_TYPE_TOP = 1,
|
||||
PHY_PATCH_TYPE_SDS,
|
||||
PHY_PATCH_TYPE_AFE,
|
||||
PHY_PATCH_TYPE_UC,
|
||||
PHY_PATCH_TYPE_UC2,
|
||||
PHY_PATCH_TYPE_NCTL0,
|
||||
PHY_PATCH_TYPE_NCTL1,
|
||||
PHY_PATCH_TYPE_NCTL2,
|
||||
PHY_PATCH_TYPE_ALGXG,
|
||||
PHY_PATCH_TYPE_ALG1G,
|
||||
PHY_PATCH_TYPE_NORMAL,
|
||||
PHY_PATCH_TYPE_DATARAM,
|
||||
PHY_PATCH_TYPE_RTCT,
|
||||
PHY_PATCH_TYPE_END
|
||||
} rtk_phypatch_type_t;
|
||||
|
||||
#define RTK_PATCH_TYPE_FLOW(_id) (PHY_PATCH_TYPE_END + _id)
|
||||
#define RTK_PATCH_TYPE_FLOWID_MAX PHY_PATCH_TYPE_END
|
||||
#define RTK_PATCH_SEQ_MAX ( PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX -1)
|
||||
|
||||
typedef struct rtk_hwpatch_s
|
||||
{
|
||||
uint8 patch_op;
|
||||
uint8 portmask;
|
||||
uint16 pagemmd;
|
||||
uint16 addr;
|
||||
uint8 msb;
|
||||
uint8 lsb;
|
||||
uint16 data;
|
||||
uint8 compare_op;
|
||||
uint16 sram_p;
|
||||
uint16 sram_rr;
|
||||
uint16 sram_rw;
|
||||
uint16 sram_a;
|
||||
} rtk_hwpatch_t;
|
||||
|
||||
typedef struct rtk_hwpatch_data_s
|
||||
{
|
||||
rtk_hwpatch_t *conf;
|
||||
uint32 size;
|
||||
} rtk_hwpatch_data_t;
|
||||
|
||||
typedef struct rtk_hwpatch_seq_s
|
||||
{
|
||||
uint8 patch_type;
|
||||
union
|
||||
{
|
||||
rtk_hwpatch_data_t data;
|
||||
uint8 flow_id;
|
||||
} patch;
|
||||
} rtk_hwpatch_seq_t;
|
||||
|
||||
typedef struct rt_phy_patch_db_s
|
||||
{
|
||||
/* patch operation */
|
||||
int32 (*fPatch_op)(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode);
|
||||
int32 (*fPatch_flow)(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode);
|
||||
|
||||
/* patch data */
|
||||
rtk_hwpatch_seq_t seq_table[RTK_PATCH_SEQ_MAX];
|
||||
rtk_hwpatch_seq_t cmp_table[RTK_PATCH_SEQ_MAX];
|
||||
|
||||
} rt_phy_patch_db_t;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /* __RTK_PHYLIB_DEF_H */
|
||||
57
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_rtl826xb.c
Executable file
57
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_rtl826xb.c
Executable file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "rtk_phylib_rtl826xb.h"
|
||||
|
||||
/* Indirect Register Access APIs */
|
||||
int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData)
|
||||
{
|
||||
int32 ret = 0;
|
||||
uint32 rData = 0;
|
||||
uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8000);
|
||||
uint32 i = 0;
|
||||
uint32 mask = 0;
|
||||
mask = UINT32_BITS_MASK(msb,lsb);
|
||||
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op));
|
||||
|
||||
for (i = 0; i < 10; i++)
|
||||
{
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 323, 15, 15, &rData));
|
||||
if (rData == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
rtk_phylib_udelay(10);
|
||||
}
|
||||
if (i == 10)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 322, 15, 0, &rData));
|
||||
*pData = REG32_FIELD_GET(rData, lsb, mask);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data)
|
||||
{
|
||||
int32 ret = 0;
|
||||
uint32 wData = 0, rData = 0;
|
||||
uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8800);
|
||||
uint32 mask = 0;
|
||||
mask = UINT32_BITS_MASK(msb,lsb);
|
||||
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sds_read(phydev, page, reg, 15, 0, &rData));
|
||||
|
||||
wData = REG32_FIELD_SET(rData, data, lsb, mask);
|
||||
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 321, 15, 0, wData));
|
||||
RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op));
|
||||
|
||||
return ret;
|
||||
}
|
||||
19
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_rtl826xb.h
Executable file
19
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/rtk_phylib_rtl826xb.h
Executable file
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __RTK_PHYLIB_RTL826XB_H
|
||||
#define __RTK_PHYLIB_RTL826XB_H
|
||||
|
||||
#if defined(RTK_PHYDRV_IN_LINUX)
|
||||
#include "rtk_phylib.h"
|
||||
#else
|
||||
//#include SDK headers
|
||||
#endif
|
||||
|
||||
int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
|
||||
int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
|
||||
|
||||
#endif /* __RTK_PHYLIB_RTL826XB_H */
|
||||
117
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/type.h
Executable file
117
feeds/ipq95xx/ipq53xx/files/drivers/net/phy/rtk/type.h
Executable file
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_TYPE_H__
|
||||
#define __COMMON_TYPE_H__
|
||||
|
||||
/*
|
||||
* Symbol Definition
|
||||
*/
|
||||
|
||||
#define USING_RTSTK_PKT_AS_RAIL
|
||||
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#ifndef ETHER_ADDR_LEN
|
||||
#define ETHER_ADDR_LEN 6
|
||||
#endif
|
||||
|
||||
#ifndef IP6_ADDR_LEN
|
||||
#define IP6_ADDR_LEN 16
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Data Type Declaration
|
||||
*/
|
||||
#ifndef uint64
|
||||
typedef unsigned long long uint64;
|
||||
#endif
|
||||
|
||||
#ifndef int64
|
||||
typedef signed long long int64;
|
||||
#endif
|
||||
|
||||
#ifndef uint32
|
||||
typedef unsigned int uint32;
|
||||
#endif
|
||||
|
||||
#ifndef int32
|
||||
typedef signed int int32;
|
||||
#endif
|
||||
|
||||
#ifndef uint16
|
||||
typedef unsigned short uint16;
|
||||
#endif
|
||||
|
||||
#ifndef int16
|
||||
typedef signed short int16;
|
||||
#endif
|
||||
|
||||
#ifndef uint8
|
||||
typedef unsigned char uint8;
|
||||
#endif
|
||||
|
||||
#ifndef int8
|
||||
typedef signed char int8;
|
||||
#endif
|
||||
|
||||
//#define CONFIG_SDK_WORDSIZE_64 /* not ready */
|
||||
#ifdef CONFIG_SDK_WORDSIZE_64
|
||||
typedef long int intptr;
|
||||
typedef unsigned long int uintptr;
|
||||
#else
|
||||
typedef int intptr;
|
||||
typedef unsigned int uintptr;
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef ipaddr_t
|
||||
typedef uint32 ipaddr_t; /* ipv4 address type */
|
||||
#endif
|
||||
|
||||
/* configuration mode type */
|
||||
typedef enum rtk_enable_e
|
||||
{
|
||||
DISABLED = 0,
|
||||
ENABLED,
|
||||
RTK_ENABLE_END
|
||||
} rtk_enable_t;
|
||||
|
||||
/* initial state of module */
|
||||
typedef enum init_state_e
|
||||
{
|
||||
INIT_NOT_COMPLETED = 0,
|
||||
INIT_COMPLETED,
|
||||
INIT_STATE_END
|
||||
} init_state_t;
|
||||
|
||||
/* ethernet address type */
|
||||
typedef struct rtk_mac_s
|
||||
{
|
||||
uint8 octet[ETHER_ADDR_LEN];
|
||||
} rtk_mac_t;
|
||||
|
||||
typedef uint32 osal_time_t;
|
||||
typedef uint32 osal_usecs_t;
|
||||
|
||||
/*
|
||||
* Macro Definition
|
||||
*/
|
||||
|
||||
#endif /* __COMMON_TYPE_H__ */
|
||||
|
||||
@@ -23,3 +23,15 @@ define Device/sercomm_ap72tip
|
||||
DEVICE_PACKAGES := ath12k-wifi-sercomm-ap72tip ath12k-firmware-qcn92xx-split-phy ath12k-firmware-ipq53xx
|
||||
endef
|
||||
TARGET_DEVICES += sercomm_ap72tip
|
||||
|
||||
define Device/edgecore_eap105
|
||||
DEVICE_TITLE := Edgecore EAP105
|
||||
DEVICE_DTS := ipq5332-edgecore-eap105
|
||||
DEVICE_DTS_CONFIG := config@mi01.6
|
||||
IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi
|
||||
IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
|
||||
IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand
|
||||
IMAGE/nand-factory.ubi := append-ubi
|
||||
DEVICE_PACKAGES := ath12k-wifi-edgecore-eap105 ath12k-firmware-qcn92xx-split-phy ath12k-firmware-ipq53xx
|
||||
endef
|
||||
TARGET_DEVICES += edgecore_eap105
|
||||
|
||||
22
feeds/ipq95xx/ipq53xx/patches/303-realtek-phy.patch
Normal file
22
feeds/ipq95xx/ipq53xx/patches/303-realtek-phy.patch
Normal file
@@ -0,0 +1,22 @@
|
||||
Index: linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/Kconfig
|
||||
===================================================================
|
||||
--- linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617.orig/drivers/net/phy/Kconfig
|
||||
+++ linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/Kconfig
|
||||
@@ -576,7 +576,7 @@ config XILINX_GMII2RGMII
|
||||
This driver support xilinx GMII to RGMII IP core it provides
|
||||
the Reduced Gigabit Media Independent Interface(RGMII) between
|
||||
Ethernet physical media devices and the Gigabit Ethernet controller.
|
||||
-
|
||||
+source "drivers/net/phy/rtk/Kconfig"
|
||||
endif # PHYLIB
|
||||
|
||||
config MICREL_KS8995MA
|
||||
Index: linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/Makefile
|
||||
===================================================================
|
||||
--- linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617.orig/drivers/net/phy/Makefile
|
||||
+++ linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/Makefile
|
||||
@@ -110,3 +110,4 @@ obj-$(CONFIG_TERANETICS_PHY) += teraneti
|
||||
obj-$(CONFIG_VITESSE_PHY) += vitesse.o
|
||||
obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
|
||||
obj-$(CONFIG_MDIO_QCA) += mdio-qca.o
|
||||
+obj-$(CONFIG_RTK_MSSDK_PHY) += rtk/
|
||||
15
profiles/edgecore_eap105.yml
Normal file
15
profiles/edgecore_eap105.yml
Normal file
@@ -0,0 +1,15 @@
|
||||
---
|
||||
profile: edgecore_eap105
|
||||
target: ipq53xx
|
||||
subtarget: generic
|
||||
description: Build image for the edgecore eap105
|
||||
image: bin/targets/ipq53xx/generic/openwrt-ipq53xx-cig_wf189-squashfs-sysupgrade.tar
|
||||
feeds:
|
||||
- name: ipq95xx
|
||||
path: ../../feeds/ipq95xx
|
||||
packages:
|
||||
- ipq53xx
|
||||
_include:
|
||||
- ucentral-ap
|
||||
diffconfig: |
|
||||
CONFIG_KERNEL_IPQ_MEM_PROFILE=0
|
||||
Reference in New Issue
Block a user