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WIFI-14438: Fix LAN port issue in Edgecore EAP105

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Signed-off-by: Tanya Singh <tanya_singh@accton.com>
This commit is contained in:
Tanya Singh
2025-02-25 11:02:50 +08:00
committed by John Crispin
parent 24dbba4c5a
commit 9d611028fd
2 changed files with 22 additions and 2 deletions
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18
feeds/qca/ipq53xx/base-files/etc/board.d/03_gpio_switches Executable file
View File

@@ -0,0 +1,18 @@
#!/bin/sh
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case $board in
edgecore,eap105)
ucidef_add_gpio_switch "eth1_phy_reset_down" "eth1_PHY_reset_down" "481" "0"
ucidef_add_gpio_switch "eth1_phy_reset_up" "eth1_PHY_reset_up" "481" "1"
;;
esac
board_config_flush
exit 0

6
feeds/qca/ipq53xx/dts/ipq5332-edgecore-eap105.dts
View File

@@ -37,7 +37,7 @@
mdio:mdio@90000 { mdio:mdio@90000 {
pinctrl-0 = <&mdio1_pins>; pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
phy-reset-gpio = <&tlmm 24 GPIO_ACTIVE_LOW &tlmm 22 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
phyaddr_fixup = <0xC90F018>; phyaddr_fixup = <0xC90F018>;
uniphyaddr_fixup = <0xC90F014>; uniphyaddr_fixup = <0xC90F014>;
mdio_clk_fixup; /* MDIO clock sequence fix up flag */ mdio_clk_fixup; /* MDIO clock sequence fix up flag */
@@ -46,6 +46,8 @@
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <2>; reg = <2>;
compatible = "ethernet-phy-id001c.c916"; compatible = "ethernet-phy-id001c.c916";
realtek,clkout-disable;
realtek,aldps-enable;
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
@@ -97,7 +99,7 @@
compatible = "qcom,nss-dp"; compatible = "qcom,nss-dp";
qcom,id = <1>; qcom,id = <1>;
reg = <0x3a500000 0x4000>; reg = <0x3a500000 0x4000>;
qcom,mactype = <1>; qcom,mactype = <0>;
local-mac-address = [000000000000]; local-mac-address = [000000000000];
mdio-bus = <&mdio>; mdio-bus = <&mdio>;
qcom,phy-mdio-addr = <2>; qcom,phy-mdio-addr = <2>;