From c95b91c39979db241abb062da2d702531ca43bca Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 14 Feb 2024 12:57:49 +0100 Subject: [PATCH] ipq95xx: various updates * finalize CIG WF198 support * add Sercomm AP72tip support * update BDF files * improve firmware package Signed-off-by: John Crispin --- feeds/ipq95xx/ath12k-firmware/Makefile | 51 +- feeds/ipq95xx/ath12k-wifi/Makefile | 19 +- .../ath12k-wifi/board-cig-wf198.bin.ipq53xx | Bin 0 -> 63488 bytes .../board-sercomm-ap72tip.bin.ipq53xx | Bin 0 -> 161792 bytes .../board-sercomm-ap72tip.bin.qcn9224 | Bin 0 -> 161792 bytes feeds/ipq95xx/ath12k-wifi/regdb.bin | Bin 0 -> 25656 bytes feeds/ipq95xx/ipq53xx/Makefile | 3 +- .../ipq53xx/base-files/etc/board.d/01_leds | 18 + .../etc/board.d/{01_network => 02_network} | 7 +- .../etc/hotplug.d/firmware/10-ath12k-caldata | 7 +- feeds/ipq95xx/ipq53xx/config-5.4 | 2 + .../arm64/boot/dts/qcom/ipq5332-cig-wf198.dts | 50 +- .../dts/qcom/ipq5332-mi01.2.dtsi.20231011 | 396 +++ .../boot/dts/qcom/ipq5332-sercomm-ap72tip.dts | 164 + .../boot/dts/qcom/ipq5332-sercomm-mi01.2.dtsi | 445 +++ .../arm64/boot/dts/qcom/ipq5332-sercomm.dtsi | 2701 +++++++++++++++++ feeds/ipq95xx/ipq53xx/image/ipq53xx.mk | 14 +- feeds/ipq95xx/ipq53xx/patches/300-pwm.patch | 40 + .../ipq95xx/ipq53xx/patches/301-button.patch | 42 + .../ipq95xx/ipq53xx/patches/302-aq-phy.patch | 66 + .../ipq95xx/qca-ssdk/patches/101-aq_phy.patch | 28 + ...07x-prepare-tree-for-old-v4.4-kernel.patch | 8 +- ...ipq807x-drop-nand.sh-from-base-files.patch | 2 +- .../0045-ucode-add-TIP-specific-fixes.patch | 2 +- patches/0058-kernel-add-v5.4-checksums.patch | 2 +- .../0068-ucode-update-to-latest-HEAD.patch | 2 +- 26 files changed, 4000 insertions(+), 69 deletions(-) create mode 100755 feeds/ipq95xx/ath12k-wifi/board-cig-wf198.bin.ipq53xx create mode 100644 feeds/ipq95xx/ath12k-wifi/board-sercomm-ap72tip.bin.ipq53xx create mode 100644 feeds/ipq95xx/ath12k-wifi/board-sercomm-ap72tip.bin.qcn9224 create mode 100755 feeds/ipq95xx/ath12k-wifi/regdb.bin create mode 100755 feeds/ipq95xx/ipq53xx/base-files/etc/board.d/01_leds rename feeds/ipq95xx/ipq53xx/base-files/etc/board.d/{01_network => 02_network} (66%) create mode 100644 feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dtsi.20231011 create mode 100644 feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-ap72tip.dts create mode 100644 feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-mi01.2.dtsi create mode 100644 feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm.dtsi create mode 100644 feeds/ipq95xx/ipq53xx/patches/300-pwm.patch create mode 100644 feeds/ipq95xx/ipq53xx/patches/301-button.patch create mode 100644 feeds/ipq95xx/ipq53xx/patches/302-aq-phy.patch create mode 100644 feeds/ipq95xx/qca-ssdk/patches/101-aq_phy.patch diff --git a/feeds/ipq95xx/ath12k-firmware/Makefile b/feeds/ipq95xx/ath12k-firmware/Makefile index 05e075182..e2d54bd38 100644 --- a/feeds/ipq95xx/ath12k-firmware/Makefile +++ b/feeds/ipq95xx/ath12k-firmware/Makefile @@ -1,11 +1,11 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ath12k-firmware +PKG_MIRROR_HASH:=a325f86b1d613f713d2e015abca4a9ff86c8448d4cd540fa022866da2c5aa042 PKG_SOURCE_PROTO:=git PKG_BRANCH:=main PKG_SOURCE_URL:=https://github.com/quic/upstream-wifi-fw.git -PKG_MIRROR_HASH:=ade4287ff2935ad1d54e5dabb8e6de28f648d0974fa76238fcc1616235e6773e -PKG_SOURCE_VERSION:=3417bb86645c5ff4c58258db7cc33e43260b4222 +PKG_SOURCE_VERSION:=e90d32aaa149800ea79760639cb5ac9ddcfc8281 PKG_MAINTAINER:=John Crispin @@ -18,20 +18,59 @@ define Package/ath12k-firmware-default DEPENDS:= endef +define Package/ath12k-firmware-qcn92xx-split-phy + $(Package/ath12k-firmware-default) + TITLE:=ath12k firmware for qcn92xx split phy devices + DEPENDS:=@(TARGET_ipq95xx||TARGET_ipq53xx) +endef + define Package/ath12k-firmware-qcn92xx $(Package/ath12k-firmware-default) TITLE:=ath12k firmware for qcn92xx devices - DEPENDS:=@TARGET_ipq95xx + DEPENDS:=@(TARGET_ipq95xx||TARGET_ipq53xx) +endef + +define Package/ath12k-firmware-ipq53xx + $(Package/ath12k-firmware-default) + TITLE:=ath12k firmware for ipq53xx devices + DEPENDS:=@TARGET_ipq53xx +endef + +define Package/ath12k-firmware-ipq53xx-wk-wk + $(Package/ath12k-firmware-default) + TITLE:=ath12k firmware for ipq53xx + wk + wk devices + DEPENDS:=@TARGET_ipq53xx endef define Build/Compile endef +define Package/ath12k-firmware-qcn92xx-split-phy/install + $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 + $(CP) $(PKG_BUILD_DIR)/ath12k-firmware/QCN9274/hw2.0_split_phy/1.2.1/WLAN.WBE.1.2.1-00148-QCAHKSWPL_SILICONZ-1/* \ + $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 +endef + define Package/ath12k-firmware-qcn92xx/install - $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw2.0 - $(INSTALL_DATA) $(PKG_BUILD_DIR)/ath12k-firmware/QCN9274/hw2.0/1.1.1/WLAN.WBE.1.1.1-00126-QCAHKSWPL_SILICONZ-1/* \ - $(1)/lib/firmware/ath12k/QCN92XX/hw2.0 + $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 + $(CP) $(PKG_BUILD_DIR)/ath12k-firmware/QCN9274/hw2.0/1.2.1/WLAN.WBE.1.2.1-00201-QCAHKSWPL_SILICONZ-1/* \ + $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 +endef + +define Package/ath12k-firmware-ipq53xx/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ5332/ + $(CP) $(PKG_BUILD_DIR)/ath12k-firmware//IPQ5322/hw1.0/1.2.1/WLAN.WBE.1.2.1-00201-QCAHKSWPL_SILICONZ-1/* \ + $(1)/lib/firmware/IPQ5332/ +endef + +define Package/ath12k-firmware-ipq53xx-wk-wk/install + $(INSTALL_DIR) $(1)/lib/firmware/IPQ5332/ + $(CP) $(PKG_BUILD_DIR)/ath12k-firmware/IPQ5322_QCN6432_QCN6432/hw1.0/testing/1.3/WLAN.WBE.1.3-02907-QCAHKSWPL_SILICONZ-1/* \ + $(1)/lib/firmware/IPQ5332/ endef $(eval $(call BuildPackage,ath12k-firmware-qcn92xx)) +$(eval $(call BuildPackage,ath12k-firmware-qcn92xx-split-phy)) +$(eval $(call BuildPackage,ath12k-firmware-ipq53xx)) +$(eval $(call BuildPackage,ath12k-firmware-ipq53xx-wk-wk)) diff --git a/feeds/ipq95xx/ath12k-wifi/Makefile b/feeds/ipq95xx/ath12k-wifi/Makefile index 6718680b3..ce4127ef1 100644 --- a/feeds/ipq95xx/ath12k-wifi/Makefile +++ b/feeds/ipq95xx/ath12k-wifi/Makefile @@ -38,10 +38,27 @@ $(call Package/ath12k-wifi-default) TITLE:=board.bin for CIG WF198 endef +define Package/ath12k-wifi-sercomm-ap72tip +$(call Package/ath12k-wifi-default) + TITLE:=board.bin for Sercomm WIFI-7 +endef + define Package/ath12k-wifi-cig-wf198/install - $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 + $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0 + $(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/ $(INSTALL_DATA) ./board-cig-wf198.bin.qcn9224 $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/board.bin + $(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/ + $(INSTALL_DATA) ./board-cig-wf198.bin.ipq53xx $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board.bin +endef + +define Package/ath12k-wifi-sercomm-ap72tip/install + $(INSTALL_DIR) $(1)/lib/firmware/ath12k/QCN92XX/hw1.0 $(1)/lib/firmware/ath12k/IPQ5332/hw1.0 + $(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/ + $(INSTALL_DATA) ./board-sercomm-ap72tip.bin.qcn9224 $(1)/lib/firmware/ath12k/QCN92XX/hw1.0/board.bin + $(INSTALL_DATA) ./regdb.bin $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/ + $(INSTALL_DATA) ./board-sercomm-ap72tip.bin.ipq53xx $(1)/lib/firmware/ath12k/IPQ5332/hw1.0/board.bin endef $(eval $(call BuildPackage,ath12k-wifi-qcom-qcn9274)) $(eval $(call BuildPackage,ath12k-wifi-cig-wf198)) +$(eval $(call BuildPackage,ath12k-wifi-sercomm-ap72tip)) diff --git a/feeds/ipq95xx/ath12k-wifi/board-cig-wf198.bin.ipq53xx b/feeds/ipq95xx/ath12k-wifi/board-cig-wf198.bin.ipq53xx new file mode 100755 index 0000000000000000000000000000000000000000..48ebfd7ae24d0788185229ca3f482b40b6ed970a GIT binary patch literal 63488 zcmeI5ZD?C%6vxl=Bx!Tgw0Y~x+I3l)cC{Nrq?<5gZ;mm>D5cak>uS|a2f9&;Z*0n( zZIt>!6k(L^mEkCi`a1kJrV~-{)8-fb;0J{<#vDwr1Hrn9*YiC0CQZ_GP1@SE&Hr?{ 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z@%Q0Lf3v}y`04maE2f4Iz6W&v8l->GK0EI?ZVf*frsTcxGxSUNZJYQfBp-hhpOA44 zhranUDx^>29Ubd7_+`AwC)uqI6L<4xXTx`XmS4>O@FCC4-v-cCE)0u99<0d(o1kH zYWh3<^; - bias-pull-down; - }; - - spi_mosi { - pins = "gpio15"; - function = "blsp0_spi"; - drive-strength = <2>; - bias-pull-down; - }; - - spi_miso { - pins = "gpio16"; - function = "blsp0_spi"; - drive-strength = <2>; - bias-pull-down; - }; - - spi_cs { - pins = "gpio17"; - function = "blsp0_spi"; - drive-strength = <2>; - bias-pull-up; - }; - }; - serial_0_pins: serial0-pinmux { pins = "gpio18", "gpio19"; function = "blsp0_uart0"; @@ -103,11 +73,11 @@ }; pwm_pins: pwm_pinmux { - /*mux_1 { + mux_1 { pins = "gpio26"; function = "pwm2"; drive-strength = <8>; - };*/ + }; mux_2 { pins = "gpio30"; function = "pwm1"; @@ -199,7 +169,6 @@ pinctrl-0 = <&pwm_pins>; pinctrl-names = "default"; used-pwm-indices = <1>, <1>, <1>, <1>; - dft-pwm-status = <0>, <1>, <1>, <0>; #pwm-cells = <2>; status = "ok"; }; @@ -329,21 +298,6 @@ status = "ok"; }; - spi@78b5000 { - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - cs-select = <0>; - status = "ok"; - - m25p80@0 { - compatible = "n25q128a11"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - spi_2: spi@78b7000 { pinctrl-0 = <&spi_2_pins>; pinctrl-names = "default"; diff --git a/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dtsi.20231011 b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dtsi.20231011 new file mode 100644 index 000000000..fac09a225 --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dtsi.20231011 @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#include "ipq5332.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart0; /*console*/ + serial1 = &blsp1_uart1; /*ble*/ + ethernet0 = "/soc/dp1"; + ethernet1 = "/soc/dp2"; + }; + + chosen { + stdout-path = "serial0"; + }; + + soc { + pinctrl@1000000 { + serial_0_pins: serial0-pinmux { /*console*/ + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + + serial_1_pins: serial1-pinmux { /*ble*/ +// pins = "gpio33", "gpio34", "gpio35", "gpio36"; + pins = "gpio33", "gpio35"; + function = "blsp1_uart2"; + drive-strength = <8>; + bias-pull-up; + }; + + //serial_2_pins: serial2-pinmux { /*gps*/ + /* pins = "gpio33", "gpio34", "gpio35", "gpio36"; + function = "blsp1_uart1"; + drive-strength = <8>; + bias-pull-up; + };*/ + + i2c_2_pins: i2c-2-pinmux { + pins = "gpio43", "gpio45"; + function = "blsp2_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + + spi_0_pins: spi0-pinmux { + spi_clock { + pins = "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_mosi { + pins = "gpio15"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_miso { + pins = "gpio16"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_cs { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_1_pins: spi_1_pins { /* tpm */ + mux { + pins = "gpio29", "gpio30", "gpio31", "gpio32"; + function = "blsp1_spi0"; + drive-strength = <8>; +// bias-disable; + bias-pull-up; + }; + }; + + mdio0_pins: mdio_pinmux { + mux_0 { + pins = "gpio25"; + function = "mdc0"; + drive-strength = <8>; + bias-disable; + }; + mux_1 { + pins = "gpio26"; + function = "mdio0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + mdio1_pins: mdio_pinmux { + mux_0 { + pins = "gpio27"; + function = "mdc1"; + drive-strength = <8>; + bias-disable; + }; + mux_1 { + pins = "gpio28"; + function = "mdio1"; + drive-strength = <8>; + bias-pull-up; + }; + }; +/* + sfp_pins: sfp_pinmux { + sfp_rx { + pins = "gpio45"; + function = "rx1"; + bias-disable; + }; + sfp_tx { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + };*/ + }; + + + dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <1>; + reg = <0x3a500000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + mdio-bus = <&mdio>; + qcom,phy-mdio-addr = <24>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + + dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a504000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + qcom,phy-mdio-addr = <0>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + +/* dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a504000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + mdio-bus = <&mdio>; + qcom,phy-mdio-addr = <30>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; +*/ + + mdio:mdio@90000 { + status = "ok"; + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + /*gpio0 for napa, gpio3 for AQR114C*/ + phy-reset-gpio = <&tlmm 0 0 &tlmm 3 0>; + + phy0: ethernet-phy@0 { + reg = <24>; + }; + phy1: ethernet-phy@1 { //aqr114c + reg = <0>; + compatible ="ethernet-phy-ieee802.3-c45"; + }; + + }; + + ess-instance { + ess-switch@3a000000 { + pinctrl-names = "default"; + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x0>; /* lan port bitmap */ + switch_wan_bmp = <0x6>; /* wan port bitmap */ + switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ +// switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <24>; + }; + port@1 { //aqr114c + port_id = <2>; + phy_address = <0>; + ethernet-phy-ieee802.3-c45; + }; +/* port@1 { + port_id = <2>; + phy_address = <30>; + media-type = "sfp"; + };*/ + + }; + }; + }; + + eud@78000 { + status = "disabled"; + }; + + /* EDMA host driver configuration for the board */ + edma@3ab00000 { + qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */ + qcom,txdesc-rings = <12>; /* Total number of Tx desc rings to be provisioned */ + qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */ + qcom,txcmpl-rings = <12>; /* Total number of Tx complete rings to be provisioned */ + qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */ + qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */ + qcom,rxdesc-ring-start = <12>; /* Rx desc ring start ID */ + qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */ + qcom,rx-page-mode = <0>; /* Rx fill ring page mode */ + qcom,tx-map-priority-level = <1>; /* Tx priority level per port */ + qcom,rx-map-priority-level = <1>; /* Rx priority level per core */ + qcom,ppeds-num = <2>; /* Number of PPEDS nodes */ + /* PPE-DS node format: */ + qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node#0 ring and queue map */ + <2 2 2 2 40 8>; /* PPEDS Node#1 ring and queue map */ + qcom,txdesc-map = <8 9 10 11>, /* Port0 per-core Tx ring map */ + <12 13 14 15>, /* Port1 per-core Tx ring map */ + <4 5 6 7>; /* used only for packets from vp*/ + qcom,txdesc-fc-grp-map = <1 2>; /* Per GMAC flow control group map */ + qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */ + qcom,rxdesc-map = <12 13 14 15>; /* Per-core Rx desc ring map */ + qcom,rx-queue-start = <0>; /* Rx queue start */ + qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */ + <1 9 17 25>, /* Priority 1 queues per-core Rx ring map */ + <2 10 18 26>, /* Priority 2 queues per-core Rx ring map */ + <3 11 19 27>, /* Priority 3 queues per-core Rx ring map */ + <4 12 20 28>, /* Priority 4 queues per-core Rx ring map */ + <5 13 21 29>, /* Priority 5 queues per-core Rx ring map */ + <6 14 22 30>, /* Priority 6 queues per-core Rx ring map */ + <7 15 23 31>; /* Priority 7 queues per-core Rx ring map */ + interrupts = <0 163 4>, /* Tx complete ring id #4 IRQ info */ + <0 164 4>, /* Tx complete ring id #5 IRQ info */ + <0 165 4>, /* Tx complete ring id #6 IRQ info */ + <0 166 4>, /* Tx complete ring id #7 IRQ info */ + <0 167 4>, /* Tx complete ring id #8 IRQ info */ + <0 168 4>, /* Tx complete ring id #9 IRQ info */ + <0 169 4>, /* Tx complete ring id #10 IRQ info */ + <0 170 4>, /* Tx complete ring id #11 IRQ info */ + <0 171 4>, /* Tx complete ring id #12 IRQ info */ + <0 172 4>, /* Tx complete ring id #13 IRQ info */ + <0 173 4>, /* Tx complete ring id #14 IRQ info */ + <0 174 4>, /* Tx complete ring id #15 IRQ info */ + <0 139 4>, /* Rx desc ring id #12 IRQ info */ + <0 140 4>, /* Rx desc ring id #13 IRQ info */ + <0 141 4>, /* Rx desc ring id #14 IRQ info */ + <0 142 4>, /* Rx desc ring id #15 IRQ info */ + <0 191 4>, /* Misc error IRQ info */ + <0 160 4>, /* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */ + <0 128 4>, /* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */ + <0 152 4>, /* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */ + <0 161 4>, /* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */ + <0 129 4>, /* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */ + <0 153 4>; /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */ + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + i2c_2: i2c@78b7000 { + status = "ok"; + pinctrl-0 = <&i2c_2_pins>; + pinctrl-names = "default"; + }; + + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + cs-select = <0>; + status = "ok"; + + m25p80@0 { + compatible = "n25q128a11"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /*tpm*/ + spi@78b6000 { + pinctrl-0 = <&spi_1_pins>; + pinctrl-names = "default"; + cs-select = <0>; + status = "ok"; + + tpm: spi-tpm@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,st33htpm-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "okay"; + }; + }; + + dma@7984000 { + status = "ok"; + }; + + nand@79b0000 { + pinctrl-0 = <&qspi_nand_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + usb3@8A00000 { + status = "ok"; + qcom,select-utmi-as-pipe-clk; + dwc3@8A00000 { + /delete-property/ #phy-cells; + /delete-property/ phys; + /delete-property/ phy-names; + }; + }; + + hs_m31phy@7b000 { + status = "ok"; + }; + + phy_x2@4b1000 { + status = "ok"; + }; + + wsi: wsi { + id = <0>; + num_chip = <3>; + }; + + pcie@18000000 { + status = "ok"; + pcie1_rp { + reg = <0 0 0 0 0>; + + qcom,mhi@1 { + reg = <0 0 0 0 0>; + qti,disable-rddm-prealloc; + qti,rddm-seg-len = <0x1000>; +#if defined(__CNSS2__) + qrtr_node_id = <0x31>; + memory-region = <0>, <&mhi_region1>; +#else + memory-region = <&qcn9224_pcie1>; + qcom,board_id = <0x16>; + qcom,wsi = <&wsi>; +#endif + }; + }; + }; + + }; +}; diff --git a/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-ap72tip.dts b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-ap72tip.dts new file mode 100644 index 000000000..6e2bd7cc6 --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-ap72tip.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + + +#ifdef __IPQ_MEM_PROFILE_512_MB__ +#include "ipq5332-512MB-memory.dtsi" +#else +#include "ipq5332-default-memory.dtsi" +#endif + +#include "ipq5332-sercomm-mi01.2.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Sercomm WiFi-7"; + compatible = "sercomm,ap72tip", "qcom,ipq5332"; + interrupt-parent = <&intc>; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + soc { + phy@4b0000 { + status = "disabled"; + }; + + + pcie@20000000 { + status = "disabled"; + pcie0_rp { + reg = <0 0 0 0 0>; + qcom,mhi@2 { + reg = <0 0 0 0 0>; + qti,disable-rddm-prealloc; + qti,rddm-seg-len = <0x1000>; +#if defined(__CNSS2__) + qrtr_node_id = <0x30>; + memory-region = <0>, <&mhi_region0>; +#else + memory-region = <&qcn9224_pcie0>; + qcom,board_id = <0x15>; + qcom,wsi = <&wsi>; +#endif + }; + }; + }; + + pinctrl@1000000 { + button_pins: button_pins { + rst_button { + pins = "gpio1"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + button@1 { + label = "rst"; + linux,code = ; + gpios = <&tlmm 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led@25 { + label = "blue:status"; + gpios = <&tca6416 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@24 { + label = "red:status"; + gpios = <&tca6416 10 GPIO_ACTIVE_HIGH>; + }; + led_power: led@16 { + label = "green:status"; + gpios = <&tca6416 11 GPIO_ACTIVE_HIGH>; + }; + led@61 { + label = "green:phy"; + gpios = <&tca6416 13 GPIO_ACTIVE_HIGH>; + }; + led@62 { + label = "yellow:phy"; + gpios = <&tca6416 14 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +&wifi0 { + qcom,rproc = <&q6_wcss_pd1>; + qcom,rproc_rpd = <&q6v5_wcss>; + qcom,multipd_arch; + qcom,userpd-subsys-name = "q6v5_wcss_userpd1"; +#if defined(__CNSS2__) + mem-region = <&q6_region>; +#else + memory-region = <&q6_region>; + qcom,wsi = <&wsi>; +#endif + qcom,board_id = <0x16>; //orig:0x12->0x16 + status = "ok"; +}; + +&qcn9224_pcie0 { + status = "disabled"; +}; + +&qcn9224_pcie1 { + status = "ok"; +}; + +&mhi_region0 { + status = "disabled"; +}; + +&mhi_region1 { + status = "ok"; +}; + +&wifi1 { + /* QCN9224 radio 5G */ + hremote_node = <&qcn9224_pcie0>; + board_id = <0x15>; + status = "disabled"; +}; + +&wifi2 { + /* QCN9224 5G+6G */ + hremote_node = <&qcn9224_pcie1>; + qcom,board_id = <0x100f>; //0x16->0x1019 + status = "ok"; +}; + +&i2c_0 { + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-mi01.2.dtsi b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-mi01.2.dtsi new file mode 100644 index 000000000..b0d081126 --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm-mi01.2.dtsi @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + +#include "ipq5332-sercomm.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart0; /*console*/ + serial1 = &blsp1_uart1; /*ble*/ + ethernet0 = "/soc/dp1"; + ethernet1 = "/soc/dp2"; + }; + + chosen { + stdout-path = "serial0"; + }; + + soc { + pinctrl@1000000 { + serial_0_pins: serial0-pinmux { /*console*/ + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + + serial_1_pins: serial1-pinmux { /*ble*/ +// pins = "gpio33", "gpio34", "gpio35", "gpio36"; + pins = "gpio33", "gpio35"; + function = "blsp1_uart2"; + drive-strength = <8>; + bias-pull-up; + }; + + //serial_2_pins: serial2-pinmux { /*gps*/ + /* pins = "gpio33", "gpio34", "gpio35", "gpio36"; + function = "blsp1_uart1"; + drive-strength = <8>; + bias-pull-up; + };*/ + + i2c_0_pins: i2c-0-pinmux { + pins = "gpio43", "gpio45"; + function = "blsp2_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + + spi_0_pins: spi0-pinmux { + spi_clock { + pins = "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_mosi { + pins = "gpio15"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_miso { + pins = "gpio16"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-down; + }; + + spi_cs { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_1_pins: spi_1_pins { /* tpm */ + mux { + pins = "gpio29", "gpio30", "gpio31", "gpio32"; + function = "blsp1_spi0"; + drive-strength = <8>; +// bias-disable; + bias-pull-up; + }; + }; + + mdio0_pins: mdio_pinmux { + mux_0 { + pins = "gpio25"; + function = "mdc0"; + drive-strength = <8>; + bias-disable; + }; + mux_1 { + pins = "gpio26"; + function = "mdio0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + mdio1_pins: mdio_pinmux { + mux_0 { + pins = "gpio27"; + function = "mdc1"; + drive-strength = <8>; + bias-disable; + }; + mux_1 { + pins = "gpio28"; + function = "mdio1"; + drive-strength = <8>; + bias-pull-up; + }; + }; +/* + sfp_pins: sfp_pinmux { + sfp_rx { + pins = "gpio45"; + function = "rx1"; + bias-disable; + }; + sfp_tx { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + };*/ + }; + + +#if 1 //AQR114C + dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <1>; + reg = <0x3a500000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + mdio-bus = <&mdio>; + qcom,phy-mdio-addr = <24>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a504000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + qcom,phy-mdio-addr = <0>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + + mdio:mdio@90000 { + status = "ok"; + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + /*gpio0 for napa, gpio3 for AQR114C*/ + //phy-reset-gpio = <&tlmm 0 0 &tlmm 3 0>; + phy-reset-gpio = <&tlmm 0 0>; + + phy0: ethernet-phy@0 { + reg = <24>; + }; + phy1: ethernet-phy@1 { //aqr114c + reg = <0>; + compatible ="ethernet-phy-ieee802.3-c45"; + }; + }; + + ess-instance { + ess-switch@3a000000 { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x0>; /* lan port bitmap */ + switch_wan_bmp = <0x6>; /* wan port bitmap */ + switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1 114c*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <24>; + }; + port@1 { //aqr114c + port_id = <2>; + phy_address = <0>; + ethernet-phy-ieee802.3-c45; + }; + }; + }; + }; + +#else //SFP + + dp1 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <1>; + reg = <0x3a500000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + mdio-bus = <&mdio>; + qcom,phy-mdio-addr = <24>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + dp2 { + device_type = "network"; + compatible = "qcom,nss-dp"; + qcom,id = <2>; + reg = <0x3a504000 0x4000>; + qcom,mactype = <1>; + local-mac-address = [000000000000]; + mdio-bus = <&mdio>; + qcom,phy-mdio-addr = <30>; + qcom,link-poll = <1>; + phy-mode = "sgmii"; + }; + + mdio:mdio@90000 { + status = "ok"; + pinctrl-0 = <&mdio1_pins>; + pinctrl-names = "default"; + /*gpio0 for napa, gpio3 for AQR114C*/ + //phy-reset-gpio = <&tlmm 0 0 &tlmm 3 0>; + phy-reset-gpio = <&tlmm 0 0>; + + phy0: ethernet-phy@0 { + reg = <24>; + }; + }; + + ess-instance { + ess-switch@3a000000 { + switch_cpu_bmp = <0x1>; /* cpu port bitmap */ + switch_lan_bmp = <0x0>; /* lan port bitmap */ + switch_wan_bmp = <0x6>; /* wan port bitmap */ + switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/ + switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1 sfp PORT_WRAPPER_10GBASE_R*/ +// switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1 sfp PORT_WRAPPER_SGMII_PLUS*/ + switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ + qcom,port_phyinfo { + port@0 { + port_id = <1>; + phy_address = <24>; + }; + port@1 { + port_id = <2>; + phy_address = <30>; + media-type = "sfp"; + }; + }; + }; + }; +#endif + + nss-macsec0 { + compatible = "qcom,nss-macsec"; + phy_addr = <24>; + mdiobus = <&mdio>; + }; + + + eud@78000 { + status = "disabled"; + }; + + /* EDMA host driver configuration for the board */ + edma@3ab00000 { + qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */ + qcom,txdesc-rings = <12>; /* Total number of Tx desc rings to be provisioned */ + qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */ + qcom,txcmpl-rings = <12>; /* Total number of Tx complete rings to be provisioned */ + qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */ + qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */ + qcom,rxdesc-ring-start = <12>; /* Rx desc ring start ID */ + qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */ + qcom,rx-page-mode = <0>; /* Rx fill ring page mode */ + qcom,tx-map-priority-level = <1>; /* Tx priority level per port */ + qcom,rx-map-priority-level = <1>; /* Rx priority level per core */ + qcom,ppeds-num = <2>; /* Number of PPEDS nodes */ + /* PPE-DS node format: */ + qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node#0 ring and queue map */ + <2 2 2 2 40 8>; /* PPEDS Node#1 ring and queue map */ + qcom,txdesc-map = <8 9 10 11>, /* Port0 per-core Tx ring map */ + <12 13 14 15>, /* Port1 per-core Tx ring map */ + <4 5 6 7>; /* used only for packets from vp*/ + qcom,txdesc-fc-grp-map = <1 2>; /* Per GMAC flow control group map */ + qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */ + qcom,rxdesc-map = <12 13 14 15>; /* Per-core Rx desc ring map */ + qcom,rx-queue-start = <0>; /* Rx queue start */ + qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */ + <1 9 17 25>, /* Priority 1 queues per-core Rx ring map */ + <2 10 18 26>, /* Priority 2 queues per-core Rx ring map */ + <3 11 19 27>, /* Priority 3 queues per-core Rx ring map */ + <4 12 20 28>, /* Priority 4 queues per-core Rx ring map */ + <5 13 21 29>, /* Priority 5 queues per-core Rx ring map */ + <6 14 22 30>, /* Priority 6 queues per-core Rx ring map */ + <7 15 23 31>; /* Priority 7 queues per-core Rx ring map */ + interrupts = <0 163 4>, /* Tx complete ring id #4 IRQ info */ + <0 164 4>, /* Tx complete ring id #5 IRQ info */ + <0 165 4>, /* Tx complete ring id #6 IRQ info */ + <0 166 4>, /* Tx complete ring id #7 IRQ info */ + <0 167 4>, /* Tx complete ring id #8 IRQ info */ + <0 168 4>, /* Tx complete ring id #9 IRQ info */ + <0 169 4>, /* Tx complete ring id #10 IRQ info */ + <0 170 4>, /* Tx complete ring id #11 IRQ info */ + <0 171 4>, /* Tx complete ring id #12 IRQ info */ + <0 172 4>, /* Tx complete ring id #13 IRQ info */ + <0 173 4>, /* Tx complete ring id #14 IRQ info */ + <0 174 4>, /* Tx complete ring id #15 IRQ info */ + <0 139 4>, /* Rx desc ring id #12 IRQ info */ + <0 140 4>, /* Rx desc ring id #13 IRQ info */ + <0 141 4>, /* Rx desc ring id #14 IRQ info */ + <0 142 4>, /* Rx desc ring id #15 IRQ info */ + <0 191 4>, /* Misc error IRQ info */ + <0 160 4>, /* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */ + <0 128 4>, /* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */ + <0 152 4>, /* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */ + <0 161 4>, /* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */ + <0 129 4>, /* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */ + <0 153 4>; /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */ + }; + + serial@78af000 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + serial@78b0000 { + pinctrl-0 = <&serial_1_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + i2c_0: i2c@78b7000 { + status = "ok"; + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + }; + + + spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + cs-select = <0>; + status = "ok"; + + m25p80@0 { + compatible = "n25q128a11"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /*tpm*/ + spi@78b6000 { + pinctrl-0 = <&spi_1_pins>; + pinctrl-names = "default"; + cs-select = <0>; + status = "ok"; + + tpm: spi-tpm@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,st33htpm-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + status = "okay"; + }; + }; + + dma@7984000 { + status = "ok"; + }; + + nand@79b0000 { + pinctrl-0 = <&qspi_nand_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + usb3@8A00000 { + status = "ok"; + qcom,select-utmi-as-pipe-clk; + dwc3@8A00000 { + /delete-property/ #phy-cells; + /delete-property/ phys; + /delete-property/ phy-names; + }; + }; + + hs_m31phy@7b000 { + status = "ok"; + }; + + phy_x2@4b1000 { + status = "ok"; + }; + + wsi: wsi { + id = <0>; + num_chip = <3>; + }; + + pcie@18000000 { + status = "ok"; + pcie1_rp { + reg = <0 0 0 0 0>; + + qcom,mhi@1 { + reg = <0 0 0 0 0>; + qti,disable-rddm-prealloc; + qti,rddm-seg-len = <0x1000>; +#if defined(__CNSS2__) + qrtr_node_id = <0x31>; + memory-region = <0>, <&mhi_region1>; +#else + memory-region = <&qcn9224_pcie1>; + qcom,board_id = <0x100f>; + qcom,wsi = <&wsi>; +#endif + }; + }; + }; + + }; +}; diff --git a/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm.dtsi b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm.dtsi new file mode 100644 index 000000000..9b4a33e6f --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/files/arch/arm64/boot/dts/qcom/ipq5332-sercomm.dtsi @@ -0,0 +1,2701 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ5332 device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie3x2_phy_pipe_clk: pcie3x2_phy_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie3x1_0_phy_pipe_clk: pcie3x1_0_phy_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + pcie3x1_1_phy_pipe_clk: pcie3x1_1_phy_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_clk_200m: cmn_pll_nss_clk_200m { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_clk_300m: cmn_pll_nss_clk_300m { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + + gcc_gpll0_out_aux: gcc_gpll0_out_aux { + compatible = "fixed-clock"; + clock-frequency = <800000000>; + #clock-cells = <0>; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2-ipq5332"; + opp-shared; + nvmem-cells = <&cpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + /* + * Listed all supported CPU frequencies and opp-supported-hw + * values to select CPU frequencies based on the limits fused. + * ------------------------------------------------------------ + * Frequency BIT3 BIT2 BIT1 BIT0 opp-supported-hw + * 1.0GHz 1.2GHz 1.5GHz No Limit + * ------------------------------------------------------------ + * 1100000000 1 1 1 1 0xF + * 1500000000 0 0 1 1 0x3 + * ----------------------------------------------------------- + */ + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0xF>; + clock-latency-ns = <200000>; + }; + + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + }; + }; + + firmware { + qfprom { + compatible = "qcom,qfprom-sec"; + img-addr = <0x4A100000>; + img-size = <0x00500000>; + scm-cmd-id = <0x1F>; + }; + }; + + qcn9224_legacy_irq0: qcn9224_legacy_irq0 { + compatible = "qcom,qcn9224_legacy_irq"; + status = "ok"; + qrtr_node_id = <0x30>; + qcn9224_in0: legacy_interrupt { + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcn9224_legacy_irq1: qcn9224_legacy_irq1 { + compatible = "qcom,qcn9224_legacy_irq"; + status = "ok"; + qrtr_node_id = <0x31>; + qcn9224_in1: legacy_interrupt { + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + dma-ranges; + compatible = "simple-bus"; + + eud@78000 { + compatible = "qcom,msm-eud"; + reg = <0x78000 0x1000>, + <0x79000 0x2000>, + <0x7a000 0x1000>; + reg-names = "eud_base", + "eud_mode_mgr", + "eud_mode_mgr2"; + interrupts = ; + interrupt-names = "eud_irq"; + qcom,eud-clock-vote-req = <1>; + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "disabled"; + }; + + hs_m31phy_0: hs_m31phy@7b000 { + compatible = "qca,ipq5332-m31-usb-hsphy"; + reg = <0x07b000 0x12C>, + <0x08af8800 0x400>; + reg-names = "m31usb_phy_base", + "qscratch_base"; + phy_type= "utmi"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + reset-names = "usb2_phy_reset"; + + status = "disabled"; + }; + + ssuniphy_0: ssuniphy@4b0000 { + compatible = "qca,ipq5332-uni-ssphy"; + reg = <0x4b0000 0x800>; + clocks = <&gcc GCC_USB0_PIPE_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + clock-names = "pipe_clk", "phy_cfg_ahb_clk", + "phy_ahb_clk"; + + resets = <&gcc GCC_USB0_PHY_BCR>; + reset-names = "por_rst"; + #phy-cells = <0>; + status = "disabled"; + }; + + prng: prng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + qcom,no-qrng-config; + }; + + pcie0_phy: phy@4b0000{ + compatible = "qca,uni-pcie-phy-gen3"; + reg = <0x4b0000 0x800>; + phy-type = "gen3"; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + clock-names = "pipe_clk", + "lane_m_clk", + "lane_s_clk", + "phy_ahb_clk"; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_phy", + "phy_ahb"; + mode-fixed = <2>; /* TBD */ + status = "disabled"; + }; + + /* PHY for PCIE1 single lane mode */ + pcie1_phy: phy@4b1000 { + compatible = "qca,uni-pcie-phy-gen3"; + reg = <0x4b1000 0x800>; + phy-type = "gen3"; + #phy-cells = <0>; + qti,multiplexed-phy; + qti,phy-mux-regs = <&tcsr_q6_block 0x2544>; + phy-ahb-shared-reset; + clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + clock-names = "pipe_clk", + "lane_m_clk", + "lane_s_clk", + "phy_ahb_clk"; + + resets = <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_ahb"; + mode-fixed = <2>; /* TBD */ + status = "disabled"; + }; + + /* PHY for PCIE2 single lane mode */ + pcie2_phy: phy@4b1800 { + compatible = "qca,uni-pcie-phy-gen3"; + reg = <0x4b1800 0x800>; + phy-type = "gen3"; + #phy-cells = <0>; + phy-ahb-shared-reset; + + qti,multiplexed-phy; + qti,phy-mux-regs = <&tcsr_q6_block 0x2544>; + + clocks = <&gcc GCC_PCIE3X1_1_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_1_M_CLK>, + <&gcc GCC_SNOC_PCIE3_1LANE_1_S_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + clock-names = "pipe_clk", + "lane_m_clk", + "lane_s_clk", + "phy_ahb_clk"; + + resets = <&gcc GCC_PCIE3X1_1_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_ahb"; + mode-fixed = <2>; /* TBD */ + status = "disabled"; + }; + + + /* PHY for PCIE1 dual lane mode */ + pcie1_phy_x2: phy_x2@4b1000 { + compatible = "qca,uni-pcie-phy-gen3"; + reg = <0x4b1000 0x1000>; + phy-type = "gen3"; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK>; + + clock-names = "pipe_clk", + "lane_m_clk", + "lane_s_clk", + "phy_ahb_clk"; + + resets = <&gcc GCC_PCIE3X2_PHY_BCR>, + <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>; + reset-names = "phy", + "phy_ahb"; + mode-fixed = <2>; /* TBD */ + x2 = <1>; + status = "disabled"; + }; + + seccrypt: qcom,seccrypt { + compatible = "qcom,seccrypt"; + status = "ok"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x0b000000 0x1000>, /*GICD*/ + <0x0b002000 0x1000>, /*GICC*/ + <0x0b001000 0x1000>, /*GICH*/ + <0x0b004000 0x1000>; /*GICV*/ + interrupts = ; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xffd>; + }; + + v2m1: v2m@1 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x1000 0xffd>; + }; + + v2m2: v2m@2 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x2000 0xffd>; + }; + }; + + lpass: lpass@0xA000000{ + compatible = "qca,lpass-ipq5332"; + reg = <0xA000000 0x3BFFFF>; + clocks = <&gcc GCC_LPASS_SWAY_CLK>, + <&gcc GCC_LPASS_CORE_AXIM_CLK>, + <&gcc GCC_SNOC_LPASS_CFG_CLK>, + <&gcc GCC_PCNOC_LPASS_CLK>; + clock-names = "sway", "axim", "snoc_cfg", "pcnoc"; + resets = <&gcc GCC_LPASS_BCR>; + reset-names = "lpass"; + status = "disabled"; + }; + + pcm: pcm@0xA3C0000{ + compatible = "qca,ipq5332-lpass-pcm"; + reg = <0xA3C0000 0x23014>; + status = "disabled"; + + pcm0: pcm0@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "out0"; + capture_memory = "lpm"; + playback_memory = "lpm"; + voice_loopback = <0>; + slave = <0>; + status = "disabled"; + }; + + pcm1: pcm1@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "out1"; + capture_memory = "lpm"; + playback_memory = "lpm"; + voice_loopback = <0>; + slave = <0>; + status = "disabled"; + }; + + }; + + pcm_lb: pcm_lb@0 { + compatible = "qca,ipq5332-pcm-lb"; + status = "disabled"; + }; + + mdio@90000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio"; + reg = <0x90000 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>; + clock-names = "gcc_mdio_ahb_clk", + "uniphy0_ahb_clk", + "uniphy0_sys_clk", + "uniphy1_ahb_clk", + "uniphy1_sys_clk"; + status = "disabled"; + }; + + ess-instance { + compatible = "qcom,ess-instance"; + ess-switch@3a000000 { + compatible = "qcom,ess-switch-ipq53xx"; + switch_access_mode = "local bus"; + reg = <0x3a000000 0x1000000>; + bm_tick_mode = <0>; /* bm tick mode */ + tm_tick_mode = <0>; /* tm tick mode */ + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_NSSNOC_NSSCC_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_IM_SLEEP_CLK>, + <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>; + clock-names = "cmn_ahb_clk", + "cmn_sys_clk", + "uniphy0_ahb_clk", + "uniphy0_sys_clk", + "uniphy1_ahb_clk", + "uniphy1_sys_clk", + "gcc_nssnoc_nsscc_clk", + "gcc_nsscc_clk", + "gcc_nssnoc_snoc_1_clk", + "gcc_nssnoc_snoc_clk", + "gcc_im_sleep_clk", + "port1_mac_clk", + "port2_mac_clk", + "nss_ppe_clk", + "nss_ppe_cfg_clk", + "nssnoc_ppe_clk", + "nssnoc_ppe_cfg_clk", + "nss_edma_clk", + "nss_edma_cfg_clk", + "nss_ppe_ipe_clk", + "nss_ppe_btq_clk", + "nss_port1_rx_clk", + "nss_port1_tx_clk", + "nss_port2_rx_clk", + "nss_port2_tx_clk", + "uniphy0_port1_rx_clk", + "uniphy0_port1_tx_clk", + "uniphy1_port5_rx_clk", + "uniphy1_port5_tx_clk"; + resets = <&nsscc NSS_CC_PPE_BCR>, + <&gcc GCC_UNIPHY0_BCR>, + <&gcc GCC_UNIPHY1_BCR>, + <&gcc GCC_UNIPHY0_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY1_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY0_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY1_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY0_XPCS_ARES>, + <&gcc GCC_UNIPHY1_XPCS_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_MAC_CLK_ARES>, + <&nsscc NSS_CC_PORT2_MAC_CLK_ARES>; + reset-names = "ppe_rst", + "uniphy0_soft_rst", + "uniphy1_soft_rst", + "uniphy0_ahb_rst", + "uniphy1_ahb_rst", + "uniphy0_sys_rst", + "uniphy1_sys_rst", + "uniphy0_xpcs_rst", + "uniphy1_xpcs_rst", + "uniphy_port1_rx_rst", + "uniphy_port1_tx_rst", + "uniphy_port2_rx_rst", + "uniphy_port2_tx_rst", + "nss_port1_rx_rst", + "nss_port1_tx_rst", + "nss_port2_rx_rst", + "nss_port2_tx_rst", + "nss_port1_mac_rst", + "nss_port2_mac_rst"; + + port_scheduler_resource { + port@0 { + port_id = <0>; + ucast_queue = <0 43>; + mcast_queue = <256 262>; + l0sp = <0 6>; + l0cdrr = <0 27>; + l0edrr = <0 27>; + l1cdrr = <0 0>; + l1edrr = <0 0>; + }; + port@1 { + port_id = <1>; + ucast_queue = <204 211>; + mcast_queue = <272 275>; + l0sp = <51 52>; + l0cdrr = <108 115>; + l0edrr = <108 115>; + l1cdrr = <23 24>; + l1edrr = <23 24>; + }; + port@2 { + port_id = <2>; + ucast_queue = <212 219>; + mcast_queue = <276 279>; + l0sp = <53 54>; + l0cdrr = <116 123>; + l0edrr = <116 123>; + l1cdrr = <25 26>; + l1edrr = <25 26>; + }; + reserved { + ucast_queue = <44 203>; + mcast_queue = <263 271>; + l0sp = <7 50>; + l0cdrr = <28 107>; + l0edrr = <28 107>; + l1cdrr = <1 22>; + l1edrr = <1 22>; + }; + }; + + port_scheduler_config { + port@0 { + port_id = <0>; + l1scheduler { + group@0 { + /* L0 SP */ + sp = <0 1 2 3 4 5 6>; + /* cpri cdrr epri edrr */ + cfg = <0 0 0 0>; + }; + }; + l0scheduler { + group@0 { + /* unicast queue */ + ucast_queue = <0>; + ucast_loop_pri = <4>; + /* multicast queue */ + mcast_queue = <256>; + /* sp cpri cdrr epri edrr */ + cfg = <0 0 0 0 0>; + }; + group@1 { + ucast_queue = <4>; + ucast_loop_pri = <4>; + cfg = <0 0 0 0 0>; + }; + group@2 { + ucast_queue = <8>; + ucast_loop_pri = <4>; + mcast_queue = <257>; + cfg = <1 0 4 0 4>; + }; + group@3 { + ucast_queue = <12>; + ucast_loop_pri = <4>; + cfg = <1 0 4 0 4>; + }; + group@4 { + ucast_queue = <16>; + ucast_loop_pri = <4>; + mcast_queue = <258>; + cfg = <2 0 8 0 8>; + }; + group@5 { + ucast_queue = <20>; + ucast_loop_pri = <4>; + cfg = <2 0 8 0 8>; + }; + group@6 { + ucast_queue = <24>; + ucast_loop_pri = <4>; + mcast_queue = <259>; + cfg = <3 0 12 0 12>; + }; + group@7 { + ucast_queue = <28>; + ucast_loop_pri = <4>; + cfg = <3 0 12 0 12>; + }; + group@8 { + ucast_queue = <32>; + ucast_loop_pri = <4>; + mcast_queue = <260>; + cfg = <4 0 16 0 16>; + }; + group@9 { + ucast_queue = <36>; + ucast_loop_pri = <4>; + mcast_queue = <261>; + cfg = <5 0 20 0 20>; + }; + group@10 { + ucast_queue = <40>; + ucast_loop_pri = <4>; + mcast_queue = <262>; + cfg = <6 0 24 0 24>; + }; + }; + }; + port@1 { + port_id = <1>; + l1scheduler { + group@0 { + sp = <51>; + cfg = <0 23 0 23>; + }; + group@1 { + sp = <52>; + cfg = <1 24 1 24>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <204>; + ucast_loop_pri = <8>; + /* max priority per SP */ + ucast_max_pri = <4>; + mcast_queue = <272>; + mcast_loop_pri = <4>; + cfg = <51 0 108 0 108>; + }; + }; + }; + port@2 { + port_id = <2>; + l1scheduler { + group@0 { + sp = <53>; + cfg = <0 25 0 25>; + }; + group@1 { + sp = <54>; + cfg = <1 26 1 26>; + }; + }; + l0scheduler { + group@0 { + ucast_queue = <212>; + ucast_loop_pri = <8>; + ucast_max_pri = <4>; + mcast_queue = <276>; + mcast_loop_pri = <4>; + cfg = <53 0 116 0 116>; + }; + }; + }; + }; + }; + }; + + edma@3ab00000 { + compatible = "qcom,edma"; + reg = <0x3ab00000 0xed000>; + reg-names = "edma-reg-base"; + reset-names = "edma_rst"; + clocks = <&nsscc NSS_CC_NSS_CSR_CLK>, + <&nsscc NSS_CC_NSSNOC_NSS_CSR_CLK>, + <&nsscc NSS_CC_CE_APB_CLK>, + <&nsscc NSS_CC_CE_AXI_CLK>, + <&nsscc NSS_CC_NSSNOC_CE_APB_CLK>, + <&nsscc NSS_CC_NSSNOC_CE_AXI_CLK>, + <&gcc GCC_NSS_TS_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSCFG_CLK>, + <&gcc GCC_NSSNOC_ATB_CLK>, + <&gcc GCC_NSSNOC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_PCNOC_1_CLK>, + <&gcc GCC_NSSNOC_QOSGEN_REF_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>, + <&gcc GCC_NSSNOC_XO_DCD_CLK>, + <&gcc GCC_SNOC_NSSNOC_CLK>, + <&gcc GCC_SNOC_NSSNOC_1_CLK>, + <&gcc GCC_MEM_NOC_AHB_CLK>, + <&gcc GCC_MEM_NOC_SNOC_AXI_CLK>, + <&gcc GCC_MEM_NOC_APSS_AXI_CLK>, + <&gcc GCC_MEM_NOC_QOSGEN_EXTREF_CLK>, + <&gcc GCC_MEM_NOC_TS_CLK>; + clock-names = "nss-csr-clk", "nss-nssnoc-csr-clk", "nss-ce-ahb-clk", + "nss-ce-axi-clk", "nss-nssnoc-ce-ahb-clk", "nss-nssnoc-ce-axi-clk", + "nss-ts-clk", "nss-nsscc-clk", "nss-nsscfg-clk", "nss-nssnoc-atb-clk", + "nss-nssnoc-nsscc-clk", "nss-nssnoc-pcnoc-1-clk", "nss-nssnoc-qosgen-ref-clk", + "nss-nssnoc-snoc-1-clk", "nss-nssnoc-snoc-clk", "nss-nssnoc-timeout-ref-clk", + "nss-nssnoc-xo-dcd-clk", "nss-snoc-nssnoc-clk", "nss-snoc-nssnoc-1-clk", + "nss-mem-noc-ahb-clk", "nss-mem-noc-snoc-axi-clk", "nss-mem-noc-apss-axi-clk", + "nss-mem-noc-qosgen-extref-clk","nss-mem-noc-ts-clk"; + }; + + ess-uniphy@7a00000 { + compatible = "qcom,ess-uniphy"; + reg = <0x7a00000 0x20000>; + uniphy_access_mode = "local bus"; + }; + + nss-ppe { + compatible = "qcom,nss-ppe"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + watchdog: watchdog@b017000 { + compatible = "qcom,kpss-wdt"; + reg = <0xb017000 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <24000000>; + + frame@b120000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupt-controller; + #interrupt-cells = <2>; + emmc_pins: emmc_pins { + emmc_clk { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + emmc_cmd { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + emmc_data { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pci0_pin: pci0-pinmux { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + pci1_pin: pci1-pinmux { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + pci2_pin: pci2-pinmux { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + qspi_nand_pins: qspi_nand_pins { + qspi_clock { + pins = "gpio13"; + function = "qspi_clk"; + drive-strength = <8>; + bias-pull-down; + }; + + qspi_cs { + pins = "gpio12"; + function = "qspi_cs"; + drive-strength = <8>; + bias-pull-up; + }; + + qspi_data { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qspi_data"; + drive-strength = <8>; + bias-pull-down; + }; + }; + +/* button_pins: button_pins { + wps_button { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + };*/ + + bt_pins: bt_pins { + PTA_0 { + pins = "gpio49"; + function = "PTA_0"; + drive-strength = <8>; + bias-disable; + }; + PTA_1 { + pins = "gpio50"; + function = "PTA_1"; + drive-strength = <8>; + bias-disable; + }; + PTA_2 { + pins = "gpio51"; + function = "PTA_2"; + drive-strength = <8>; + bias-disable; + }; +/* bt_reset { + pins = "gpio32"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + };*/ + + }; + }; + + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq5332"; + reg = <0x1800000 0x80000>; + clocks = <&xo>, + <&sleep_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&pcie3x2_phy_pipe_clk>, + <&pcie3x1_0_phy_pipe_clk>, + <&pcie3x1_1_phy_pipe_clk>; + clock-names = "xo", + "sleep_clk", + "usb3phy_0_cc_pipe_clk", + "pcie3x2_phy_pipe_clk", + "pcie3x1_0_phy_pipe_clk", + "pcie3x1_1_phy_pipe_clk"; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + + nsscc: nsscc@39b00000{ + compatible = "qcom,nsscc-ipq5332"; + reg = <0x39b00000 0x80000>; + clocks = <&xo>, + <&cmn_pll_nss_clk_200m>, + <&cmn_pll_nss_clk_300m>, + <&gcc_gpll0_out_aux>; + clock-names = "xo", + "cmn_pll_nss_clk_200m", + "cmn_pll_nss_clk_300m", + "gcc_gpll0_out_aux"; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + + dcc@797f000 { + compatible = "qcom,dcc-v2-ipq5332"; + reg = <0x40ff000 0x1000>, + <0x4080000 0x800>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x0>; + status = "disabled"; + }; + + pwm { + compatible = "qti,ipq5332-pwm"; + reg = <0x1941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + clock-names = "core"; + src-freq = <100000000>; + pwm-base-index = <0>; + used-pwm-indices = <1>, <1>, <1>, <1>; + status = "disabled"; + }; + + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1d000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + sdhc_1: sdhci@7804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>, <0x7805000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&xo>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "xo", "iface", "core"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + non-removable; + status = "disabled"; + }; + + spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078b5000 0x600>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + +/* spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078b7000 0x600>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + };*/ + + spi1: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078b6000 0x600>; + interrupts = ; + spi-max-frequency = <50000000>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + +/* i2c_0: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c_1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + dmas = <&blsp_dma 7>, <&blsp_dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + };*/ + + + i2c_2: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x7984000 0x1c000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + nand: nand@79b0000 { + compatible = "qcom,ipq5332-nand"; + reg = <0x79b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "io_macro"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>, + <&qpic_bam 3>; + dma-names = "tx", "rx", "cmd", "sts"; + qcom,io_macro_max_clk = <320000000>; + qcom,io_macro_clk_rates = <24000000 100000000 200000000 \ + 320000000>; + status = "disabled"; + + nandcs@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; + }; + + tcsr_boot_misc: syscon@193d100 { + compatible = "syscon"; + reg = <0x0193d100 0x4>; + }; + + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x01905000 0x8000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 0>; + }; + + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr_boot_misc 0>; + }; + + usb3: usb3@8A00000 { + compatible = "qcom,ipq5018-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + reg = <0x8AF8800 0x100>, + <0x8A00000 0xe000>; + reg-names = "qscratch_base", "dwc3_base"; + + clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_LFPS_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + + clock-names = "master", + "sleep", + "mock_utmi", + "cfg_ahb_clk", + "aux_clk", + "lfps_clk", + "pipe_clk"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>, + <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_LFPS_CLK>; + + assigned-clock-rates = <133330000>, + <60000000>, + <2000000>, + <25000000>; + + resets = <&gcc GCC_USB_BCR>; + + qca,host = <1>; + qcom,phy-mux-regs = <&tcsr_q6_block 0x2540>; + status = "disabled"; + + dwc_0: dwc3@8A00000 { + compatible = "snps,dwc3"; + reg = <0x8A00000 0xe000>; + interrupts = ; + usb-phy = <&hs_m31phy_0>; + #phy-cells = <0>; + phys = <&ssuniphy_0>; + phy-names = "usb3-phy"; + snps,dis_ep_cache_eviction; + tx-fifo-resize; + snps,usb3-u1u2-disable; + snps,nominal-elastic-buffer; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-ref-clock-adjustment = <0x49459>; + snps,quirk-ref-clock-period = <0x10>; + snps,quirk-30m-sb-sel = <0x0>; + dr_mode = "host"; + }; + }; + + + eip: eip196@39800000 { + compatible = "qcom,eip"; + reg-names = "eip_pbase"; + reg = <0x39800000 0x7ffff>; + reg_offset = <0x80000>; + ranges; + clocks = <&nsscc NSS_CC_EIP_CLK>, + <&nsscc NSS_CC_NSSNOC_EIP_CLK>; + clock-names = "eip_clk", "eip_nocclk"; + clock-frequency = /bits/ 64 <300000000 300000000>; + status = "ok"; + interrupts = , + , + , + ; + + dma0 { + tx_cpu = /bits/ 8 <0>; + rx_cpu = /bits/ 8 <0>; + ring-name = "lookaside"; + ring-id = /bits/ 8 <0>; + }; + + dma1 { + tx_cpu = /bits/ 8 <1>; + rx_cpu = /bits/ 8 <1>; + ring-name = "lookaside"; + ring-id = /bits/ 8 <1>; + }; + + dma2 { + tx_cpu = /bits/ 8 <2>; + rx_cpu = /bits/ 8 <2>; + ring-name = "lookaside"; + ring-id = /bits/ 8 <2>; + }; + + dma3 { + tx_cpu = /bits/ 8 <3>; + rx_cpu = /bits/ 8 <3>; + ring-name = "lookaside"; + ring-id = /bits/ 8 <3>; + }; + }; + + eip_crypto: eip_crypto { + compatible = "qcom,eip_crypto"; + status = "ok"; + }; + + /* 1L controller with 2L/2x1L Flexible PHY 2nd lane */ + pcie2: pcie@10000000 { + pinctrl-0 = <&pci2_pin>; + pinctrl-names = "default"; + compatible = "qti,pcie-ipq5332"; + reg = <0x10000000 0xf1d + 0x10000F20 0xa8 + 0x10001000 0x1000 + 0xf0000 0x3000 + 0x10100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + axi-halt-val = <0x1e>; /* increase halt window size to 1GB */ + + ranges = <0x81000000 0 0x10200000 0x10200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x10300000 0x10300000 + 0 0x7d00000>; /* non-prefetchable memory */ + + phys = <&pcie2_phy>; + phy-names = "pciephy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 399 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 400 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 401 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 402 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + clocks = <&gcc GCC_PCIE3X1_1_AXI_M_CLK>, + <&gcc GCC_PCIE3X1_1_AXI_S_CLK>, + <&gcc GCC_PCIE3X1_1_AHB_CLK>, + <&gcc GCC_PCIE3X2_AUX_CLK>, + <&gcc GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X1_1_RCHG_CLK>; + + clock-names = "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge", + "rchng"; + + axi-m-clk-rate = <240000000>; + axi-s-clk-rate = <240000000>; + aux-clk-rate = <2000000>; + + resets = <&gcc GCC_PCIE3X1_1_PIPE_ARES>, + <&gcc GCC_PCIE3X1_1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X1_1_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X1_1_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X1_1_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X1_1_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X1_1_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_1_AUX_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_m", + "axi_s", + "axi_m_sticky", + "axi_s_sticky", + "ahb", + "aux"; + + msi-parent = <&v2m0>; + max-payload-size = <1>; + perst-gpio = <&tlmm 44 GPIO_ACTIVE_LOW>; + status = "disabled"; + nvmem-cells = <&pcie2_disable>; + + pcie2_rp: pcie2_rp { + reg = <0 0 0 0 0>; + }; + }; + + /* 2L controller with 2L/2x1L Flexible PHY. + * Connected to the 1st lane of the Flexible PHY in 1L mode + */ + pcie1: pcie@18000000 { + pinctrl-0 = <&pci1_pin>; + pinctrl-names = "default"; + compatible = "qti,pcie-ipq5332"; + reg = <0x18000000 0xf1d + 0x18000F20 0xa8 + 0x18001000 0x1000 + 0x88000 0x3000 + 0x18100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + slv-addr-space-sz = <0x8000000>; + axi-halt-val = <0x1e>; /* increase halt window size to 1GB */ + + phys = <&pcie1_phy_x2>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x18200000 0x18200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x18300000 0x18300000 + 0 0x7d00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 412 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 413 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 414 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 415 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_CLK>, + <&gcc GCC_PCIE3X2_AHB_CLK>, + <&gcc GCC_PCIE3X2_AUX_CLK>, + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X2_RCHG_CLK>; + + clock-names = "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge", + "rchng"; + + axi-m-clk-rate = <266666667>; + axi-s-clk-rate = <240000000>; + aux-clk-rate = <2000000>; + + resets = <&gcc GCC_PCIE3X2_PIPE_ARES>, + <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X2_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X2_AUX_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_m", + "axi_s", + "axi_m_sticky", + "axi_s_sticky", + "ahb", + "aux"; + + msi-parent = <&v2m0>; + max-payload-size = <1>; + perst-gpio = <&tlmm 47 GPIO_ACTIVE_LOW>; + status = "disabled"; + nvmem-cells = <&pcie1_disable>; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; + + /* 1L controller with USB/PCIe combo PHY */ + pcie0: pcie@20000000 { + pinctrl-0 = <&pci0_pin>; + pinctrl-names = "default"; + compatible = "qti,pcie-ipq5332"; + reg = <0x20000000 0xf1d + 0x20000F20 0xa8 + 0x20001000 0x1000 + 0x80000 0x3000 + 0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + axi-halt-val = <0x1e>; /* increase halt window size to 1GB */ + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0x20200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x20300000 0x20300000 + 0 0xfd00000>; /* non-prefetchable memory */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 35 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 36 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 37 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 38 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interrupts = ; + interrupt-names = "global_irq"; + + clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, + <&gcc GCC_PCIE3X1_0_AHB_CLK>, + <&gcc GCC_PCIE3X1_0_AUX_CLK>, + <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3X1_0_RCHG_CLK>; + + clock-names = "axi_m", + "axi_s", + "ahb", + "aux", + "axi_bridge", + "rchng"; + + axi-m-clk-rate = <240000000>; + axi-s-clk-rate = <240000000>; + aux-clk-rate = <2000000>; + + resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>, + <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>; + + reset-names = "pipe", + "sticky", + "axi_m", + "axi_s", + "axi_m_sticky", + "axi_s_sticky", + "ahb", + "aux"; + + msi-parent = <&v2m0>; + max-payload-size = <1>; + perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "disabled"; + nvmem-cells = <&pcie0_disable>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5332-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + #clock-cells = <1>; + #mbox-cells = <1>; + }; + + wifi0: wifi@c0000000 { + compatible = "qcom,cnss-qca5332", "qcom,ipq5332-wifi"; + reg = <0xc000000 0x1000000>; + #ifdef __IPQ_MEM_PROFILE_256_MB__ + qcom,tgt-mem-mode = <2>; + #elif __IPQ_MEM_PROFILE_512_MB__ + qcom,tgt-mem-mode = <1>; + #else + qcom,tgt-mem-mode = <0>; + #endif + qcom,rproc = <&q6v5_wcss>; + qcom,bdf-addr = <0x4B500000 0x4B500000 0x4B500000 + 0x0 0x0 0x0>; + qcom,caldb-addr = <0x4CE00000 0x4CE00000 0x0 + 0x0 0x0 0x0>; + qcom,caldb-size = <0x500000>; + interrupts = <0 559 1>, /* misc-pulse1 */ + <0 560 1>, /* misc-latch */ + <0 561 1>, /* sw-exception */ + <0 422 1>, /* ce0 */ + <0 423 1>, /* ce1 */ + <0 424 1>, /* ce2 */ + <0 425 1>, /* ce3 */ + <0 426 1>, /* ce4 */ + <0 427 1>, /* ce5 */ + <0 428 1>, /* ce6 */ + <0 429 1>, /* ce7 */ + <0 430 1>, /* ce8 */ + <0 431 1>, /* ce9 */ + <0 432 1>, /* ce10 */ + <0 433 1>, /* ce11 */ + <0 491 1>, /* host2wbm-desc-feed */ + <0 495 1>, /* host2reo-re-injection */ + <0 493 1>, /* host2reo-command */ + <0 544 1>, /* host2rxdma-monitor-ring1 */ + <0 457 1>, /* reo2ost-exception */ + <0 466 1>, /* wbm2host-rx-release */ + <0 497 1>, /* reo2host-status */ + <0 454 1>, /* reo2host-destination-ring4 */ + <0 453 1>, /* reo2host-destination-ring3 */ + <0 452 1>, /* reo2host-destination-ring2 */ + <0 451 1>, /* reo2host-destination-ring1 */ + <0 488 1>, /* rxdma2host-monitor-destination-mac3 */ + <0 488 1>, /* rxdma2host-monitor-destination-mac2 */ + <0 484 1>, /* rxdma2host-monitor-destination-mac1 */ + <0 554 1>, /* host2rxdma-host-buf-ring-mac3 */ + <0 554 1>, /* host2rxdma-host-buf-ring-mac2 */ + <0 549 1>, /* host2rxdma-host-buf-ring-mac1 */ + <0 507 1>, /* host2tcl-input-ring4 */ + <0 500 1>, /* host2tcl-input-ring3 */ + <0 499 1>, /* host2tcl-input-ring2 */ + <0 498 1>, /* host2tcl-input-ring1 */ + <0 450 1>, /* wbm2host-tx-completions-ring4 */ + <0 449 1>, /* wbm2host-tx-completions-ring3 */ + <0 448 1>, /* wbm2host-tx-completions-ring2 */ + <0 447 1>, /* wbm2host-tx-completions-ring1 */ + <0 543 1>, /* host2tx-monitor-ring1 */ + <0 486 1>, /* txmon2host-monitor-destination-mac3 */ + <0 486 1>, /* txmon2host-monitor-destination-mac2 */ + <0 482 1>, /* txmon2host-monitor-destination-mac1 */ + <0 419 1>, /* umac_reset */ + /* Unused Interrupts */ + <0 558 1>, /* host2rxdma-monitor-ring3 */ + <0 558 1>, /* host2rxdma-monitor-ring2 */ + <0 558 1>, /* ppdu-end-interrupts-mac3 */ + <0 558 1>, /* ppdu-end-interrupts-mac2 */ + <0 558 1>, /* ppdu-end-interrupts-mac1 */ + <0 558 1>, /* rxdma2host-monitor-status-ring-mac3 */ + <0 558 1>, /* rxdma2host-monitor-status-ring-mac2 */ + <0 558 1>, /* rxdma2host-monitor-status-ring-mac1 */ + <0 558 1>, /* rxdma2host-destination-ring-mac3 */ + <0 558 1>, /* rxdma2host-destination-ring-mac2 */ + <0 558 1>; /* rxdma2host-destination-ring-mac1 */ + + interrupt-names = "misc-pulse1", + "misc-latch", + "sw-exception", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring4", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "host2tx-monitor-ring1", + "txmon2host-monitor-destination-mac3", + "txmon2host-monitor-destination-mac2", + "txmon2host-monitor-destination-mac1", + "umac_reset", + /* Unused Interrupts */ + "host2rxdma-monitor-ring3", + "host2rxdma-monitor-ring2", + "ppdu-end-interrupts-mac3", + "ppdu-end-interrupts-mac2", + "ppdu-end-interrupts-mac1", + "rxdma2host-monitor-status-ring-mac3", + "rxdma2host-monitor-status-ring-mac2", + "rxdma2host-monitor-status-ring-mac1", + "rxdma2host-destination-ring-mac3", + "rxdma2host-destination-ring-mac2", + "rxdma2host-destination-ring-mac1"; + /* 36 indicates GPIO number for LED_2G. + * 0 indicates that the GPIO is active high. + */ + led-gpio = <&tlmm 36 0>; + status = "disabled"; + qcom,pta-num = <0>; + qcom,coex-mode = <0x2>; + qcom,bt-active-time = <0x18>; + qcom,bt-priority-time = <0x12>; + qcom,coex-algo = <0x2>; + qcom,pta-priority = <0x80800505>; + }; + + wifi1: wifi1@f00000 { + compatible = "qcom,cnss-qcn9224"; + qcom,wlan-ramdump-dynamic = <0x600000>; + qrtr_node_id = <0x30>; + qca,auto-restart; + status = "disabled"; + interrupt-bmap = <0x100512>; +#ifdef __IPQ_MEM_PROFILE_512_MB__ + /* qcn9224 tgt-mem-mode=1 layout - 37MB + * +=========+==============+=========+ + * | Region | Start Offset | Size | + * +---------+--------------+---------+ + * | HREMOTE | 0x4EC00000 | 20MB | + * +---------+--------------+---------+ + * | M3 Dump | 0x50000000 | 1MB | + * +---------+--------------+---------+ + * | ETR | 0x50100000 | 1MB | + * +---------+--------------+---------+ + * | Caldb | 0x50200000 | 8MB | + * +---------+--------------+---------+ + * |Pageable | 0x50A00000 | 7MB | + * +==================================+ + */ + base-addr = <0x4EC00000>; + m3-dump-addr = <0x50000000>; + etr-addr = <0x50100000>; + caldb-addr = <0x50200000>; + pageable-addr = <0x50A00000>; + hremote-size = <0x1400000>; + pageable-size = <0x700000>; + tgt-mem-mode = <0x1>; +#else + /* qcn9224 tgt-mem-mode=0 layout - 50MB + * +=========+==============+=========+ + * | Region | Start Offset | Size | + * +---------+--------------+---------+ + * | HREMOTE | 0x4EC00000 | 28MB | + * +---------+--------------+---------+ + * | M3 Dump | 0x50800000 | 1MB | + * +---------+--------------+---------+ + * | ETR | 0x50900000 | 1MB | + * +---------+--------------+---------+ + * | Caldb | 0x50A00000 | 8MB | + * +---------+--------------+---------+ + * |Pageable | 0x51200000 | 12MB | + * +==================================+ + */ + base-addr = <0x4EC00000>; + m3-dump-addr = <0x50800000>; + etr-addr = <0x50900000>; + caldb-addr = <0x50A00000>; + pageable-addr = <0x51200000>; + hremote-size = <0x1C00000>; + pageable-size = <0xC00000>; + tgt-mem-mode = <0x0>; +#endif + caldb-size = <0x800000>; + qca,extended-intc; + interrupts-extended = + <&qcn9224_in0 5 0>, + <&qcn9224_in0 6 0>, + <&qcn9224_in0 7 0>, + <&qcn9224_in0 8 0>, + <&qcn9224_in0 9 0>, + <&qcn9224_in0 10 0>, + <&qcn9224_in0 11 0>, + <&qcn9224_in0 12 0>, + <&qcn9224_in0 13 0>, + <&qcn9224_in0 14 0>, + <&qcn9224_in0 15 0>, + <&qcn9224_in0 16 0>, + <&qcn9224_in0 17 0>, + <&qcn9224_in0 18 0>, + <&qcn9224_in0 19 0>, + <&qcn9224_in0 20 0>, + <&qcn9224_in0 49 0>, + <&qcn9224_in0 48 0>, + <&qcn9224_in0 47 0>, + <&qcn9224_in0 46 0>, + <&qcn9224_in0 45 0>, + <&qcn9224_in0 44 0>, + <&qcn9224_in0 43 0>, + <&qcn9224_in0 42 0>, + <&qcn9224_in0 50 0>, + <&qcn9224_in0 52 0>, + <&qcn9224_in0 51 0>, + <&qcn9224_in0 30 0>, + <&qcn9224_in0 29 0>, + <&qcn9224_in0 28 0>, + <&qcn9224_in0 27 0>, + <&qcn9224_in0 26 0>, + <&qcn9224_in0 25 0>, + <&qcn9224_in0 31 0>, + <&qcn9224_in0 80 0>, + <&qcn9224_in0 71 0>, + <&qcn9224_in0 96 0>, + <&qcn9224_in0 97 0>, + <&qcn9224_in0 67 0>, + <&qcn9224_in0 100 0>, + <&qcn9224_in0 99 0>, + <&qcn9224_in0 68 0>, + <&qcn9224_in0 69 0>, + <&qcn9224_in0 121 0>, + <&qcn9224_in0 119 0>, + <&qcn9224_in0 122 0>, + <&qcn9224_in0 120 0>, + <&qcn9224_in0 116 0>, + <&qcn9224_in0 113 0>, + <&qcn9224_in0 115 0>, + <&qcn9224_in0 112 0>, + <&qcn9224_in0 114 0>, + <&qcn9224_in0 111 0>, + <&qcn9224_in0 110 0>, + <&qcn9224_in0 109 0>, + <&qcn9224_in0 108 0>, + <&qcn9224_in0 39 0>, + <&qcn9224_in0 38 0>, + <&qcn9224_in0 37 0>, + <&qcn9224_in0 36 0>, + <&qcn9224_in0 35 0>, + <&qcn9224_in0 34 0>, + <&qcn9224_in0 33 0>, + <&qcn9224_in0 41 0>, + <&qcn9224_in0 40 0>, + <&qcn9224_in0 32 0>, + <&qcn9224_in0 24 0>, + <&qcn9224_in0 23 0>, + <&qcn9224_in0 22 0>, + <&qcn9224_in0 21 0>, + <&qcn9224_in0 66 0>, + <&qcn9224_in0 78 0>, + <&qcn9224_in0 117 0>, + <&qcn9224_in0 118 0>, + <&qcn9224_in0 61 0>, + <&qcn9224_in0 60 0>, + <&qcn9224_in0 57 0>, + <&qcn9224_in0 56 0>, + <&qcn9224_in0 63 0>, + <&qcn9224_in0 62 0>, + <&qcn9224_in0 59 0>, + <&qcn9224_in0 58 0>, + <&qcn9224_in0 65 0>, + <&qcn9224_in0 83 0>, + <&qcn9224_in0 75 0>, + <&qcn9224_in0 82 0>, + <&qcn9224_in0 81 0>, + <&qcn9224_in0 74 0>, + <&qcn9224_in0 73 0>, + <&qcn9224_in0 72 0>, + <&qcn9224_in0 98 0>, + <&qcn9224_in0 107 0>, + <&qcn9224_in0 106 0>, + <&qcn9224_in0 105 0>, + <&qcn9224_in0 104 0>, + <&qcn9224_in0 103 0>, + <&qcn9224_in0 102 0>, + <&qcn9224_in0 101 0>, + <&qcn9224_in0 76 0>, + <&qcn9224_in0 77 0>, + <&qcn9224_in0 143 0>, + <&qcn9224_in0 142 0>, + <&qcn9224_in0 141 0>, + <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "ce12", + "ce13", + "ce14", + "ce15", + "reo2sw8_intr2", + "reo2sw7_intr2", + "reo2sw6_intr2", + "reo2sw5_intr2", + "reo2sw4_intr2", + "reo2sw3_intr2", + "reo2sw2_intr2", + "reo2sw1_intr2", + "reo2sw0_intr2", + "reo2sw8_intr", + "reo2sw7_intr", + "reo2sw6_inrr", + "reo2sw5_intr", + "reo2sw4_intr", + "reo2sw3_intr", + "reo2sw2_intr", + "reo2sw1_intr", + "reo2sw0_intr", + "reo2status_intr2", + "reo_status", + "reo2rxdma_out_2", + "reo2rxdma_out_1", + "reo_cmd", + "sw2reo6", + "sw2reo5", + "sw2reo1", + "sw2reo", + "rxdma2reo_mlo_0_dst_ring1", + "rxdma2reo_mlo_0_dst_ring0", + "rxdma2reo_mlo_1_dst_ring1", + "rxdma2reo_mlo_1_dst_ring0", + "rxdma2reo_dst_ring1", + "rxdma2reo_dst_ring0", + "rxdma2sw_dst_ring1", + "rxdma2sw_dst_ring0", + "rxdma2release_dst_ring1", + "rxdma2release_dst_ring0", + "sw2rxdma_2_src_ring", + "sw2rxdma_1_src_ring", + "sw2rxdma_0", + "wbm2sw6_release2", + "wbm2sw5_release2", + "wbm2sw4_release2", + "wbm2sw3_release2", + "wbm2sw2_release2", + "wbm2sw1_release2", + "wbm2sw0_release2", + "wbm2sw6_release", + "wbm2sw5_release", + "wbm2sw4_release", + "wbm2sw3_release", + "wbm2sw2_release", + "wbm2sw1_release", + "wbm2sw0_release", + "wbm2sw_link", + "wbm_error_release", + "sw2txmon_src_ring", + "sw2rxmon_src_ring", + "txmon2sw_p1_intr1", + "txmon2sw_p1_intr0", + "txmon2sw_p0_dest1", + "txmon2sw_p0_dest0", + "rxmon2sw_p1_intr1", + "rxmon2sw_p1_intr0", + "rxmon2sw_p0_dest1", + "rxmon2sw_p0_dest0", + "sw_release", + "sw2tcl_credit2", + "sw2tcl_credit", + "sw2tcl4", + "sw2tcl5", + "sw2tcl3", + "sw2tcl2", + "sw2tcl1", + "sw2wbm1", + "misc_8", + "misc_7", + "misc_6", + "misc_5", + "misc_4", + "misc_3", + "misc_2", + "misc_1", + "misc_0", + "mhi2", + "mhi1", + "mhi0", + "inta"; + }; + + + wifi2: wifi2@f00000 { + compatible = "qcom,cnss-qcn9224"; + qcom,wlan-ramdump-dynamic = <0x600000>; + qrtr_node_id = <0x31>; + qca,auto-restart; + status = "disabled"; + interrupt-bmap = <0x100512>; +#ifdef __IPQ_MEM_PROFILE_512_MB__ + /* qcn9224 tgt-mem-mode=1 layout - 37MB + * +=========+==============+=========+ + * | Region | Start Offset | Size | + * +---------+--------------+---------+ + * | HREMOTE | 0x51100000 | 20MB | + * +---------+--------------+---------+ + * | M3 Dump | 0x52500000 | 1MB | + * +---------+--------------+---------+ + * | ETR | 0x52600000 | 1MB | + * +---------+--------------+---------+ + * | Caldb | 0x52700000 | 8MB | + * +---------+--------------+---------+ + * |Pageable | 0x52F00000 | 7MB | + * +==================================+ + */ + base-addr = <0x51100000>; + m3-dump-addr = <0x52500000>; + etr-addr = <0x52600000>; + caldb-addr = <0x52700000>; + pageable-addr = <0x52F00000>; + hremote-size = <0x1400000>; + pageable-size = <0x700000>; + tgt-mem-mode = <0x1>; +#else + /* qcn9224 tgt-mem-mode=0 layout - 50MB + * +=========+==============+=========+ + * | Region | Start Offset | Size | + * +---------+--------------+---------+ + * | HREMOTE | 0x51E00000 | 28MB | + * +---------+--------------+---------+ + * | M3 Dump | 0x53A00000 | 1MB | + * +---------+--------------+---------+ + * | ETR | 0x53B00000 | 1MB | + * +---------+--------------+---------+ + * | Caldb | 0x53C00000 | 8MB | + * +---------+--------------+---------+ + * |Pageable | 0x54400000 | 12MB | + * +==================================+ + */ + base-addr = <0x51E00000>; + m3-dump-addr = <0x53A00000>; + etr-addr = <0x53B00000>; + caldb-addr = <0x53C00000>; + pageable-addr = <0x54400000>; + hremote-size = <0x1C00000>; + pageable-size = <0xC00000>; + tgt-mem-mode = <0x0>; +#endif + caldb-size = <0x800000>; + qca,extended-intc; + interrupts-extended = + <&qcn9224_in1 5 0>, + <&qcn9224_in1 6 0>, + <&qcn9224_in1 7 0>, + <&qcn9224_in1 8 0>, + <&qcn9224_in1 9 0>, + <&qcn9224_in1 10 0>, + <&qcn9224_in1 11 0>, + <&qcn9224_in1 12 0>, + <&qcn9224_in1 13 0>, + <&qcn9224_in1 14 0>, + <&qcn9224_in1 15 0>, + <&qcn9224_in1 16 0>, + <&qcn9224_in1 17 0>, + <&qcn9224_in1 18 0>, + <&qcn9224_in1 19 0>, + <&qcn9224_in1 20 0>, + <&qcn9224_in1 49 0>, + <&qcn9224_in1 48 0>, + <&qcn9224_in1 47 0>, + <&qcn9224_in1 46 0>, + <&qcn9224_in1 45 0>, + <&qcn9224_in1 44 0>, + <&qcn9224_in1 43 0>, + <&qcn9224_in1 42 0>, + <&qcn9224_in1 50 0>, + <&qcn9224_in1 52 0>, + <&qcn9224_in1 51 0>, + <&qcn9224_in1 30 0>, + <&qcn9224_in1 29 0>, + <&qcn9224_in1 28 0>, + <&qcn9224_in1 27 0>, + <&qcn9224_in1 26 0>, + <&qcn9224_in1 25 0>, + <&qcn9224_in1 31 0>, + <&qcn9224_in1 80 0>, + <&qcn9224_in1 71 0>, + <&qcn9224_in1 96 0>, + <&qcn9224_in1 97 0>, + <&qcn9224_in1 67 0>, + <&qcn9224_in1 100 0>, + <&qcn9224_in1 99 0>, + <&qcn9224_in1 68 0>, + <&qcn9224_in1 69 0>, + <&qcn9224_in1 121 0>, + <&qcn9224_in1 119 0>, + <&qcn9224_in1 122 0>, + <&qcn9224_in1 120 0>, + <&qcn9224_in1 116 0>, + <&qcn9224_in1 113 0>, + <&qcn9224_in1 115 0>, + <&qcn9224_in1 112 0>, + <&qcn9224_in1 114 0>, + <&qcn9224_in1 111 0>, + <&qcn9224_in1 110 0>, + <&qcn9224_in1 109 0>, + <&qcn9224_in1 108 0>, + <&qcn9224_in1 39 0>, + <&qcn9224_in1 38 0>, + <&qcn9224_in1 37 0>, + <&qcn9224_in1 36 0>, + <&qcn9224_in1 35 0>, + <&qcn9224_in1 34 0>, + <&qcn9224_in1 33 0>, + <&qcn9224_in1 41 0>, + <&qcn9224_in1 40 0>, + <&qcn9224_in1 32 0>, + <&qcn9224_in1 24 0>, + <&qcn9224_in1 23 0>, + <&qcn9224_in1 22 0>, + <&qcn9224_in1 21 0>, + <&qcn9224_in1 66 0>, + <&qcn9224_in1 78 0>, + <&qcn9224_in1 117 0>, + <&qcn9224_in1 118 0>, + <&qcn9224_in1 61 0>, + <&qcn9224_in1 60 0>, + <&qcn9224_in1 57 0>, + <&qcn9224_in1 56 0>, + <&qcn9224_in1 63 0>, + <&qcn9224_in1 62 0>, + <&qcn9224_in1 59 0>, + <&qcn9224_in1 58 0>, + <&qcn9224_in1 65 0>, + <&qcn9224_in1 83 0>, + <&qcn9224_in1 75 0>, + <&qcn9224_in1 82 0>, + <&qcn9224_in1 81 0>, + <&qcn9224_in1 74 0>, + <&qcn9224_in1 73 0>, + <&qcn9224_in1 72 0>, + <&qcn9224_in1 98 0>, + <&qcn9224_in1 107 0>, + <&qcn9224_in1 106 0>, + <&qcn9224_in1 105 0>, + <&qcn9224_in1 104 0>, + <&qcn9224_in1 103 0>, + <&qcn9224_in1 102 0>, + <&qcn9224_in1 101 0>, + <&qcn9224_in1 76 0>, + <&qcn9224_in1 77 0>, + <&qcn9224_in1 143 0>, + <&qcn9224_in1 142 0>, + <&qcn9224_in1 141 0>, + <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "ce12", + "ce13", + "ce14", + "ce15", + "reo2sw8_intr2", + "reo2sw7_intr2", + "reo2sw6_intr2", + "reo2sw5_intr2", + "reo2sw4_intr2", + "reo2sw3_intr2", + "reo2sw2_intr2", + "reo2sw1_intr2", + "reo2sw0_intr2", + "reo2sw8_intr", + "reo2sw7_intr", + "reo2sw6_inrr", + "reo2sw5_intr", + "reo2sw4_intr", + "reo2sw3_intr", + "reo2sw2_intr", + "reo2sw1_intr", + "reo2sw0_intr", + "reo2status_intr2", + "reo_status", + "reo2rxdma_out_2", + "reo2rxdma_out_1", + "reo_cmd", + "sw2reo6", + "sw2reo5", + "sw2reo1", + "sw2reo", + "rxdma2reo_mlo_0_dst_ring1", + "rxdma2reo_mlo_0_dst_ring0", + "rxdma2reo_mlo_1_dst_ring1", + "rxdma2reo_mlo_1_dst_ring0", + "rxdma2reo_dst_ring1", + "rxdma2reo_dst_ring0", + "rxdma2sw_dst_ring1", + "rxdma2sw_dst_ring0", + "rxdma2release_dst_ring1", + "rxdma2release_dst_ring0", + "sw2rxdma_2_src_ring", + "sw2rxdma_1_src_ring", + "sw2rxdma_0", + "wbm2sw6_release2", + "wbm2sw5_release2", + "wbm2sw4_release2", + "wbm2sw3_release2", + "wbm2sw2_release2", + "wbm2sw1_release2", + "wbm2sw0_release2", + "wbm2sw6_release", + "wbm2sw5_release", + "wbm2sw4_release", + "wbm2sw3_release", + "wbm2sw2_release", + "wbm2sw1_release", + "wbm2sw0_release", + "wbm2sw_link", + "wbm_error_release", + "sw2txmon_src_ring", + "sw2rxmon_src_ring", + "txmon2sw_p1_intr1", + "txmon2sw_p1_intr0", + "txmon2sw_p0_dest1", + "txmon2sw_p0_dest0", + "rxmon2sw_p1_intr1", + "rxmon2sw_p1_intr0", + "rxmon2sw_p0_dest1", + "rxmon2sw_p0_dest0", + "sw_release", + "sw2tcl_credit2", + "sw2tcl_credit", + "sw2tcl4", + "sw2tcl5", + "sw2tcl3", + "sw2tcl2", + "sw2tcl1", + "sw2wbm1", + "misc_8", + "misc_7", + "misc_6", + "misc_5", + "misc_4", + "misc_3", + "misc_2", + "misc_1", + "misc_0", + "mhi2", + "mhi1", + "mhi0", + "inta"; + }; + + wifi3: wifi3@f00000 { + compatible = "qcom,cnss-qcn9160"; + msi-parent = <&v2m0>; + status = "disabled"; + }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + global_timer = <0x4A5000>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + qcom,smp2p-feature-ssr-ack; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + tcsr_q6_block: syscon@1945000 { + compatible = "syscon"; + reg = <0x1945000 0xE000>; + }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-q6-mpd"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + firmware = "IPQ5332/q6_fw0.mdt"; + reg = <0x0d100000 0x4040>, + <0x193d21c 0x8>, + <0x193d204 0x4>, + <0x1825000 0x90b8>, + <0x4a1000 0x4>, + <0xD190488 0x4>; + reg-names = "qdsp6", + "tcsr-msip", + "tcsr-q6", + "ce_ahb", + "qtimer", + "l2vic_int"; + + interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + resets = <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + + reset-names = "wcss_reset", + "wcss_q6_reset"; + + clocks = <&gcc GCC_Q6_TSCTR_1TO2_CLK>, + <&gcc GCC_Q6SS_TRIG_CLK>, + <&gcc GCC_Q6_AXIS_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6SS_ATBM_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6SS_PCLKDBG_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>; + + clock-names = "q6_tsctr_1to2", + "q6ss_trig", + "q6_axis", + "q6_ahb_s", + "q6ss_atbm", + "q6_ahb", + "q6_axim", + "q6ss_pclkdbg", + "wcss_ecahb", + "sys_noc_wcss_ahb", + "mem_noc_q6_axi"; + + assigned-clocks = <&gcc GCC_Q6_TSCTR_1TO2_CLK>, + <&gcc GCC_Q6SS_TRIG_CLK>, + <&gcc GCC_Q6_AXIS_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6SS_ATBM_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6SS_PCLKDBG_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>; + + assigned-clock-rates = <300000000>, + <120000000>, + <266666667>, + <133333333>, + <240000000>, + <133333333>, + <533333333>, + <120000000>, + <133333333>, + <133333333>, + <533333333>; + + qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>, + <&m3_dump>, + <&q6_etr_region>, + <&q6_caldb_region>; + qcom,rproc = <&q6v5_wcss>; + qcom,bootargs_smem = <507>; + qcom,bootargs_version = <2>; + qcom,userpd-bootargs; + license-file = ""; + qcom,heartbeat_smem = <508>; + glink-edge { + interrupts = ; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + global_timer = <0x4A5000>; + + qrtr_requests { + qcom,glink-channels = "IPCRTR"; + }; + }; + + q6_wcss_pd1: remoteproc_pd1 { + compatible = "qcom,ipq5332-wcss-ahb-mpd"; + reg = <0x004ab000 0x20>; + reg-names = "rmb"; + firmware = "IPQ5332/q6_fw1.mdt"; + iu_firmware = "IPQ5332/iu_fw.mdt"; + qcom,halt-regs = <&tcsr_q6_block 0xa000 0x18 0x0>; + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + resets = <&gcc GCC_WCSSAON_ARES>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_CE_BCR>; + reset-names = "wcss_aon_reset", + "wcss_reset", + "ce_reset"; + + clocks = <&gcc GCC_WCSS_DBG_IFC_APB_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_NTS_CLK>, + <&gcc GCC_WCSS_AXIS_CLK>, + <&gcc GCC_WCSS_DBG_IFC_ATB_CLK>, + <&gcc GCC_WCSS_DBG_IFC_ATB_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_APB_CLK>, + <&gcc GCC_WCSS_AXIM_CLK>, + <&gcc GCC_WCSS_DBG_IFC_NTS_BDG_CLK>, + <&gcc GCC_CE_AXI_CLK>, + <&gcc GCC_CE_PCNOC_AHB_CLK>, + <&gcc GCC_CE_AHB_CLK>; + + clock-names = "dbg-apb-bdg", + "dbg-nts", + "wcss_axi_s_clk", + "dbg-atb", + "dbg-atb-bdg", + "dbg-apb", + "wcss_axi_m_clk", + "dbg-nts-bdg", + "ce-axi", + "ce-pcnoc-ahb", + "ce-ahb"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + qcom,offloaded_to_q6; + }; + + q6_wcss_pd2: remoteproc_pd2 { + compatible = "qcom,ipq5332-wcss-pcie-mpd"; + firmware = "IPQ5332/q6_fw2.mdt"; + qcom,halt-regs = <&tcsr_q6_block 0xa000 0x18 0x0>; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + + q6_wcss_pd3: remoteproc_pd3 { + compatible = "qcom,ipq5332-wcss-pcie-mpd"; + firmware = "IPQ5332/q6_fw3.mdt"; + qcom,halt-regs = <&tcsr_q6_block 0xa000 0x18 0x0>; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + }; + + apss_clk: qcom,apss_clk@b111000 { + compatible = "qcom,apss-ipq5332"; + reg = <0xb111000 0x6000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + msm_imem: qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tz-log-buf-addr@720 { + compatible = "qcom,msm-imem-tz-log-buf-addr"; + reg = <0x720 4>; + }; + + restart-reason-buf-addr@7a4 { + compatible = "qcom,msm-imem-restart-reason-buf-addr"; + reg = <0x7a4 4>; + }; + }; + + qfprom_nvmem: qfprom_nvmem@a4000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xa4000 0x721>; + + cpu_speed_bin: cpu_speed_bin@1d { + reg = <0x1d 0x2>; + bits = <7 2>; + }; + + tsens_calib_sel: calib@3E0 { + reg = <0x3E0 0x4>; + }; + + tsens_calib_offset: calib@3A4 { + reg = <0x3A4 0xC>; + }; + + pcie0_disable: pcie0_disable@25 { + reg = <0x25 0x1>; + bits = <3 1>; + }; + + pcie1_disable: pcie1_disable@25 { + reg = <0x25 0x1>; + bits = <4 1>; + }; + + pcie2_disable: pcie2_disable@25 { + reg = <0x25 0x1>; + bits = <2 1>; + }; + }; + }; + + license_manager { + compatible = "qti,license-manager-service"; + device-license-termination; + }; + +/* gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + status = "ok"; + + button@1 { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + };*/ + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + pmu-v7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + qti,tzlog { + compatible = "qti,tzlog-ipq5332"; + interrupts = ; + qti,tz-diag-buf-size = <0x3000>; + qti,tz-ring-off = <7>; + qti,tz-log-pos-info-off = <810>; + }; + + qti,scm_restart_reason { + compatible = "qti_ipq5332,scm_restart_reason"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + qti,sps { + compatible = "qti,msm-sps-4k"; + qti,pipe-attr-ee; + }; + + + qcom,test@0 { + compatible = "qcom,testmhi"; + qcom,wlan-ramdump-dynamic = <0x600000>; + }; + + qti,gadget_diag@0 { + compatible = "qti,gadget-diag"; + status = "disabled"; + }; + + ctx_save: ctx-save { + compatible = "qti,ctxt-save-ipq5332"; + }; + + qseecom: qseecom { + compatible = "ipq9574-qseecom"; + memory-region = <&tzapp>; + status = "ok"; + }; +}; + +#include "ipq5332-coresight.dtsi" +#include "ipq5332-thermal.dtsi" diff --git a/feeds/ipq95xx/ipq53xx/image/ipq53xx.mk b/feeds/ipq95xx/ipq53xx/image/ipq53xx.mk index 76cfac808..9f275b02c 100644 --- a/feeds/ipq95xx/ipq53xx/image/ipq53xx.mk +++ b/feeds/ipq95xx/ipq53xx/image/ipq53xx.mk @@ -8,6 +8,18 @@ define Device/cig_wf198 IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand IMAGE/nand-factory.ubi := append-ubi - DEVICE_PACKAGES := ath12k-wifi-cig-wf198 + DEVICE_PACKAGES := ath12k-wifi-cig-wf198 ath12k-firmware-qcn92xx-split-phy ath12k-firmware-ipq53xx endef TARGET_DEVICES += cig_wf198 + +define Device/sercomm_ap72tip + DEVICE_TITLE := Sercomm AP72 TIP + DEVICE_DTS := ipq5332-sercomm-ap72tip + DEVICE_DTS_CONFIG := config@mi01.2-qcn9160-c1 + IMAGES := sysupgrade.tar nand-factory.bin nand-factory.ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata + IMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand + IMAGE/nand-factory.ubi := append-ubi + DEVICE_PACKAGES := ath12k-wifi-sercomm-ap72tip ath12k-firmware-qcn92xx-split-phy ath12k-firmware-ipq53xx +endef +TARGET_DEVICES += sercomm_ap72tip diff --git a/feeds/ipq95xx/ipq53xx/patches/300-pwm.patch b/feeds/ipq95xx/ipq53xx/patches/300-pwm.patch new file mode 100644 index 000000000..b283d159c --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/patches/300-pwm.patch @@ -0,0 +1,40 @@ +Index: linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/pwm/pwm-ipq.c +=================================================================== +--- linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617.orig/drivers/pwm/pwm-ipq.c ++++ linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/pwm/pwm-ipq.c +@@ -110,6 +110,7 @@ struct ipq_pwm_chip { + + static ssize_t count; + static uint32_t used_pwm[MAX_PWM_DEVICES]; ++//static uint32_t dft_pwm[MAX_PWM_DEVICES]; + + static const uint32_t pwm_ctrl_register[] = { + ADSS_GLB_PWM0_CTRL_REG, +@@ -330,6 +331,7 @@ static int ipq_pwm_probe(struct platform + struct device *dev; + unsigned int base_index; + int ret; ++ //unsigned int i; + const void *dev_data; + unsigned long src_freq = SRC_FREQ; + struct resource *res = NULL; +@@ -387,6 +389,19 @@ static int ipq_pwm_probe(struct platform + dev_err(dev, "pwmchip_add() failed: %d\n", ret); + return ret; + } ++ ++ /*count = of_property_count_u32_elems(dev->of_node, "dft-pwm-status"); ++ if (!of_property_read_u32_array(dev->of_node, "dft-pwm-status", ++ dft_pwm, count)) { ++ for(i = 0; i < count; i++) { ++ if(dft_pwm[i] > 0) { ++ ipq_pwm_request(&(pwm->chip), &(pwm->chip.pwms[i])); ++ ipq_pwm_config(&(pwm->chip), &(pwm->chip.pwms[i]), 500000000, 1000000000); ++ } ++ } ++ }*/ ++ ipq_pwm_request(&(pwm->chip), &(pwm->chip.pwms[1])); ++ ipq_pwm_config(&(pwm->chip), &(pwm->chip.pwms[1]), 500000000, 1000000000); + + return 0; + } diff --git a/feeds/ipq95xx/ipq53xx/patches/301-button.patch b/feeds/ipq95xx/ipq53xx/patches/301-button.patch new file mode 100644 index 000000000..ad5e24709 --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/patches/301-button.patch @@ -0,0 +1,42 @@ +Index: linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/arch/arm64/boot/dts/qcom/ipq5332.dtsi +=================================================================== +--- linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617.orig/arch/arm64/boot/dts/qcom/ipq5332.dtsi ++++ linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/arch/arm64/boot/dts/qcom/ipq5332.dtsi +@@ -918,15 +918,6 @@ + }; + }; + +- button_pins: button_pins { +- wps_button { +- pins = "gpio35"; +- function = "gpio"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- }; +- + bt_pins: bt_pins { + PTA_0 { + pins = "gpio49"; +@@ -2577,21 +2568,6 @@ + device-license-termination; + }; + +- gpio_keys { +- compatible = "gpio-keys"; +- pinctrl-0 = <&button_pins>; +- pinctrl-names = "default"; +- status = "ok"; +- +- button@1 { +- label = "wps"; +- linux,code = ; +- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +- linux,input-type = <1>; +- debounce-interval = <60>; +- }; +- }; +- + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; diff --git a/feeds/ipq95xx/ipq53xx/patches/302-aq-phy.patch b/feeds/ipq95xx/ipq53xx/patches/302-aq-phy.patch new file mode 100644 index 000000000..ff3f1b518 --- /dev/null +++ b/feeds/ipq95xx/ipq53xx/patches/302-aq-phy.patch @@ -0,0 +1,66 @@ +Index: linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/aquantia_main.c +=================================================================== +--- linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617.orig/drivers/net/phy/aquantia_main.c ++++ linux-5.4.213-qsdk-b2d40c94fad765a48c03f492d669aeecbbb9b617/drivers/net/phy/aquantia_main.c +@@ -31,6 +31,9 @@ + #define PHY_ID_AQCS109 0x03a1b5c2 + #define PHY_ID_AQR405 0x03a1b4b0 + ++#define PHY_ID_AQR114C 0x31c31c22 ++#define PHY_ID_AQR114C_B1 0x31c31c23 ++ + #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 + #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) + #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 +@@ -1101,6 +1104,42 @@ static struct phy_driver aqr_driver[] = + .ack_interrupt = aqr_ack_interrupt, + .read_status = aqr_read_status, + }, ++{ ++ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), ++ .name = "Aquantia AQR114C", ++ .probe = aqr107_probe, ++ .config_init = aqr107_config_init, ++ .config_aneg = aqr_config_aneg, ++ .config_intr = aqr_config_intr, ++ .ack_interrupt = aqr_ack_interrupt, ++ .read_status = aqr107_read_status, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr107_suspend, ++ .resume = aqr107_resume, ++ .get_sset_count = aqr107_get_sset_count, ++ .get_strings = aqr107_get_strings, ++ .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++}, ++{ ++ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C_B1), ++ .name = "Aquantia AQR114C_B1", ++ .probe = aqr107_probe, ++ .config_init = aqr107_config_init, ++ .config_aneg = aqr_config_aneg, ++ .config_intr = aqr_config_intr, ++ .ack_interrupt = aqr_ack_interrupt, ++ .read_status = aqr107_read_status, ++ .get_tunable = aqr107_get_tunable, ++ .set_tunable = aqr107_set_tunable, ++ .suspend = aqr107_suspend, ++ .resume = aqr107_resume, ++ .get_sset_count = aqr107_get_sset_count, ++ .get_strings = aqr107_get_strings, ++ .get_stats = aqr107_get_stats, ++ .link_change_notify = aqr107_link_change_notify, ++}, + }; + + module_phy_driver(aqr_driver); +@@ -1120,6 +1159,8 @@ static struct mdio_device_id __maybe_unu + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, ++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, ++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C_B1) }, + { } + }; + diff --git a/feeds/ipq95xx/qca-ssdk/patches/101-aq_phy.patch b/feeds/ipq95xx/qca-ssdk/patches/101-aq_phy.patch new file mode 100644 index 000000000..b9c3399c6 --- /dev/null +++ b/feeds/ipq95xx/qca-ssdk/patches/101-aq_phy.patch @@ -0,0 +1,28 @@ +Index: qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec/include/hsl/phy/hsl_phy.h +=================================================================== +--- qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec.orig/include/hsl/phy/hsl_phy.h ++++ qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec/include/hsl/phy/hsl_phy.h +@@ -609,6 +609,9 @@ typedef struct { + #define AQUANTIA_PHY_113C_B0 0x31c31C12 + #define AQUANTIA_PHY_113C_B1 0x31c31C13 + #define AQUANTIA_PHY_112C 0x03a1b792 ++/*sercomm*/ ++#define AQUANTIA_PHY_114C 0x31c31c22 ++#define AQUANTIA_PHY_114C_B1 0x31c31c23 + #define RTL_PHY 0X001CCAF3 + + #define PHY_805XV2 0x004DD082 +Index: qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec/src/hsl/phy/hsl_phy.c +=================================================================== +--- qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec.orig/src/hsl/phy/hsl_phy.c ++++ qca-ssdk-09cba788ef5680e3e5b9deaa376da8d6bc13a7ec/src/hsl/phy/hsl_phy.c +@@ -285,6 +286,9 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui + case AQUANTIA_PHY_113C_B0: + case AQUANTIA_PHY_113C_B1: + case AQUANTIA_PHY_112C: ++ /*sercomm*/ ++ case AQUANTIA_PHY_114C: ++ case AQUANTIA_PHY_114C_B1: + phytype = AQUANTIA_PHY_CHIP; + break; + case QCA8030_PHY: diff --git a/patches/0038-ipq807x-prepare-tree-for-old-v4.4-kernel.patch b/patches/0038-ipq807x-prepare-tree-for-old-v4.4-kernel.patch index 6ec7632ef..4b89504ff 100644 --- a/patches/0038-ipq807x-prepare-tree-for-old-v4.4-kernel.patch +++ b/patches/0038-ipq807x-prepare-tree-for-old-v4.4-kernel.patch @@ -702,7 +702,7 @@ index 18cafe60a2..a860c557de 100644 echo "generic patches directory is present. please move your patches to the pending directory" ; \ exit 1; \ fi -+ifneq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx),y) ++ifneq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) $(call PatchDir,$(LINUX_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/) $(call PatchDir,$(LINUX_DIR),$(GENERIC_PATCH_DIR),generic/) $(call PatchDir,$(LINUX_DIR),$(GENERIC_HACK_DIR),generic-hack/) @@ -714,7 +714,7 @@ index 18cafe60a2..a860c557de 100644 echo "All kernel patches must start with either generic/ or platform/"; \ false; \ } -+ifneq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx),y) ++ifneq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) $(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/) $(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_PATCH_DIR),generic/) $(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_HACK_DIR),generic-hack/) @@ -749,7 +749,7 @@ index b5e3e7ff6f..36e1377617 100644 endif GENERIC_PLATFORM_DIR := $(TOPDIR)/target/linux/generic -+ifeq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx),y) ++ifeq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) +GENERIC_BACKPORT_DIR := +GENERIC_PATCH_DIR := +GENERIC_HACK_DIR := @@ -765,7 +765,7 @@ index b5e3e7ff6f..36e1377617 100644 __config_list = $(firstword $(wildcard $(call __config_name_list,$(1)))) find_kernel_config=$(if $(__config_list),$(__config_list),$(lastword $(__config_name_list))) -+ifeq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx),y) ++ifeq ($(CONFIG_TARGET_ipq807x)$(CONFIG_TARGET_ipq60xx)$(CONFIG_TARGET_ipq50xx)$(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) +GENERIC_LINUX_CONFIG:=$(GENERIC_PLATFORM_DIR)/config-5.4-qsdk +else GENERIC_LINUX_CONFIG = $(call find_kernel_config,$(GENERIC_PLATFORM_DIR)) diff --git a/patches/0042-ipq807x-drop-nand.sh-from-base-files.patch b/patches/0042-ipq807x-drop-nand.sh-from-base-files.patch index fe704c23d..19460b0bf 100644 --- a/patches/0042-ipq807x-drop-nand.sh-from-base-files.patch +++ b/patches/0042-ipq807x-drop-nand.sh-from-base-files.patch @@ -16,7 +16,7 @@ index dc89de2035..dd1d0760f8 100644 endef endif -+ifeq ($(CONFIG_LINUX_4_4)$(CONFIG_TARGET_ipq95xx),y) ++ifeq ($(CONFIG_LINUX_4_4)$(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) + define Package/base-files/ipq807x-support + rm -f $(1)/lib/upgrade/nand.sh + endef diff --git a/patches/0045-ucode-add-TIP-specific-fixes.patch b/patches/0045-ucode-add-TIP-specific-fixes.patch index 8b62a5b8a..cf8199df9 100644 --- a/patches/0045-ucode-add-TIP-specific-fixes.patch +++ b/patches/0045-ucode-add-TIP-specific-fixes.patch @@ -20,7 +20,7 @@ index e2fe4c8bad..4bdd955832 100644 -DUCI_SUPPORT=OFF \ -DULOOP_SUPPORT=OFF -+ifeq ($(CONFIG_TARGET_ipq95xx),y) ++ifeq ($(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) +TARGET_CFLAGS += -DQCA_WIFI_7 +endif + diff --git a/patches/0058-kernel-add-v5.4-checksums.patch b/patches/0058-kernel-add-v5.4-checksums.patch index 55270fa13..32088e4f4 100644 --- a/patches/0058-kernel-add-v5.4-checksums.patch +++ b/patches/0058-kernel-add-v5.4-checksums.patch @@ -21,7 +21,7 @@ index daf1f1740a..ec9733780d 100644 +LINUX_KERNEL_HASH-5.4.158 = 6e018fecdc8fc24553756e582d83b82d65b10a6b03ef36262a24911f839b8d59 +endif + -+ifeq ($(CONFIG_TARGET_ipq95xx),y) ++ifeq ($(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) +LINUX_VERSION-5.4 = .213 +LINUX_KERNEL_HASH-5.4.213 = d13de2f5e02569eebeb40ee9373fc0b4d0bf6b69595b38ea95c1f878a5bd0447 +endif diff --git a/patches/0068-ucode-update-to-latest-HEAD.patch b/patches/0068-ucode-update-to-latest-HEAD.patch index f4cac2393..69e0d83df 100644 --- a/patches/0068-ucode-update-to-latest-HEAD.patch +++ b/patches/0068-ucode-update-to-latest-HEAD.patch @@ -58,7 +58,7 @@ index 5cae355e68..a999d58f93 100644 + -DDEBUG_SUPPORT=ON \ + -DLOG_SUPPORT=OFF - ifeq ($(CONFIG_TARGET_ipq95xx),y) + ifeq ($(CONFIG_TARGET_ipq95xx)$(CONFIG_TARGET_ipq53xx),y) TARGET_CFLAGS += -DQCA_WIFI_7 @@ -73,115 +85,40 @@ define Package/libucode DEPENDS:=+libjson-c