ipq50xx: CIG-WF186h Kernel/Firmware upgrade

Upgrade to 5018 ath11k 12.0 wireless driver +  kernel 5.4

Fixes: WIFI-13038
Signed-off-by: Ken <xshi@actiontec.com>

feeds/ipq807x_v5.4/ath11k-firmware/files/IPQ5018_map_spruce/fw_version.txt

@@ -0,0 +1 @@
+WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 v1

feeds/ipq807x_v5.4/ath11k-firmware/files/IPQ5018_map_spruce/m3_fw.flist

@@ -1,3 +1,3 @@
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b00
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b01
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/m3_fw.b02
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/m3_fw.b00
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/m3_fw.b01
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/m3_fw.b02

feeds/ipq807x_v5.4/ath11k-firmware/files/IPQ5018_map_spruce/q6_fw.flist

@@ -1,23 +1,19 @@
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b00
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b01
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b02
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b03
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b04
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b05
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b07
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b08
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b09
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b10
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b11
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b13
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b14
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b15
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b16
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b17
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b18
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b20
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b21
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b22
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b23
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b25
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/q6_fw.b26
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b00
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b01
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b02
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b03
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b04
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b05
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b07
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b08
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b09
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b10
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b11
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b13
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b14
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b15
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b16
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b17
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b18
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b20
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/q6_fw.b21

feeds/ipq807x_v5.4/ath11k-firmware/files/QCN6122_map_spruce/m3_fw.flist

@@ -1,3 +1,3 @@
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b00
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b01
-build/ms/bin/5018.wlanfw2.map_spr_spr_eval_cs/PIL_IMAGES/qcn6122/m3_fw.b02
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/qcn6122/m3_fw.b00
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/qcn6122/m3_fw.b01
+build/ms/bin/5018.wlanfw2.map_spruce_eval/PIL_IMAGES/qcn6122/m3_fw.b02

feeds/ipq807x_v5.4/ath11k-wifi/Makefile

@@ -25,6 +25,7 @@ endef
 
 ALLWIFIBOARDS:= \
 	cig-wf186w \
+	cig-wf186h \
 	cig-wf660a \
 	cig-wf194c \
 	cig-wf194c4 \
@@ -343,6 +344,7 @@ define Package/ath11k-wifi-cig-wf188n-us/install
 endef
 
 $(eval $(call generate-ath11k-wifi-package,cig-wf186w,Cigtech WF186w))
+$(eval $(call generate-ath11k-wifi-package,cig-wf186h,Cigtech WF186h))
 $(eval $(call generate-ath11k-wifi-package,cig-wf660a,Cigtech WF660a))
 $(eval $(call generate-ath11k-wifi-package,cig-wf194c,Cigtech WF194c))
 $(eval $(call generate-ath11k-wifi-package,cig-wf194c4,Cigtech WF194c4))

feeds/ipq807x_v5.4/ipq50xx/base-files/etc/board.d/02_network

@@ -15,6 +15,9 @@ qcom_setup_interfaces()
 	cig,wf186w)
 		ucidef_add_switch "switch0" "4:wan" "0:lan" "1:lan" "2:lan" "3:lan" "6@eth0"
 		;;
+	cig,wf186h)
+		ucidef_add_switch "switch0" "4:wan" "1:lan" "2:lan" "6@eth0"
+		;;
 	edgecore,oap101|\
  	edgecore,oap101-6e|\
 	edgecore,oap101e|\
@@ -42,6 +45,7 @@ qcom_setup_macs()
 	local board="$1"
 
 	case $board in
+	cig,wf186h|\
 	cig,wf186w)
 		mtd=$(find_mtd_chardev "0:APPSBLENV")
 		[ -z "$mtd" ] && return;

feeds/ipq807x_v5.4/ipq50xx/base-files/etc/hotplug.d/firmware/10-ath11k-caldata

@@ -63,6 +63,7 @@ case "$FIRMWARE" in
 ath11k/IPQ5018/hw1.0/caldata.bin)
 	case "$board" in
 	cig,wf186w|\
+	cig,wf186h|\
 	edgecore,eap104|\
 	edgecore,oap101|\
 	edgecore,oap101-6e|\
@@ -77,6 +78,7 @@ ath11k/IPQ5018/hw1.0/caldata.bin)
 ath11k/qcn6122/hw1.0/caldata_1.bin)
 	case "$board" in
 	cig,wf186w|\
+	cig,wf186h|\
 	edgecore,oap101|\
 	edgecore,oap101-6e|\
 	edgecore,oap101e|\
@@ -98,7 +100,8 @@ ath11k/qcn6122/hw1.0/caldata_2.bin)
 	;;
 ath11k-macs)
 	case "$board" in
-	cig,wf186w)
+	cig,wf186w|\
+	cig,wf186h)
 		ath11k_generate_macs_wf186w
 		;;
 	edgecore,eap104|\

feeds/ipq807x_v5.4/ipq50xx/base-files/lib/upgrade/platform.sh

@@ -69,6 +69,7 @@ platform_check_image() {
 	board=$(board_name)
 	case $board in
 	cig,wf186w|\
+	cig,wf186h|\
 	edgecore,eap104|\
 	hfcl,ion4xi_w|\
 	yuncore,fap655|\
@@ -111,6 +112,7 @@ platform_do_upgrade() {
                 nand_upgrade_tar "$1"
                 ;;
 	cig,wf186w|\
+	cig,wf186h|\
 	yuncore,fap655)
 		[ -f /proc/boot_info/rootfs/upgradepartition ] && {
 			CI_UBIPART="$(cat /proc/boot_info/rootfs/upgradepartition)"

feeds/ipq807x_v5.4/ipq50xx/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186h.dts

@@ -0,0 +1,973 @@
+/dts-v1/;
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "ipq5018.dtsi"
+
+/ {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	model = "cig wf186h";
+	compatible = "cig,wf186h","qcom,ipq5018-ap-mp03.3", "qcom,ipq5018-mp03.3", "qcom,ipq5018";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+		serial0 = &blsp1_uart1;
+		serial1 = &blsp1_uart2;
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
+	};
+
+	chosen {
+		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
+		bootargs-append = " swiotlb=1 coherent_pool=2M";
+		stdout-path = "serial0";
+	};
+
+	reserved-memory {
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+	/*            256 MB Profile
+	 * +=========+==============+========================+
+	 * |        |              |                         |
+	 * | Region | Start Offset |          Size           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |  NSS   |  0x40000000  |          8MB            |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * | Linux  |  0x40800000  | Depends on total memory |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * +        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * | uboot  |  0x4A600000  |           4MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |  SBL   |  0x4AA00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  smem  |  0x4AB00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |   TZ   |  0x4AC00000  |           4MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |   Q6   |  0x4B000000  |          16MB           |
+	 * |  code/ |              |                         |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |IPQ5018 |  0x4C000000  |          13MB           |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * | M3 Dump|  0x4CD00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  QDSS  |  0x4CE00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |QCN6122 |  0x4CF00000  |          15MB           |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * | M3 Dump|  0x4DE00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  QDSS  |  0x4DF00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |QCN9000 |  0x4E000000  |          25MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |  MHI1  |  0x4F900000  |           9MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |                                                 |
+	 * |      Rest of the memory for Linux               |
+	 * |                                                 |
+	 * +=================================================+
+	 */
+
+		q6_mem_regions: q6_mem_regions@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 0x3000000>;
+		};
+
+		q6_code_data: q6_code_data@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 01000000>;
+		};
+
+		q6_ipq5018_data: q6_ipq5018_data@4c000000 {
+			no-map;
+			reg = <0x0 0x4c000000 0x0 0xD00000>;
+		};
+
+		m3_dump: m3_dump@4CD00000 {
+			no-map;
+			reg = <0x0 0x4CD00000 0x0 0x100000>;
+		};
+
+		q6_etr_region:q6_etr_dump@4CE00000 {
+			no-map;
+			reg = <0x0 0x4CE00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_data1: q6_qcn6122_data1@4CF00000 {
+			no-map;
+			reg = <0x0 0x4CF00000 0x0 0xF00000>;
+		};
+
+		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4DE00000 {
+			no-map;
+			reg = <0x0 0x4DE00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4DF00000 {
+			no-map;
+			reg = <0x0 0x4DF00000 0x0 0x100000>;
+		};
+
+		q6_qcn9000_region: qcn9000_pcie0@4E000000 {
+			no-map;
+			reg = <0x0 0x4E000000 0x0 0x01900000>;
+		};
+
+	#if defined(__CNSS2__)
+		mhi_region1: dma_pool1@4F900000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0x0 0x4F900000 0x0 0x00500000>;
+		};
+	#endif
+	#elif __IPQ_MEM_PROFILE_512_MB__
+	/*                      512 MB Profile
+	 * +==========+==============+=========================+
+	 * |          |              |                         |
+	 * |  Region  | Start Offset |          Size           |
+	 * |          |              |                         |
+	 * +----------+--------------+-------------------------+
+	 * |    NSS   |  0x40000000  |          16MB           |
+	 * +----------+--------------+-------------------------+
+	 * |   Linux  |  0x41000000  | Depends on total memory |
+	 * +----------+--------------+-------------------------+
+	 * |   uboot  |  0x4A600000  |           4MB           |
+	 * +----------+--------------+-------------------------+
+	 * |    SBL   |  0x4AA00000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * |   smem   |  0x4AB00000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * |    TZ    |  0x4AC00000  |           4MB           |
+	 * +----------+--------------+-------------------------+
+	 * |    Q6    |              |                         |
+	 * |   code/  |  0x4B000000  |          20MB           |
+	 * |   data   |              |                         |
+	 * +----------+--------------+-------------------------+
+	 * |  IPQ5018 |              |                         |
+	 * |   data   |  0x4C400000  |          13MB           |
+	 * +----------+--------------+-------------------------+
+	 * |  IPQ5018 |              |                         |
+	 * |  M3 Dump |  0x4D100000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * |  IPQ5018 |              |                         |
+	 * |   QDSS   |  0x4D200000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * |  IPQ5018 |              |                         |
+	 * |  Caldb   |  0x4D300000  |           2MB           |
+	 * +----------+--------------+-------------------------+
+	 * | QCN6122_1|              |                         |
+	 * |   data   |  0x4D500000  |          13MB           |
+	 * +----------+--------------+-------------------------+
+	 * | QCN6122_1|              |                         |
+	 * |  M3 Dump |  0x4E200000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * | QCN6122_1|              |                         |
+	 * |   QDSS   |  0x4E300000  |           1MB           |
+	 * +----------+--------------+-------------------------+
+	 * | QCN6122_1|              |                         |
+	 * |  Caldb   |  0x4E400000  |           5MB           |
+	 * +----------+--------------+-------------------------+
+	 * |                                                   |
+	 * |            Rest of the memory for Linux           |
+	 * |                                                   |
+	 * +===================================================+
+	 */
+		q6_mem_regions: q6_mem_regions@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 0x4D00000>;
+		};
+
+		q6_code_data: q6_code_data@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 01400000>;
+		};
+
+		q6_ipq5018_data: q6_ipq5018_data@4C400000 {
+			no-map;
+			reg = <0x0 0x4C400000 0x0 0xD00000>;
+		};
+
+		m3_dump: m3_dump@4D100000 {
+			no-map;
+			reg = <0x0 0x4D100000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4D200000 {
+			no-map;
+			reg = <0x0 0x4D200000 0x0 0x100000>;
+		};
+
+		q6_caldb_region: q6_caldb_region@4D300000 {
+			no-map;
+			reg = <0x0 0x4D300000 0x0 0x200000>;
+		};
+
+		q6_qcn6122_data1: q6_qcn6122_data1@4D500000 {
+			no-map;
+			reg = <0x0 0x4D500000 0x0 0xD00000>;
+		};
+
+		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
+			no-map;
+			reg = <0x0 0x4E200000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
+			no-map;
+			reg = <0x0 0x4E300000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E400000 {
+			no-map;
+			reg = <0x0 0x4E400000 0x0 0x500000>;
+		};
+	#else
+	/*                      1G Profile
+	 * +=========+==============+========================+
+	 * |        |              |                         |
+	 * | Region | Start Offset |          Size           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |  NSS   |  0x40000000  |          16MB           |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * | Linux  |  0x41000000  | Depends on total memory |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * | uboot  |  0x4A600000  |           4MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |  SBL   |  0x4AA00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  smem  |  0x4AB00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |   TZ   |  0x4AC00000  |           4MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |   Q6   |  0x4B000000  |          16MB           |
+	 * |  code/ |              |                         |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |IPQ5018 |  0x4C000000  |          13MB           |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * | M3 Dump|  0x4CD00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  QDSS  |  0x4CE00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * | caldb  |  0x4CF00000  |           2MB           |
+	 * +--------+--------------+-------------------------+
+	 * |QCN6122 |  0x4D100000  |          13MB           |
+	 * |  data  |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * | M3 Dump|  0x4DE00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * |  QDSS  |  0x4DF00000  |           1MB           |
+	 * +--------+--------------+-------------------------+
+	 * | caldb  |  0x4E000000  |           5MB           |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |QCN9000 |  0x4E500000  |          53MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |  MHI1  |  0x51A00000  |           9MB           |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |                                                 |
+	 * |      Rest of the memory for Linux               |
+	 * |                                                 |
+	 * +=================================================+
+	 */
+
+		q6_mem_regions: q6_mem_regions@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 0x3500000>;
+		};
+
+		q6_code_data: q6_code_data@4B000000 {
+			no-map;
+			reg = <0x0 0x4B000000 0x0 01000000>;
+		};
+
+		q6_ipq5018_data: q6_ipq5018_data@4C000000 {
+			no-map;
+			reg = <0x0 0x4C000000 0x0 0xD00000>;
+		};
+
+		m3_dump: m3_dump@4CD00000 {
+			no-map;
+			reg = <0x0 0x4CD00000 0x0 0x100000>;
+		};
+
+		q6_etr_region: q6_etr_dump@4CE00000 {
+			no-map;
+			reg = <0x0 0x4CE00000 0x0 0x100000>;
+		};
+
+		q6_caldb_region: q6_caldb_region@4CF00000 {
+			no-map;
+			reg = <0x0 0x4CF00000 0x0 0x200000>;
+		};
+
+		q6_qcn6122_data1: q6_qcn6122_data1@4D100000 {
+			no-map;
+			reg = <0x0 0x4D100000 0x0 0xD00000>;
+		};
+
+		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4DE00000 {
+			no-map;
+			reg = <0x0 0x4DE00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4DF00000 {
+			no-map;
+			reg = <0x0 0x4DF00000 0x0 0x100000>;
+		};
+
+		q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E000000 {
+			no-map;
+			reg = <0x0 0x4E000000 0x0 0x500000>;
+		};
+
+		q6_qcn9000_region: qcn9000_pcie0@4E500000 {
+			no-map;
+			reg = <0x0 0x4E500000 0x0 0x03500000>;
+		};
+
+#if defined(__CNSS2__)
+		mhi_region1: dma_pool1@51a00000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0x0 0x51A00000 0x0 0x00500000>;
+		};
+#endif
+	#endif
+	};
+
+	soc {
+		serial@78af000 {
+			status = "ok";
+		};
+
+		blsp1_uart2: serial@78b0000 {
+			pinctrl-0 = <&blsp1_uart_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+		};
+
+		qpic_bam: dma@7984000{
+			status = "ok";
+		};
+
+		nand: qpic-nand@79b0000 {
+			pinctrl-0 = <&qspi_nand_pins>;
+			pinctrl-names = "default";
+			status = "ok";
+		};
+
+		spi_0: spi@78b5000 { /* BLSP1 QUP0 */
+			pinctrl-0 = <&blsp0_spi_pins>;
+			pinctrl-names = "default";
+			cs-select = <0>;
+			status = "ok";
+
+			m25p80@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0>;
+				compatible = "n25q128a11";
+				linux,modalias = "m25p80", "n25q128a11";
+				spi-max-frequency = <50000000>;
+				use-default-sizes;
+			};
+		};
+
+		mdio0: mdio@88000 {
+			status = "ok";
+
+			ethernet-phy@0 {
+				reg = <7>;
+			};
+		};
+
+		mdio1: mdio@90000 {
+			status = "ok";
+			pinctrl-0 = <&mdio1_pins>;
+			pinctrl-names = "default";
+			phy-reset-gpio = <&tlmm 35 0>;
+			cig_clk_div = <0xff>;
+			ethernet-phy@0 {
+				reg = <0x1d>;
+			};
+		};
+
+		realtek@29{
+			compatible = "realtek,rtl8367s";
+			mii-bus = <&mdio1>;
+			realtek,extif0 = <0 0 10 1 1 1 1 1 2>;
+			switch = <&tlmm 35 0>;
+			phy-addr = <29>;
+                        status = "ok";
+		};
+		ess-instance {
+			num_devices = <0x1>;
+			ess-switch@0x39c00000 {
+				switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
+				cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
+				qcom,port_phyinfo {
+					port@0 {
+						port_id = <1>;
+						phy_address = <7>;
+						mdiobus = <&mdio0>;
+					};
+					port@1 {
+						port_id = <2>;
+						forced-speed = <1000>;
+						mdiobus = <&mdio1>;
+						forced-duplex = <1>;
+					};
+				};
+				led_source@0 {
+					source = <0>;
+					mode = "normal";
+					speed = "all";
+					blink_en = "enable";
+					active = "high";
+				};
+			};
+		};
+
+		wifi0: wifi@c000000 {
+			status = "ok";
+		};
+
+		dp1 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
+			clock-names = "nss-snoc-gmac-axi-clk";
+			qcom,id = <2>;
+			reg = <0x39D00000 0x10000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,mactype = <2>;
+			mdio-bus = <&mdio1>;
+			local-mac-address = [000000000000];
+			phy-mode = "sgmii";
+			qcom,rx-page-mode = <0>;
+		};
+
+		dp2 {
+			device_type = "network";
+			compatible = "qcom,nss-dp";
+			clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
+			clock-names = "nss-snoc-gmac-axi-clk";
+			qcom,id = <1>;
+			reg = <0x39C00000 0x10000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,mactype = <2>;
+			qcom,link-poll = <1>;
+			qcom,phy-mdio-addr = <7>;
+			mdio-bus = <&mdio0>;
+			local-mac-address = [000000000000];
+			phy-mode = "sgmii";
+			qcom,rx-page-mode = <0>;
+		};
+
+		nss-macsec1 {
+			compatible = "qcom,nss-macsec";
+			phy_addr = <0x1c>;
+			mdiobus = <&mdio1>;
+		};
+
+		pcm: pcm@0xA3C0000{
+			pinctrl-0 = <&audio_pins>;
+			pinctrl-names = "default";
+		};
+
+		gpio_keys {
+			compatible = "gpio-keys";
+			pinctrl-0 = <&button_pins>;
+			pinctrl-names = "default";
+
+			button@1 {
+				label = "rst";
+				linux,code = <KEY_RESTART>;
+				gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+				linux,input-type = <1>;
+				debounce-interval = <60>;
+			};
+		};
+	};
+
+	qcom,test@0 {
+		status = "ok";
+	};
+
+	thermal-zones {
+		status = "ok";
+	};
+};
+
+&soc {
+         pwm: pwm@0x1941010 {
+                pinctrl-0 = <&pwm_pins>;
+                pinctrl-names = "default";
+                used-pwm-indices = <1>, <1>, <1>, <1>;
+                dft-pwm-status = <1>, <0>, <0>, <0>;
+                status = "ok";
+        };
+};
+
+
+&tlmm {
+	pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>;
+	pinctrl-names = "default";
+
+	blsp0_uart_pins: uart_pins {
+		blsp0_uart_rx_tx {
+			pins = "gpio20", "gpio21";
+			function = "blsp0_uart0";
+			bias-disable;
+		};
+	};
+
+	blsp1_uart_pins: blsp1_uart_pins {
+		blsp1_uart_rx_tx {
+			pins = "gpio23", "gpio25", "gpio24", "gpio26";
+			function = "blsp1_uart2";
+			bias-disable;
+		};
+	};
+
+	blsp0_spi_pins: blsp0_spi_pins {
+		mux {
+			pins = "gpio10", "gpio11", "gpio12", "gpio13";
+			function = "blsp0_spi";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	qspi_nand_pins: qspi_nand_pins {
+		qspi_clock {
+				pins = "gpio9";
+				function = "qspi_clk";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+		qspi_cs {
+				pins = "gpio8";
+				function = "qspi_cs";
+				drive-strength = <8>;
+				bias-disable;
+			};
+
+		qspi_data {
+				pins = "gpio4", "gpio5", "gpio6", "gpio7";
+				function = "qspi_data";
+				drive-strength = <8>;
+				bias-disable;
+			};
+	};
+
+	mdio1_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mux_1 {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	phy_led_pins: phy_led_pins {
+		gephy_led_pin {
+			pins = "gpio46";
+			function = "led0";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	i2c_pins: i2c_pins {
+		i2c_scl {
+			pins = "gpio25";
+			function = "blsp2_i2c1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		i2c_sda {
+			pins = "gpio26";
+			function = "blsp2_i2c1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	button_pins: button_pins {
+		rst_button {
+			pins = "gpio27";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	audio_pins: audio_pinmux {
+		mux_1 {
+			pins = "gpio24";
+			function = "audio_rxbclk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_2 {
+			pins = "gpio25";
+			function = "audio_rxfsync";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_3 {
+			pins = "gpio26";
+			function = "audio_rxd";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_4 {
+			pins = "gpio27";
+			function = "audio_txmclk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_5 {
+			pins = "gpio28";
+			function = "audio_txbclk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_6 {
+			pins = "gpio29";
+			function = "audio_txfsync";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mux_7 {
+			pins = "gpio30";
+			function = "audio_txd";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	pwm_pins: pwm_pinmux {
+	        mux_1 {
+	            pins = "gpio0";
+	            function = "pwm10";
+	            drive-strength = <8>;
+	        };
+		mux_2 {
+				pins = "gpio1";
+				function = "pwm20";
+				drive-strength = <8>;
+			};
+		mux_3 {
+				pins = "gpio45";
+				function = "pwm3";
+				drive-strength = <8>;
+			};
+	};
+	
+};
+
+&usb3 {
+	status = "disabled";
+	device-power-gpio = <&tlmm 24 1>;
+};
+
+&eud {
+	status = "ok";
+};
+
+&pcie_x1 {
+	perst-gpio = <&tlmm 18 GPIO_ACTIVE_LOW>;
+};
+
+&pcie_x2 {
+	perst-gpio = <&tlmm 15 GPIO_ACTIVE_LOW>;
+};
+
+&dwc_0 {
+	/delete-property/ #phy-cells;
+	/delete-property/ phys;
+	/delete-property/ phy-names;
+};
+
+&hs_m31phy_0 {
+	status = "ok";
+};
+
+/*&pcie_x2phy {
+	status = "ok";
+};*/
+
+&pcie_x1_rp {
+        status = "disabled";
+
+	mhi_0: qcom,mhi@0 {
+		reg = <0 0 0 0 0 >;
+	};
+};
+
+&pcie_x2_rp {
+	status = "disabled";
+
+	mhi_1: qcom,mhi@1 {
+		reg = <0 0 0 0 0 >;
+
+	};
+};
+
+
+&q6v5_wcss {
+	compatible = "qcom,ipq5018-q6-mpd";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+	firmware = "IPQ5018/q6_fw.mdt";
+	reg = <0x0cd00000 0x4040>,
+	      <0x1938000 0x8>,
+	      <0x193d204 0x4>;
+	reg-names = "qdsp6",
+		    "tcsr-msip",
+		    "tcsr-q6";
+	resets = <&gcc GCC_WCSSAON_RESET>,
+		 <&gcc GCC_WCSS_Q6_BCR>;
+
+	reset-names = "wcss_aon_reset",
+		      "wcss_q6_reset";
+
+	clocks = <&gcc GCC_Q6_AXIS_CLK>,
+		 <&gcc GCC_WCSS_ECAHB_CLK>,
+		 <&gcc GCC_Q6_AXIM_CLK>,
+		 <&gcc GCC_Q6_AXIM2_CLK>,
+		 <&gcc GCC_Q6_AHB_CLK>,
+		 <&gcc GCC_Q6_AHB_S_CLK>,
+		 <&gcc GCC_WCSS_AXI_S_CLK>;
+	clock-names = "gcc_q6_axis_clk",
+		      "gcc_wcss_ecahb_clk",
+		      "gcc_q6_axim_clk",
+		      "gcc_q6_axim2_clk",
+		      "gcc_q6_ahb_clk",
+		      "gcc_q6_ahb_s_clk",
+		      "gcc_wcss_axi_s_clk";
+
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	memory-region = <&q6_mem_regions>, <&q6_etr_region>;
+#else
+	memory-region = <&q6_mem_regions>, <&q6_etr_region>,
+			<&q6_caldb_region>;
+#endif
+
+	qcom,rproc = <&q6v5_wcss>;
+	qcom,bootargs_smem = <507>;
+	boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
+		    <0x2 0x4 0x2 0x12 0x0 0x0>;
+	status = "ok";
+	q6_wcss_pd1: remoteproc_pd1@4ab000 {
+		compatible = "qcom,ipq5018-wcss-ahb-mpd";
+		reg = <0x4ab000 0x20>;
+		reg-names = "rmb";
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "IPQ5018/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 8 0>,
+				      <&wcss_smp2p_in 9 0>,
+				      <&wcss_smp2p_in 12 0>,
+				      <&wcss_smp2p_in 11 0>;
+		interrupt-names = "fatal",
+				  "ready",
+				  "spawn-ack",
+				  "stop-ack";
+
+		resets = <&gcc GCC_WCSSAON_RESET>,
+			 <&gcc GCC_WCSS_BCR>,
+			 <&gcc GCC_CE_BCR>;
+		reset-names = "wcss_aon_reset",
+			      "wcss_reset",
+			      "ce_reset";
+
+		clocks = <&gcc GCC_WCSS_AHB_S_CLK>,
+			 <&gcc GCC_WCSS_ACMT_CLK>,
+			 <&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names = "gcc_wcss_ahb_s_clk",
+			      "gcc_wcss_acmt_clk",
+			      "gcc_wcss_axi_m_clk";
+
+		qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
+
+		qcom,smem-states = <&wcss_smp2p_out 8>,
+				   <&wcss_smp2p_out 9>,
+				   <&wcss_smp2p_out 10>;
+		qcom,smem-state-names = "shutdown",
+					"stop",
+					"spawn";
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
+				<&q6_etr_region>;
+	#else
+		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
+				<&q6_etr_region>, <&q6_caldb_region>;
+	#endif
+
+	};
+
+	q6_wcss_pd2: remoteproc_pd2 {
+		compatible = "qcom,ipq5018-wcss-pcie-mpd";
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "qcn6122/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 16 0>,
+				      <&wcss_smp2p_in 17 0>,
+				      <&wcss_smp2p_in 20 0>,
+				      <&wcss_smp2p_in 19 0>;
+		interrupt-names = "fatal",
+				  "ready",
+				  "spawn-ack",
+				  "stop-ack";
+
+		qcom,smem-states = <&wcss_smp2p_out 16>,
+				   <&wcss_smp2p_out 17>,
+				   <&wcss_smp2p_out 18>;
+		qcom,smem-state-names = "shutdown",
+					"stop",
+					"spawn";
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
+				<&q6_qcn6122_etr_1>;
+	#else
+		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
+				<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
+	#endif
+
+	};
+};
+
+&i2c_0 {
+	pinctrl-0 = <&i2c_pins>;
+	pinctrl-names = "default";
+};
+
+&wifi0 {
+	/* IPQ5018 */
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+	qcom,rproc = <&q6_wcss_pd1>;
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	qcom,tgt-mem-mode = <2>;
+#else
+	qcom,tgt-mem-mode = <1>;
+#endif
+	qcom,board_id = <0x24>;
+#ifdef __CNSS2__
+	qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
+	qcom,caldb-addr = <0x4D300000 0x4D300000 0 0 0>;
+	qcom,caldb-size = <0x200000>;
+	mem-region = <&q6_ipq5018_data>;
+#else
+	memory-region = <&q6_ipq5018_data>;
+#endif
+	status = "ok";
+};
+
+&wifi1 {
+	/* QCN6122 5G */
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
+	qcom,rproc = <&q6_wcss_pd2>;
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	qcom,tgt-mem-mode = <2>;
+#else
+	qcom,tgt-mem-mode = <1>;
+#endif
+	qcom,board_id = <0x60>;
+#ifdef __CNSS2__
+	qcom,bdf-addr = <0x4D500000 0x4D500000 0x4D300000 0x0 0x0>;
+	qcom,caldb-addr = <0x4E400000 0x4E400000 0 0 0>;
+	qcom,caldb-size = <0x500000>;
+	mem-region = <&q6_qcn6122_data1>;
+#else
+	memory-region = <&q6_qcn6122_data1>;
+#endif
+	status = "ok";
+};
+

feeds/ipq807x_v5.4/ipq50xx/image/ipq50xx.mk

@@ -1,10 +1,19 @@
 KERNEL_LOADADDR := 0x41080000
 
+define Device/cig_wf186h
+  DEVICE_TITLE := Cigtech WF-186h
+  DEVICE_DTS := qcom-ipq5018-cig-wf186h
+  SUPPORTED_DEVICES := cig,wf186h
+  DEVICE_PACKAGES := ath11k-wifi-cig-wf186h ath11k-firmware-ipq50xx-map-spruce
+  DEVICE_DTS_CONFIG := config@mp03.3
+endef
+TARGET_DEVICES += cig_wf186h
+
 define Device/cig_wf186w
   DEVICE_TITLE := Cigtech WF-186w
   DEVICE_DTS := qcom-ipq5018-cig-wf186w
   SUPPORTED_DEVICES := cig,wf186w
-  DEVICE_PACKAGES := ath11k-wifi-cig-wf186w ath11k-firmware-ipq50xx-map-spruce kmod-switch-rtl8367c
+  DEVICE_PACKAGES := ath11k-wifi-cig-wf186w ath11k-firmware-ipq50xx-map-spruce
   DEVICE_DTS_CONFIG := config@mp03.3
 endef
 TARGET_DEVICES += cig_wf186w

feeds/ipq807x_v5.4/ipq50xx/patches/700-RTL8367C_S.patch

@@ -207,11 +207,63 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
  
  	mdio_node = of_parse_phandle(np, "mii-bus", 0);
  	if (!mdio_node) {
+
+Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/include/linux/rtl8367.h
+===================================================================
+--- linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d.orig/include/linux/rtl8367.h
++++ linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/include/linux/rtl8367.h
+@@ -18,6 +18,8 @@ enum rtl8367_port_speed {
+ 	RTL8367_PORT_SPEED_10 = 0,
+ 	RTL8367_PORT_SPEED_100,
+ 	RTL8367_PORT_SPEED_1000,
++	RTL8367S_PORT_SPEED_500M,
++	RTL8367S_PORT_SPEED_2500M,
+ };
+ 
+ struct rtl8367_port_ability {
+@@ -42,6 +44,9 @@ enum rtl8367_extif_mode {
+ 	RTL8367B_EXTIF_MODE_RMII_MAC = 7,
+ 	RTL8367B_EXTIF_MODE_RMII_PHY,
+ 	RTL8367B_EXTIF_MODE_RGMII_33V,
++	RTL8367S_EXTIF_MODE_1000X = 10,
++	RTL8367S_EXTIF_MODE_SGMII,
++	RTL8367S_EXTIF_MODE_HSGMII,
+ };
+ 
+ struct rtl8367_extif_config {
+Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/mdio-qca.c
+===================================================================
+--- linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d.orig/drivers/net/phy/mdio-qca.c
++++ linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/mdio-qca.c
+@@ -574,7 +574,7 @@ static int qca_mdio_probe(struct platfor
+ 	struct resource *res;
+ 	int ret, i;
+ 	struct reset_control *rst = ERR_PTR(-EINVAL);
+-
++	int clk_div = 0xf;
+ 	if (of_machine_is_compatible("qcom,ipq5018")) {
+ 		qca_tcsr_ldo_rdy_set(true);
+ 		rst = of_reset_control_get(pdev->dev.of_node, "gephy_mdc_rst");
+@@ -582,9 +582,13 @@ static int qca_mdio_probe(struct platfor
+ 			reset_control_deassert(rst);
+ 			usleep_range(100000, 110000);
+ 		}
++		if (0 == of_property_read_u32(pdev->dev.of_node, "cig_clk_div", &ret)) //read the mdio clock value from dts
++                        clk_div = ret;
++	    dev_err(&pdev->dev,"CIG clk_div =%x\n",clk_div);
+ 	}
+ 
+-	ret = qca_phy_reset(pdev);
++	
++    	    ret = qca_phy_reset(pdev);
+ 	if (ret)
+ 		dev_err(&pdev->dev, "Could not find reset gpio\n");
+ 
 Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/rtl8367c.c
 ===================================================================
 --- /dev/null
 +++ linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/rtl8367c.c
-@@ -0,0 +1,2462 @@
+@@ -0,0 +1,2975 @@
 +/*
 + * Platform driver for the Realtek RTL8367R-VB/S/C ethernet switches
 + *
@@ -231,6 +283,14 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +#include <linux/delay.h>
 +#include <linux/skbuff.h>
 +#include <linux/rtl8367.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include <linux/pm.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++
 +
 +#include "rtl8366_smi.h"
 +
@@ -508,6 +568,84 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +
 +#define    RTL8367S_DW8051_EN_OFFSET    5
 +#define SGMII_INIT_SIZE 1223
++
++/*****/
++#define RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET		13
++#define RTL8367S_REG_AUTO_NEGO_EN_OFFSET 		12
++#define RTL8367S_REG_POWER_DOWN_OFFSET 			11
++#define RTL8367S_REG_RESTART_AUTO_NEGO_OFFSET 		9
++#define RTL8367S_REG_DUPLEX_MODE_OFFSET 		8
++#define RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET	6
++#define RTL8367S_SET_BIT(x,bit) (x |= (1<<bit))
++#define RTL8367S_CLEAR_BIT(x,bit) (x &= ~(1<<bit))
++#define RTL8367S_DATA_INIT 0x1140
++#define RTL8367S_CHECK_BIT(x,bit) ((x>>bit)&0x1)
++
++#define PHY_CONTROL_REG		0
++#define PHY_STATUS_REG    	1
++#define RTL8367C_REGBITLENGTH               16
++#define RTL8367C_REG_PHY_AD    0x130f
++#define RTL8367C_PDNPHY_OFFSET    5
++#define MDC_MDIO_PHY_ID     0x1d  /* PHY ID 0 or 29 */
++#define MDC_MDIO_CTRL0_REG          0x1f
++#define MDC_MDIO_ADDR_OP           0x000E
++#define MDC_MDIO_ADDRESS_REG        0x17
++#define MDC_MDIO_DATA_WRITE_REG     0x18
++#define MDC_MDIO_CTRL1_REG          0x15
++#define MDC_MDIO_WRITE_OP          0x0003
++#define MDC_MDIO_READ_OP           0x0001
++#define MDC_MDIO_DATA_READ_REG      0x19
++#ifdef MDIO_12_5_MHZ
++#define CTRL_0_REG_C45_DEFAULT_VALUE	        0x15107
++#else
++#define CTRL_0_REG_C45_DEFAULT_VALUE		0x151FF
++#endif
++#define IPQ_MDIO_BASE				0x90000
++#define MDIO_CTRL_0_REG				0x40
++#define MDIO_CTRL_1_REG				0x44
++#define MDIO_CTRL_2_REG				0x48
++#define MDIO_CTRL_3_REG				0x4c
++#define MDIO_CTRL_4_REG				0x50
++#define MDIO_CTRL_4_ACCESS_BUSY			(1 << 16)
++#define MDIO_CTRL_4_ACCESS_START		(1 << 8)
++#define MDIO_CTRL_4_ACCESS_CODE_READ		0
++#define MDIO_CTRL_4_ACCESS_CODE_WRITE		1
++#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR        0
++#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE       1
++#define MDIO_CTRL_4_ACCESS_CODE_C45_READ        2
++#define CTRL_0_REG_DEFAULT_VALUE	        0x150FF
++#define MDIO_CTRL_4_ACCESS_BUSY			(1 << 16)
++#define IPQ_MDIO_RETRY				1000
++#define IPQ_MDIO_DELAY				5
++#define RTL8367C_REG_GPHY_OCP_MSB_0    0x1d15
++#define RTL8367C_CFG_CPU_OCPADR_MSB_MASK    0xFC0
++#define RTL8367C_PHY_BASE               0x2000
++#define RTL8367C_PHY_EXT_BASE           0xA000
++#define RTL8367C_REGDATAMAX                 0xFFFF
++#define RTL8367C_PHY_OFFSET             5
++#define RTL8367C_PHY_REGNOMAX           0x1F
++
++typedef enum rt_error_code_e
++{
++    RT_ERR_FAILED = -1,                             /* General Error                                                                    */
++    /* 0x0000xxxx for common error code */
++    RT_ERR_OK = 0,                                  /* 0x00000000, OK          */
++    RT_ERR_INPUT,                                   /* 0x00000001, invalid input parameter     */
++    RT_ERR_UNIT_ID,                                 /* 0x00000002, invalid unit id      */
++    RT_ERR_PORT_ID,                                 /* 0x00000003, invalid port id    */
++    RT_ERR_PORT_MASK,                               /* 0x00000004, invalid port mask   */
++    RT_ERR_PORT_LINKDOWN,                           /* 0x00000005, link down port status   */
++    RT_ERR_ENTRY_INDEX,                             /* 0x00000006, invalid entry index      */
++    RT_ERR_NULL_POINTER,                            /* 0x00000007, input parameter is null pointer          */
++    RT_ERR_QUEUE_ID,                                /* 0x00000008, invalid queue id     */
++    RT_ERR_QUEUE_NUM,                               /* 0x00000009, invalid queue number   */
++    RT_ERR_BUSYWAIT_TIMEOUT,                        /* 0x0000000a, busy watting time out    */
++    RT_ERR_MAC,                                     /* 0x0000000b, invalid mac address    */
++    RT_ERR_OUT_OF_RANGE,                            /* 0x0000000c, input parameter out of range   */
++    RT_ERR_PHY_REG_ID,                              /* 0x000e0001, invalid PHY reg id*/
++    RT_ERR_SMI,					    /* 0x0000000e, SMI error       */  
++};
++
 +u8 Sgmii_Init[SGMII_INIT_SIZE] = {
 +0x02,0x03,0xA9,0xE4,0xF5,0xA8,
 +0xD2,0xAF,0x22,0x00,0x00,0x02,0x04,0x35,
@@ -898,6 +1036,7 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +0x00,0x00,0x42,0x06,0x31,0x00,0x00,0x00,
 +0xE4,0xF5,0x8E,0x22};
 +
++static int rtl8367c_setAsicReg(struct rtl8366_smi *smi,u32 reg, u32 value);
 +
 +struct rtl8367b_initval {
 +	u16 reg;
@@ -1822,7 +1961,422 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +    return 0;
 +}
 +
++static int rtl8367c_setAsicReg(struct rtl8366_smi *smi, u32 reg, u32 value)
++{
 +
++    int err;
++
++    REG_WR(smi, reg, value);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++
++    return RT_ERR_OK;
++}
++
++static int rtl8367c_getAsicReg(struct rtl8366_smi *smi, u32 reg, u32 *pValue)
++{
++    u32 regData;
++    int err;
++
++    REG_RD(smi, reg, &regData);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++
++    *pValue = regData;
++
++    return RT_ERR_OK;
++}
++
++static int rtl8367c_setAsicRegBits(struct rtl8366_smi *smi, u32 reg, u32 bits, u32 value)
++{
++    u32 regData;
++    int err;
++    u32 bitsShift;
++    u32 valueShifted;
++
++    if(bits >= (1 << RTL8367C_REGBITLENGTH) )
++        return RT_ERR_INPUT;
++
++    bitsShift = 0;
++    while(!(bits & (1 << bitsShift)))
++    {
++        bitsShift++;
++        if(bitsShift >= RTL8367C_REGBITLENGTH)
++            return RT_ERR_INPUT;
++    }
++    valueShifted = value << bitsShift;
++
++    if(valueShifted > RTL8367C_REGDATAMAX)
++        return RT_ERR_INPUT;
++    REG_RD(smi, reg, &regData);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++    regData = regData & (~bits);
++    regData = regData | (valueShifted & bits);
++    REG_WR(smi, reg, regData);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++ 
++    return RT_ERR_OK;
++}
++
++static int rtl8367c_getAsicPHYOCPReg(struct rtl8366_smi *smi, int phyNo, u32 ocpAddr, u32 *pRegData)
++{
++    int retVal;
++    u32 regAddr;
++    u32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;
++
++	 /* OCP prefix */
++    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);
++    retVal = rtl8367c_setAsicRegBits(smi, RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix);
++    if(retVal != RT_ERR_OK)
++        return retVal;
++
++    /*prepare access address*/
++    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);
++    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);
++    regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;
++    retVal = rtl8367c_getAsicReg(smi, regAddr, pRegData);
++        if(retVal != RT_ERR_OK)
++       	 return retVal;
++
++    return RT_ERR_OK;
++
++
++}
++
++static int rtl8367c_setAsicPHYOCPReg(struct rtl8366_smi *smi, int phyNo, u32 ocpAddr, u32 ocpData )
++{
++    int retVal;
++    u32 regAddr;
++    u32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;
++
++    /* OCP prefix */
++    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);
++    if((retVal = rtl8367c_setAsicRegBits(smi, RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK)
++        return retVal;
++
++    /*prepare access address*/
++    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);
++    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);
++    regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;
++    if((retVal = rtl8367c_setAsicReg(smi, regAddr, ocpData)) != RT_ERR_OK)
++        return retVal;
++
++    return RT_ERR_OK;
++}
++
++static u16 rtl8367c_getAsicPHYReg(struct rtl8366_smi *smi, int phyNo, u32 phyAddr, u32 *pRegData )
++{
++    u32 ocp_addr;
++
++    ocp_addr = 0xa400 + phyAddr*2;
++
++    return rtl8367c_getAsicPHYOCPReg(smi, phyNo, ocp_addr, pRegData);
++}
++
++static u32 rtl8367c_setAsicPHYReg(struct rtl8366_smi *smi, int phyNo, u32 phyAddr, u32 phyData )
++{
++    u32 ocp_addr;
++
++    if(phyAddr > RTL8367C_PHY_REGNOMAX)
++        return RT_ERR_PHY_REG_ID;
++
++    ocp_addr = 0xa400 + phyAddr*2;
++
++    return rtl8367c_setAsicPHYOCPReg(smi, phyNo, ocp_addr, phyData);
++}
++
++static int dal_rtl8367c_port_phyReg_set(struct rtl8366_smi *smi, int port, u32 reg, u32 regData)
++{
++    int retVal;
++
++
++    if ((retVal = rtl8367c_setAsicPHYReg(smi, port, reg, regData)) != RT_ERR_OK)
++        return retVal;
++
++    return RT_ERR_OK;
++}
++
++static int dal_rtl8367c_port_phyReg_get(struct rtl8366_smi *smi, int port, u32 reg, u32 *pData)
++{
++    int retVal;
++
++
++    if ((retVal = rtl8367c_getAsicPHYReg(smi, port, reg, pData)) != RT_ERR_OK)
++        return retVal;
++
++    return RT_ERR_OK;
++}
++
++static int ipq_mdio_wait_busy(void)
++{
++	int i;
++	u32 busy;
++	for (i = 0; i < IPQ_MDIO_RETRY; i++) {
++		busy = readl(IPQ_MDIO_BASE +
++			MDIO_CTRL_4_REG) &
++			MDIO_CTRL_4_ACCESS_BUSY;
++		if (!busy)
++			return 0;
++	}
++	printk("%s: MDIO operation timed out\n",__func__);
++	return -ETIMEDOUT;
++}
++
++
++static int rtk_mdio_write(struct rtl8366_smi *smi, int mii_id, int regnum, u32 value)
++{
++        u32 cmd;
++
++        if (regnum & MII_ADDR_C45) {
++                unsigned int mmd = (regnum >> 16) & 0x1F;
++                unsigned int reg = regnum & 0xFFFF;
++
++                writel(CTRL_0_REG_C45_DEFAULT_VALUE,
++                        IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
++
++                /* Issue the phy address and reg */
++                writel((mii_id << 8) | mmd,
++                        IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
++
++                writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
++
++                /* issue read command */
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
++
++                writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
++
++                if (ipq_mdio_wait_busy())
++                        return -ETIMEDOUT;
++        } else {
++                writel(CTRL_0_REG_DEFAULT_VALUE,
++                        IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
++
++                /* Issue the phy addreass and reg */
++                writel((mii_id << 8 | regnum),
++                        IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
++        }
++
++        /* Issue a write data */
++        writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
++
++        if (regnum & MII_ADDR_C45) {
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ;
++        } else {
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE ;
++        }
++
++        writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
++	/* Wait for write complete */
++
++        if (ipq_mdio_wait_busy())
++                return -ETIMEDOUT;
++
++        return 0;
++}
++
++static int rtk_mdio_read(struct rtl8366_smi *smi, int mii_id, int regnum, u32 *data)
++{
++        u32 val,cmd;
++
++        if (regnum & MII_ADDR_C45) {
++
++                unsigned int mmd = (regnum >> 16) & 0x1F;
++                unsigned int reg = regnum & 0xFFFF;
++
++                writel(CTRL_0_REG_C45_DEFAULT_VALUE,
++                        IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
++
++                /* Issue the phy address and reg */
++                writel((mii_id << 8) | mmd,
++                        IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
++
++
++                writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
++
++                /* issue read command */
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
++        } else {
++
++                writel(CTRL_0_REG_DEFAULT_VALUE,
++                        IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
++
++                /* Issue the phy address and reg */
++                writel((mii_id << 8 | regnum ) ,
++                        IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
++
++                /* issue read command */
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ ;
++        }
++
++        /* issue read command */
++        writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
++
++        if (ipq_mdio_wait_busy())
++                return -ETIMEDOUT;
++
++	if (regnum & MII_ADDR_C45) {
++                cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_READ;
++                writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
++
++                if (ipq_mdio_wait_busy())
++                        return -ETIMEDOUT;
++        }
++
++        /* Read data */
++        val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG);
++
++        if (data != NULL)
++                *data = val;
++
++        return val;
++}
++
++static int rtl8367c_setAsicRegBit(struct rtl8366_smi *smi, u32 reg, u32 bit, u32 value)
++{
++    u32 regData;
++    int err;
++
++    if(bit >= RTL8367C_REGBITLENGTH)
++        return RT_ERR_INPUT;
++
++    REG_RD(smi, reg, &regData);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++
++    if(value)
++        regData = regData | (1 << bit);
++    else
++        regData = regData & (~(1 << bit));
++
++    REG_WR(smi, reg, regData);
++    if(err != RT_ERR_OK)
++        return RT_ERR_SMI;
++
++    return RT_ERR_OK;
++}
++
++static int rtl8367c_setAsicPortEnableAll(struct rtl8366_smi *smi, u32 enable)
++{
++    if(enable >= 2)
++        return RT_ERR_INPUT;
++    return rtl8367c_setAsicRegBit(smi, RTL8367C_REG_PHY_AD, RTL8367C_PDNPHY_OFFSET, enable);
++}
++
++static int dal_rtl8367c_port_phyEnableAll_set(struct switch_dev *dev,const struct switch_attr *attr,struct switch_val *val)
++{
++    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
++    int retVal;
++    u32 data;
++    int port = val->port_vlan;
++    int enable;
++    enable = val->value.i;
++    if(enable >= 2)
++	    return -EINVAL;
++    
++    if ((retVal = rtl8367c_setAsicPortEnableAll(smi, enable)) != RT_ERR_OK)
++            return retVal;
++    
++    if ((retVal = dal_rtl8367c_port_phyReg_get(smi, port, PHY_CONTROL_REG, &data)) != RT_ERR_OK)
++            return retVal;
++
++    if (1 == enable)
++    {
++	    RTL8367S_CLEAR_BIT(data,RTL8367S_REG_POWER_DOWN_OFFSET);
++	    RTL8367S_SET_BIT(data,RTL8367S_REG_RESTART_AUTO_NEGO_OFFSET);
++    }
++    else
++    {
++	    RTL8367S_SET_BIT(data,RTL8367S_REG_POWER_DOWN_OFFSET);
++    }
++
++    if ((retVal = dal_rtl8367c_port_phyReg_set(smi, port, PHY_CONTROL_REG, data)) != RT_ERR_OK)
++            return retVal;
++
++    return RT_ERR_OK;
++}
++
++int get_port_state(struct switch_dev *dev,const struct switch_attr *attr,struct switch_val *val)
++{
++	
++	struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
++	u32 data;
++	int port;
++	port = val->port_vlan;
++
++	dal_rtl8367c_port_phyReg_get(smi, port, PHY_CONTROL_REG, &data);
++
++	if(RTL8367S_CHECK_BIT(data,RTL8367S_REG_POWER_DOWN_OFFSET)) //check whether bit11 is true
++	{
++		printk("disabled\n");
++	}
++	else
++	{	
++		printk("enabled\n");
++	}
++
++	return 0;
++}
++
++static int dal_rtl8367c_port_crtl_status(struct switch_dev *dev,const struct switch_attr *attr,struct switch_val *val)
++{
++    struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
++    int retVal;
++    u32 data;
++    int port = val->port_vlan;
++    int enable;
++    enable = val->value.i;
++    if(enable >= 5)
++            return -EINVAL;
++    if ((retVal = dal_rtl8367c_port_phyReg_get(smi, port, PHY_CONTROL_REG, &data)) != RT_ERR_OK)
++            return retVal;
++    RTL8367S_CLEAR_BIT(data,RTL8367S_REG_AUTO_NEGO_EN_OFFSET); //diasble auto
++    switch(enable) 
++    {
++	case 0: //10M-half
++	    {
++		RTL8367S_CLEAR_BIT(data,RTL8367S_REG_DUPLEX_MODE_OFFSET);
++		RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET);
++	        RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET);
++	    }
++	    break;
++	case 1: //10M-full
++	    {
++                RTL8367S_SET_BIT(data,RTL8367S_REG_DUPLEX_MODE_OFFSET);
++                RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET);
++                RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET);
++	    }    
++	    break;
++	case 2: //100M-half
++	    {
++	        RTL8367S_CLEAR_BIT(data,RTL8367S_REG_DUPLEX_MODE_OFFSET);
++		RTL8367S_SET_BIT(data,RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET);
++                RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET);
++	    }
++	    break;
++	case 3: //100M-full
++	    {
++	        RTL8367S_SET_BIT(data,RTL8367S_REG_DUPLEX_MODE_OFFSET);
++		RTL8367S_SET_BIT(data,RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET);
++                RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET);
++	    }
++	    break;
++	case 4: //1000M-full == auto
++	    {
++		RTL8367S_SET_BIT(data,RTL8367S_REG_DUPLEX_MODE_OFFSET);
++                RTL8367S_CLEAR_BIT(data,RTL8367S_REG_SPEED_SELECTION_LOW_OFFSET);
++                RTL8367S_SET_BIT(data,RTL8367S_REG_SPEED_SELECTION_HIGH_OFFSET);
++	    }
++	    break;
++	default:
++	    return -EINVAL;
++    }
++
++    if ((retVal = dal_rtl8367c_port_phyReg_set(smi, port, PHY_CONTROL_REG, data)) != RT_ERR_OK)
++            return retVal;
++    return RT_ERR_OK;
++}
 +
 +static int rtl8367s_extif_set_force(struct rtl8366_smi *smi, int id, int mode, 
 +				   struct rtl8367_port_ability *pa)
@@ -2273,7 +2827,6 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +		rtl8366_smi_read_reg(smi, RTL8367S_SDS_MISC, &sds_misc);
 +
 +	rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
-+
 +	link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
 +	if (!link->link)
 +		return 0;
@@ -2347,7 +2900,6 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +			        RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
 +}
 +
-+
 +static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
 +				       const struct switch_attr *attr,
 +				       struct switch_val *val)
@@ -2410,6 +2962,20 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +		.max = 33,
 +		.set = NULL,
 +		.get = rtl8366_sw_get_port_mib,
++	}, {
++		.type = SWITCH_TYPE_INT,
++		.name = "enable_port",
++		.description = "Enable or disable the port",
++		.set = dal_rtl8367c_port_phyEnableAll_set,
++		.get = get_port_state,
++		.max = 1,
++	}, {
++		.type = SWITCH_TYPE_INT,
++		.name = "set_autoNego",
++		.description = "Set auto nego of the port---"
++			       "0:10M-half  1:10M-full  2:100M-half  3:100M-full  4:1000M-full(auto)",
++		.set = dal_rtl8367c_port_crtl_status,
++		.max = 4,
 +	},
 +};
 +
@@ -2669,59 +3235,7 @@ Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/p
 +
 +module_platform_driver(rtl8367b_driver);
 +
-+MODULE_DESCRIPTION(RTL8367B_DRIVER_DESC);
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_DESCRIPTION(RTL8367S_DRIVER_DESC);
 +MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
++MODULE_ALIAS("platform:" RTL8367S_DRIVER_NAME);
 +
-Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/include/linux/rtl8367.h
-===================================================================
---- linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d.orig/include/linux/rtl8367.h
-+++ linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/include/linux/rtl8367.h
-@@ -18,6 +18,8 @@ enum rtl8367_port_speed {
- 	RTL8367_PORT_SPEED_10 = 0,
- 	RTL8367_PORT_SPEED_100,
- 	RTL8367_PORT_SPEED_1000,
-+	RTL8367S_PORT_SPEED_500M,
-+	RTL8367S_PORT_SPEED_2500M,
- };
- 
- struct rtl8367_port_ability {
-@@ -42,6 +44,9 @@ enum rtl8367_extif_mode {
- 	RTL8367B_EXTIF_MODE_RMII_MAC = 7,
- 	RTL8367B_EXTIF_MODE_RMII_PHY,
- 	RTL8367B_EXTIF_MODE_RGMII_33V,
-+	RTL8367S_EXTIF_MODE_1000X = 10,
-+	RTL8367S_EXTIF_MODE_SGMII,
-+	RTL8367S_EXTIF_MODE_HSGMII,
- };
- 
- struct rtl8367_extif_config {
-Index: linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/mdio-qca.c
-===================================================================
---- linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d.orig/drivers/net/phy/mdio-qca.c
-+++ linux-5.4.164-qsdk-26349818b464f8c7b52d59ce73579d9f3dd6bd5d/drivers/net/phy/mdio-qca.c
-@@ -574,7 +574,7 @@ static int qca_mdio_probe(struct platfor
- 	struct resource *res;
- 	int ret, i;
- 	struct reset_control *rst = ERR_PTR(-EINVAL);
--
-+	int clk_div = 0xf;
- 	if (of_machine_is_compatible("qcom,ipq5018")) {
- 		qca_tcsr_ldo_rdy_set(true);
- 		rst = of_reset_control_get(pdev->dev.of_node, "gephy_mdc_rst");
-@@ -582,9 +582,13 @@ static int qca_mdio_probe(struct platfor
- 			reset_control_deassert(rst);
- 			usleep_range(100000, 110000);
- 		}
-+		if (0 == of_property_read_u32(pdev->dev.of_node, "cig_clk_div", &ret)) //read the mdio clock value from dts
-+                        clk_div = ret;
-+	    dev_err(&pdev->dev,"CIG clk_div =%x\n",clk_div);
- 	}
- 
--	ret = qca_phy_reset(pdev);
-+	
-+    	    ret = qca_phy_reset(pdev);
- 	if (ret)
- 		dev_err(&pdev->dev, "Could not find reset gpio\n");
- 

patches/0028-Patch-Add-RTL8367C-S-switch-compile-option.patch

@@ -0,0 +1,48 @@
+From 5da6b1fb680c9a0315cb810be2d7bd6745d51883 Mon Sep 17 00:00:00 2001
+From: Ken <xshi@actiontec.com>
+Date: Tue, 17 Oct 2023 11:01:25 +0800
+Subject: [PATCH] [Patch] Add RTL8367C/S switch compile option
+
+---
+ package/kernel/linux/modules/netdevices.mk | 18 +++++++++++++++++-
+ 1 file changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
+index b8f2466cb4..1905e79a4f 100644
+--- a/package/kernel/linux/modules/netdevices.mk
++++ b/package/kernel/linux/modules/netdevices.mk
+@@ -7,6 +7,22 @@
+ 
+ NETWORK_DEVICES_MENU:=Network Devices
+ 
++define KernelPackage/switch-rtl8367c
++  SUBMENU:=$(NETWORK_DEVICES_MENU)
++  TITLE:=Realtek RTL8367C/S switch support
++  DEPENDS:=+kmod-switch-rtl8366-smi
++  KCONFIG:=CONFIG_RTL8367C_PHY=y
++  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8367c.ko
++  AUTOLOAD:=$(call AutoLoad,43,rtl8367c,1)
++endef
++
++define KernelPackage/switch-rtl8367c/description
++ Realtek RTL8367C/S switch support
++endef
++
++$(eval $(call KernelPackage,switch-rtl8367c))
++
++
+ define KernelPackage/sis190
+   SUBMENU:=$(NETWORK_DEVICES_MENU)
+   TITLE:=SiS 190 Fast/Gigabit Ethernet support
+@@ -456,7 +472,7 @@ define KernelPackage/switch-rtl8366-smi
+   SUBMENU:=$(NETWORK_DEVICES_MENU)
+   TITLE:=Realtek RTL8366 SMI switch interface support
+   DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio
+-  KCONFIG:=CONFIG_RTL8366_SMI
++  KCONFIG:=CONFIG_RTL8366_SMI=y
+   FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366_smi.ko
+   AUTOLOAD:=$(call AutoLoad,42,rtl8366_smi,1)
+ endef
+-- 
+2.34.1
+

profiles/cig_wf186h-ath12.yml

@@ -0,0 +1,23 @@
+---
+profile: cig_wf186h
+target: ipq50xx
+subtarget: generic
+description: Build image for the Cigtech Wall Plate WF186h
+image: bin/targets/ipq50xx/generic.openwrt-ipq50xx-cig_wf186h-squashfs-sysupgrade.tar
+feeds:
+  - name: ipq807x
+    path: ../../feeds/ipq807x_v5.4
+include:
+  - ucentral-ap
+packages:
+  - ipq50xx
+diffconfig: |
+  CONFIG_KERNEL_IPQ_MEM_PROFILE=512
+  CONFIG_PACKAGE_i2c-tools=y
+  CONFIG_PACKAGE_libi2c=y
+  CONFIG_PACKAGE_coreutils=y
+  CONFIG_PACKAGE_coreutils-stty=y
+  CONFIG_PACKAGE_kmod-switch-rtl8366-smi=y
+  CONFIG_PACKAGE_kmod-switch-rtl8367c=y
+
+