scottk/wlan-ap
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/wlan-ap.git synced 2025-10-30 10:02:53 +00:00
Code Issues Packages Projects Releases 10 Wiki Activity

ipq807x: drop v4.4 kernel

Browse Source 
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
2024-05-01 11:58:59 +02:00
parent f74dd74cef
commit de425e8f17
2491 changed files with 16 additions and 1124897 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
.github/workflows/build-dev.yml vendored
View File

@@ -21,7 +21,7 @@ jobs:
strategy:
fail-fast: false
matrix:
target: [ 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf196', 'cig_wf189', 'cig_wf660a', 'cybertan_eww622-a1', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap111', 'edgecore_ecw5211', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'edgecore_oap102', 'hfcl_ion4','hfcl_ion4xi_wp', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4xi_w', 'hfcl_ion4xi_HMR', 'hfcl_ion4x_w', 'indio_um-305ax', 'indio_um-325ac', 'indio_um-510ac-v3', 'indio_um-550ac', 'indio_um-310ax-v1', 'indio_um-510axp-v1', 'indio_um-510axm-v1', 'sercomm_ap72tip', 'udaya_a5-id2', 'wallys_dr40x9', 'wallys_dr6018', 'wallys_dr6018-v4', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655' ]
target: [ 'cig_wf186h', 'cig_wf186w', 'cig_wf188n', 'cig_wf196', 'cig_wf189', 'cybertan_eww631-a1', 'cybertan_eww631-b1', 'edgecore_eap101', 'edgecore_eap102', 'edgecore_eap104', 'edgecore_eap111', 'edgecore_ecw5211', 'edgecore_oap101', 'edgecore_oap101-6e', 'edgecore_oap101e', 'edgecore_oap101e-6e', 'hfcl_ion4', 'hfcl_ion4xe', 'hfcl_ion4xi', 'hfcl_ion4x', 'hfcl_ion4x_2', 'hfcl_ion4xi_w', 'hfcl_ion4x_w', 'indio_um-305ax', 'indio_um-325ac', 'indio_um-510ac-v3', 'indio_um-550ac', 'sercomm_ap72tip', 'udaya_a5-id2', 'wallys_dr40x9', 'wallys_dr6018', 'wallys_dr6018-v4', 'yuncore_ax820', 'yuncore_ax840', 'yuncore_fap640', 'yuncore_fap650', 'yuncore_fap655' ]
steps:
- uses: actions/checkout@v3

55
feeds/ipq807x/aq-fw-download/Makefile
View File

@@ -1,55 +0,0 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=aq-fw-download
PKG_BRANCH:=master
PKG_VERSION:=1.0
PKG_RELEASE:=1
PKG_BUILD_DIR:=$(BUILD_DIR)/aq-fw-download
include $(INCLUDE_DIR)/package.mk
define AquantiaUtil
define Package/aq-fw-download
SECTION:=utils
CATEGORY:=Utilities
DEPENDS:=@TARGET_ipq806x||TARGET_ipq||TARGET_ipq40xx||TARGET_ipq807x_32||TARGET_ipq807x
TITLE:=Aquantia FW downloader utitlity
endef
define Package/aq-fw-download/description
Aquantia FW downloader utitlity
endef
TARGET_CPPFLAGS := \
-D_GNU_SOURCE \
-I$(LINUX_SRC_DIR)/include \
-I$(LINUX_SRC_DIR)/arch/$(LINUX_KARCH)/include \
-I$(PKG_BUILD_DIR) \
$(TARGET_CPPFLAGS)
define Build/Prepare
mkdir -p $(PKG_BUILD_DIR)
$(CP) ./src/* $(PKG_BUILD_DIR)/
endef
define Build/Compile
CFLAGS="$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)" \
LDFLAGS="$(TARGET_LDFLAGS)" \
$(MAKE) -C $(PKG_BUILD_DIR) \
$(TARGET_CONFIGURE_OPTS)
endef
define Package/aq-fw-download/install
$(INSTALL_DIR) $$(1)/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/aq-fw-download $$(1)/sbin/aq-fw-download
endef
$$(eval $$(call BuildPackage,aq-fw-download))
endef
#Build/Compile=true
$(eval $(call AquantiaUtil))

14
feeds/ipq807x/aq-fw-download/src/Makefile
View File

@@ -1,14 +0,0 @@
ifndef CFLAGS
CFLAGS = -O2 -g
endif
INCLUDES=-Iinclude -Iinclude/registerMap \
-Iinclude/registerMap/APPIA \
-Iinclude/registerMap/HHD
all: aq-fw-download
%.o: %.c
$(CC) $(INCLUDES) $(CFLAGS) -c -o $@ $^
aq-fw-download: mdioBootLoadCLD.o src/AQ_PhyInterface.o src/AQ_API.o
$(CC) $(LDFLAGS) -o $@ $^ $(LIBS)

246
feeds/ipq807x/aq-fw-download/src/include/AQ_API.h
View File

@@ -1,246 +0,0 @@
/*
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*! \file
This file contains the AQ_API function and datatype declarations. */
#ifndef AQ_API_TOKEN
#define AQ_API_TOKEN
#include <stdint.h>
#include "AQ_User.h"
#include "AQ_ReturnCodes.h"
/*******************************************************************
General
*******************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*! This typedef defines the bool datatype which takes the values
true and false.*/
typedef enum {False = 0, True = 1} AQ_boolean;
/*@}*/
/*******************************************************************
Device Identity
*******************************************************************/
/*! \defgroup deviceIdentity Device Identity
All AQ_API functions accept a parameter identifying the target PHY that
should be acted upon. */
/*@{*/
/*! This enumeration is used to describe the different types of
Aquantia PHY.*/
typedef enum
{
/*! 1/2/4-port package, 40nm architechture.*/
AQ_DEVICE_APPIA,
/*! 1/2/4-port package, 28nm architechture.*/
AQ_DEVICE_HHD
} AQ_API_Device;
/*! This structure is used to specify a particular Aquantia PHY port
within the system.*/
typedef struct
{
/*! The type of Aquantia PHY*/
AQ_API_Device device;
/*! Uniquely identifies the port within the system. AQ_Port must be
defined to whatever data type is suitable for the platform.
AQ_API functions will never do anything with PHY_ID other than
pass it down to the platform's PHY register read/write
functions.*/
AQ_Port PHY_ID;
} AQ_API_Port;
/*@}*/
/*! This function boot-loads the instruction and data memory (IRAM and
DRAM) of a set of Aquantia PHYs from a .cld format image file (the
same image file used to burn the FLASH). During boot-load of each
Aquantia PHY, the processor is halted, and after programming is
complete the processor is released. Note that calling this
function leaves the daisy-chain disabled to prevent RAM over-
write. To exit MDIO boot-load mode, use the function
AQ_API_EnableDaisyChain.
Unlike most of the other functions in this API, this function can
operate on a group of PHYs simultaneously. This is referred to as
gang-loading. To facilitate this, this function takes as
parameters 3 parallel arrays: PHY_IDs, provisioningAddresses, and
resultCodes. The length of these arrays must be identical, and is
specified by the num_PHY_IDs parameter.
In order to check the integrity of the boot-load operation, a
CRC-16 value is calculated over the IRAM and DRAM. After the image
has been loaded, this value is directly compared against each
PHY's Mailbox CRC-16 in 1E.0201.
The value of register 1E.C441 must be the same for all the boot-
loaded PHYs. This will be checked before the boot-load is
performed, and if a non-uniform value is read from any of the
PHYs, the function will fail before any writes are performed.
A separate result code is returned for each of the boot-loaded
PHYs, in the OUT parameter, resultCodes.
Individual Port Return codes:
AQ_RET_BOOTLOAD_PROVADDR_OOR: The specified provisioning address
was outside of the permitted range.
AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS: The values of the register(s)
that must be uniform across the ports being bootloaded were not
uniform.
AQ_RET_BOOTLOAD_CRC_MISMATCH: The image was completely loaded into
memory, but the after the port exited bootload the running
checksum that was read from the uP memory mailbox was not the
expected value. This indicates that the memory has potentially
been corrupted, and the PHY should be reset before trying the
bootload again.
Overall Return codes (the return value from the function call):
AQ_RET_OK: all ports were successfully bootloaded.
AQ_RET_ERROR: One or more ports were not successfully bootloaded.
*/
AQ_Retcode AQ_API_WriteBootLoadImage
(
/*! An array identifying the target PHY ports.*/
AQ_API_Port** ports,
/*! The length of the arrays ports, provisioningAddresses, and
resultCodes. These are parallel arrays, and must all be of the
same length.*/
unsigned int numPorts,
/*! The provisioning addresses of each of the PHYs specified in
ports. This can range from 0 through 47, and is also known as
the daisy-chain address or the hop-count. If the PHYs are
connected to a FLASH using the daisy-chain, this is the distance
from the PHY to the FLASH, and is used to identify customized
provisioning for each PHY from the provisioning data within the
image. Otherwise, it is an arbitrary number. The length of this
array must match the length of ports.*/
unsigned int* provisioningAddresses,
/*! OUT: The result code indicating success or failure of boot-
loading each of the PHYs specified in ports.*/
AQ_Retcode* resultCodes,
/*! A pointer to the size of the image (in bytes) that is being
loaded into the Aquantia PHY.*/
uint32_t* imageSizePointer,
/*! The image being loaded into the Aquantia PHY. This is the same
regardless of whether the target is internal RAM or FLASH.*/
uint8_t* image,
/*! The 5-bit address to be used during the gang-loading operation.
During the boot-loading process, each of the PHYs specified in
ports will be changed such that they are addressed on the MDIO
bus at gangloadAddress. This allows all the PHYs to be loaded
simultaneously. Before returning, each PHY will be moved back to
its original MDIO address. If ports contains only a single
element, callers will probably want to use the PHY's original
MDIO address for this parameter.*/
uint8_t gangload_MDIO_address,
/*! The address of the PHYs while in gangload mode. This is
ultimately some combination of the system address and the
gangload MDIO address, specified by gangload_MDIO_address. For
most platforms, gangload_MDIO_address and gangload_PHY_ID should
have the same value.*/
AQ_API_Port* gangloadPort
);
/*! This function boot-loads the instruction and data memory (IRAM and
DRAM) of a set of Aquantia PHYs from a .cld format image file (the
same image file used to burn the FLASH), as well as a separately
provided provisioning table image file.The provisioning table
image allows additional provisioning to be provided, beyond what
is built in to the .cld image. If provTableSizePointer or
provTableImage are NULL, this function behaves like
AQ_API_WriteBootLoadImage.
Aside from the additional provisioing table, this function behaves
exactly the same as AQ_API_WriteBootLoadImage. For additional
documentation and information on return codes, refer to
AQ_API_WriteBootLoadImage.
Individual Port Return codes (same as AQ_API_WriteBootLoadImage,
plus):
AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE: The supplied provisioning
table image does not fit within the alloted space.*/
AQ_Retcode AQ_API_WriteBootLoadImageWithProvTable
(
/*! An array identifying the target PHY ports.*/
AQ_API_Port** ports,
/*! The length of the arrays ports, provisioningAddresses, and
resultCodes. These are parallel arrays, and must all be of the
same length.*/
unsigned int numPorts,
/*! The provisioning addresses of each of the PHYs specified in
ports. This can range from 0 through 47, and is also known as
the daisy-chain address or the hop-count. If the PHYs are
connected to a FLASH using the daisy-chain, this is the distance
from the PHY to the FLASH, and is used to identify customized
provisioning for each PHY from the provisioning data within the
image. Otherwise, it is an arbitrary number. The length of this
array must match the length of ports.*/
unsigned int* provisioningAddresses,
/*! OUT: The result code indicating success or failure of boot-
loading each of the PHYs specified in ports.*/
AQ_Retcode* resultCodes,
/*! A pointer to the size of the image (in bytes) that is being
loaded into the Aquantia PHY.*/
uint32_t* imageSizePointer,
/*! The image being loaded into the Aquantia PHY. This is the same
regardless of whether the target is internal RAM or FLASH.*/
uint8_t* image,
/*! The 5-bit address to be used during the gang-loading operation.
During the boot-loading process, each of the PHYs specified in
ports will be changed such that they are addressed on the MDIO
bus at gangloadAddress. This allows all the PHYs to be loaded
simultaneously. Before returning, each PHY will be moved back to
its original MDIO address. If ports contains only a single
element, callers will probably want to use the PHY's original
MDIO address for this parameter.*/
uint8_t gangload_MDIO_address,
/*! The address of the PHYs while in gangload mode. This is
ultimately some combination of the system address and the
gangload MDIO address, specified by gangload_MDIO_address. For
most platforms, gangload_MDIO_address and gangload_PHY_ID should
have the same value.*/
AQ_API_Port* gangloadPort,
/*! A pointer to the size of the provTableImage (in bytes) that is
being loaded into the Aquantia PHY.*/
uint32_t* provTableSizePointer,
/*! The additional provisioning table image being loaded into the
Aquantia PHY.*/
uint8_t* provTableImage
);
/*! Calling this function disables boot-loading and enables the daisy-
chain. This would typically be called after using MDIO boot-
loading on a daisy-chain enabled PHY. Re-enabling the daisy-chain
after performing an MDIO bootload will cause the PHY to reboot
from FLASH.*/
AQ_Retcode AQ_API_EnableDaisyChain
(
/*! The target PHY port.*/
AQ_API_Port* port
);
#ifdef __cplusplus
}
#endif
#endif

171
feeds/ipq807x/aq-fw-download/src/include/AQ_PhyInterface.h
View File

@@ -1,171 +0,0 @@
/* AQ_PhyInterface.h */
/***********************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* Description:
*
* Declares the base PHY register read and write functions that are
* called by the API functions. The platform integrator must provide
* the implementation of these routines.
*
***********************************************************************/
/*! \file
* Declares the base PHY register read and write functions that are
* called by the API functions. The platform integrator must provide
* the implementation of these routines. */
#ifndef AQ_PHY_INTERFACE_TOKEN
#define AQ_PHY_INTERFACE_TOKEN
#include "AQ_API.h"
#include "AQ_User.h"
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************
MDIO Access Functions
*******************************************************************/
/*! \defgroup mdioAccessFunctions MDIO Access Functions
The MDIO access functions are required by the API to access the register space
of each Aquantia PHY deployed in a system. The body of these functions needs to
be written by the system designer, as the method of accessing the PHY will
be unique to the target system. They are designed to be generic read and
write access functions, as the MDIO addressing scheme relies on each
MMD to maintain a 16 bit address pointer that determines the register where
the next read or write is coming from. Consequently, various levels of
optimization of the MDIO interface are possible: from re-writing the MMD
address pointer on every transaction, to storing shadow copies of the MMD
address pointers and only updating the MMD address pointer as necessary.
Thus these functions leave the MDIO optimization to the system engineer.
*/
/*@{*/
/*! Provides generic synchronous PHY register write functionality. It is the
* responsibility of the system designer to provide the specific MDIO address
* pointer updates, etc. in order to accomplish this write operation.
* It will be assumed that the write has been completed by the time this
* function returns.*/
void AQ_API_MDIO_Write
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being written. */
unsigned int address,
/*! The 16-bits of data to write to the specified PHY register. */
unsigned int data
);
/*! Provides generic synchronous PHY register read functionality. It is the
* responsibility of the system designer to provide the specific MDIO address
* pointer updates, etc. in order to accomplish this read operation.*/
unsigned int AQ_API_MDIO_Read
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being read. */
unsigned int address
);
#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
/*! Provides generic asynchronous/buffered PHY register write functionality.
* It is the responsibility of the system designer to provide the specific
* MDIO address pointer updates, etc. in order to accomplish this write
* operation. The write need not necessarily have been completed by the time
* this function returns. All register reads and writes to a particular PHY_ID
* that are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead
* MUST be performed in the order that the calls are made. */
void AQ_API_MDIO_BlockWrite
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being written. */
unsigned int address,
/*! The 16-bits of data to write to the specified PHY register. */
unsigned int data
);
/*! Provides generic asynchronous/buffered PHY register read functionality.
* It is the responsibility of the system designer to provide the specific
* MDIO address pointer updates, etc. in order to accomplish this read
* operation. All register reads and writes to a particular PHY_ID that
* are requested by calling AQ_API_MDIO_BlockWrite or AQ_API_MDIO_BlockRead
* MUST be performed in the order that the calls are made. The register value
* may subsequently be fetched by calling AQ_API_MDIO_BlockOperationExecute.*/
void AQ_API_MDIO_BlockRead
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being read. */
unsigned int address
);
/* Retrieve the results of all PHY register reads to PHY_ID previously
* requested via calls to AQ_API_MDIO_BlockRead. The read and write
* operations previously performed by calls to AQ_API_MDIO_BlockRead and
* AQ_API_MDIO_BlockRead must have all been completed by the time this
* function returns, in the order that the calls were performed. The
* return value is an array representing the fetched results of all
* pending calls to AQ_API_MDIO_BlockRead, in the order that the calls
* were performed. Callers should track the number of pending block
* reads to determine the size of the returned array. */
unsigned int * AQ_API_MDIO_BlockOperationExecute
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID
);
/* Returns the maximum number of asynchronous/buffered PHY register
* read/write operations. Callers will call AQ_API_MDIO_BlockOperationExecute
* before issuing additional calls to AQ_API_MDIO_BlockWrite or
* AQ_API_MDIO_BlockRead to avoid a buffer overflow. */
unsigned int AQ_API_MDIO_MaxBlockOperations
(
);
#endif
/*@}*/
#ifdef __cplusplus
}
#endif
#endif

71
feeds/ipq807x/aq-fw-download/src/include/AQ_PlatformRoutines.h
View File

@@ -1,71 +0,0 @@
/*AQ_PlatformRoutines.h*/
/************************************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* Description:
*
* Declares the platform interface functions that will be called by AQ_API
* functions. The platform integrator must provide the implementation of
* these functions.
*
************************************************************************************/
/*! \file
* Declares the platform interface functions that will be called by AQ_API
* functions. The platform integrator must provide the implementation of
* these functions. */
#ifndef AQ_PHY_PLATFORMROUTINES_TOKEN
#define AQ_PHY_PLATFORMROUTINES_TOKEN
#include <stdint.h>
#include "AQ_API.h"
#include "AQ_User.h"
#include "AQ_ReturnCodes.h"
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************
Time Delay
*******************************************************************/
/*! \defgroup delay Time Delay
@{
*/
/*! Returns after at least milliseconds have elapsed. This must be implemented
* in a platform-approriate way. AQ_API functions will call this function to
* block for the specified period of time. If necessary, PHY register reads
* may be performed on port to busy-wait. */
void AQ_API_Wait
(
uint32_t milliseconds, /*!< The delay in milliseconds */
AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/
);
/*@}*/
#ifdef __cplusplus
}
#endif
#endif

323
feeds/ipq807x/aq-fw-download/src/include/AQ_RegMacro.h
View File

@@ -1,323 +0,0 @@
/* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*! \file
This file contains macros for accessing the AQ PHYs' registers
using the device-specific register map data structures and definitions.
*/
#ifndef AQ_REG_MACRO_TOKEN
#define AQ_REG_MACRO_TOKEN
#include "AQ_PhyInterface.h"
#define AQ_API_ReadRegister(id,reg,wd) AQ_API_ReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd)
#define AQ_API_ReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_ReadRegister_Devs_ ## devices(id,reg,wd)
#define AQ_API_ReadRegister_Devs_APPIA(id,reg,wd) \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \
(0))
#define AQ_API_ReadRegister_Devs_HHD(id,reg,wd) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \
(0))
#define AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Read (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Read (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \
(0)))
#define AQ_API_ReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,wd)
#define AQ_API_WriteRegister(id,reg,wd,value) AQ_API_WriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value)
#define AQ_API_WriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_WriteRegister_Devs_ ## devices(id,reg,wd,value)
#define AQ_API_WriteRegister_Devs_APPIA(id,reg,wd,value) \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \
((void)0))
#define AQ_API_WriteRegister_Devs_HHD(id,reg,wd,value) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \
((void)0))
#define AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_Write (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_Write (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \
((void)0)))
#define AQ_API_WriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,wd,value)
#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
#define AQ_API_BlockReadRegister(id,reg,wd) AQ_API_BlockReadRegister_DeviceRestricted(APPIA_HHD,id,reg,wd)
#define AQ_API_BlockReadRegister_DeviceRestricted(devices,id,reg,wd) AQ_API_BlockReadRegister_Devs_ ## devices(id,reg,wd)
#define AQ_API_BlockReadRegister_Devs_APPIA(id,reg,wd) \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \
((void)0))
#define AQ_API_BlockReadRegister_Devs_HHD(id,reg,wd) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \
((void)0))
#define AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockRead (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd)) : \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockRead (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd)) : \
((void)0)))
#define AQ_API_BlockReadRegister_Devs_HHD_APPIA(id,reg,wd) AQ_API_BlockReadRegister_Devs_APPIA_HHD(id,reg,wd)
#define AQ_API_BlockWriteRegister(id,reg,wd,value) AQ_API_BlockWriteRegister_DeviceRestricted(APPIA_HHD,id,reg,wd,value)
#define AQ_API_BlockWriteRegister_DeviceRestricted(devices,id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_ ## devices(id,reg,wd,value)
#define AQ_API_BlockWriteRegister_Devs_APPIA(id,reg,wd,value) \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \
((void)0))
#define AQ_API_BlockWriteRegister_Devs_HHD(id,reg,wd,value) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \
((void)0))
#define AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value) \
((port->device == AQ_DEVICE_HHD) ? AQ_API_MDIO_BlockWrite (id,reg ## _HHD_mmdAddress,(reg ## _HHD_baseRegisterAddress + wd),value) : \
((port->device == AQ_DEVICE_APPIA) ? AQ_API_MDIO_BlockWrite (id,reg ## _APPIA_mmdAddress,(reg ## _APPIA_baseRegisterAddress + wd),value) : \
((void)0)))
#define AQ_API_BlockWriteRegister_Devs_HHD_APPIA(id,reg,wd,value) AQ_API_BlockWriteRegister_Devs_APPIA_HHD(id,reg,wd,value)
#endif
#define AQ_API_Variable(reg) AQ_API_Variable_DeviceRestricted(APPIA_HHD,reg)
#define AQ_API_Variable_DeviceRestricted(devices,reg) AQ_API_Variable_Devs_ ## devices(reg)
#define AQ_API_Variable_Devs_APPIA(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \
#define AQ_API_Variable_Devs_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \
#define AQ_API_Variable_Devs_APPIA_HHD(reg) uint8_t _local ## reg ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _APPIA* _local ## reg ## _APPIA = (reg ## _APPIA*) _local ## reg ## _space; \
reg ## _HHD* _local ## reg ## _HHD = (reg ## _HHD*) _local ## reg ## _space; \
#define AQ_API_Variable_Devs_HHD_APPIA(reg) AQ_API_Variable_Devs_APPIA_HHD(reg)
#define AQ_API_DeclareLocalStruct(reg,localvar) AQ_API_DeclareLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar)
#define AQ_API_DeclareLocalStruct_DeviceRestricted(devices,reg,localvar) AQ_API_DeclareLocalStruct_Devs_ ## devices(reg,localvar)
#define AQ_API_DeclareLocalStruct_Devs_APPIA(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \
#define AQ_API_DeclareLocalStruct_Devs_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \
#define AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar) uint8_t localvar ## _space[ sizeof(reg ## _BiggestVersion) ];\
reg ## _APPIA* localvar ## _APPIA = (reg ## _APPIA*) localvar ## _space; \
reg ## _HHD* localvar ## _HHD = (reg ## _HHD*) localvar ## _space; \
#define AQ_API_DeclareLocalStruct_Devs_HHD_APPIA(reg,localvar) AQ_API_DeclareLocalStruct_Devs_APPIA_HHD(reg,localvar)
#define AQ_API_Set(id,reg,field,value) AQ_API_Set_DeviceRestricted(APPIA_HHD,id,reg,field,value)
#define AQ_API_Set_DeviceRestricted(devices,id,reg,field,value) AQ_API_Set_Devs_ ## devices(id,reg,field,value)
#define AQ_API_Set_Devs_APPIA(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_APPIA: \
_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \
if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \
{ \
_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \
AQ_API_WriteRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \
} \
break; \
default: break; \
} \
}
#define AQ_API_Set_Devs_HHD(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_HHD: \
_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \
if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \
{ \
_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \
AQ_API_WriteRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \
} \
break; \
default: break; \
} \
}
#define AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_APPIA: \
_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \
if (_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field != value) \
{ \
_local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field = value; \
AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field,_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field); \
} \
break; \
case AQ_DEVICE_HHD: \
_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \
if (_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field != value) \
{ \
_local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field = value; \
AQ_API_WriteRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field,_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field); \
} \
break; \
default: break; \
} \
}
#define AQ_API_Set_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Set_Devs_APPIA_HHD(id,reg,field,value)
#define AQ_API_Get(id,reg,field,value) AQ_API_Get_DeviceRestricted(APPIA_HHD,id,reg,field,value)
#define AQ_API_Get_DeviceRestricted(devices,id,reg,field,value) AQ_API_Get_Devs_ ## devices(id,reg,field,value)
#define AQ_API_Get_Devs_APPIA(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_APPIA: \
_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA(id,reg,reg ## _APPIA_ ## field); \
value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \
break; \
default: value = 0; break; \
} \
}
#define AQ_API_Get_Devs_HHD(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_HHD: \
_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_HHD(id,reg,reg ## _HHD_ ## field); \
value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \
break; \
default: value = 0; break; \
} \
}
#define AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value) { \
switch (port->device) { \
case AQ_DEVICE_APPIA: \
_local ## reg ## _APPIA->word_ ## reg ## _APPIA_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _APPIA_ ## field); \
value = _local ## reg ## _APPIA->bits_ ## reg ## _APPIA_ ## field.field; \
break; \
case AQ_DEVICE_HHD: \
_local ## reg ## _HHD->word_ ## reg ## _HHD_ ## field = AQ_API_ReadRegister_Devs_APPIA_HHD(id,reg,reg ## _HHD_ ## field); \
value = _local ## reg ## _HHD->bits_ ## reg ## _HHD_ ## field.field; \
break; \
default: value = 0; break; \
} \
}
#define AQ_API_Get_Devs_HHD_APPIA(id,reg,field,value) AQ_API_Get_Devs_APPIA_HHD(id,reg,field,value)
#define AQ_API_BitfieldOfLocalStruct(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field)
#define AQ_API_BitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field)
#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field) \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \
(0))
#define AQ_API_BitfieldOfLocalStruct_Devs_HHD(reg,localvar,field) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \
(0))
#define AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field) : \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field) : \
(0)))
#define AQ_API_BitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field) AQ_API_BitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field)
#define AQ_API_AssignBitfieldOfLocalStruct(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(APPIA_HHD,reg,localvar,field,value)
#define AQ_API_AssignBitfieldOfLocalStruct_DeviceRestricted(devices,reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_ ## devices(reg,localvar,field,value)
#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA(reg,localvar,field,value) \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \
(0))
#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD(reg,localvar,field,value) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \
(0))
#define AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->bits_ ## reg ## _HHD ## _ ## field.field = value) : \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->bits_ ## reg ## _APPIA ## _ ## field.field = value) : \
(0)))
#define AQ_API_AssignBitfieldOfLocalStruct_Devs_HHD_APPIA(reg,localvar,field,value) AQ_API_AssignBitfieldOfLocalStruct_Devs_APPIA_HHD(reg,localvar,field,value)
#define AQ_API_WordOfLocalStruct(localvar,wd) AQ_API_WordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd)
#define AQ_API_WordOfLocalStruct_DeviceRestricted(devices,localvar,wd) AQ_API_WordOfLocalStruct_Devs_ ## devices(localvar,wd)
#define AQ_API_WordOfLocalStruct_Devs_APPIA(localvar,wd) \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \
(0))
#define AQ_API_WordOfLocalStruct_Devs_HHD(localvar,wd) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \
(0))
#define AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd) : \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd) : \
(0)))
#define AQ_API_WordOfLocalStruct_Devs_HHD_APPIA(localvar,wd) AQ_API_WordOfLocalStruct_Devs_APPIA_HHD(localvar,wd)
#define AQ_API_AssignWordOfLocalStruct(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_DeviceRestricted(APPIA_HHD,localvar,wd,value)
#define AQ_API_AssignWordOfLocalStruct_DeviceRestricted(devices,localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_ ## devices(localvar,wd,value)
#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA(localvar,wd,value) \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \
(0))
#define AQ_API_AssignWordOfLocalStruct_Devs_HHD(localvar,wd,value) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \
(0))
#define AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value) \
((port->device == AQ_DEVICE_HHD) ? ((localvar ## _HHD)->u ## wd.word_ ## wd = value) : \
((port->device == AQ_DEVICE_APPIA) ? ((localvar ## _APPIA)->u ## wd.word_ ## wd = value) : \
(0)))
#define AQ_API_AssignWordOfLocalStruct_Devs_HHD_APPIA(localvar,wd,value) AQ_API_AssignWordOfLocalStruct_Devs_APPIA_HHD(localvar,wd,value)
#endif

113
feeds/ipq807x/aq-fw-download/src/include/AQ_ReturnCodes.h
View File

@@ -1,113 +0,0 @@
/* AQ_ReturnCodes.h */
/************************************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* Description:
*
* This file defines the AQ_API functions' integral return codes.
*
*
************************************************************************************/
/*! \file
This file defines the AQ_API functions' integral return codes.
*/
#ifndef AQ_RETURNCODES_TOKEN
#define AQ_RETURNCODES_TOKEN
/*! \defgroup ReturnCodes
@{
*/
/*! Most AQ_API functions return AQ_Retcode to report success or failure.
* The values used are defined as preprocessor symbols in AQ_ReturnCodes.h.
* Callers should prefer to test the return values by equivalence to these
* symbols, rather than using the integer values directly, as these may
* not be stable across releases. The set of possible return codes that may
* be returned by a particular API function can be found in the function's
* documentation, as well as information on how to interpret each of the
* possible return codes. */
typedef unsigned int AQ_Retcode;
/*! \defgroup Success
@{ */
#define AQ_RET_OK 0
/*@}*/
/*! \defgroup GeneralErrors
@{ */
#define AQ_RET_ERROR 100
#define AQ_RET_UP_BUSY_TIMEOUT 101
/*@}*/
/*! \defgroup FunctionSpecificResults
@{ */
#define AQ_RET_FLASH_READY 200
#define AQ_RET_FLASH_READINESS_TIMEOUT 204
#define AQ_RET_FLASHINTF_READY 201
#define AQ_RET_FLASHINTF_NOTREADY 202
#define AQ_RET_FLASHINTF_READINESS_TIMEOUT 203
#define AQ_RET_FLASH_TYPE_UNKNOWN 205
#define AQ_RET_FLASH_TYPE_BAD 206
#define AQ_RET_FLASH_IMAGE_CORRUPT 207
#define AQ_RET_FLASH_IMAGE_TOO_LARGE 208
#define AQ_RET_FLASH_IMAGE_MISMATCH 209
#define AQ_RET_FLASH_PAGE_SIZE_CHANGED 210
#define AQ_RET_BOOTLOAD_PROVADDR_OOR 211
#define AQ_RET_BOOTLOAD_NONUNIFORM_REGVALS 212
#define AQ_RET_BOOTLOAD_CRC_MISMATCH 213
#define AQ_RET_BOOTLOAD_PROVTABLE_TOO_LARGE 228
#define AQ_RET_LOOPBACK_BAD_ENTRY_STATE 214
#define AQ_RET_DEBUGTRACE_FREEZE_TIMEOUT 215
#define AQ_RET_DEBUGTRACE_UNFREEZE_TIMEOUT 216
#define AQ_RET_CABLEDIAG_ALREADY_RUNNING 217
#define AQ_RET_CABLEDIAG_STILL_RUNNING 218
#define AQ_RET_CABLEDIAG_BAD_PAIRSTATUS 219
#define AQ_RET_CABLEDIAG_RESULTS_ALREDY_COLLECTED 220
#define AQ_RET_CABLEDIAG_BAD_NUM_SAMPLES 221
#define AQ_RET_CABLEDIAG_REPORTEDPAIR_MISMATCH 222
#define AQ_RET_CABLEDIAG_REPORTEDPAIR_OOR 223
#define AQ_RET_CABLEDIAG_STARTED_PAIR_B 224
#define AQ_RET_CABLEDIAG_STARTED_PAIR_C 225
#define AQ_RET_CABLEDIAG_STARTED_PAIR_D 226
#define AQ_RET_CABLEDIAG_TXENABLE_MISMATCH 227
#define AQ_RET_SERDESEYE_BAD_SERDES_MODE 229
#define AQ_RET_SERDESEYE_BAD_MEAS_COUNT 230
#define AQ_RET_SERDESEYE_MEAS_TIMEOUT 231
#define AQ_RET_SERDESEYE_LANE_OOR 232
#define AQ_RET_SERDESEYE_COORD_OOR 233
#define AQ_RET_PIFMAILBOX_ERROR 234
#define AQ_RET_PIFMAILBOX_TIMEOUT 235
#define AQ_RET_SEC_TABLE_INDEX_OOR 236
/*@}*/
/*@}*/
#endif

97
feeds/ipq807x/aq-fw-download/src/include/AQ_User.h
View File

@@ -1,97 +0,0 @@
/*AQ_User.h*/
/************************************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* Description:
*
* This file contains preprocessor symbol definitions and type definitions
* for the platform-integrator controlled compile-time AQ_API options.
*
************************************************************************************/
/*! \file
This file contains preprocessor symbol definitions and type definitions
for the platform-integrator controlled compile-time AQ_API options.
*/
#ifndef AQ_USER_TOKEN
#define AQ_USER_TOKEN
/*! \defgroup User User Definitions
This module contains the definitions used to configure AQ_API behavior as desired. */
/*@{*/
/*! Specify the proper data type for AQ_Port. This will depend on the
* platform-specific implementation of the PHY register read/write functions.*/
typedef unsigned int AQ_Port;
/*! If defined, AQ_API functions will print various error and info messages
* to stdout. If not, nothing will be printed and AQ_API.c will NOT include
* stdio.h. */
#define AQ_VERBOSE
/*! If defined, the PHY interface supports block (asynchronous) read/write
* operation. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is defined, then
* the API will call the block-operation functions and so implementations
* for each must be provided. If AQ_PHY_SUPPORTS_BLOCK_READ_WRITE is not
* defined, they will not be called, and need not be implemented. */
#undef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
/*! If defined, time.h exists, and so the associated functions wil be used to
* compute the elapsed time spent in a polling loop, to ensure that the
* maximum time-out period will not be exceeded. If not defined, then
* AQ_MDIO_READS_PER_SECOND will be used to calculate the minimum possible
* elapsed time. */
#define AQ_TIME_T_EXISTS
/*! The maximum number of synchronous PHY register reads that can be performed
* per second. A worst case number can be derived as follows:
*
* AQ_MDIO_READS_PER_SECOND = MDIO Clock Frequency / 64
*
* If using MDIO preamble suppression, multiply this number by 2
*
* For instance, if a 5MHz MDIO clock is being used without preamble supression
* AQ_MDIO_READS_PER_SECOND = 78125
*
* If AQ_TIME_T_EXISTS is defined, this will be ignored and need not be
* defined. If AQ_TIME_T_EXISTS is not defined, this must be defined. */
#define AQ_MDIO_READS_PER_SECOND 78125
/*! If defined, after writing to one of the registers that can trigger a
* processor-intensive MDIO operation, AQ_API functions will poll the
* the "processor intensive MDIO operation in progress" bit and wait for it
* to be zero before proceeding. */
#define AQ_ENABLE_UP_BUSY_CHECKS
/*! If defined, the register map header files containing reverse-packed
* structs will be included. If not, the register map header files containing
* non-reverse-packed structs will be included. The proper choice is typically
* a function of the endianness of the platform; on big-endian systems the
* reverse-packed structs should be used, and on little-endian systems the
* non-reverse-packed structs should be used. */
/*#define AQ_REVERSED_BITFIELD_ORDERING*/
/*@}*/
#endif

5581
feeds/ipq807x/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers.h
View File

File diff suppressed because it is too large Load Diff

2134
feeds/ipq807x/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_Defines.h
View File

File diff suppressed because it is too large Load Diff

5581
feeds/ipq807x/aq-fw-download/src/include/registerMap/APPIA/AQ_APPIA_Global_registers_reversed.h
View File

File diff suppressed because it is too large Load Diff

387
feeds/ipq807x/aq-fw-download/src/include/registerMap/AQ_RegGroupMaxSizes.h
View File

@@ -1,387 +0,0 @@
/* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef AQ_REG_GROUP_MAX_SIZES
#define AQ_REG_GROUP_MAX_SIZES
#define AQ_Autonegotiation10GBaseT_ControlRegister_BiggestVersion AQ_Autonegotiation10GBaseT_ControlRegister_HHD
#define AQ_Autonegotiation10GBaseT_StatusRegister_BiggestVersion AQ_Autonegotiation10GBaseT_StatusRegister_HHD
#define AQ_AutonegotiationAdvertisementRegister_BiggestVersion AQ_AutonegotiationAdvertisementRegister_HHD
#define AQ_AutonegotiationEeeAdvertisementRegister_BiggestVersion AQ_AutonegotiationEeeAdvertisementRegister_HHD
#define AQ_AutonegotiationEeeLinkPartnerAbilityRegister_BiggestVersion AQ_AutonegotiationEeeLinkPartnerAbilityRegister_HHD
#define AQ_AutonegotiationExtendedNextPageTransmitRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageTransmitRegister_HHD
#define AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationExtendedNextPageUnformattedCodeRegister_HHD
#define AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerBasePageAbilityRegister_HHD
#define AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageAbilityRegister_HHD
#define AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_BiggestVersion AQ_AutonegotiationLinkPartnerExtendedNextPageUnformattedCodeRegister_HHD
#define AQ_AutonegotiationReceiveLinkPartnerStatus_BiggestVersion AQ_AutonegotiationReceiveLinkPartnerStatus_HHD
#define AQ_AutonegotiationReceiveReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReceiveReservedVendorProvisioning_APPIA
#define AQ_AutonegotiationReceiveReservedVendorStatus_BiggestVersion AQ_AutonegotiationReceiveReservedVendorStatus_HHD
#define AQ_AutonegotiationReceiveVendorAlarms_BiggestVersion AQ_AutonegotiationReceiveVendorAlarms_HHD
#define AQ_AutonegotiationReceiveVendorInterruptMask_BiggestVersion AQ_AutonegotiationReceiveVendorInterruptMask_HHD
#define AQ_AutonegotiationReservedVendorProvisioning_BiggestVersion AQ_AutonegotiationReservedVendorProvisioning_HHD
#define AQ_AutonegotiationReservedVendorStatus_BiggestVersion AQ_AutonegotiationReservedVendorStatus_HHD
#define AQ_AutonegotiationStandardControl_1_BiggestVersion AQ_AutonegotiationStandardControl_1_HHD
#define AQ_AutonegotiationStandardDeviceIdentifier_BiggestVersion AQ_AutonegotiationStandardDeviceIdentifier_HHD
#define AQ_AutonegotiationStandardDevicesInPackage_BiggestVersion AQ_AutonegotiationStandardDevicesInPackage_HHD
#define AQ_AutonegotiationStandardInterruptMask_BiggestVersion AQ_AutonegotiationStandardInterruptMask_HHD
#define AQ_AutonegotiationStandardPackageIdentifier_BiggestVersion AQ_AutonegotiationStandardPackageIdentifier_HHD
#define AQ_AutonegotiationStandardStatus_1_BiggestVersion AQ_AutonegotiationStandardStatus_1_HHD
#define AQ_AutonegotiationStandardStatus_2_BiggestVersion AQ_AutonegotiationStandardStatus_2_HHD
#define AQ_AutonegotiationTransmitVendorAlarms_BiggestVersion AQ_AutonegotiationTransmitVendorAlarms_APPIA
#define AQ_AutonegotiationTransmitVendorInterruptMask_BiggestVersion AQ_AutonegotiationTransmitVendorInterruptMask_HHD
#define AQ_AutonegotiationVendorGlobalInterruptFlags_BiggestVersion AQ_AutonegotiationVendorGlobalInterruptFlags_HHD
#define AQ_AutonegotiationVendorProvisioning_BiggestVersion AQ_AutonegotiationVendorProvisioning_HHD
#define AQ_AutonegotiationVendorStatus_BiggestVersion AQ_AutonegotiationVendorStatus_HHD
#define AQ_GbePhyExtendedWolControl_BiggestVersion AQ_GbePhyExtendedWolControl_HHD
#define AQ_GbePhySgmii0RxStatus_BiggestVersion AQ_GbePhySgmii0RxStatus_HHD
#define AQ_GbePhySgmii0TxStatus_BiggestVersion AQ_GbePhySgmii0TxStatus_HHD
#define AQ_GbePhySgmii1RxStatus_BiggestVersion AQ_GbePhySgmii1RxStatus_HHD
#define AQ_GbePhySgmii1TxStatus_BiggestVersion AQ_GbePhySgmii1TxStatus_HHD
#define AQ_GbePhySgmii1WolStatus_BiggestVersion AQ_GbePhySgmii1WolStatus_HHD
#define AQ_GbePhySgmiiRxAlarms_BiggestVersion AQ_GbePhySgmiiRxAlarms_HHD
#define AQ_GbePhySgmiiRxInterruptMask_BiggestVersion AQ_GbePhySgmiiRxInterruptMask_HHD
#define AQ_GbePhySgmiiTestControl_BiggestVersion AQ_GbePhySgmiiTestControl_HHD
#define AQ_GbePhySgmiiTxAlarms_BiggestVersion AQ_GbePhySgmiiTxAlarms_HHD
#define AQ_GbePhySgmiiTxInterruptMask_BiggestVersion AQ_GbePhySgmiiTxInterruptMask_HHD
#define AQ_GbePhySgmiiWolStatus_BiggestVersion AQ_GbePhySgmiiWolStatus_HHD
#define AQ_GbePhyVendorGlobalInterruptFlags_BiggestVersion AQ_GbePhyVendorGlobalInterruptFlags_HHD
#define AQ_GbePhyWolControl_BiggestVersion AQ_GbePhyWolControl_HHD
#define AQ_GbePhysgmii1WolStatus_BiggestVersion AQ_GbePhysgmii1WolStatus_APPIA
#define AQ_GbeReservedProvisioning_BiggestVersion AQ_GbeReservedProvisioning_HHD
#define AQ_GbeStandardDeviceIdentifier_BiggestVersion AQ_GbeStandardDeviceIdentifier_HHD
#define AQ_GbeStandardDevicesInPackage_BiggestVersion AQ_GbeStandardDevicesInPackage_HHD
#define AQ_GbeStandardPackageIdentifier_BiggestVersion AQ_GbeStandardPackageIdentifier_HHD
#define AQ_GbeStandardStatus_2_BiggestVersion AQ_GbeStandardStatus_2_HHD
#define AQ_GbeStandardVendorDevicesInPackage_BiggestVersion AQ_GbeStandardVendorDevicesInPackage_HHD
#define AQ_GlobalAlarms_BiggestVersion AQ_GlobalAlarms_HHD
#define AQ_GlobalCableDiagnosticImpedance_BiggestVersion AQ_GlobalCableDiagnosticImpedance_HHD
#define AQ_GlobalCableDiagnosticStatus_BiggestVersion AQ_GlobalCableDiagnosticStatus_APPIA
#define AQ_GlobalChipIdentification_BiggestVersion AQ_GlobalChipIdentification_APPIA
#define AQ_GlobalChipRevision_BiggestVersion AQ_GlobalChipRevision_APPIA
#define AQ_GlobalChip_wideStandardInterruptFlags_BiggestVersion AQ_GlobalChip_wideStandardInterruptFlags_HHD
#define AQ_GlobalChip_wideVendorInterruptFlags_BiggestVersion AQ_GlobalChip_wideVendorInterruptFlags_HHD
#define AQ_GlobalControl_BiggestVersion AQ_GlobalControl_HHD
#define AQ_GlobalDaisyChainStatus_BiggestVersion AQ_GlobalDaisyChainStatus_HHD
#define AQ_GlobalDiagnosticProvisioning_BiggestVersion AQ_GlobalDiagnosticProvisioning_HHD
#define AQ_GlobalEeeProvisioning_BiggestVersion AQ_GlobalEeeProvisioning_HHD
#define AQ_GlobalFaultMessage_BiggestVersion AQ_GlobalFaultMessage_HHD
#define AQ_GlobalFirmwareID_BiggestVersion AQ_GlobalFirmwareID_HHD
#define AQ_GlobalGeneralProvisioning_BiggestVersion AQ_GlobalGeneralProvisioning_HHD
#define AQ_GlobalGeneralStatus_BiggestVersion AQ_GlobalGeneralStatus_HHD
#define AQ_GlobalInterruptChip_wideStandardMask_BiggestVersion AQ_GlobalInterruptChip_wideStandardMask_HHD
#define AQ_GlobalInterruptChip_wideVendorMask_BiggestVersion AQ_GlobalInterruptChip_wideVendorMask_HHD
#define AQ_GlobalInterruptMask_BiggestVersion AQ_GlobalInterruptMask_HHD
#define AQ_GlobalLedProvisioning_BiggestVersion AQ_GlobalLedProvisioning_HHD
#define AQ_GlobalMailboxInterface_BiggestVersion AQ_GlobalMailboxInterface_HHD
#define AQ_GlobalMicroprocessorScratchPad_BiggestVersion AQ_GlobalMicroprocessorScratchPad_HHD
#define AQ_GlobalNvrInterface_BiggestVersion AQ_GlobalNvrInterface_HHD
#define AQ_GlobalNvrProvisioning_BiggestVersion AQ_GlobalNvrProvisioning_HHD
#define AQ_GlobalPinStatus_BiggestVersion AQ_GlobalPinStatus_HHD
#define AQ_GlobalPrimaryStatus_BiggestVersion AQ_GlobalPrimaryStatus_APPIA
#define AQ_GlobalReservedProvisioning_BiggestVersion AQ_GlobalReservedProvisioning_HHD
#define AQ_GlobalReservedStatus_BiggestVersion AQ_GlobalReservedStatus_HHD
#define AQ_GlobalResetControl_BiggestVersion AQ_GlobalResetControl_HHD
#define AQ_GlobalSmbus_0Provisioning_BiggestVersion AQ_GlobalSmbus_0Provisioning_HHD
#define AQ_GlobalSmbus_1Provisioning_BiggestVersion AQ_GlobalSmbus_1Provisioning_HHD
#define AQ_GlobalStandardControl_1_BiggestVersion AQ_GlobalStandardControl_1_HHD
#define AQ_GlobalStandardDeviceIdentifier_BiggestVersion AQ_GlobalStandardDeviceIdentifier_HHD
#define AQ_GlobalStandardDevicesInPackage_BiggestVersion AQ_GlobalStandardDevicesInPackage_HHD
#define AQ_GlobalStandardPackageIdentifier_BiggestVersion AQ_GlobalStandardPackageIdentifier_HHD
#define AQ_GlobalStandardStatus_2_BiggestVersion AQ_GlobalStandardStatus_2_HHD
#define AQ_GlobalStandardVendorDevicesInPackage_BiggestVersion AQ_GlobalStandardVendorDevicesInPackage_HHD
#define AQ_GlobalStatus_BiggestVersion AQ_GlobalStatus_HHD
#define AQ_GlobalThermalProvisioning_BiggestVersion AQ_GlobalThermalProvisioning_HHD
#define AQ_GlobalThermalStatus_BiggestVersion AQ_GlobalThermalStatus_HHD
#define AQ_Kr0AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationAdvertisementWord_HHD
#define AQ_Kr0AutonegotiationControl_BiggestVersion AQ_Kr0AutonegotiationControl_HHD
#define AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0AutonegotiationExtendedNextPageAdvertisementWord_HHD
#define AQ_Kr0AutonegotiationStatus_BiggestVersion AQ_Kr0AutonegotiationStatus_HHD
#define AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationAdvertisementWord_HHD
#define AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr0LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD
#define AQ_Kr1AutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationAdvertisementWord_HHD
#define AQ_Kr1AutonegotiationControl_BiggestVersion AQ_Kr1AutonegotiationControl_HHD
#define AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1AutonegotiationExtendedNextPageAdvertisementWord_HHD
#define AQ_Kr1AutonegotiationStatus_BiggestVersion AQ_Kr1AutonegotiationStatus_HHD
#define AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationAdvertisementWord_HHD
#define AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_BiggestVersion AQ_Kr1LinkPartnerAutonegotiationExtendedNextPageAdvertisementWord_HHD
#define AQ_MsmLineFifoControlRegister_BiggestVersion AQ_MsmLineFifoControlRegister_HHD
#define AQ_MsmLineGeneralControlRegister_BiggestVersion AQ_MsmLineGeneralControlRegister_HHD
#define AQ_MsmLineGeneralStatusRegister_BiggestVersion AQ_MsmLineGeneralStatusRegister_HHD
#define AQ_MsmLineRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmLineRxAlignmentErrorsCounterRegister_HHD
#define AQ_MsmLineRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineRxBroadcastFramesCounterRegister_HHD
#define AQ_MsmLineRxErrorsCounterRegister_BiggestVersion AQ_MsmLineRxErrorsCounterRegister_HHD
#define AQ_MsmLineRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmLineRxFcsErrorsCounterRegister_HHD
#define AQ_MsmLineRxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineRxGoodFramesCounterRegister_HHD
#define AQ_MsmLineRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmLineRxInRangeLengthErrorsCounterRegister_HHD
#define AQ_MsmLineRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineRxMulticastFramesCounterRegister_HHD
#define AQ_MsmLineRxOctetsCounterRegister_BiggestVersion AQ_MsmLineRxOctetsCounterRegister_HHD
#define AQ_MsmLineRxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineRxPauseFramesCounterRegister_HHD
#define AQ_MsmLineRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmLineRxTooLongErrorsCounterRegister_HHD
#define AQ_MsmLineRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineRxUnicastFramesCounterRegister_HHD
#define AQ_MsmLineRxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineRxVlanFramesCounterRegister_HHD
#define AQ_MsmLineTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmLineTxBroadcastFramesCounterRegister_HHD
#define AQ_MsmLineTxErrorsCounterRegister_BiggestVersion AQ_MsmLineTxErrorsCounterRegister_HHD
#define AQ_MsmLineTxGoodFramesCounterRegister_BiggestVersion AQ_MsmLineTxGoodFramesCounterRegister_HHD
#define AQ_MsmLineTxIpgControlRegister_BiggestVersion AQ_MsmLineTxIpgControlRegister_HHD
#define AQ_MsmLineTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmLineTxMulticastFramesCounterRegister_HHD
#define AQ_MsmLineTxOctetsCounterRegister_BiggestVersion AQ_MsmLineTxOctetsCounterRegister_HHD
#define AQ_MsmLineTxPauseFramesCounterRegister_BiggestVersion AQ_MsmLineTxPauseFramesCounterRegister_HHD
#define AQ_MsmLineTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmLineTxUnicastFramesCounterRegister_HHD
#define AQ_MsmLineTxVlanFramesCounterRegister_BiggestVersion AQ_MsmLineTxVlanFramesCounterRegister_HHD
#define AQ_MsmSystemFifoControlRegister_BiggestVersion AQ_MsmSystemFifoControlRegister_HHD
#define AQ_MsmSystemGeneralControlRegister_BiggestVersion AQ_MsmSystemGeneralControlRegister_HHD
#define AQ_MsmSystemGeneralStatusRegister_BiggestVersion AQ_MsmSystemGeneralStatusRegister_HHD
#define AQ_MsmSystemRxAlignmentErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxAlignmentErrorsCounterRegister_HHD
#define AQ_MsmSystemRxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxBroadcastFramesCounterRegister_HHD
#define AQ_MsmSystemRxErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxErrorsCounterRegister_HHD
#define AQ_MsmSystemRxFcsErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxFcsErrorsCounterRegister_HHD
#define AQ_MsmSystemRxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemRxGoodFramesCounterRegister_HHD
#define AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxInRangeLengthErrorsCounterRegister_HHD
#define AQ_MsmSystemRxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxMulticastFramesCounterRegister_HHD
#define AQ_MsmSystemRxOctetsCounterRegister_BiggestVersion AQ_MsmSystemRxOctetsCounterRegister_HHD
#define AQ_MsmSystemRxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemRxPauseFramesCounterRegister_HHD
#define AQ_MsmSystemRxTooLongErrorsCounterRegister_BiggestVersion AQ_MsmSystemRxTooLongErrorsCounterRegister_HHD
#define AQ_MsmSystemRxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemRxUnicastFramesCounterRegister_HHD
#define AQ_MsmSystemRxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemRxVlanFramesCounterRegister_HHD
#define AQ_MsmSystemTxBroadcastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxBroadcastFramesCounterRegister_HHD
#define AQ_MsmSystemTxErrorsCounterRegister_BiggestVersion AQ_MsmSystemTxErrorsCounterRegister_HHD
#define AQ_MsmSystemTxGoodFramesCounterRegister_BiggestVersion AQ_MsmSystemTxGoodFramesCounterRegister_HHD
#define AQ_MsmSystemTxIpgControlRegister_BiggestVersion AQ_MsmSystemTxIpgControlRegister_HHD
#define AQ_MsmSystemTxMulticastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxMulticastFramesCounterRegister_HHD
#define AQ_MsmSystemTxOctetsCounterRegister_BiggestVersion AQ_MsmSystemTxOctetsCounterRegister_HHD
#define AQ_MsmSystemTxPauseFramesCounterRegister_BiggestVersion AQ_MsmSystemTxPauseFramesCounterRegister_HHD
#define AQ_MsmSystemTxUnicastFramesCounterRegister_BiggestVersion AQ_MsmSystemTxUnicastFramesCounterRegister_HHD
#define AQ_MsmSystemTxVlanFramesCounterRegister_BiggestVersion AQ_MsmSystemTxVlanFramesCounterRegister_HHD
#define AQ_MssEgressControlRegister_BiggestVersion AQ_MssEgressControlRegister_HHD
#define AQ_MssEgressEccInterruptStatusRegister_BiggestVersion AQ_MssEgressEccInterruptStatusRegister_HHD
#define AQ_MssEgressInterruptMaskRegister_BiggestVersion AQ_MssEgressInterruptMaskRegister_HHD
#define AQ_MssEgressInterruptStatusRegister_BiggestVersion AQ_MssEgressInterruptStatusRegister_HHD
#define AQ_MssEgressLutAddressControlRegister_BiggestVersion AQ_MssEgressLutAddressControlRegister_HHD
#define AQ_MssEgressLutControlRegister_BiggestVersion AQ_MssEgressLutControlRegister_HHD
#define AQ_MssEgressLutDataControlRegister_BiggestVersion AQ_MssEgressLutDataControlRegister_HHD
#define AQ_MssEgressMtuSizeControlRegister_BiggestVersion AQ_MssEgressMtuSizeControlRegister_HHD
#define AQ_MssEgressPnControlRegister_BiggestVersion AQ_MssEgressPnControlRegister_HHD
#define AQ_MssEgressSaExpiredStatusRegister_BiggestVersion AQ_MssEgressSaExpiredStatusRegister_HHD
#define AQ_MssEgressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssEgressSaThresholdExpiredStatusRegister_HHD
#define AQ_MssEgressVlanControlRegister_BiggestVersion AQ_MssEgressVlanControlRegister_HHD
#define AQ_MssEgressVlanTpid_0Register_BiggestVersion AQ_MssEgressVlanTpid_0Register_HHD
#define AQ_MssEgressVlanTpid_1Register_BiggestVersion AQ_MssEgressVlanTpid_1Register_HHD
#define AQ_MssIngressControlRegister_BiggestVersion AQ_MssIngressControlRegister_HHD
#define AQ_MssIngressEccInterruptStatusRegister_BiggestVersion AQ_MssIngressEccInterruptStatusRegister_HHD
#define AQ_MssIngressInterruptMaskRegister_BiggestVersion AQ_MssIngressInterruptMaskRegister_HHD
#define AQ_MssIngressInterruptStatusRegister_BiggestVersion AQ_MssIngressInterruptStatusRegister_HHD
#define AQ_MssIngressLutAddressControlRegister_BiggestVersion AQ_MssIngressLutAddressControlRegister_HHD
#define AQ_MssIngressLutControlRegister_BiggestVersion AQ_MssIngressLutControlRegister_HHD
#define AQ_MssIngressLutDataControlRegister_BiggestVersion AQ_MssIngressLutDataControlRegister_HHD
#define AQ_MssIngressMtuSizeControlRegister_BiggestVersion AQ_MssIngressMtuSizeControlRegister_HHD
#define AQ_MssIngressSaControlRegister_BiggestVersion AQ_MssIngressSaControlRegister_HHD
#define AQ_MssIngressSaExpiredStatusRegister_BiggestVersion AQ_MssIngressSaExpiredStatusRegister_HHD
#define AQ_MssIngressSaIcvErrorStatusRegister_BiggestVersion AQ_MssIngressSaIcvErrorStatusRegister_HHD
#define AQ_MssIngressSaReplayErrorStatusRegister_BiggestVersion AQ_MssIngressSaReplayErrorStatusRegister_HHD
#define AQ_MssIngressSaThresholdExpiredStatusRegister_BiggestVersion AQ_MssIngressSaThresholdExpiredStatusRegister_HHD
#define AQ_MssIngressVlanControlRegister_BiggestVersion AQ_MssIngressVlanControlRegister_HHD
#define AQ_MssIngressVlanTpid_0Register_BiggestVersion AQ_MssIngressVlanTpid_0Register_HHD
#define AQ_MssIngressVlanTpid_1Register_BiggestVersion AQ_MssIngressVlanTpid_1Register_HHD
#define AQ_Pcs10GBaseT_Status_BiggestVersion AQ_Pcs10GBaseT_Status_APPIA
#define AQ_Pcs10G_Status_BiggestVersion AQ_Pcs10G_Status_HHD
#define AQ_Pcs10G_base_rPcsTest_patternControl_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternControl_HHD
#define AQ_Pcs10G_base_rPcsTest_patternErrorCounter_BiggestVersion AQ_Pcs10G_base_rPcsTest_patternErrorCounter_HHD
#define AQ_Pcs10G_base_rTestPatternSeedA_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedA_HHD
#define AQ_Pcs10G_base_rTestPatternSeedB_BiggestVersion AQ_Pcs10G_base_rTestPatternSeedB_HHD
#define AQ_PcsEeeCapabilityRegister_BiggestVersion AQ_PcsEeeCapabilityRegister_HHD
#define AQ_PcsEeeWakeErrorCounter_BiggestVersion AQ_PcsEeeWakeErrorCounter_HHD
#define AQ_PcsReceiveStandardInterruptMask_BiggestVersion AQ_PcsReceiveStandardInterruptMask_APPIA
#define AQ_PcsReceiveVendorAlarms_BiggestVersion AQ_PcsReceiveVendorAlarms_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_1IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_2IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_3IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_4IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_5IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_6IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_7IterationCounter_HHD
#define AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_BiggestVersion AQ_PcsReceiveVendorCorrectedFrame_8IterationCounter_HHD
#define AQ_PcsReceiveVendorCrc_8ErrorCounter_BiggestVersion AQ_PcsReceiveVendorCrc_8ErrorCounter_HHD
#define AQ_PcsReceiveVendorDebug_BiggestVersion AQ_PcsReceiveVendorDebug_HHD
#define AQ_PcsReceiveVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsErrorFrameCounter_HHD
#define AQ_PcsReceiveVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsReceiveVendorFcsNoErrorFrameCounter_HHD
#define AQ_PcsReceiveVendorInterruptMask_BiggestVersion AQ_PcsReceiveVendorInterruptMask_HHD
#define AQ_PcsReceiveVendorProvisioning_BiggestVersion AQ_PcsReceiveVendorProvisioning_HHD
#define AQ_PcsReceiveVendorState_BiggestVersion AQ_PcsReceiveVendorState_HHD
#define AQ_PcsReceiveVendorUncorrectedFrameCounter_BiggestVersion AQ_PcsReceiveVendorUncorrectedFrameCounter_HHD
#define AQ_PcsReceiveXfi0Provisioning_BiggestVersion AQ_PcsReceiveXfi0Provisioning_HHD
#define AQ_PcsReceiveXfi0VendorState_BiggestVersion AQ_PcsReceiveXfi0VendorState_HHD
#define AQ_PcsReceiveXfi1Provisioning_BiggestVersion AQ_PcsReceiveXfi1Provisioning_HHD
#define AQ_PcsReceiveXfi1VendorState_BiggestVersion AQ_PcsReceiveXfi1VendorState_HHD
#define AQ_PcsSerdesMuxSwapTxrxRegister_BiggestVersion AQ_PcsSerdesMuxSwapTxrxRegister_HHD
#define AQ_PcsStandardControl_1_BiggestVersion AQ_PcsStandardControl_1_HHD
#define AQ_PcsStandardControl_2_BiggestVersion AQ_PcsStandardControl_2_HHD
#define AQ_PcsStandardDeviceIdentifier_BiggestVersion AQ_PcsStandardDeviceIdentifier_HHD
#define AQ_PcsStandardDevicesInPackage_BiggestVersion AQ_PcsStandardDevicesInPackage_HHD
#define AQ_PcsStandardInterruptMask_BiggestVersion AQ_PcsStandardInterruptMask_HHD
#define AQ_PcsStandardPackageIdentifier_BiggestVersion AQ_PcsStandardPackageIdentifier_HHD
#define AQ_PcsStandardSpeedAbility_BiggestVersion AQ_PcsStandardSpeedAbility_HHD
#define AQ_PcsStandardStatus_1_BiggestVersion AQ_PcsStandardStatus_1_HHD
#define AQ_PcsStandardStatus_2_BiggestVersion AQ_PcsStandardStatus_2_HHD
#define AQ_PcsTransmitReservedVendorProvisioning_BiggestVersion AQ_PcsTransmitReservedVendorProvisioning_HHD
#define AQ_PcsTransmitVendorAlarms_BiggestVersion AQ_PcsTransmitVendorAlarms_APPIA
#define AQ_PcsTransmitVendorDebug_BiggestVersion AQ_PcsTransmitVendorDebug_HHD
#define AQ_PcsTransmitVendorFcsErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsErrorFrameCounter_HHD
#define AQ_PcsTransmitVendorFcsNoErrorFrameCounter_BiggestVersion AQ_PcsTransmitVendorFcsNoErrorFrameCounter_HHD
#define AQ_PcsTransmitVendorInterruptMask_BiggestVersion AQ_PcsTransmitVendorInterruptMask_APPIA
#define AQ_PcsTransmitVendorProvisioning_BiggestVersion AQ_PcsTransmitVendorProvisioning_HHD
#define AQ_PcsTransmitXfi0VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi0VendorProvisioning_HHD
#define AQ_PcsTransmitXfi0VendorState_BiggestVersion AQ_PcsTransmitXfi0VendorState_HHD
#define AQ_PcsTransmitXfi1VendorProvisioning_BiggestVersion AQ_PcsTransmitXfi1VendorProvisioning_HHD
#define AQ_PcsTransmitXfi1VendorState_BiggestVersion AQ_PcsTransmitXfi1VendorState_HHD
#define AQ_PcsTransmitXfiVendorProvisioning_BiggestVersion AQ_PcsTransmitXfiVendorProvisioning_HHD
#define AQ_PcsTransmitXgsVendorState_BiggestVersion AQ_PcsTransmitXgsVendorState_HHD
#define AQ_PcsVendorGlobalInterruptFlags_BiggestVersion AQ_PcsVendorGlobalInterruptFlags_HHD
#define AQ_PhyXS_EeeCapabilityRegister_BiggestVersion AQ_PhyXS_EeeCapabilityRegister_HHD
#define AQ_PhyXS_EeeWakeErrorCounter_BiggestVersion AQ_PhyXS_EeeWakeErrorCounter_HHD
#define AQ_PhyXS_Receive_xauiTx_PcsStatus_BiggestVersion AQ_PhyXS_Receive_xauiTx_PcsStatus_HHD
#define AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Receive_xauiTx_ReservedVendorProvisioning_HHD
#define AQ_PhyXS_Receive_xauiTx_VendorAlarms_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorAlarms_HHD
#define AQ_PhyXS_Receive_xauiTx_VendorDebug_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorDebug_HHD
#define AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Receive_xauiTx_VendorInterruptMask_HHD
#define AQ_PhyXS_SerdesConfiguration_BiggestVersion AQ_PhyXS_SerdesConfiguration_HHD
#define AQ_PhyXS_SerdesLane_0Configuration_BiggestVersion AQ_PhyXS_SerdesLane_0Configuration_HHD
#define AQ_PhyXS_SerdesLane_1Configuration_BiggestVersion AQ_PhyXS_SerdesLane_1Configuration_HHD
#define AQ_PhyXS_SerdesLane_2Configuration_BiggestVersion AQ_PhyXS_SerdesLane_2Configuration_HHD
#define AQ_PhyXS_SerdesLane_3Configuration_BiggestVersion AQ_PhyXS_SerdesLane_3Configuration_HHD
#define AQ_PhyXS_SerdesLut_BiggestVersion AQ_PhyXS_SerdesLut_HHD
#define AQ_PhyXS_StandardControl_1_BiggestVersion AQ_PhyXS_StandardControl_1_HHD
#define AQ_PhyXS_StandardDeviceIdentifier_BiggestVersion AQ_PhyXS_StandardDeviceIdentifier_HHD
#define AQ_PhyXS_StandardDevicesInPackage_BiggestVersion AQ_PhyXS_StandardDevicesInPackage_HHD
#define AQ_PhyXS_StandardPackageIdentifier_BiggestVersion AQ_PhyXS_StandardPackageIdentifier_HHD
#define AQ_PhyXS_StandardSpeedAbility_BiggestVersion AQ_PhyXS_StandardSpeedAbility_HHD
#define AQ_PhyXS_StandardStatus_1_BiggestVersion AQ_PhyXS_StandardStatus_1_HHD
#define AQ_PhyXS_StandardStatus_2_BiggestVersion AQ_PhyXS_StandardStatus_2_HHD
#define AQ_PhyXS_StandardXGXS_LaneStatus_BiggestVersion AQ_PhyXS_StandardXGXS_LaneStatus_HHD
#define AQ_PhyXS_StandardXGXS_TestControl_BiggestVersion AQ_PhyXS_StandardXGXS_TestControl_HHD
#define AQ_PhyXS_SystemInterfaceConnectionStatus_BiggestVersion AQ_PhyXS_SystemInterfaceConnectionStatus_HHD
#define AQ_PhyXS_Transmit_xauiRx_PcsStatus_BiggestVersion AQ_PhyXS_Transmit_xauiRx_PcsStatus_HHD
#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorProvisioning_HHD
#define AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_BiggestVersion AQ_PhyXS_Transmit_xauiRx_ReservedVendorState_HHD
#define AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_StandardInterruptMask_HHD
#define AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_BiggestVersion AQ_PhyXS_Transmit_xauiRx_TestPatternErrorCounter_HHD
#define AQ_PhyXS_Transmit_xauiRx_VendorAlarms_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorAlarms_HHD
#define AQ_PhyXS_Transmit_xauiRx_VendorDebug_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorDebug_HHD
#define AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_BiggestVersion AQ_PhyXS_Transmit_xauiRx_VendorInterruptMask_HHD
#define AQ_PhyXS_VendorGlobalInterruptFlags_BiggestVersion AQ_PhyXS_VendorGlobalInterruptFlags_HHD
#define AQ_PifMailboxControl_BiggestVersion AQ_PifMailboxControl_HHD
#define AQ_Pma10GBaseT_FastRetrainStatusAndControl_BiggestVersion AQ_Pma10GBaseT_FastRetrainStatusAndControl_HHD
#define AQ_Pma10GBaseT_PairSwapAndPolarityStatus_BiggestVersion AQ_Pma10GBaseT_PairSwapAndPolarityStatus_HHD
#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelA_HHD
#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelB_HHD
#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelC_HHD
#define AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_BiggestVersion AQ_Pma10GBaseT_ReceiveSignalPowerChannelD_HHD
#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelA_HHD
#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelB_HHD
#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelC_HHD
#define AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_MinimumOperatingMarginChannelD_HHD
#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelA_HHD
#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelB_HHD
#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelC_HHD
#define AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_BiggestVersion AQ_Pma10GBaseT_SNR_OperatingMarginChannelD_HHD
#define AQ_Pma10GBaseT_SkewDelay_BiggestVersion AQ_Pma10GBaseT_SkewDelay_HHD
#define AQ_Pma10GBaseT_Status_BiggestVersion AQ_Pma10GBaseT_Status_HHD
#define AQ_Pma10GBaseT_TestModes_BiggestVersion AQ_Pma10GBaseT_TestModes_HHD
#define AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_BiggestVersion AQ_Pma10GBaseT_TxPowerBackoffAndShortReachSetting_HHD
#define AQ_PmaReceiveReservedVendorProvisioning_BiggestVersion AQ_PmaReceiveReservedVendorProvisioning_HHD
#define AQ_PmaReceiveReservedVendorState_BiggestVersion AQ_PmaReceiveReservedVendorState_HHD
#define AQ_PmaReceiveVendorState_BiggestVersion AQ_PmaReceiveVendorState_HHD
#define AQ_PmaStandardControl_1_BiggestVersion AQ_PmaStandardControl_1_HHD
#define AQ_PmaStandardControl_2_BiggestVersion AQ_PmaStandardControl_2_HHD
#define AQ_PmaStandardDeviceIdentifier_BiggestVersion AQ_PmaStandardDeviceIdentifier_HHD
#define AQ_PmaStandardDevicesInPackage_BiggestVersion AQ_PmaStandardDevicesInPackage_HHD
#define AQ_PmaStandardPackageIdentifier_BiggestVersion AQ_PmaStandardPackageIdentifier_HHD
#define AQ_PmaStandardSpeedAbility_BiggestVersion AQ_PmaStandardSpeedAbility_HHD
#define AQ_PmaStandardStatus_1_BiggestVersion AQ_PmaStandardStatus_1_HHD
#define AQ_PmaStandardStatus_2_BiggestVersion AQ_PmaStandardStatus_2_HHD
#define AQ_PmaTransmitReservedVendorProvisioning_BiggestVersion AQ_PmaTransmitReservedVendorProvisioning_HHD
#define AQ_PmaTransmitStandardInterruptMask_BiggestVersion AQ_PmaTransmitStandardInterruptMask_HHD
#define AQ_PmaTransmitVendorAlarms_BiggestVersion AQ_PmaTransmitVendorAlarms_HHD
#define AQ_PmaTransmitVendorDebug_BiggestVersion AQ_PmaTransmitVendorDebug_HHD
#define AQ_PmaTransmitVendorLASI_InterruptMask_BiggestVersion AQ_PmaTransmitVendorLASI_InterruptMask_HHD
#define AQ_PmaVendorGlobalInterruptFlags_BiggestVersion AQ_PmaVendorGlobalInterruptFlags_HHD
#define AQ_PmdStandard10G_ExtendedAbilityRegister_BiggestVersion AQ_PmdStandard10G_ExtendedAbilityRegister_HHD
#define AQ_PmdStandardSignalDetect_BiggestVersion AQ_PmdStandardSignalDetect_HHD
#define AQ_PmdStandardTransmitDisableControl_BiggestVersion AQ_PmdStandardTransmitDisableControl_HHD
#define AQ_Sgmii0WolStatus_BiggestVersion AQ_Sgmii0WolStatus_HHD
#define AQ_TimesyncPcsCapability_BiggestVersion AQ_TimesyncPcsCapability_HHD
#define AQ_TimesyncPcsReceivePathDataDelay_BiggestVersion AQ_TimesyncPcsReceivePathDataDelay_HHD
#define AQ_TimesyncPcsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPcsTransmitPathDataDelay_HHD
#define AQ_TimesyncPhyXsCapability_BiggestVersion AQ_TimesyncPhyXsCapability_HHD
#define AQ_TimesyncPhyXsReceivePathDataDelay_BiggestVersion AQ_TimesyncPhyXsReceivePathDataDelay_HHD
#define AQ_TimesyncPhyXsTransmitPathDataDelay_BiggestVersion AQ_TimesyncPhyXsTransmitPathDataDelay_HHD
#define AQ_TimesyncPmaCapability_BiggestVersion AQ_TimesyncPmaCapability_HHD
#define AQ_TimesyncPmaReceivePathDataDelay_BiggestVersion AQ_TimesyncPmaReceivePathDataDelay_HHD
#define AQ_TimesyncPmaTransmitPathDataDelay_BiggestVersion AQ_TimesyncPmaTransmitPathDataDelay_HHD
#define AQ_XenpakBasic_ApsLoading_BiggestVersion AQ_XenpakBasic_ApsLoading_HHD
#define AQ_XenpakBasic_ApsVoltage_BiggestVersion AQ_XenpakBasic_ApsVoltage_HHD
#define AQ_XenpakBasic_BitRate_BiggestVersion AQ_XenpakBasic_BitRate_HHD
#define AQ_XenpakBasic_Checksum_BiggestVersion AQ_XenpakBasic_Checksum_HHD
#define AQ_XenpakBasic_ConnectorType_BiggestVersion AQ_XenpakBasic_ConnectorType_HHD
#define AQ_XenpakBasic_DomCapability_BiggestVersion AQ_XenpakBasic_DomCapability_HHD
#define AQ_XenpakBasic_Encoding_BiggestVersion AQ_XenpakBasic_Encoding_HHD
#define AQ_XenpakBasic_Low_powerStartupCapability_BiggestVersion AQ_XenpakBasic_Low_powerStartupCapability_HHD
#define AQ_XenpakBasic_PackageIdentifier_BiggestVersion AQ_XenpakBasic_PackageIdentifier_HHD
#define AQ_XenpakBasic_Protocol_BiggestVersion AQ_XenpakBasic_Protocol_HHD
#define AQ_XenpakBasic_Reserved_0x11_BiggestVersion AQ_XenpakBasic_Reserved_0x11_HHD
#define AQ_XenpakBasic_Reserved_0x19_BiggestVersion AQ_XenpakBasic_Reserved_0x19_HHD
#define AQ_XenpakBasic_Reserved_0x7c_BiggestVersion AQ_XenpakBasic_Reserved_0x7c_HHD
#define AQ_XenpakBasic_StandardsComplianceCodes_BiggestVersion AQ_XenpakBasic_StandardsComplianceCodes_HHD
#define AQ_XenpakBasic_TransceiverType_BiggestVersion AQ_XenpakBasic_TransceiverType_HHD
#define AQ_XenpakBasic_VendorDateCode_BiggestVersion AQ_XenpakBasic_VendorDateCode_HHD
#define AQ_XenpakBasic_VendorIdentifier_BiggestVersion AQ_XenpakBasic_VendorIdentifier_HHD
#define AQ_XenpakBasic_VendorName_BiggestVersion AQ_XenpakBasic_VendorName_HHD
#define AQ_XenpakBasic_VendorPartNumber_BiggestVersion AQ_XenpakBasic_VendorPartNumber_HHD
#define AQ_XenpakBasic_VendorPartRevisionNumber_BiggestVersion AQ_XenpakBasic_VendorPartRevisionNumber_HHD
#define AQ_XenpakBasic_VendorSerialNumber_BiggestVersion AQ_XenpakBasic_VendorSerialNumber_HHD
#define AQ_XenpakBasic__3_3vLoading_BiggestVersion AQ_XenpakBasic__3_3vLoading_HHD
#define AQ_XenpakBasic__5vLoading_BiggestVersion AQ_XenpakBasic__5vLoading_HHD
#define AQ_XenpakControl_BiggestVersion AQ_XenpakControl_HHD
#define AQ_XenpakCustomer_Reserved_0x7e_BiggestVersion AQ_XenpakCustomer_Reserved_0x7e_HHD
#define AQ_XenpakDom_Alarms_BiggestVersion AQ_XenpakDom_Alarms_HHD
#define AQ_XenpakDom_Capability_BiggestVersion AQ_XenpakDom_Capability_HHD
#define AQ_XenpakDom_ControlAndStatus_BiggestVersion AQ_XenpakDom_ControlAndStatus_HHD
#define AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdLSW_HHD
#define AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureAlarmThresholdMSW_HHD
#define AQ_XenpakDom_HighTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdLSW_HHD
#define AQ_XenpakDom_HighTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_HighTemperatureWarningThresholdMSW_HHD
#define AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdLSW_HHD
#define AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureAlarmThresholdMSW_HHD
#define AQ_XenpakDom_LowTemperatureWarningThresholdLSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdLSW_HHD
#define AQ_XenpakDom_LowTemperatureWarningThresholdMSW_BiggestVersion AQ_XenpakDom_LowTemperatureWarningThresholdMSW_HHD
#define AQ_XenpakDom_Status_BiggestVersion AQ_XenpakDom_Status_HHD
#define AQ_XenpakDom_TemperatureLSW_BiggestVersion AQ_XenpakDom_TemperatureLSW_HHD
#define AQ_XenpakDom_TemperatureMSW_BiggestVersion AQ_XenpakDom_TemperatureMSW_HHD
#define AQ_XenpakDom_TxControl_BiggestVersion AQ_XenpakDom_TxControl_HHD
#define AQ_XenpakHeader_BasicMemoryStartAddress_BiggestVersion AQ_XenpakHeader_BasicMemoryStartAddress_HHD
#define AQ_XenpakHeader_CustomerMemoryOffset_BiggestVersion AQ_XenpakHeader_CustomerMemoryOffset_HHD
#define AQ_XenpakHeader_ExtendedVendorMemoryOffset_BiggestVersion AQ_XenpakHeader_ExtendedVendorMemoryOffset_HHD
#define AQ_XenpakHeader_MemoryUsed_BiggestVersion AQ_XenpakHeader_MemoryUsed_HHD
#define AQ_XenpakHeader_NvrSize_BiggestVersion AQ_XenpakHeader_NvrSize_HHD
#define AQ_XenpakHeader_VendorMemoryStartAddress_BiggestVersion AQ_XenpakHeader_VendorMemoryStartAddress_HHD
#define AQ_XenpakHeader_XenpakMsaVersionSupported_BiggestVersion AQ_XenpakHeader_XenpakMsaVersionSupported_HHD
#define AQ_XenpakLASI__Control_BiggestVersion AQ_XenpakLASI__Control_HHD
#define AQ_XenpakLASI__Status_BiggestVersion AQ_XenpakLASI__Status_HHD
#define AQ_XenpakRxAlarm_Control_BiggestVersion AQ_XenpakRxAlarm_Control_HHD
#define AQ_XenpakRxAlarm_Status_BiggestVersion AQ_XenpakRxAlarm_Status_HHD
#define AQ_XenpakTxAlarm_Control_BiggestVersion AQ_XenpakTxAlarm_Control_HHD
#define AQ_XenpakTxAlarm_Status_BiggestVersion AQ_XenpakTxAlarm_Status_HHD
#define AQ_XenpakVendor_Reserved_0xae_BiggestVersion AQ_XenpakVendor_Reserved_0xae_HHD
#endif

69
feeds/ipq807x/aq-fw-download/src/include/registerMap/AQ_RegMaps.h
View File

@@ -1,69 +0,0 @@
/*AQ_RegMaps.h*/
/************************************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* Description:
*
* This file contains includes all appropriate Aquantia PHY device-specific
* register map headers.
*
************************************************************************************/
/*! \file
* This file contains includes all appropriate Aquantia PHY device-specific
* register map headers.
*/
#ifndef AQ_REGISTERMAPS_HEADER
#define AQ_REGISTERMAPS_HEADER
#include "AQ_User.h"
#include "AQ_RegGroupMaxSizes.h"
#ifndef AQ_REVERSED_BITFIELD_ORDERING
/*
* Include non-reversed header files (bitfields ordered from LSbit to MSbit)
*/
/* APPIA */
#include "AQ_APPIA_Global_registers.h"
#include "AQ_APPIA_Global_registers_Defines.h"
/* HHD */
#include "AQ_HHD_Global_registers.h"
#include "AQ_HHD_Global_registers_Defines.h"
#else
/*
* Include reversed header files (bitfields ordered from MSbit to LSbit)
*/
/* APPIA */
#include "AQ_APPIA_Global_registers_reversed.h"
#include "AQ_APPIA_Global_registers_Defines.h"
/* HHD */
#include "AQ_HHD_Global_registers_reversed.h"
#include "AQ_HHD_Global_registers_Defines.h"
#endif
#endif

12123
feeds/ipq807x/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers.h
View File

File diff suppressed because it is too large Load Diff

4413
feeds/ipq807x/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_Defines.h
View File

File diff suppressed because it is too large Load Diff

12123
feeds/ipq807x/aq-fw-download/src/include/registerMap/HHD/AQ_HHD_Global_registers_reversed.h
View File

File diff suppressed because it is too large Load Diff

193
feeds/ipq807x/aq-fw-download/src/mdioBootLoadCLD.c
View File

@@ -1,193 +0,0 @@
/* mdioBootLoadCLD.c */
/************************************************************************************
* Copyright (c) 2015 Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $File: //depot/icm/proj/Dena/rev1.0/c/Systems/tools/windows/flashUtilities/src/mdioBootLoadCLD.c $
*
* $Revision: #12 $
*
* $DateTime: 2014/05/19 15:34:49 $
*
* $Author: joshd $
*
* $Label: $
*
************************************************************************************/
/*! \file
This file contains the main (int, char**) file for the mdioBootLoadCLD program, which burns a flash image into a target
Aquantia PHY using the AQ_API. This program calls the API function: <BR><BR>
uint8_t AQ_API_WriteBootLoadImage (uint8_t PHY_ID, uint8_t *image, uint16_t *crc16) <BR><BR>
to boot load a cld flash image into an Aquantia PHY */
/*! \addtogroup mdioBootLoad
@{
*/
/*! \def DEBUG
Uncomment this to compile in debug mode. This sets the source to an arbitrary file, defined by DEBUG_FILENAME,
and an arbitrary PHY_ID, defined by DEBUG_PHY_ID. */
/* #define DEBUG */
/*! The debug source file name */
#define DEBUG_FILENAME "HelloWorld.cld"
/*! The debug PHY ID */
#define DEBUG_PHY_ID 0
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <stdarg.h>
#include <errno.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
#include "AQ_API.h"
#include "AQ_PhyInterface.h"
int sock;
char devname[7];
int sock_init()
{
if ((sock = socket(AF_INET, SOCK_DGRAM, 0)) < 0) {
fprintf(stderr, "Error creating socket: %s\n", strerror(errno));
return -1;
}
return 0;
}
int main ( int argc, char **argp)
{
/* declare local variables */
FILE *pFile;
uint8_t* image;
uint8_t byte;
unsigned int PHY_ID;
AQ_Retcode resultCode;
AQ_Retcode resultCodes[4];
uint32_t i;
uint32_t imageSize;
char sourceFileName[1000];
AQ_API_Port targetPort0;
AQ_API_Port* targetPorts[1];
AQ_API_Port broadcastPort;
unsigned int provisioningAddresses[1] = {0};
uint32_t reg1, reg2;
targetPorts[0] = &targetPort0;
if(argc < 4) {
fprintf (stderr, "enter file name/netdev name/phy address\n");
return (101);
}
/*Copy the file name from command line arg*/
if (strlcpy (sourceFileName, argp[1], sizeof(sourceFileName)) >= sizeof(sourceFileName)) {
fprintf (stderr, "Filename: %s too long \n", argp[1]);
return (101);
}
/*Copy the interface name from command line arg*/
strlcpy (devname, argp[2], sizeof(devname));
/*Get PHY Address from command line arg*/
PHY_ID = (unsigned int)strtoul(argp[3], NULL, 0);
/* FIXME: set port and device type */
targetPort0.device = AQ_DEVICE_HHD;
targetPort0.PHY_ID = PHY_ID;
broadcastPort.device = AQ_DEVICE_HHD;
broadcastPort.PHY_ID = PHY_ID;
/* open the source in binary read mode */
pFile = fopen(sourceFileName, "rb");
if (pFile == NULL)
{
fprintf (stderr, "Unable to open source file %s\n", sourceFileName);
return (101);
}
fseek (pFile, 0, SEEK_END);
imageSize = ftell (pFile);
image = (uint8_t*) malloc (imageSize * sizeof(uint8_t));
fseek (pFile, 0, SEEK_SET);
/* load the file */
for (i = 0; i < imageSize; i++)
{
byte = (uint8_t) fgetc (pFile);
image[i] = byte;
}
fclose(pFile);
if (sock_init() < 0)
{
fprintf (stderr, "Unable to initialize interface\n");
return (200);
}
/* Write in the Auantia phy scratch pad register,
* read back the same reg and match the values written.
*/
AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x300, 0xdead);
AQ_API_MDIO_Write(PHY_ID, 0x1e, 0x301, 0xbeaf);
reg1 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x300);
reg2 = AQ_API_MDIO_Read(PHY_ID, 0x1e, 0x301);
if(reg1 != 0xdead && reg2 != 0xbeaf) {
fprintf (stderr, "Scratchpad Read/Write test fail\n");
return (101);
}
/* call the boot-load function */
resultCode = AQ_API_WriteBootLoadImage(targetPorts, 1, provisioningAddresses, resultCodes, &imageSize, image, PHY_ID, &broadcastPort);
switch (resultCode)
{
case 0:
printf("Image load good - mailbox CRC-16 matches\n");
free (image);
close(sock);
return 0;
case 1:
fprintf (stderr, "CRC-16 on file is bad\n");
free (image);
close(sock);
return 1;
case 2:
fprintf (stderr, "CRC-16 check on image load failed (mailbox CRC-16 check)\n");
free (image);
close(sock);
return 2;
default:
fprintf (stderr, "Invalid return code\n");
free (image);
close(sock);
}
return 12;
}
/*@}*/

1021
feeds/ipq807x/aq-fw-download/src/src/AQ_API.c
View File

File diff suppressed because it is too large Load Diff

141
feeds/ipq807x/aq-fw-download/src/src/AQ_PhyInterface.c
View File

@@ -1,141 +0,0 @@
/* AQ_PhyInterface.c */
/************************************************************************************
* Copyright (c) 2015, Aquantia
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $Revision: #12 $
*
* $DateTime: 2015/02/25 15:34:49 $
*
* $Label: $
*
************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/ioctl.h>
#include <string.h>
#include <unistd.h>
#include <time.h>
#include <errno.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <net/if.h>
#include <linux/sockios.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include "AQ_PhyInterface.h"
#include "AQ_PlatformRoutines.h"
#define MII_ADDR_C45 (0x8000)
extern int sock;
extern char devname[7];
static struct ifreq ifr;
/*! Provides generic synchronous PHY register write functionality. It is the
* responsibility of the system designer to provide the specific MDIO address
* pointer updates, etc. in order to accomplish this write operation.
* It will be assumed that the write has been completed by the time this
* function returns.*/
void AQ_API_MDIO_Write(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being written. */
unsigned int address,
/*! The 16-bits of data to write to the specified PHY register. */
unsigned int data)
{
struct mii_ioctl_data mii;
/*
* Frame the control structures
* and send the ioctl to kernel.
*/
memset(&ifr, 0, sizeof(ifr));
strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name));
memset(&mii, 0, sizeof(mii));
memcpy(&mii, &ifr.ifr_data, sizeof(mii));
mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD;
mii.reg_num = address;
mii.val_in = data;
memcpy(&ifr.ifr_data, &mii, sizeof(mii));
if (ioctl(sock, SIOCSMIIREG, &ifr) < 0) {
fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name,
strerror(errno));
}
return;
}
/*! Provides generic synchronous PHY register read functionality. It is the
* responsibility of the system designer to provide the specific MDIO address
* pointer updates, etc. in order to accomplish this read operation.*/
unsigned int AQ_API_MDIO_Read
(
/*! Uniquely identifies the port within the system. AQ_Port must be
* defined to a whatever data type is suitable for the platform.*/
AQ_Port PHY_ID,
/*! The address of the MMD within the target PHY. */
unsigned int MMD,
/*! The 16-bit address of the PHY register being read. */
unsigned int address)
{
struct mii_ioctl_data mii;
/*
* Frame the control structures
* and send the ioctl to kernel.
*/
memset(&ifr, 0, sizeof(ifr));
strlcpy(ifr.ifr_name, devname, sizeof(ifr.ifr_name));
memset(&mii, 0, sizeof(mii));
memcpy(&mii, &ifr.ifr_data, sizeof(mii));
mii.phy_id = MII_ADDR_C45 | PHY_ID << 5 | MMD;
mii.reg_num = address;
memcpy(&ifr.ifr_data, &mii, sizeof(mii));
if (ioctl(sock, SIOCGMIIREG, &ifr) < 0) {
fprintf(stderr, "SIOCGMIIREG on %s failed: %s\n", ifr.ifr_name,
strerror(errno));
return -1;
} else {
memcpy(&mii, &ifr.ifr_data, sizeof(mii));
}
return mii.val_out;
}
/*! Returns after at least milliseconds have elapsed. This must be implemented
* * in a platform-approriate way. AQ_API functions will call this function to
* * block for the specified period of time. If necessary, PHY register reads
* * may be performed on port to busy-wait. */
void AQ_API_Wait(
uint32_t milliseconds, /*!< The delay in milliseconds */
AQ_API_Port* port /*!< The PHY to use if delay reads are necessary*/ )
{
unsigned long long mirco = milliseconds *1000;
usleep(mirco);
}

31
feeds/ipq807x/ipq807x/Makefile
View File

@@ -1,31 +0,0 @@
include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=ipq807x
BOARDNAME:=Qualcomm Atheros AX
SUBTARGETS:=ipq807x ipq60xx ipq50xx
FEATURES:=squashfs ramdisk nand pcie usb
KERNELNAME:=Image dtbs
CPU_TYPE:=cortex-a7
DEVICE_TYPE:=qsdk
KERNEL_PATCHVER:=4.4
KERNEL_NAME_SUFFIX=-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016
KERNEL_QSDK_4_4:=y
GENERIC_BACKPORT_DIR :=
GENERIC_PATCH_DIR :=
GENERIC_HACK_DIR :=
GENERIC_FILES_DIR :=
GENERIC_LINUX_CONFIG:=${CURDIR}/config-$(KERNEL_PATCHVER)-qsdk
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += kmod-qca-nss-dp kmod-qca-ssdk swconfig \
kmod-qca-nss-drv \
kmod-usb-phy-ipq807x kmod-usb-dwc3-of-simple \
kmod-ath11k-ahb kmod-qrtr_mproc wpad \
kmod-gpio-button-hotplug kmod-bootconfig \
qca-thermald-10.4 qca-ssdk-shell \
uboot-envtools
$(eval $(call BuildTarget))

68
feeds/ipq807x/ipq807x/base-files/etc/board.d/01_leds
View File

@@ -1,68 +0,0 @@
#!/bin/sh
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
sercomm,wallaby|\
wallys,dr6018|\
wallys,dr6018-v4|\
cig,wf188n|\
cig,wf194c|\
cig,wf194c4)
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" "tx rx link"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tpt"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tpt"
;;
edgecore,eap101)
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tpt"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tpt"
ucidef_set_led_netdev "lan1" "lan1" "green:lan1" "eth1"
ucidef_set_led_netdev "lan2" "lan2" "green:lan2" "eth2"
ucidef_set_led_netdev "poe" "poe" "green:wan" "eth0"
;;
edgecore,eap102|\
edgecore,oap102)
ucidef_set_led_netdev "poe" "poe" "green:wan" "eth0"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tpt"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tpt"
;;
edgecore,eap104)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy1tpt"
ucidef_set_led_netdev "wan" "wan" "yellow:uplink" "eth0"
;;
liteon,wpx8324)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "orange:wifi2" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy1tpt"
ucidef_set_led_netdev "wan" "wan" "blue:uplink" "eth0"
;;
hfcl,ion4xi|\
hfcl,ion4xi_wp|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
hfcl,ion4xe)
ucidef_set_led_wlan "wlan5g" "WLAN5G" "blue:wifi5" "phy0tpt"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "blue:wifi2" "phy1tpt"
;;
glinet,ax1800|\
glinet,axt1800)
ucidef_set_led_netdev "wan" "WAN" "blue:wan" "eth0" "tx rx link"
;;
yuncore,fap650|\
yuncore,fap655|\
muxi,ap3220l)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy1tpt"
;;
esac
board_config_flush
exit 0

283
feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network
View File

@@ -1,283 +0,0 @@
#!/bin/sh
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
qcom_setup_interfaces()
{
local board="$1"
ucidef_add_switch "switch0"
ucidef_add_switch_attr "switch0" "enable" "false"
ucidef_add_switch_attr "switch0" "reset" "false"
case $board in
hfcl,ion4xi|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xe)
ucidef_set_interface_wan "eth0 eth1"
ucidef_set_interface_lan ""
;;
cig,wf188|\
tplink,ex227|\
tplink,ex447)
ucidef_set_interface_wan "eth0"
ucidef_set_interface_lan ""
;;
qcom,ipq6018-cp01|\
qcom,ipq807x-hk01)
ucidef_set_interface_lan "eth0 eth1 eth2 eth3 eth4"
ucidef_set_interface_wan "eth5"
;;
cig,wf194c|\
cig,wf194c4|\
edgecore,eap106|\
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
qcom,ipq5018-mp03.1|\
qcom,ipq5018-mp03.3|\
yuncore,ax840|\
motorola,q14|\
sercomm,wallaby|\
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2)
ucidef_set_interface_lan "eth0"
ucidef_set_interface_wan "eth1"
;;
edgecore,eap101|\
glinet,axt1800)
ucidef_set_interface_lan "eth1 eth2"
ucidef_set_interface_wan "eth0"
;;
edgecore,eap102|\
edgecore,oap102|\
liteon,wpx8324|\
wallys,dr6018|\
cig,wf188n|\
cig,wf196|\
muxi,ap3220l)
ucidef_set_interface_lan "eth1"
ucidef_set_interface_wan "eth0"
;;
cig,wf660a)
ucidef_set_interface_wan "eth0"
;;
cig,wf186w)
ucidef_add_switch "switch0" "4:wan" "0:lan" "1:lan" "2:lan" "3:lan" "6@eth0"
;;
cig,wf186h)
ucidef_add_switch "switch0" "4:wan" "1:lan" "2:lan" "6@eth0"
;;
yuncore,fap650)
ucidef_set_interface_lan "eth3 eth2 eth1 eth0"
ucidef_set_interface_wan "eth4"
;;
hfcl,ion4xi_wp)
ucidef_set_interface_lan "eth0 eth1 eth2 eth3"
ucidef_set_interface_wan "eth4"
;;
hfcl,ion4xi_w|\
hfcl,ion4x_w)
ucidef_set_interface_wan "eth0"
;;
hfcl,ion4xi_HMR)
ucidef_set_interface_lan "eth1"
ucidef_set_interface_wan "eth0"
;;
qcom,ipq807x-hk14)
ucidef_set_interface_lan "eth0 eth1 eth2 eth3"
ucidef_set_interface_wan "eth4"
;;
wallys,dr6018-v4|\
glinet,ax1800|\
meshpp,s618-cp03|\
meshpp,s618-cp01)
ucidef_set_interface_lan "eth1 eth2 eth3 eth4"
ucidef_set_interface_wan "eth0"
;;
cybertan,eww622-a1)
ucidef_set_interface_wan "eth0"
ucidef_add_switch "switch1" \
"6@eth1" "1:lan" "2:lan" "3:lan" "4:lan"
;;
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g)
ucidef_set_interface_wan "eth0"
ucidef_set_interface_lan "eth1"
;;
qcom,ipq5018-mp03.1)
ucidef_set_interface_lan "eth1"
ucidef_set_interface_wan "eth0"
ucidef_add_switch "switch1"
ucidef_add_switch_attr "switch1" "enable" "false"
ucidef_add_switch_attr "switch1" "reset" "true"
;;
qcom,ipq5018-mp03.3)
ucidef_set_interface_lan "eth1"
ucidef_set_interface_wan "eth0"
ucidef_add_switch "switch1"
ucidef_add_switch_attr "switch1" "enable" "false"
ucidef_add_switch_attr "switch1" "reset" "true"
;;
edgecore,eap104)
ucidef_set_interface_wan "eth0"
ucidef_add_switch "switch1" \
"6@eth1" "1:lan" "2:lan" "3:lan" "4:lan"
;;
cybertan,eww631-a1)
ucidef_set_interface_wan "eth0"
ucidef_set_interface_lan ""
;;
cybertan,eww631-b1)
ucidef_add_switch "switch1" "5:wan" "4:lan" "3:lan" "2:lan" "6@eth0"
;;
wallys,dr5018)
ucidef_set_interface_lan "eth0 eth1"
ucidef_add_switch "switch1"
ucidef_add_switch_attr "switch1" "enable" "false"
ucidef_add_switch_attr "switch1" "reset" "true"
;;
yuncore,fap655)
ucidef_add_switch "switch1" \
"6@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
;;
esac
}
qcom_setup_macs()
{
local board="$1"
case $board in
cig,wf194c|\
cig,wf194c4)
mtd=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mtd" ] && return;
mac=$(grep BaseMacAddress= $mtd | cut -dx -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth0 $lan_mac
ucidef_set_network_device_mac eth1 $wan_mac
ip link set eth0 address $lan_mac
ip link set eth1 address $wan_mac
ucidef_set_label_macaddr $wan_mac
;;
cig,wf186w)
mtd=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mtd" ] && return;
mac=$(grep BaseMacAddress= $mtd | cut -dx -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
#lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth0 $wan_mac
# ucidef_set_network_device_mac eth1 $wan_mac
ip link set eth0 address $wan_mac
# ip link set eth1 address $wan_mac
# ucidef_set_label_macaddr $wan_mac
;;
cig,wf186h)
mtd=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mtd" ] && return;
mac=$(grep BaseMacAddress= $mtd | cut -dx -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
ucidef_set_network_device_mac eth0 $wan_mac
ip link set eth0 address $wan_mac
;;
cybertan,eww631-a1|\
cybertan,eww631-b1)
mtd=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mtd" ] && return;
mac=$(grep BaseMacAddress= $mtd | cut -d '=' -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth0 $wan_mac
ip link set eth0 address $wan_mac
ucidef_set_label_macaddr $wan_mac
;;
cig,wf188n|\
cig,wf196)
mtd=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mtd" ] && return;
mac=$(grep BaseMacAddress= $mtd | cut -dx -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth1 $lan_mac
ucidef_set_network_device_mac eth0 $wan_mac
ip link set eth0 address $wan_mac
ip link set eth1 address $lan_mac
ucidef_set_label_macaddr $wan_mac
;;
cig,wf660a)
mmc_dev=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mmc_dev" ] && mmc_dev=$(find_mmc_part "0:APPSBLENV")
[ -z "$mmc_dev" ] && return
mac=$(grep BaseMacAddress= $mmc_dev | cut -dx -f2)
[ -z "$mac" ] && return;
wan_mac=$(macaddr_canonicalize $mac)
ucidef_set_network_device_mac eth0 $wan_mac
ip link set eth0 address $wan_mac
;;
cybertan,eww622-a1)
mac=$(grep -i -m 1 mac_addr_base= /dev/`cat /proc/mtd | grep devinfo | cut -d: -f1` | cut -d= -f2)
[ -z "$mac" ] && mac="00:11:22:33:44:55"
wan_mac=$(macaddr_canonicalize $mac)
lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth0 $wan_mac
ucidef_set_network_device_mac eth1 $lan_mac
ucidef_set_label_macaddr $wan_mac
;;
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
yuncore,ax840)
wan_mac=$(cat /sys/class/net/eth1/address)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
yuncore,fap650)
wan_mac=$(cat /sys/class/net/eth4/address)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
yuncore,fap655)
wan_mac=$(cat /sys/class/net/eth0/address)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
muxi,ap3220l)
wan_mac=$(mtd_get_mac_binary 0:Product_Info 0x5b)
lan_mac=$(macaddr_add "$wan_mac" 1)
ucidef_set_network_device_mac eth0 $wan_mac
ucidef_set_network_device_mac eth1 $lan_mac
ip link set eth0 address $wan_mac
ip link set eth1 address $lan_mac
;;
*)
wan_mac=$(cat /sys/class/net/eth0/address)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
wallys,dr5018)
mac=$(grep -i -m 1 BaseMacAddress= /dev/`cat /proc/mtd | grep APPSBLENV | cut -d: -f1` | cut -d= -f2)
[ -z "$mac"] && mac="00:11:22:33:44:00"
wan_mac=$(macaddr_canonicalize $mac)
ucidef_set_network_device_mac eth0 $wan_mac
ucidef_set_label_macaddr $wan_mac
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$wan_mac" ] && ucidef_set_label_macaddr "$wan_mac"
}
board_config_update
board=$(board_name)
qcom_setup_interfaces $board
qcom_setup_macs $board
board_config_flush
exit 0

17
feeds/ipq807x/ipq807x/base-files/etc/board.d/03_wifi
View File

@@ -1,17 +0,0 @@
#!/bin/sh
. /lib/functions/uci-defaults.sh
board_config_update
board=$(board_name)
case "$board" in
edgecore,eap106)
ucidef_set_wifi_scanning 'soc/10000000.pci/pci0001:00/0001:00:00.0/0001:01:00.0'
;;
esac
board_config_flush
exit 0

334
feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
View File

@@ -1,334 +0,0 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions.sh
. /lib/functions/system.sh
ath11k_generate_macs() {
touch /lib/firmware/ath11k-macs
eth=$(cat /sys/class/net/eth0/address)
mac1=$(macaddr_add $eth 2)
mac2=$(macaddr_add $eth 3)
mac3=$(macaddr_add $eth 4)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_eap101() {
touch /lib/firmware/ath11k-macs
eth=$(cat /sys/class/net/eth0/address)
mac1=$(macaddr_add $eth 4)
mac2=$(macaddr_add $eth 3)
mac3=$(macaddr_add $eth 5)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_wf194() {
touch /lib/firmware/ath11k-macs
mac=$(grep BaseMacAddress= /dev/mtd14 | cut -dx -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 2)
mac2=$(macaddr_add $eth 3)
mac3=$(macaddr_add $eth 4)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_ion4x() {
local dev=$(find_mtd_chardev "0:ART")
touch /lib/firmware/ath11k-macs
wifimac0=$(grep WLAN0_BASEMAC= $dev |cut -d '=' -f2)
wifimac1=$(grep WLAN1_BASEMAC= $dev |cut -d '=' -f2)
wifimac2=00:00:00:00:00:00
echo -ne \\x${wifimac0//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${wifimac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${wifimac2//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_pax1800() {
touch /lib/firmware/ath11k-macs
eth=$(cat /sys/class/net/eth0/address)
mac1=$(macaddr_add $eth 10)
mac2=$(macaddr_add $eth 2)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_wf660a() {
touch /lib/firmware/ath11k-macs
mmc_dev=$(find_mtd_chardev "0:APPSBLENV")
[ -z "$mmc_dev" ] && mmc_dev=$(find_mmc_part "0:APPSBLENV")
[ -n "$mmc_dev" ] && mac=$(grep BaseMacAddress= $mmc_dev | cut -dx -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 1)
mac2=$(macaddr_add $eth 2)
mac3=$(macaddr_add $eth 3)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_wf186w() {
touch /lib/firmware/ath11k-macs
local dev=$(find_mtd_chardev "0:APPSBLENV")
mac=$(grep BaseMacAddress= $dev | cut -dx -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 2)
mac2=$(macaddr_add $eth 3)
mac3=$(macaddr_add $eth 4)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_wf186h() {
touch /lib/firmware/ath11k-macs
local dev=$(find_mtd_chardev "0:APPSBLENV")
mac=$(grep BaseMacAddress= $dev | cut -dx -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 2)
mac2=$(macaddr_add $eth 3)
mac3=$(macaddr_add $eth 4)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac3//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_eww631_a1() {
touch /lib/firmware/ath11k-macs
local dev=$(find_mtd_chardev "0:APPSBLENV")
mac=$(grep BaseMacAddress= $dev | cut -d '=' -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 1)
mac2=$(macaddr_add $eth 2)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
}
ath11k_generate_macs_eww631_b1() {
touch /lib/firmware/ath11k-macs
local dev=$(find_mtd_chardev "0:APPSBLENV")
mac=$(grep BaseMacAddress= $dev | cut -d '=' -f2)
eth=$(macaddr_canonicalize $mac)
mac1=$(macaddr_add $eth 2)
mac2=$(macaddr_add $eth 3)
echo -ne \\x${mac1//:/\\x} >> /lib/firmware/ath11k-macs
echo -ne \\x${mac2//:/\\x} >> /lib/firmware/ath11k-macs
}
caldata_die() {
echo "caldata: " "$*"
exit 1
}
caldata_extract() {
local part=$1
local offset=$(($2))
local count=$(($3))
local mtd
mtd=$(find_mtd_chardev $part)
if [ -z "$mtd" ]; then
mtd=/dev/$(echo $(find_mmc_part $part) | sed 's/^.\{5\}//')
fi
[ -n "$mtd" ] || caldata_die "no mtd device found for partition $part"
dd if=$mtd of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
caldata_die "failed to extract calibration data from $mtd"
}
board=$(board_name)
case "$FIRMWARE" in
"ath11k/IPQ8074/hw2.0/caldata.bin")
case "$board" in
cig,wf194c|\
cig,wf194c4|\
cig,wf196|\
edgecore,eap102 |\
edgecore,oap102 |\
edgecore,eap106 |\
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
qcom,ipq807x-hk01|\
qcom,ipq807x-hk14|\
tplink,ex227|\
tplink,ex447|\
sercomm,wallaby)
caldata_extract "0:ART" 0x1000 0x20000
;;
esac
;;
"ath11k/IPQ6018/hw1.0/caldata.bin")
case "$board" in
cig,wf188|\
cig,wf188n|\
cig,wf660a|\
edgecore,eap101|\
hfcl,ion4xi|\
hfcl,ion4x_2|\
hfcl,ion4x|\
hfcl,ion4xe|\
hfcl,ion4xi_wp|\
wallys,dr6018|\
wallys,dr6018-v4|\
meshpp,ipq6018-cp01|\
meshpp,ipq6018-cp03|\
qcom,ipq6018-cp03|\
qcom,ipq6018-cp01|\
xiaomi,ax1800|\
glinet,ax1800|\
yuncore,ax840|\
yuncore,fap650|\
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2)
caldata_extract "0:ART" 0x1000 0x20000
;;
esac
;;
ath11k/IPQ5018/hw1.0/caldata.bin)
case "$board" in
cig,wf186w|\
cig,wf186h|\
cybertan,eww622-a1|\
cybertan,eww631-a1|\
cybertan,eww631-b1|\
wallys,dr5018|\
edgecore,eap104|\
yuncore,fap655|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
liteon,wpx8324|\
motorola,q14|\
muxi,ap3220l|\
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g|\
qcom,ipq5018-mp03.1)
caldata_extract "0:ART" 0x1000 0x20000
;;
esac
;;
ath11k/qcn6122/hw1.0/caldata_1.bin)
case "$board" in
cig,wf186w|\
cig,wf186h|\
wallys,dr5018|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
cybertan,eww631-a1|\
cybertan,eww631-b1|\
yuncore,fap655|\
motorola,q14)
caldata_extract "0:ART" 0x26800 0x20000
;;
esac
;;
ath11k/qcn6122/hw1.0/caldata_2.bin)
case "$board" in
motorola,q14|\
wallys,dr5018|\
edgecore,eap104|\
liteon,wpx8324)
caldata_extract "0:ART" 0x4c000 0x20000
;;
cybertan,eww631-a1|\
cybertan,eww631-b1|\
muxi,ap3220l)
caldata_extract "0:ART" 0x26800 0x20000
;;
esac
;;
ath11k/QCN9074/hw1.0/caldata_1.bin)
case "$board" in
cig,wf196|\
wallys,dr6018-v4|\
cybertan,eww622-a1|\
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g|\
qcom,ipq5018-mp03.1|\
qcom,ipq807x-hk14)
caldata_extract "0:ART" 0x26800 0x20000
;;
esac
;;
ath11k/QCN9074/hw1.0/caldata_2.bin)
case "$board" in
qcom,ipq807x-hk14|\
qcom,ipq5018-mp03.3)
caldata_extract "0:ART" 0x4C000 0x20000
;;
esac
;;
ath11k-macs)
case "$board" in
hfcl,ion4xi|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
hfcl,ion4xi_wp|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xe)
ath11k_generate_macs_ion4x
;;
edgecore,eap101)
ath11k_generate_macs_eap101
;;
yuncore,ax840|\
yuncore,fap655|\
edgecore,eap102|\
edgecore,oap102|\
edgecore,eap104|\
edgecore,eap106|\
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g|\
cig,wf188n)
ath11k_generate_macs
;;
cig,wf194c|\
cig,wf194c4|\
cig,wf196)
ath11k_generate_macs_wf194
;;
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2)
ath11k_generate_macs_pax1800
;;
cig,wf660a)
ath11k_generate_macs_wf660a
;;
cig,wf186w)
ath11k_generate_macs_wf186w
;;
cig,wf186h)
ath11k_generate_macs_wf186h
;;
cybertan,eww631-a1)
ath11k_generate_macs_eww631_a1
;;
cybertan,eww631-b1)
ath11k_generate_macs_eww631_b1
;;
esac
;;
*)
exit 1
;;
esac

16
feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@@ -1,16 +0,0 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/pre-cal-pci-0001:01:00.0.bin")
case $board in
edgecore,eap106)
caldata_extract "0:ART" 0x33000 0x2f20
;;
esac
esac

40
feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/net/50-dvlan
View File

@@ -1,40 +0,0 @@
#!/bin/sh
. /lib/functions.sh
debug() {
logger -t HOTPLUG-DVLAN "$*"
}
if [ "${INTERFACE:0:4}" != "wlan" ]; then
exit 0
fi
case "$(board_name)" in
"cig,wf186w")
wan_iface="eth0"
switch_dev="switch0"
switch_wan_port=4
switch_cpu_port=6
;;
*)
exit 0
esac
VSTR="$(echo $INTERFACE | egrep -o 'v([0-9]+)$')"
[ -z "$VSTR" ] && exit 0
VID="${VSTR:1}"
[ $VID -lt 1 -o $VID -gt 4096 ] && exit 0
if [ "$ACTION" = "add" ]; then
debug "[$INTERFACE] Dynamic VLAN $VID added, configuring switch"
swconfig dev ${switch_dev} vlan $VID set ports "${switch_wan_port}t ${switch_cpu_port}t"
elif [ "$ACTION" = "remove" ]; then
let cnt="$(bridge vlan show vid $VID | egrep "^wlan" | wc -l)"
debug "[$INTERFACE] Dynamic VLAN interface removed, references left = $cnt"
if [ $cnt -eq 0 ]; then
debug "[$INTERFACE] No more references, removing $VID from switch"
swconfig dev ${switch_dev} vlan $VID set ports ""
fi
fi

3
feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/net/macs
View File

@@ -1,3 +0,0 @@
#!/bin/sh
mac=$(cat /etc/board.json | jsonfilter -e '@["network_device"]["'$DEVICENAME'"]'.macaddr)
[ -n "$mac" ] && ip link set $DEVICENAME address $mac

30
feeds/ipq807x/ipq807x/base-files/etc/init.d/aq_phy
View File

@@ -1,30 +0,0 @@
#!/bin/sh /etc/rc.common
START=30
boot() {
. /lib/functions.sh
case "$(board_name)" in
cig,wf194c|\
cig,wf194c4|\
cig,wf196)
aq-fw-download /lib/firmware/AQR-G4_v5.5.6-AQR_CIG_WIFI_ID44858_VER1745.cld miireg 0 > /dev/null
sleep 1
ssdk_sh debug phy set 0 0x4004c441 0x8
;;
edgecore,eap106)
aq-fw-download /lib/firmware/AQR-G4_v5.5.6-AQR_CIG_WIFI_ID44858_VER1745.cld miireg 8 > /dev/null
sleep 1
ssdk_sh debug phy set 8 0x4004c441 0x8
;;
esac
case "$(board_name)" in
cig,wf196)
# setup the leds
ssdk_sh debug phy set 0 0x401ec431 0xc00f
ssdk_sh debug phy set 0 0x401ec430 0x806f
;;
esac
}

26
feeds/ipq807x/ipq807x/base-files/etc/init.d/bootcount
View File

@@ -1,26 +0,0 @@
#!/bin/sh /etc/rc.common
START=99
boot() {
case "$(board_name)" in
hfcl,ion4xe|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
hfcl,ion4xi_wp|\
hfcl,ion4xi)
fw_setenv boot_count 0
;;
edgecore,eap101|\
edgecore,eap102|\
edgecore,oap102|\
edgecore.eap104)
avail=$(fw_printenv -n upgrade_available)
[ "${avail}" -eq 1 ] || fw_setenv upgrade_available 1
fw_setenv bootcount 0
;;
esac
}

14
feeds/ipq807x/ipq807x/base-files/etc/init.d/wdt
View File

@@ -1,14 +0,0 @@
#!/bin/sh /etc/rc.common
START=10
boot() {
. /lib/functions.sh
case "$(board_name)" in
cig,wf188|\
cig,wf188n)
watchdog -t 5 /dev/watchdog1
;;
esac
}

BIN
feeds/ipq807x/ipq807x/base-files/lib/firmware/AQR-G4_v5.4.B-AQR_CIG_WIFI_ID44715_VER1673.cld
View File

Binary file not shown.

BIN
feeds/ipq807x/ipq807x/base-files/lib/firmware/AQR-G4_v5.5.6-AQR_CIG_WIFI_ID44858_VER1745.cld
View File

Binary file not shown.

126
feeds/ipq807x/ipq807x/base-files/lib/upgrade/dualboot_datachk.sh
View File

@@ -1,126 +0,0 @@
# The U-Boot loader with the datachk patchset for dualbooting requires image
# sizes and checksums to be provided in the U-Boot environment.
# The devices come with 2 main partitions - while one is active
# sysupgrade will flash the other. The boot order is changed to boot the
# newly flashed partition. If the new partition can't be booted due to
# upgrade failures the previously used partition is loaded.
platform_post_upgrade_sanity_check()
{
local part_name=$1
local inactive_mtd=$2
local cfg_md5=$3
local part_offset=$4
local part_size=$5
md5_part_disk=$(dd if=/dev/${inactive_mtd} bs=$((64*1024)) skip=$((part_offset / (64*1024))) count=$((part_size / (64*1024))) 2>&- | md5sum | awk '{print $1}')
if [ "${cfg_md5}" != "${md5_part_disk}" ]; then
echo "post-flashing checksum mismatch: ${part_name}" >&2
echo "${cfg_md5} != ${md5_part_disk}"
return 1
fi
return 0
}
platform_do_upgrade_dualboot_datachk() {
local tar_file="$1"
local restore_backup
local primary_kernel_mtd
local setenv_script="/tmp/fw_env_upgrade"
local kernel_mtd="$(find_mtd_index $PART_NAME)"
local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
# detect to which flash region the new image is written to.
#
# 1. check what is the mtd index for the first flash region on this
# device
# 2. check if the target partition ("inactive") has the mtd index of
# the first flash region
#
# - when it is: the new bootseq will be 1,2 and the first region is
# modified
# - when it isnt: bootseq will be 2,1 and the second region is
# modified
#
# The detection has to be done via the hardcoded mtd partition because
# the current boot might be done with the fallback region. Let us
# assume that the current bootseq is 1,2. The bootloader detected that
# the image in flash region 1 is corrupt and thus switches to flash
# region 2. The bootseq in the u-boot-env is now still the same and
# the sysupgrade code can now only rely on the actual mtd indexes and
# not the bootseq variable to detect the currently booted flash
# region/image.
#
# In the above example, an implementation which uses bootseq ("1,2") to
# detect the currently booted image would assume that region 1 is booted
# and then overwrite the variables for the wrong flash region (aka the
# one which isn't modified). This could result in a device which doesn't
# boot anymore to Linux until it was reflashed with ap51-flash.
local next_boot_part="1"
case "$(board_name)" in
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2)
primary_kernel_mtd=9
;;
*)
echo "failed to detect primary kernel mtd partition for board"
return 1
;;
esac
[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
# rootfs without EOF marker
rootfs_length=$((rootfs_length-4))
local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
# md5 checksum of rootfs with EOF marker
local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
#
# add tar support to get_image() to use default_do_upgrade() instead?
#
# take care of restoring a saved config
[ -n "$UPGRADE_BACKUP" ] && restore_backup="${MTD_CONFIG_ARGS} -j ${UPGRADE_BACKUP}"
mtd -q erase inactive
tar xf $tar_file ${board_dir}/root -O | mtd -n -p $kernel_length $restore_backup write - $PART_NAME
tar xf $tar_file ${board_dir}/kernel -O | mtd -n write - $PART_NAME
platform_post_upgrade_sanity_check "kernel" "mtd${kernel_mtd}" $kernel_md5 0 $kernel_length || return 1
platform_post_upgrade_sanity_check "rootfs" "mtd${kernel_mtd}" $rootfs_md5 $kernel_length $rootfs_length || return 1
# prepare new u-boot env
if [ "$next_boot_part" = "1" ]; then
echo "bootseq 1,2" > $setenv_script
else
echo "bootseq 2,1" > $setenv_script
fi
printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
# store u-boot env changes
mkdir -p /var/lock
fw_setenv -s $setenv_script || {
echo "failed to update U-Boot environment"
return 1
}
}

391
feeds/ipq807x/ipq807x/base-files/lib/upgrade/nand.sh
View File

@@ -1,391 +0,0 @@
# Copyright (C) 2014 OpenWrt.org
#
. /lib/functions.sh
# 'kernel' partition or UBI volume on NAND contains the kernel
CI_KERNPART="${CI_KERNPART:-kernel}"
# 'ubi' partition on NAND contains UBI
CI_UBIPART="${CI_UBIPART:-ubi}"
# 'rootfs' UBI volume on NAND contains the rootfs
CI_ROOTPART="${CI_ROOTPART:-rootfs}"
# ipq807x qsdk kernel misbehaves
CI_IPQ807X=0
# update BOOTCONFIG partitions (rotate rootfs/rootfs_1)
CI_BOOTCFG=0
# update uboot-env if upgrade suceeded
CI_FWSETENV=
ubi_mknod() {
local dir="$1"
local dev="/dev/$(basename $dir)"
[ -e "$dev" ] && return 0
local devid="$(cat $dir/dev)"
local major="${devid%%:*}"
local minor="${devid##*:}"
mknod "$dev" c $major $minor
}
nand_find_volume() {
local ubidevdir ubivoldir
ubidevdir="/sys/devices/virtual/ubi/$1"
[ ! -d "$ubidevdir" ] && return 1
for ubivoldir in $ubidevdir/${1}_*; do
[ ! -d "$ubivoldir" ] && continue
if [ "$( cat $ubivoldir/name )" = "$2" ]; then
basename $ubivoldir
ubi_mknod "$ubivoldir"
return 0
fi
done
}
nand_find_ubi() {
local ubidevdir ubidev mtdnum
mtdnum="$( find_mtd_index $1 )"
[ ! "$mtdnum" ] && return 1
for ubidevdir in /sys/devices/virtual/ubi/ubi*; do
[ ! -d "$ubidevdir" ] && continue
cmtdnum="$( cat $ubidevdir/mtd_num )"
[ ! "$mtdnum" ] && continue
if [ "$mtdnum" = "$cmtdnum" ]; then
ubidev=$( basename $ubidevdir )
ubi_mknod "$ubidevdir"
echo $ubidev
return 0
fi
done
}
nand_get_magic_long() {
dd if="$1" skip=$2 bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"'
}
get_magic_long_tar() {
( tar xf $1 $2 -O | dd bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2> /dev/null
}
identify_magic() {
local magic=$1
case "$magic" in
"55424923")
echo "ubi"
;;
"31181006")
echo "ubifs"
;;
"68737173")
echo "squashfs"
;;
"d00dfeed")
echo "fit"
;;
"4349"*)
echo "combined"
;;
*)
echo "unknown $magic"
;;
esac
}
identify() {
identify_magic $(nand_get_magic_long "$1" "${2:-0}")
}
identify_tar() {
identify_magic $(get_magic_long_tar "$1" "$2")
}
nand_restore_config() {
sync
local ubidev=$( nand_find_ubi $CI_UBIPART )
local ubivol="$( nand_find_volume $ubidev rootfs_data )"
[ ! "$ubivol" ] &&
ubivol="$( nand_find_volume $ubidev $CI_ROOTPART )"
mkdir /tmp/new_root
if ! mount -t ubifs /dev/$ubivol /tmp/new_root; then
echo "mounting ubifs $ubivol failed"
rmdir /tmp/new_root
return 1
fi
mv "$1" "/tmp/new_root/$BACKUP_FILE"
umount /tmp/new_root
sync
rmdir /tmp/new_root
}
nand_upgrade_prepare_ubi() {
local rootfs_length="$1"
local rootfs_type="$2"
local rootfs_data_max="$(fw_printenv -n rootfs_data_max 2>/dev/null)"
[ -n "$rootfs_data_max" ] && rootfs_data_max=$(printf %d "$rootfs_data_max")
local kernel_length="$3"
local has_env="${4:-0}"
[ -n "$rootfs_length" -o -n "$kernel_length" ] || return 1
local mtdnum="$( find_mtd_index "$CI_UBIPART" )"
if [ ! "$mtdnum" ]; then
echo "cannot find ubi mtd partition $CI_UBIPART"
return 1
fi
[ "$CI_IPQ807X" = 1 ] && ubidetach -f -m $mtdnum
local ubidev="$( nand_find_ubi "$CI_UBIPART" )"
if [ ! "$ubidev" ]; then
ubiattach -m "$mtdnum"
sync
ubidev="$( nand_find_ubi "$CI_UBIPART" )"
fi
if [ ! "$ubidev" ]; then
ubiformat /dev/mtd$mtdnum -y
ubiattach -m "$mtdnum"
sync
ubidev="$( nand_find_ubi "$CI_UBIPART" )"
[ "$has_env" -gt 0 ] && {
ubimkvol /dev/$ubidev -n 0 -N ubootenv -s 1MiB
ubimkvol /dev/$ubidev -n 1 -N ubootenv2 -s 1MiB
}
fi
local kern_ubivol="$( nand_find_volume $ubidev $CI_KERNPART )"
local root_ubivol="$( nand_find_volume $ubidev $CI_ROOTPART )"
local data_ubivol="$( nand_find_volume $ubidev rootfs_data )"
local ubiblk ubiblkvol
for ubiblk in /dev/ubiblock*_? ; do
[ -e "$ubiblk" ] || continue
echo "removing ubiblock${ubiblk:13}"
ubiblkvol=ubi${ubiblk:13}
if ! ubiblock -r /dev/$ubiblkvol; then
echo "cannot remove $ubiblk"
return 1
fi
done
# kill volumes
[ "$kern_ubivol" ] && ubirmvol /dev/$ubidev -N $CI_KERNPART || true
[ "$root_ubivol" -a "$root_ubivol" != "$kern_ubivol" ] && ubirmvol /dev/$ubidev -N $CI_ROOTPART || true
[ "$data_ubivol" ] && ubirmvol /dev/$ubidev -N rootfs_data || true
# update kernel
if [ -n "$kernel_length" ]; then
if ! ubimkvol /dev/$ubidev -N $CI_KERNPART -s $kernel_length; then
echo "cannot create kernel volume"
return 1;
fi
fi
# update rootfs
if [ -n "$rootfs_length" ]; then
local rootfs_size_param
if [ "$rootfs_type" = "ubifs" ]; then
rootfs_size_param="-m"
else
rootfs_size_param="-s $rootfs_length"
fi
if ! ubimkvol /dev/$ubidev -N $CI_ROOTPART $rootfs_size_param; then
echo "cannot create rootfs volume"
return 1;
fi
fi
# create rootfs_data for non-ubifs rootfs
if [ "$rootfs_type" != "ubifs" ]; then
local availeb=$(cat /sys/devices/virtual/ubi/$ubidev/avail_eraseblocks)
local ebsize=$(cat /sys/devices/virtual/ubi/$ubidev/eraseblock_size)
local avail_size=$(( $availeb * $ebsize ))
local rootfs_data_size_param="-m"
if [ -n "$rootfs_data_max" ] &&
[ "$rootfs_data_max" != "0" ] &&
[ "$rootfs_data_max" -le "$avail_size" ]; then
rootfs_data_size_param="-s $rootfs_data_max"
fi
if ! ubimkvol /dev/$ubidev -N rootfs_data $rootfs_data_size_param; then
echo "cannot initialize rootfs_data volume"
return 1
fi
fi
sync
return 0
}
nand_qca_update_bootconfig() {
local primary="0"
local mtdnum
local part
[ -f /proc/boot_info/rootfs/primaryboot ] || return
[ -f /proc/boot_info/getbinary_bootconfig ] || return
[ "$(cat /proc/boot_info/rootfs/primaryboot)" = "0" ] && primary="1"
echo "$primary" > /proc/boot_info/rootfs/primaryboot 2>/dev/null
for part in "0:BOOTCONFIG" "0:BOOTCONFIG1"; do
mtdnum="$(find_mtd_index "$part")"
[ -c "/dev/mtd${mtdnum}" ] && {
mtd -qq write /proc/boot_info/getbinary_bootconfig \
"/dev/mtd${mtdnum}" 2>/dev/null &&\
echo "partition '$part' updated"
}
done
}
nand_do_upgrade_success() {
local conf_tar="/tmp/sysupgrade.tgz"
sync
[ "$CI_BOOTCFG" = 1 ] && nand_qca_update_bootconfig
[ -f "$conf_tar" ] && nand_restore_config "$conf_tar" && sync
[ -n "$CI_FWSETENV" ] && fw_setenv $CI_FWSETENV
echo "sysupgrade successful"
umount -a
reboot -f
}
# Flash the UBI image to MTD partition
nand_upgrade_ubinized() {
local ubi_file="$1"
local mtdnum="$(find_mtd_index "$CI_UBIPART")"
[ ! "$mtdnum" ] && {
CI_UBIPART="rootfs"
mtdnum="$(find_mtd_index "$CI_UBIPART")"
}
if [ ! "$mtdnum" ]; then
echo "cannot find mtd device $CI_UBIPART"
umount -a
reboot -f
fi
local mtddev="/dev/mtd${mtdnum}"
ubidetach -p "${mtddev}" || true
sync
ubiformat "${mtddev}" -y -f "${ubi_file}"
ubiattach -p "${mtddev}"
nand_do_upgrade_success
}
# Write the UBIFS image to UBI volume
nand_upgrade_ubifs() {
local rootfs_length=$( (cat $1 | wc -c) 2> /dev/null)
nand_upgrade_prepare_ubi "$rootfs_length" "ubifs" "" ""
local ubidev="$( nand_find_ubi "$CI_UBIPART" )"
local root_ubivol="$(nand_find_volume $ubidev $CI_ROOTPART)"
ubiupdatevol /dev/$root_ubivol -s $rootfs_length $1
nand_do_upgrade_success
}
nand_upgrade_fit() {
local fit_file="$1"
local fit_length="$(wc -c < "$fit_file")"
nand_upgrade_prepare_ubi "" "" "$fit_length" "1"
local fit_ubidev="$(nand_find_ubi "$CI_UBIPART")"
local fit_ubivol="$(nand_find_volume $fit_ubidev "$CI_KERNPART")"
ubiupdatevol /dev/$fit_ubivol -s $fit_length $fit_file
nand_do_upgrade_success
}
nand_upgrade_tar() {
local tar_file="$1"
local kernel_mtd="$(find_mtd_index $CI_KERNPART)"
local board_dir=$(tar tf "$tar_file" | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
kernel_length=$( (tar xf "$tar_file" ${board_dir}/kernel -O | wc -c) 2> /dev/null)
local has_rootfs=0
local rootfs_length
local rootfs_type
tar tf "$tar_file" ${board_dir}/root 1>/dev/null 2>/dev/null && has_rootfs=1
[ "$has_rootfs" = "1" ] && {
rootfs_length=$( (tar xf "$tar_file" ${board_dir}/root -O | wc -c) 2> /dev/null)
rootfs_type="$(identify_tar "$tar_file" ${board_dir}/root)"
}
local has_kernel=1
local has_env=0
[ "$CI_IPQ807X" = 0 -a "$kernel_length" != 0 -a -n "$kernel_mtd" ] && {
tar xf $tar_file ${board_dir}/kernel -O | mtd write - $CI_KERNPART
}
[ "$CI_IPQ807X" = 0 ] && {
[ "$kernel_length" = 0 -o ! -z "$kernel_mtd" ] && has_kernel=
}
nand_upgrade_prepare_ubi "$rootfs_length" "$rootfs_type" "${has_kernel:+$kernel_length}" "$has_env"
local ubidev="$( nand_find_ubi "$CI_UBIPART" )"
[ "$has_kernel" = "1" ] && {
local kern_ubivol="$( nand_find_volume $ubidev $CI_KERNPART )"
tar xf "$tar_file" ${board_dir}/kernel -O | \
ubiupdatevol /dev/$kern_ubivol -s $kernel_length -
}
[ "$has_rootfs" = "1" ] && {
local root_ubivol="$( nand_find_volume $ubidev $CI_ROOTPART )"
tar xf "$tar_file" ${board_dir}/root -O | \
ubiupdatevol /dev/$root_ubivol -s $rootfs_length -
}
nand_do_upgrade_success
}
# Recognize type of passed file and start the upgrade process
nand_do_upgrade() {
local file_type=$(identify $1)
[ ! "$( find_mtd_index "$CI_UBIPART" )" ] && CI_UBIPART="rootfs"
case "$file_type" in
"fit") nand_upgrade_fit $1;;
"ubi") nand_upgrade_ubinized $1;;
"ubifs") nand_upgrade_ubifs $1;;
*) nand_upgrade_tar $1;;
esac
}
# Check if passed file is a valid one for NAND sysupgrade. Currently it accepts
# 3 types of files:
# 1) UBI - should contain an ubinized image, header is checked for the proper
# MAGIC
# 2) UBIFS - should contain UBIFS partition that will replace "rootfs" volume,
# header is checked for the proper MAGIC
# 3) TAR - archive has to include "sysupgrade-BOARD" directory with a non-empty
# "CONTROL" file (at this point its content isn't verified)
#
# You usually want to call this function in platform_check_image.
#
# $(1): board name, used in case of passing TAR file
# $(2): file to be checked
nand_do_platform_check() {
local board_name="$1"
local tar_file="$2"
local control_length=$( (tar xf $tar_file sysupgrade-$board_name/CONTROL -O | wc -c) 2> /dev/null)
local file_type="$(identify $2)"
[ "$control_length" = 0 -a "$file_type" != "ubi" -a "$file_type" != "ubifs" -a "$file_type" != "fit" ] && {
echo "Invalid sysupgrade file."
return 1
}
return 0
}

304
feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh
View File

@@ -1,304 +0,0 @@
. /lib/functions/system.sh
RAMFS_COPY_BIN='fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock /tmp/downgrade'
qca_do_upgrade() {
local tar_file="$1"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
local dev=$(find_mtd_chardev "0:HLOS")
tar Oxf $tar_file ${board_dir}/kernel | mtd write - ${dev}
if [ -n "$UPGRADE_BACKUP" ]; then
tar Oxf $tar_file ${board_dir}/root | mtd -j "$UPGRADE_BACKUP" write - rootfs
else
tar Oxf $tar_file ${board_dir}/root | mtd write - rootfs
fi
}
find_mmc_part() {
local DEVNAME PARTNAME
if grep -q "$1" /proc/mtd; then
echo "" && return 0
fi
for DEVNAME in /sys/block/mmcblk*/mmcblk*p*; do
PARTNAME=$(grep PARTNAME ${DEVNAME}/uevent | cut -f2 -d'=')
[ "$PARTNAME" = "$1" ] && echo "/dev/$(basename $DEVNAME)" && return 0
done
}
do_flash_emmc() {
local tar_file=$1
local emmcblock=$(find_mmc_part $2)
local board_dir=$3
local part=$4
[ -b "$emmcblock" ] || emmcblock=$(find_mmc_part $2)
[ -z "$emmcblock" ] && {
echo failed to find $2
return
}
echo erase $4 / $emmcblock
dd if=/dev/zero of=${emmcblock} 2> /dev/null
echo flash $4
tar Oxf $tar_file ${board_dir}/$part | dd of=${emmcblock}
}
spi_nor_emmc_do_upgrade_bootconfig() {
local tar_file="$1"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
[ -f /proc/boot_info/getbinary_bootconfig ] || {
echo "bootconfig does not exist"
exit
}
CI_ROOTPART="$(cat /proc/boot_info/rootfs/upgradepartition)"
CI_KERNPART="$(cat /proc/boot_info/0:HLOS/upgradepartition)"
[ -n "$CI_KERNPART" -a -n "$CI_ROOTPART" ] || {
echo "kernel or rootfs partition is unknown"
exit
}
local primary="0"
[ "$(cat /proc/boot_info/rootfs/primaryboot)" = "0" ] && primary="1"
echo "$primary" > /proc/boot_info/rootfs/primaryboot 2>/dev/null
echo "$primary" > /proc/boot_info/0:HLOS/primaryboot 2>/dev/null
cp /proc/boot_info/getbinary_bootconfig /tmp/bootconfig
do_flash_emmc $tar_file $CI_KERNPART $board_dir kernel
do_flash_emmc $tar_file $CI_ROOTPART $board_dir root
local emmcblock="$(find_mmc_part "rootfs_data")"
if [ -e "$emmcblock" ]; then
mkfs.ext4 -F "$emmcblock"
fi
for part in "0:BOOTCONFIG" "0:BOOTCONFIG1"; do
local mtdchar=$(echo $(find_mtd_chardev $part) | sed 's/^.\{5\}//')
if [ -n "$mtdchar" ]; then
echo start to update $mtdchar
mtd -qq write /proc/boot_info/getbinary_bootconfig "/dev/${mtdchar}" 2>/dev/null && echo update mtd $mtdchar
else
emmcblock=$(find_mmc_part $part)
echo erase ${emmcblock}
dd if=/dev/zero of=${emmcblock} 2> /dev/null
echo update $emmcblock
dd if=/tmp/bootconfig of=${emmcblock} 2> /dev/null
fi
done
}
emmc_do_upgrade() {
local tar_file="$1"
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
do_flash_emmc $tar_file '0:HLOS' $board_dir kernel
do_flash_emmc $tar_file 'rootfs' $board_dir root
local emmcblock="$(find_mmc_part "rootfs_data")"
if [ -e "$emmcblock" ]; then
mkfs.ext4 -F "$emmcblock"
fi
}
platform_check_image() {
local magic_long="$(get_magic_long "$1")"
board=$(board_name)
case $board in
cig,wf186w|\
cig,wf186h|\
cig,wf188|\
cig,wf660a|\
cig,wf188n|\
cig,wf194c|\
cig,wf194c4|\
cig,wf196|\
cybertan,eww622-a1|\
cybertan,eww631-a1|\
cybertan,eww631-b1|\
glinet,ax1800|\
glinet,axt1800|\
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
wallys,dr5018|\
wallys,dr6018|\
wallys,dr6018-v4|\
edgecore,eap101|\
edgecore,eap102|\
edgecore,oap102|\
edgecore,eap104|\
liteon,wpx8324|\
edgecore,eap106|\
hfcl,ion4xi|\
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
hfcl,ion4xi_wp|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xe|\
muxi,ap3220l|\
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2|\
tplink,ex227|\
tplink,ex447|\
yuncore,ax840|\
yuncore,fap650|\
yuncore,fap655|\
motorola,q14|\
muxi,ap3220l|\
qcom,ipq6018-cp01|\
qcom,ipq807x-hk01|\
qcom,ipq807x-hk14|\
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g|\
qcom,ipq5018-mp03.3)
[ "$magic_long" = "73797375" ] && return 0
;;
esac
return 1
}
platform_do_upgrade() {
CI_UBIPART="rootfs"
CI_ROOTPART="ubi_rootfs"
CI_IPQ807X=1
board=$(board_name)
case $board in
cig,wf188)
qca_do_upgrade $1
;;
cig,wf660a)
spi_nor_emmc_do_upgrade_bootconfig $1
;;
motorola,q14)
emmc_do_upgrade $1
;;
cig,wf188n|\
cig,wf194c|\
cig,wf194c4|\
cig,wf196|\
cybertan,eww622-a1|\
glinet,ax1800|\
glinet,axt1800|\
indio,um-310ax-v1|\
indio,um-510axp-v1|\
indio,um-510axm-v1|\
qcom,ipq6018-cp01|\
qcom,ipq807x-hk01|\
qcom,ipq807x-hk14|\
optimcloud,d60|\
optimcloud,d60-5g|\
optimcloud,d50|\
optimcloud,d50-5g|\
qcom,ipq5018-mp03.3|\
wallys,dr5018|\
wallys,dr6018|\
wallys,dr6018-v4|\
yuncore,fap650|\
tplink,ex447|\
tplink,ex227|\
meshpp,s618-cp03|\
meshpp,s618-cp01)
nand_upgrade_tar "$1"
;;
hfcl,ion4xi|\
hfcl,ion4x|\
hfcl,ion4x_2|\
hfcl,ion4xe)
if grep -q rootfs_1 /proc/cmdline; then
CI_UBIPART="rootfs"
fw_setenv primary 0 || exit 1
else
CI_UBIPART="rootfs_1"
fw_setenv primary 1 || exit 1
fi
nand_upgrade_tar "$1"
;;
hfcl,ion4xi_w|\
hfcl,ion4x_w|\
hfcl,ion4xi_HMR|\
hfcl,ion4xi_wp)
wp_part=$(fw_printenv primary | cut -d = -f2)
echo "Current Primary is $wp_part"
if [[ $wp_part == 1 ]]; then
CI_UBIPART="rootfs"
CI_FWSETENV="primary 0"
else
CI_UBIPART="rootfs_1"
CI_FWSETENV="primary 1"
fi
nand_upgrade_tar "$1"
;;
edgecore,eap104|\
liteon,wpx8324|\
edgecore,eap106)
CI_UBIPART="rootfs1"
[ "$(find_mtd_chardev rootfs)" ] && CI_UBIPART="rootfs"
nand_upgrade_tar "$1"
;;
edgecore,eap101|\
edgecore,eap102|\
edgecore,oap102)
if [ "$(find_mtd_chardev rootfs)" ]; then
CI_UBIPART="rootfs"
else
if [ -e /tmp/downgrade ]; then
CI_UBIPART="rootfs1"
{ echo 'active 1'; echo 'upgrade_available 0'; } > /tmp/fw_setenv.txt || exit 1
CI_FWSETENV="-s /tmp/fw_setenv.txt"
elif grep -q rootfs1 /proc/cmdline; then
CI_UBIPART="rootfs2"
CI_FWSETENV="active 2"
else
CI_UBIPART="rootfs1"
CI_FWSETENV="active 1"
fi
fi
nand_upgrade_tar "$1"
;;
plasmacloud,pax1800-v1|\
plasmacloud,pax1800-v2)
PART_NAME="inactive"
platform_do_upgrade_dualboot_datachk "$1"
;;
cig,wf186w|\
cig,wf186h|\
yuncore,ax840|\
yuncore,fap655)
[ -f /proc/boot_info/rootfs/upgradepartition ] && {
CI_UBIPART="$(cat /proc/boot_info/rootfs/upgradepartition)"
CI_BOOTCFG=1
}
nand_upgrade_tar "$1"
;;
cybertan,eww631-a1|\
cybertan,eww631-b1)
boot_part=$(fw_printenv bootfrom | cut -d = -f2)
echo "Current bootfrom is $boot_part"
if [[ $boot_part == 1 ]]; then
CI_UBIPART="rootfs"
CI_FWSETENV="bootfrom 0"
else
CI_UBIPART="rootfs_1"
CI_FWSETENV="bootfrom 1"
fi
nand_upgrade_tar "$1"
;;
esac
}

832
feeds/ipq807x/ipq807x/config-4.4
View File

@@ -1,832 +0,0 @@
# CONFIG_AHCI_IPQ is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_AMBA_PL08X is not set
# CONFIG_APM_EMULATION is not set
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
# CONFIG_AR8216_PHY is not set
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
# CONFIG_ARCH_IPQ40XX is not set
# CONFIG_ARCH_IPQ806x is not set
# CONFIG_ARCH_IPQ807x is not set
# CONFIG_ARCH_IPQ6018 is not set
# CONFIG_ARCH_IPQ5018 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_QCOM=y
CONFIG_QSEECOM=m
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_ARM_CCI400_PMU=y
CONFIG_ARM_CCI_PMU=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_MODULE_PLTS=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PSCI=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ARM_QCOM_CPUFREQ=y
# CONFIG_ARM_SMMU is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
# CONFIG_ATA is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BOOTCONFIG_PARTITION is not set
# CONFIG_VIRTIO_BLK is not set
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_BOUNCE=y
CONFIG_BUILD_BIN2C=y
# CONFIG_CNSS_QCN9000 is not set
# CONFIG_CNSS2 is not set
# CONFIG_CNSS2_GENL is not set
# CONFIG_CNSS2_DEBUG is not set
# CONFIG_CNSS2_PM is not set
# CONFIG_CNSS2_PCI_DRIVER is not set
# CONFIG_CNSS2_CALIBRATION_SUPPORT is not set
# CONFIG_CNSS2_SMMU is not set
# CONFIG_CNSS2_RAMDUMP is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CC_STACKPROTECTOR=y
# CONFIG_CC_STACKPROTECTOR_NONE is not set
CONFIG_CC_STACKPROTECTOR_REGULAR=y
# CONFIG_CHARGER_QCOM_SMBB is not set
CONFIG_CLEANCACHE=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_OF=y
CONFIG_CLKSRC_PROBE=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_CONFIGFS_FS=y
CONFIG_COREDUMP=y
# CONFIG_CORESIGHT is not set
# CONFIG_CORESIGHT_CSR is not set
# CONFIG_CORESIGHT_CTI is not set
# NFIG_CORESIGHT_EVENT is not set
# CONFIG_CORESIGHT_HWEVENT is not set
# CONFIG_CORESIGHT_LINKS_AND_SINKS is not set
# CONFIG_CORESIGHT_LINK_AND_SINK_TMC is not set
# CONFIG_CORESIGHT_QCOM_REPLICATOR is not set
# CONFIG_CORESIGHT_QPDI is not set
# CONFIG_CORESIGHT_SINK_ETBV10 is not set
# CONFIG_CORESIGHT_SINK_TPIU is not set
# CONFIG_CORESIGHT_SOURCE_DUMMY is not set
# CONFIG_CORESIGHT_SOURCE_ETM3X is not set
# CONFIG_CORESIGHT_SOURCE_ETM4X is not set
# CONFIG_CORESIGHT_REMOTE_ETM is not set
# CONFIG_CORESIGHT_STM is not set
# CONFIG_CORESIGHT_TPDA is not set
# CONFIG_CORESIGHT_TPDM is not set
# CONFIG_CORESIGHT_TPDM_DEFAULT_ENABLE is not set
# CONFIG_CORESIGHT_STREAM is not set
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
# CONFIG_CPU_SW_DOMAIN_PAN is not set
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
# CONFIG_CPU_THERMAL is not set
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_CRYPTO_DEV_QCOM_MSM_QCE is not set
# CONFIG_CRYPTO_DEV_OTA_CRYPTO is not set
# CONFIG_FIPS_ENABLE is not set
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_CMAC=y
# CONFIG_CRYPTO_DEV_QCOM_ICE is not set
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_XZ=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_GCM=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_GPIO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEBUG_MEM_USAGE is not set
# CONFIG_DEBUG_UART_8250 is not set
# CONFIG_DEBUG_USER is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DEVMEM=y
# CONFIG_DIAG_OVER_USB is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_DWMAC_IPQ806X is not set
# CONFIG_DWMAC_SUNXI is not set
# CONFIG_DW_DMAC_PCI is not set
# CONFIG_VHOST_NET is not set
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_EXT4_FS=y
# CONFIG_EXT4_USE_FOR_EXT2 is not set
CONFIG_FB=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_QCOM_QPIC=y
CONFIG_FB_QCOM_QPIC_ER_SSD1963_PANEL=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_MBCACHE=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
# CONFIG_GENERIC_CPUFREQ_KRAIT is not set
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_DEVRES=y
# CONFIG_GPIO_LATCH is not set
# CONFIG_GPIO_NXP_74HC153 is not set
CONFIG_GPIO_SYSFS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_BPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
# CONFIG_SRD_TRACE is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_XZ=y
# CONFIG_HAVE_KPROBES is not set
# CONFIG_HAVE_KRETPROBES is not set
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_OPTPROBES is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_SMP=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_UID16=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_QUP=y
# CONFIG_IIO is not set
# CONFIG_IIO_BUFFER is not set
# CONFIG_IIO_TRIGGER is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_INPUT_PM8941_PWRKEY is not set
CONFIG_IOMMU_HELPER=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
# CONFIG_IPQ_DWC3_QTI_EXTCON is not set
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_5018 is not set
# CONFIG_IPQ_APSS_5018 is not set
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_APSS_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_ADSS_807x is not set
# CONFIG_IPQ_APSS_807x is not set
# CONFIG_IPQ_GCC_807x is not set
# CONFIG_IPQ_ADCC_4019 is not set
# CONFIG_IPQ_LCC_806X is not set
# CONFIG_IPQ_REMOTEPROC_ADSP is not set
# CONFIG_IPQ_SUBSYSTEM_RESTART is not set
# CONFIG_IPQ_SUBSYSTEM_RESTART_TEST is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
# CONFIG_IPC_ROUTER is not set
# CONFIG_IPC_ROUTER_SECURITY is not set
# CONFIG_IPC_LOGGING is not set
CONFIG_KPSS_XCC=y
# CONFIG_KRAITCC is not set
# CONFIG_KRAIT_CLOCKS is not set
# CONFIG_KRAIT_L2_ACCESSORS is not set
CONFIG_LEDS_IPQ=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TLC591XX=y
# CONFIG_LEDS_PCA9956B is not set
CONFIG_LIBFDT=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_GPIO=y
# CONFIG_MDIO_QCA is not set
CONFIG_MFD_QCOM_RPM=y
CONFIG_MFD_SPMI_PMIC=y
# CONFIG_SLIMBUS is not set
# CONFIG_SLIMBUS_MSM_CTRL is not set
# CONFIG_SLIMBUS_MSM_NGD is not set
# CONFIG_OF_SLIMBUS is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGHT_HAVE_PCI=y
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_QCOM_DML=y
CONFIG_MMC_QCOM_TUNING=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_OF_ARASAN is not set
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
# CONFIG_MMC_TIFM_SD is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MPLS_ROUTING is not set
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MHI is not set
# CONFIG_MSM_IPC_ROUTER_MHI_XPRT is not set
# CONFIG_MSM_MHI_DEBUG is not set
# CONFIG_MSM_MHI_DEV is not set
# CONFIG_MSM_MHI_UCI is not set
# CONFIG_DIAGFWD_BRIDGE_CODE is not set
# CONFIG_MSM_BUS_SCALING is not set
# CONFIG_BUS_TOPOLOGY_ADHOC is not set
# CONFIG_QPNP_REVID is not set
# CONFIG_SPS is not set
# CONFIG_SPS_SUPPORT_NDP_BAM is not set
# CONFIG_USB_BAM is not set
# CONFIG_SPS_SUPPORT_BAMDMA is not set
# CONFIG_IPA is not set
# CONFIG_IPA3 is not set
# CONFIG_EP_PCIE is not set
# CONFIG_GSI is not set
# CONFIG_PFT is not set
# CONFIG_SEEMP_CORE is not set
# CONFIG_GPIO_USB_DETECT is not set
# CONFIG_MSM_GLINK is not set
# CONFIG_MSM_GLINK_LOOPBACK_SERVER is not set
# CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT is not set
# CONFIG_MSM_GLINK_PKT is not set
# CONFIG_MSM_IPC_ROUTER_GLINK_XPRT is not set
# CONFIG_MSM_QMI_INTERFACE is not set
# CONFIG_MSM_TEST_QMI_CLIENT is not set
# CONFIG_GLINK_DEBUG_FS is not set
# CONFIG_MSM_RPM_SMD is not set
# CONFIG_MSM_RPM_GLINK is not set
CONFIG_MSM_RPM_LOG=y
# CONFIG_MSM_SMEM is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOM_SMEM_PARTS=y
CONFIG_MTD_SPINAND_GIGADEVICE=y
CONFIG_MTD_SPINAND_MT29F=y
CONFIG_MTD_SPINAND_ONDIEECC=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET=y
# CONFIG_NET_DSA_MV88E6063 is not set
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NO_BOOTMEM=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NUM_ALT_PARTITION=8
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=5
CONFIG_PCI=y
# CONFIG_PCIEAER is not set
CONFIG_PCIE_DW=y
# CONFIG_PCIE_DW_PLAT is not set
CONFIG_PCIE_PME=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_IPQ_BALDUR_USB is not set
# CONFIG_PHY_IPQ_UNIPHY_USB is not set
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
CONFIG_PHY_QCA_PCIE_QMP=y
# CONFIG_PHY_QCOM_UFS is not set
# CONFIG_PHY_IPQ_UNIPHY_PCIE is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ807x is not set
# CONFIG_PINCTRL_IPQ5018 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PL330_DMA is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_OPP=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
CONFIG_PROC_PAGE_MONITOR=y
# CONFIG_PROC_STRIPPED is not set
CONFIG_PSTORE=y
CONFIG_PSTORE_RAM=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PWM=y
CONFIG_PWM_IPQ4019=y
# CONFIG_PWM_PCA9685 is not set
CONFIG_PWM_SYSFS=y
CONFIG_QCOM_ADM=y
# CONFIG_QCOM_APM is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QTI_BT_TTY is not set
# CONFIG_QCOM_COINCELL is not set
# CONFIG_QCOM_DCC is not set
CONFIG_QCOM_GDSC=y
CONFIG_QCOM_GSBI=y
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_MEMORY_DUMP_V2 is not set
# CONFIG_QCOM_MDT_LOADER is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
CONFIG_QCOM_RPM_CLK=y
# CONFIG_QCOM_RTB is not set
# CONFIG_QCOM_PM is not set
CONFIG_QCOM_SCM=y
CONFIG_QCOM_SCM_32=y
# CONFIG_HAVE_ARM_SMCCC is not set
CONFIG_QCA_SCM_RESTART_REASON=y
CONFIG_IPQ_TCSR=y
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_SMD is not set
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMEM_STATE=y
# CONFIG_QCOM_SMD is not set
CONFIG_QCOM_SMP2P=y
# CONFIG_QCOM_SPMI_VADC is not set
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_TZ_LOG=y
CONFIG_QCOM_WDT=y
CONFIG_QMI_ENCDEC=y
CONFIG_RATIONAL=y
# CONFIG_RCU_BOOST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_EXPERT is not set
CONFIG_RCU_STALL_COMMON=y
CONFIG_RD_GZIP=y
CONFIG_REGMAP=y
# CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS is not set
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_CPR3 is not set
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_QCOM_RPM=y
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_IPQ40XX is not set
# CONFIG_REGULATOR_RPM_SMD is not set
# CONFIG_REGULATOR_RPM_GLINK is not set
CONFIG_RELAY=y
CONFIG_REMOTEPROC=y
# CONFIG_IPQ807X_REMOTEPROC is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_NET_L3_MASTER_DEV=y
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_PM8XXX is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
# CONFIG_SATA_AHCI is not set
CONFIG_SCHED_HRTICK=y
# CONFIG_SCSI is not set
# CONFIG_SCHED_INFO is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250 is not set
# CONFIG_SERIAL_8250_CONSOLE is not set
# CONFIG_SERIAL_8250_DMA is not set
# CONFIG_SERIAL_AMBA_PL010 is not set
# CONFIG_SERIAL_AMBA_PL011 is not set
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
# CONFIG_VIRTIO_CONSOLE is not set
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SND is not set
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
CONFIG_SND_PROC_FS=y
# CONFIG_SND_COMPRESS_OFFLOAD is not set
CONFIG_SND_PCM=y
CONFIG_SND_SOC=y
# CONFIG_SND_SOC_APQ8016_SBC is not set
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_IPQ is not set
# CONFIG_SND_SOC_IPQ806X_LPAIF is not set
# CONFIG_SND_SOC_IPQ806X_PCM_RAW is not set
CONFIG_SND_SOC_IPQ_ADSS=y
CONFIG_SND_SOC_IPQ_CODEC=y
CONFIG_SND_SOC_IPQ_CPU_DAI=y
CONFIG_SND_SOC_IPQ_MBOX=y
CONFIG_SND_SOC_IPQ_PCM_I2S=y
CONFIG_SND_SOC_IPQ_PCM_RAW=y
CONFIG_SND_SOC_IPQ_PCM_SPDIF=y
CONFIG_SND_SOC_IPQ_PCM_TDM=y
CONFIG_SND_SOC_IPQ_STEREO=y
CONFIG_SND_SOC_QCOM=y
# CONFIG_SND_SOC_STORM is not set
CONFIG_SOUND=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_QUP=y
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_VSC7385 is not set
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_SRCU=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_STOPWATCH is not set
CONFIG_SUSPEND=y
CONFIG_SWCONFIG=y
CONFIG_SWIOTLB=y
# CONFIG_SWAP is not set
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
# CONFIG_THUMB2_KERNEL is not set
# CONFIG_TICK_CPU_ACCOUNTING is not set
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_TRACING_EVENTS_GPIO=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_XZ=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_USB_GADGET=n
CONFIG_USB_SUPPORT=y
# CONFIG_USB_DWC3_OF_SIMPLE is not set
# CONFIG_USB_QCOM_8X16_PHY is not set
# CONFIG_USB_QCOM_KS_BRIDGE is not set
# CONFIG_USB_QCOM_QUSB_PHY is not set
# CONFIG_USB_QCOM_QMP_PHY is not set
# CONFIG_USB_QCA_M31_PHY is not set
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
CONFIG_USE_OF=y
CONFIG_VDSO=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WL_TI is not set
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XPS=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA_FLAG=0
CONFIG_QCOM_CACHE_DUMP=y
CONFIG_QCOM_CACHE_DUMP_ON_PANIC=y
# CONFIG_QCOM_RESTART_REASON is not set
# CONFIG_QCOM_DLOAD_MODE is not set
CONFIG_FW_AUTH=y
CONFIG_FW_AUTH_TEST=m
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_PUBLIC_KEY_ALGO_RSA=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=n
CONFIG_KEYS=y
# CONFIG_SKB_RECYCLER is not set
CONFIG_SKB_RECYCLER_MULTI_CPU=y
# CONFIG_SKB_RECYCLER_PREALLOC is not set
# CONFIG_U_SERIAL_CONSOLE is not set
CONFIG_SCSI_SCAN_ASYNC=y
# CONFIG_NF_IPV6_DUMMY_HEADER is not set
# CONFIG_RMNET is not set
# CONFIG_RMNET_DATA is not set
# CONFIG_RMNET_CTL is not set
# CONFIG_MSM_SECURE_BUFFER is not set
# CONFIG_STAGING is not set
# CONFIG_ANDROID is not set
# CONFIG_ION is not set
# CONFIG_ION_DUMMY is not set
# CONFIG_ION_MSM is not set
# CONFIG_ION_TEST is not set
# CONFIG_CMA is not set
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_DMA_CMA is not set
# CONFIG_CMA_AREAS is not set
# CONFIG_CMA_SIZE_MBYTES is not set
# CONFIG_CMA_SIZE_SEL_MBYTES is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
# CONFIG_CMA_ALIGNMENT is not set
# CONFIG_ASHMEM is not set
# CONFIG_ANDROID_TIMED_OUTPUT is not set
# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
# CONFIG_SYNC is not set
# CONFIG_SW_SYNC is not set
# CONFIG_FSL_MC_BUS is not set
# CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS is not set
CONFIG_ALLOC_SKB_PAGE_FRAG_DISABLE=y
# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set
# CONFIG_MAILBOX is not set
# CONFIG_MAILBOX_TEST is not set
# CONFIG_QCOM_APCS_IPC is not set
# CONFIG_QCOM_GLINK_SSR is not set
# CONFIG_QCOM_Q6V5_WCSS is not set
# CONFIG_QCOM_SYSMON is not set
# CONFIG_QRTR is not set
# CONFIG_QRTR_SMD is not set
# CONFIG_QRTR_TUN is not set
# CONFIG_RPMSG is not set
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_VIRTIO is not set
# CONFIG_RPMSG_CHAR is not set
# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set
# CONFIG_RPMSG_QCOM_SMD is not set
CONFIG_QCA_MINIDUMP=y
# CONFIG_QCA_MINIDUMP_DEBUG is not set
# CONFIG_QRTR_USB is not set
# CONFIG_QRTR_FIFO is not set
CONFIG_QRTR_MHI=y
CONFIG_MHI_BUS=y
# CONFIG_MHI_QTI is not set
# CONFIG_MHI_NETDEV is not set
# CONFIG_MHI_DEBUG is not set
# CONFIG_MHI_UCI is not set
# CONFIG_MHI_SATELLITE is not set
# CONFIG_DIAG_OVER_QRTR is not set
# CONFIG_MSM_ADSPRPC is not set
CONFIG_CRYPTO_MICHAEL_MIC=y
# CONFIG_ARCH_HAS_KCOV is not set
# CONFIG_KCOV is not set
# CONFIG_GCC_PLUGINS is not set
# CONFIG_QTI_Q6V5_ADSP is not set
# CONFIG_MSM_RPM_RPMSG is not set
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_REGULATOR_RPM_GLINK is not set
# CONFIG_MTD_NAND_SERIAL is not set
# CONFIG_ARM_QTI_IPQ60XX_CPUFREQ is not set
# CONFIG_PAGE_SCOPE_MULTI_PAGE_READ is not set
# CONFIG_CRYPTO_NO_ZERO_LEN_HASH is not set
# CONFIG_CRYPTO_DISABLE_AES192_TEST is not set
# CONFIG_QTI_EUD is not set
# CONFIG_EUD_EXTCON_SUPPORT is not set
# CONFIG_CLK_TEST_5018 is not set
CONFIG_MAP_E_SUPPORT=y
# CONFIG_IPQ_FLASH_16M_PROFILE is not set
# CONFIG_QGIC2_MSI is not set
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_LEDS_GPIO=y
# CONFIG_ARCH_IPQ256M is not set
CONFIG_SKB_FIXED_SIZE_2K=y
# CONFIG_IPQ_MEM_PROFILE is not set
# CONFIG_VIRTIO_NET is not set
# CONFIG_QCA_85XX_SWITCH is not set
CONFIG_AQ_PHY=y
CONFIG_DIAG_CHAR=y
# CONFIG_HW_RANDOM_VIRTIO is not set
# CONFIG_CRYPTO_DEV_QCEDEV is not set
# CONFIG_CRYPTO_DEV_QCRYPTO is not set
# CONFIG_MHI_BUS_TEST is not set
# CONFIG_NF_CONNTRACK_RTCACHE is not set
# CONFIG_NF_LOG_IPV6 is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y

4794
feeds/ipq807x/ipq807x/config-4.4-qsdk
View File

File diff suppressed because it is too large Load Diff

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-cig-wf186h.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186h.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-cig-wf186w.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186w.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-eap104.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-eap104.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-eww622-a1.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-eww622-a1.dts"
/ {
model = "CyberTan EWW622-A1";
compatible = "cybertan,eww622-a1", "qcom,ipq5018";
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

10
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-eww631-a1.dts
View File

@@ -1,10 +0,0 @@
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-eww631-a1.dts"
/ {
model = "CyberTan EWW631-A1";
compatible = "cybertan,eww631-a1", "qcom,ipq5018";
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

10
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-eww631-b1.dts
View File

@@ -1,10 +0,0 @@
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-eww631-b1.dts"
/ {
model = "CyberTan EWW631-B1";
compatible = "cybertan,eww631-b1", "qcom,ipq5018";
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-hfcl-ion4x_w.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4x_w.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-hfcl-ion4xi_HMR.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4xi_HMR.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-hfcl-ion4xi_w.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4xi_w.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-liteon-wpx8324.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-liteon-wpx8324.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-muxi-ap3220l.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-muxi-ap3220l.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-optimcloud-d50-5g.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-optimcloud-d50-5g.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-optimcloud-d50.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-optimcloud-d50.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-optimcloud-d60-5g.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-optimcloud-d50-5g.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-optimcloud-d60.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-optimcloud-d50.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-q14.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-q14.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

10
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-wallys-dr5018.dts
View File

@@ -1,10 +0,0 @@
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-wallys-dr5018.dts"
/ {
model = "Wallys DR5018";
compatible = "wallys,dr5018", "qcom,ipq5018";
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

23
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-yuncore-fap655.dts
View File

@@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq5018-yuncore-fap655.dts"
/ {
pmuv8: pmu {
compatible = "arm,cortex-a7-pmu";
};
};

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-cig-wf188.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-cig-wf188.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-cig-wf188n.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-cig-wf188n.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-cig-wf660a.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-cig-wf660a.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-edgecore-eap101.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-edgecore-eap101.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-gl-ax1800.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-gl-axt1800.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-gl-axt1800.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4x.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4x.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4x_2.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4x_2.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4xe.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4xe.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4xi.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4xi.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4xi_wp.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4xi_wp.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-indio-um-310ax-v1.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-indio-um-310ax-v1.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-indio-um-510axm-v1.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-indio-um-510axm-v1.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-indio-um-510axp-v1.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-indio-um-510axp-v1.dts"
#include "qcom-ipq6018.dtsi"

2
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-meshpp-s618-cp01.dts
View File

@@ -1,2 +0,0 @@
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-meshpp-s618-cp01.dts"
#include "qcom-ipq6018.dtsi"

2
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-meshpp-s618-cp03.dts
View File

@@ -1,2 +0,0 @@
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-meshpp-s618-cp03.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-pax1800-v1.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-pax1800-v1.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-pax1800-v2.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-pax1800-v2.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-wallys-dr6018-v4.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-wallys-dr6018-v4.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-wallys-dr6018.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-wallys-dr6018.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-yuncore-ax840.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-yuncore-ax840.dts"
#include "qcom-ipq6018.dtsi"

18
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-yuncore-fap650.dts
View File

@@ -1,18 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-yuncore-fap650.dts"
#include "qcom-ipq6018.dtsi"

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-eap102.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-eap106.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-eap106.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-ex227.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-ex227.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-ex447.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-ex447.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-oap102.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-oap102.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf194c.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf194c.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf194c4.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf194c4.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

26
feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf196.dts
View File

@@ -1,26 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf196.dts"
/ {
soc {
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
};

1441
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-hfcl-ion4xi_HMR.dtsi
View File

File diff suppressed because it is too large Load Diff

1007
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186h.dts
View File

File diff suppressed because it is too large Load Diff

1007
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186w.dts
View File

File diff suppressed because it is too large Load Diff

1030
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eap104.dts
View File

File diff suppressed because it is too large Load Diff

901
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eww622-a1.dts
View File

@@ -1,901 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.1";
compatible = "qcom,ipq5018-mp03.1", "qcom,ipq5018";
interrupt-parent = <&intc>;
#ifdef __IPQ_MEM_PROFILE_256_MB__
AUTO_MOUNT;
#endif
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 8MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x40800000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* + | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 23MB |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C700000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4C900000 | 17MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4DA00000 | 16MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01700000>;
};
m3_dump@4c700000 {
no-map;
reg = <0x0 0x4C700000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
qcn9000_pcie0@4c900000 {
no-map;
reg = <0x0 0x4C900000 0x0 0x01100000>;
};
mhi_region1: dma_pool1@4da00000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4da00000 0x0 0x01000000>;
};
#elif __IPQ_MEM_PROFILE_512_MB__
/* 512 MB Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 16MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x41000000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 24MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C900000 | 1MB |
* +--------+--------------+-------------------------+
* | caldb | 0x4CA00000 | 2MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4CC00000 | 30MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4EA00000 | 16MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01800000>;
};
m3_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c900000 {
no-map;
reg = <0x0 0x4c900000 0x0 0x100000>;
};
q6_caldb_region:q6_caldb_region@4ca00000 {
no-map;
reg = <0x0 0x4ca00000 0x0 0x200000>;
};
qcn9000_pcie0@4cc00000 {
no-map;
reg = <0x0 0x4CC00000 0x0 0x01E00000>;
};
mhi_region1: dma_pool1@4ea00000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4ea00000 0x0 0x01000000>;
};
#else
/* 1G Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 16MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x41000000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 24MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C900000 | 1MB |
* +--------+--------------+-------------------------+
* | caldb | 0x4CA00000 | 2MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4CC00000 | 45MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4F900000 | 24MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01800000>;
};
m3_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c900000 {
no-map;
reg = <0x0 0x4c900000 0x0 0x100000>;
};
q6_caldb_region:q6_caldb_region@4ca00000 {
no-map;
reg = <0x0 0x4ca00000 0x0 0x200000>;
};
qcn9000_pcie0@4cc00000 {
no-map;
reg = <0x0 0x4CC00000 0x0 0x02D00000>;
};
mhi_region1: dma_pool1@4F900000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4F900000 0x0 0x01800000>;
};
#endif
};
soc {
serial@78af000 {
status = "ok";
};
blsp1_uart2: serial@78b0000 {
pinctrl-0 = <&blsp1_uart_pins>;
pinctrl-names = "default";
};
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "ok";
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 39 0>;
ethernet-phy@0 {
reg = <0>;
};
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
ethernet-phy@4 {
reg = <4>;
};
};
ess-instance {
num_devices = <0x2>;
ess-switch@0x39c00000 {
compatible = "qcom,ess-switch-ipq50xx";
device_id = <0>;
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
};
port@1 {
port_id = <2>;
forced-speed = <1000>;
forced-duplex = <1>;
};
};
led_source@0 {
source = <2>;
mode = "normal";
speed = "1000M";
blink_en = "enable";
active = "high";
};
led_source@1 {
source = <0>;
mode = "normal";
speed = "100M";
blink_en = "enable";
active = "high";
};
};
ess-switch1@1 {
compatible = "qcom,ess-switch-qca83xx";
device_id = <1>;
switch_access_mode = "mdio";
mdio-bus = <&mdio1>;
reset_gpio = <0x27>;
switch_cpu_bmp = <0x40>; /* cpu port bitmap */
switch_lan_bmp = <0x3c>; /* lan port bitmap */
switch_wan_bmp = <0x0>; /* wan port bitmap */
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x00010 0x2613a0 /* PORT6 FORCE MODE*/
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
};
};
wifi0: wifi@c000000 {
qcom,bdf-addr = <0x4BA00000 0x4BA00000 0x4BA00000
0x0 0x0>;
qcom,caldb-addr = <0x4CA00000 0x4CA00000 0x4CA00000
0x0 0x0>;
qcom,caldb-size = <0x200000>;
status = "ok";
};
ess-uniphy@98000 {
status = "disabled";
};
qcom,sps {
status = "ok";
};
qcom,usbbam@8B04000 {
status = "ok";
};
qcom,diag@0 {
status = "ok";
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
rpm_etm0 {
status = "disabled";
};
};
thermal-zones {
status = "ok";
};
};
&tlmm {
pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>;
pinctrl-names = "default";
blsp0_uart_pins: blsp0_uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
blsp1_uart_pins: blsp1_uart_pins {
blsp1_uart_rx_tx {
pins = "gpio23", "gpio25", "gpio24", "gpio26";
function = "blsp1_uart2";
bias-disable;
};
};
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
phy_led_pins: phy_led_pins {
gephy_led_pin_1g {
pins = "gpio30";
function = "led2";
drive-strength = <8>;
bias-pull-down;
};
gephy_led_pin_100 {
pins = "gpio46";
function = "led0";
drive-strength = <8>;
bias-pull-down;
};
};
i2c_pins: i2c_pins {
i2c_scl {
pins = "gpio25";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
i2c_sda {
pins = "gpio26";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
};
button_pins: button_pins {
wps_button {
pins = "gpio27";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
reset_button {
pins = "gpio28";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds_pinmux {
sys_blue {
pins = "gpio1";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
sys_green {
pins = "gpio35";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
sys_red {
pins = "gpio31";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button@1 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
button@2 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_sys: led@1 {
label = "sys:blue";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>; /* GPIO_1 */
default-state="on";
};
led@35 {
label = "sys:green";
gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; /* GPIO_35 */
default-state="off";
};
led@31 {
label = "sys:red";
gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; /* GPIO_31 */
default-state="off";
};
};
};
&usb3 {
qcom,multiplexed-phy;
qcom,phy-mux-regs = <&tcsr_q6_block 0x2540>;
device-power-gpio = <&tlmm 24 1>;
status = "ok";
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "ok";
perst-gpio = <&tlmm 15 1>;
};
&bt {
status = "ok";
};
&wcss {
status = "ok";
};
&q6v5_wcss {
status = "disabled";
};
&q6v5_m3 {
status = "disabled";
};
&tcsr_mutex_block {
status = "ok";
};
&tcsr_mutex {
status = "ok";
};
&smem {
status = "ok";
};
&apcs_glb {
status = "ok";
};
&tcsr_q6_block {
status = "ok";
};
&qcom_q6v5_wcss {
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_region>, <&q6_etr_region>;
#else
memory-region = <&q6_region>, <&q6_etr_region>,
<&q6_caldb_region>;
#endif
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
};
};
&i2c_0 {
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
status = "disabled";
};
&dbm_1p5 {
status = "ok";
};
&msm_imem {
status = "ok";
};
&blsp1_uart1 {
status = "ok";
};
&ssuniphy_0 {
status = "ok";
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "ok";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "ok";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
qrtr_instance_id = <0x20>;
#address-cells = <0x2>;
#size-cells = <0x2>;
memory-region = <&mhi_region1>;
#if !defined(__CNSS2__)
base-addr = <0x4CC00000>;
m3-dump-addr = <0x4E000000>;
etr-addr = <0x4E100000>;
qcom,caldb-addr = <0x4E200000>;
qcom,tgt-mem-mode = <0x1>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
#endif
};
};
&wifi0 {
/* IPQ5018 */
qcom,board_id = <0x24>;
status = "ok";
};
&wifi3 {
/* QCN9000 5G */
board_id = <0xa0>;
status = "ok";
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};

908
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eww631-a1.dts
View File

@@ -1,908 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.5-C1";
compatible = "qcom,ipq5018-mp03.5-c1", "qcom,ipq5018";
interrupt-parent = <&intc>;
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 8MB |
* +----------+--------------+-------------------------+
* | Linux | 0x40800000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 13MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D100000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D300000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4E400000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4F300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4F400000 | 1MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x4500000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x1400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xD00000>;
};
m3_dump: m3_dump@4D100000 {
no-map;
reg = <0x0 0x4D100000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0xF00000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
no-map;
reg = <0x0 0x4E200000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
no-map;
reg = <0x0 0x4E300000 0x0 0x100000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E400000 {
no-map;
reg = <0x0 0x4E400000 0x0 0xF00000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4F300000 {
no-map;
reg = <0x0 0x4F300000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F400000 {
no-map;
reg = <0x0 0x4F400000 0x0 0x100000>;
};
#else
/* 512MB/1GB Profiles
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 16MB |
* +----------+--------------+-------------------------+
* | Linux | 0x41000000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 14MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D300000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | Caldb | 0x4D400000 | 2MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D600000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E600000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E700000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | Caldb | 0x4E800000 | 5MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4ED00000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4FD00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4FE00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | Caldb | 0x4FF00000 | 5MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x5400000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 01400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xE00000>;
};
m3_dump: m3_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0x100000>;
};
q6_caldb_region: q6_caldb_region@4D400000 {
no-map;
reg = <0x0 0x4D400000 0x0 0x200000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D600000 {
no-map;
reg = <0x0 0x4D600000 0x0 0x1000000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E600000 {
no-map;
reg = <0x0 0x4E600000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E700000 {
no-map;
reg = <0x0 0x4E700000 0x0 0x100000>;
};
q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E800000 {
no-map;
reg = <0x0 0x4E800000 0x0 0x500000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E900000 {
no-map;
reg = <0x0 0x4ED00000 0x0 0x1000000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4FD00000 {
no-map;
reg = <0x0 0x4FD00000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4FE00000 {
no-map;
reg = <0x0 0x4FE00000 0x0 0x100000>;
};
q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4FF00000 {
no-map;
reg = <0x0 0x4FF00000 0x0 0x500000>;
};
#endif
};
soc {
serial@78af000 {
status = "ok";
};
blsp1_uart2: serial@78b0000 {
pinctrl-0 = <&blsp1_uart_pins>;
pinctrl-names = "default";
};
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "disabled";
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 39 0>;
ethernet-phy@0 {
reg = <28>;
};
};
ess-instance {
num_devices = <0x1>;
ess-switch@0x39c00000 {
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
mdiobus = <&mdio0>;
};
/*
port@1 {
port_id = <2>;
phy_address = <0x1c>;
mdiobus = <&mdio1>;
port_mac_sel = "QGMAC_PORT";
};
*/
};
led_source@0 {
source = <0>;
mode = "normal";
speed = "all";
blink_en = "enable";
active = "high";
};
};
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
/*
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <28>;
mdio-bus = <&mdio1>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
*/
qcom,test@0 {
status = "ok";
};
lpass: lpass@0xA000000{
status = "disabled";
};
pcm: pcm@0xA3C0000{
pinctrl-0 = <&audio_pins>;
pinctrl-names = "default";
status = "disabled";
};
pcm_lb: pcm_lb@0 {
status = "disabled";
};
};
thermal-zones {
status = "ok";
};
};
&tlmm {
pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>;
pinctrl-names = "default";
blsp0_uart_pins: blsp0_uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
blsp1_uart_pins: blsp1_uart_pins {
blsp1_uart_rx_tx {
pins = "gpio23", "gpio25", "gpio24", "gpio26";
function = "blsp1_uart2";
bias-disable;
};
};
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
phy_led_pins: phy_led_pins {
gephy_led_pin {
pins = "gpio46";
function = "led0";
drive-strength = <8>;
bias-pull-down;
};
};
i2c_pins: i2c_pins {
i2c_scl {
pins = "gpio25";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
i2c_sda {
pins = "gpio26";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio28";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
audio_pins: audio_pinmux {
mux_1 {
pins = "gpio24";
function = "audio_rxbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_2 {
pins = "gpio25";
function = "audio_rxfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_3 {
pins = "gpio26";
function = "audio_rxd";
drive-strength = <8>;
bias-pull-down;
};
mux_4 {
pins = "gpio27";
function = "audio_txmclk";
drive-strength = <8>;
bias-pull-down;
};
mux_5 {
pins = "gpio28";
function = "audio_txbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_6 {
pins = "gpio29";
function = "audio_txfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_7 {
pins = "gpio30";
function = "audio_txd";
drive-strength = <8>;
bias-pull-down;
};
};
leds_pins: leds_pinmux {
sys_blue {
pins = "gpio30";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
sys_red {
pins = "gpio36";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
sys_green {
pins = "gpio37";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button@1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led@30 {
label = "sys:blue";
gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; /* GPIO_30 */
default-state="on";
/* linux,default-trigger = "timer";
active-delay = <700>;
inactive-delay = <700>;
default-state="on"; */
};
led@36 {
label = "sys:red";
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; /* GPIO_36 */
default-state="off";
/* linux,default-trigger = "timer";
active-delay = <700>;
inactive-delay = <700>;
default-state="on"; */
};
led@37 {
label = "sys:green";
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; /* GPIO_37 */
default-state="off";
/* linux,default-trigger = "timer";
active-delay = <700>;
inactive-delay = <700>;
default-state="on"; */
};
};
};
&usb3 {
status = "disabled";
device-power-gpio = <&tlmm 24 1>;
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "disabled";
perst-gpio = <&tlmm 15 1>;
};
&bt {
status = "ok";
};
&dwc_0 {
/delete-property/ #phy-cells;
/delete-property/ phys;
/delete-property/ phy-names;
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "disabled";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "disabled";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
};
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};
&qcom_q6v5_wcss {
qcom,multipd_arch;
memory-region = <&q6_mem_regions>;
qcom,share_bootargs;
qcom,bootargs_smem = <507>;
boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
<0x2 0x4 0x2 0x12 0x0 0x0>;
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>;
#else
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>, <&q6_caldb_region>;
#endif
};
/* QCN6122 6G */
q6v5_wcss_userpd2 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 16 0>,
<&wcss_smp2p_in 17 0>,
<&wcss_smp2p_in 20 0>,
<&wcss_smp2p_in 19 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 16>,
<&wcss_smp2p_out 17>,
<&wcss_smp2p_out 18>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <2>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>;
#else
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
#endif
};
/* QCN6122 5G */
q6v5_wcss_userpd3 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 24 0>,
<&wcss_smp2p_in 25 0>,
<&wcss_smp2p_in 28 0>,
<&wcss_smp2p_in 27 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 24>,
<&wcss_smp2p_out 25>,
<&wcss_smp2p_out 26>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <3>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>;
#else
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
#endif
};
};
&i2c_0 {
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
status = "disabled";
};
&qgic_msi_0 {
status = "ok";
};
&qgic_msi_1 {
status = "ok";
};
&wifi0 {
/* IPQ5018 */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x24>;
qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
#else
qcom,caldb-addr = <0x4D400000>;
m3-dump-addr = <0x4D200000>;
#endif
qcom,caldb-size = <0x200000>;
status = "ok";
};
&wifi1 {
/* QCN6122 6G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x60>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "ok";
};
&wifi2 {
/* QCN6122 6G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0xb0>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "disabled";
};

971
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eww631-b1.dts
View File

@@ -1,971 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.5-C1";
compatible = "qcom,ipq5018-mp03.5-c1", "qcom,ipq5018";
interrupt-parent = <&intc>;
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 8MB |
* +----------+--------------+-------------------------+
* | Linux | 0x40800000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 13MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D100000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D300000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4E400000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4F300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4F400000 | 1MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x4500000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x1400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xD00000>;
};
m3_dump: m3_dump@4D100000 {
no-map;
reg = <0x0 0x4D100000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0xF00000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
no-map;
reg = <0x0 0x4E200000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
no-map;
reg = <0x0 0x4E300000 0x0 0x100000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E400000 {
no-map;
reg = <0x0 0x4E400000 0x0 0xF00000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4F300000 {
no-map;
reg = <0x0 0x4F300000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F400000 {
no-map;
reg = <0x0 0x4F400000 0x0 0x100000>;
};
#else
/* 512MB/1GB Profiles
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 16MB |
* +----------+--------------+-------------------------+
* | Linux | 0x41000000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 14MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D300000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | Caldb | 0x4D400000 | 2MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D600000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E600000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E700000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | Caldb | 0x4E800000 | 5MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4ED00000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4FD00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4FE00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | Caldb | 0x4FF00000 | 5MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x5400000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 01400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xE00000>;
};
m3_dump: m3_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0x100000>;
};
q6_caldb_region: q6_caldb_region@4D400000 {
no-map;
reg = <0x0 0x4D400000 0x0 0x200000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D600000 {
no-map;
reg = <0x0 0x4D600000 0x0 0x1000000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E600000 {
no-map;
reg = <0x0 0x4E600000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E700000 {
no-map;
reg = <0x0 0x4E700000 0x0 0x100000>;
};
q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E800000 {
no-map;
reg = <0x0 0x4E800000 0x0 0x500000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E900000 {
no-map;
reg = <0x0 0x4ED00000 0x0 0x1000000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4FD00000 {
no-map;
reg = <0x0 0x4FD00000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4FE00000 {
no-map;
reg = <0x0 0x4FE00000 0x0 0x100000>;
};
q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4FF00000 {
no-map;
reg = <0x0 0x4FF00000 0x0 0x500000>;
};
#endif
};
soc {
serial@78af000 {
status = "ok";
};
/*
blsp1_uart2: serial@78b0000 {
pinctrl-0 = <&blsp1_uart_pins>;
pinctrl-names = "default";
};
*/
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "ok";
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 38 0>;
ethernet-phy@0 {
reg = <0>;
};
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
ethernet-phy@4 {
reg = <4>;
};
};
ess-instance {
num_devices = <0x2>;
ess-switch@0x39c00000 {
compatible = "qcom,ess-switch-ipq50xx";
device_id = <0>;
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
};
port@1 {
port_id = <2>;
forced-speed = <1000>;
forced-duplex = <1>;
};
};
led_source@0 {
source = <0>;
mode = "normal";
speed = "all";
blink_en = "enable";
active = "high";
};
};
ess-switch1@1 {
compatible = "qcom,ess-switch-qca83xx";
device_id = <1>;
switch_access_mode = "mdio";
mdio-bus = <&mdio1>;
reset_gpio = <0x26>;
switch_cpu_bmp = <0x40>; /* cpu port bitmap (Port 6 GMAC) */
switch_lan_bmp = <0x3c>; /* lan port bitmap */
switch_wan_bmp = <0x0>; /* wan port bitmap */
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x00010 0x2613a0 /* PORT6 FORCE MODE*/
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
};
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
qcom,test@0 {
status = "ok";
};
/*
lpass: lpass@0xA000000{
status = "disabled";
};
pcm: pcm@0xA3C0000{
pinctrl-0 = <&audio_pins>;
pinctrl-names = "default";
status = "disabled";
};
pcm_lb: pcm_lb@0 {
status = "disabled";
};
*/
};
thermal-zones {
status = "ok";
};
};
&tlmm {
pinctrl-0 = <&blsp0_uart_pins>; //<&blsp0_uart_pins &phy_led_pins>;
pinctrl-names = "default";
blsp0_uart_pins: blsp0_uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
/*
blsp1_uart_pins: blsp1_uart_pins {
blsp1_uart_rx_tx {
pins = "gpio23", "gpio25", "gpio24", "gpio26";
function = "blsp1_uart2";
bias-disable;
};
};
*/
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
/*
phy_led_pins: phy_led_pins {
gephy_led_pin {
pins = "gpio46";
function = "led0";
drive-strength = <8>;
bias-pull-down;
};
};
*/
i2c_pins: i2c_pins {
i2c_scl {
pins = "gpio25";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
i2c_sda {
pins = "gpio26";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio28";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
/*
audio_pins: audio_pinmux {
mux_1 {
pins = "gpio24";
function = "audio_rxbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_2 {
pins = "gpio25";
function = "audio_rxfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_3 {
pins = "gpio26";
function = "audio_rxd";
drive-strength = <8>;
bias-pull-down;
};
mux_4 {
pins = "gpio27";
function = "audio_txmclk";
drive-strength = <8>;
bias-pull-down;
};
mux_5 {
pins = "gpio28";
function = "audio_txbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_6 {
pins = "gpio29";
function = "audio_txfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_7 {
pins = "gpio30";
function = "audio_txd";
drive-strength = <8>;
bias-pull-down;
};
};
*/
poe_pins: poe_pinmux {
/*
LAN port PoE output enable
H --> enable; L --> disable (Default setting to H)
*/
mux_0 { /* PoE_OUT_EN */
pins = "gpio24";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
output-high;
};
mux_1 { /* PSE_INT_N */
pins = "gpio27";
function = "gpio";
bias-pull-up;
input;
};
};
leds_pins: leds_pinmux {
sys_green {
pins = "gpio1";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
sys_blue {
pins = "gpio30";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
sys_red {
pins = "gpio46";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button@1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led@1 {
label = "sys:green";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>; /* GPIO_1/ATST_QP0 */
default-state="off";
};
led@30 {
label = "sys:blue";
gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; /* GPIO_30 */
default-state="on";
};
led@46 {
label = "sys:red";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>; /* GPIO_46 */
default-state="off";
};
};
};
&usb3 {
status = "disabled";
device-power-gpio = <&tlmm 24 1>;
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "disabled";
perst-gpio = <&tlmm 15 1>;
};
&bt {
status = "disabled";
};
&dwc_0 {
/delete-property/ #phy-cells;
/delete-property/ phys;
/delete-property/ phy-names;
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "disabled";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "disabled";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
};
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};
&qcom_q6v5_wcss {
qcom,multipd_arch;
memory-region = <&q6_mem_regions>;
qcom,share_bootargs;
qcom,bootargs_smem = <507>;
boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
<0x2 0x4 0x2 0x12 0x0 0x0>;
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>;
#else
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>, <&q6_caldb_region>;
#endif
};
/* QCN6122 6G */
q6v5_wcss_userpd2 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 16 0>,
<&wcss_smp2p_in 17 0>,
<&wcss_smp2p_in 20 0>,
<&wcss_smp2p_in 19 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 16>,
<&wcss_smp2p_out 17>,
<&wcss_smp2p_out 18>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <2>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>;
#else
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
#endif
};
/* QCN6122 5G */
q6v5_wcss_userpd3 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 24 0>,
<&wcss_smp2p_in 25 0>,
<&wcss_smp2p_in 28 0>,
<&wcss_smp2p_in 27 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 24>,
<&wcss_smp2p_out 25>,
<&wcss_smp2p_out 26>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <3>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>;
#else
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
#endif
};
};
&i2c_0 {
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
status = "ok";
};
&qgic_msi_0 {
status = "ok";
};
&qgic_msi_1 {
status = "ok";
};
&wifi0 {
/* IPQ5018 */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x24>;
qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
#else
qcom,caldb-addr = <0x4D400000>;
m3-dump-addr = <0x4D200000>;
#endif
qcom,caldb-size = <0x200000>;
status = "ok";
};
&wifi1 {
/* QCN6122 6G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x60>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "ok";
};
&wifi2 {
/* QCN6122 6G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0xb0>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "disabled";
};

1063
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4x_w.dts
View File

File diff suppressed because it is too large Load Diff

1059
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4xi_HMR.dts
View File

File diff suppressed because it is too large Load Diff

1063
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4xi_w.dts
View File

File diff suppressed because it is too large Load Diff

1441
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-hfcl-ion4xi_w.dtsi
View File

File diff suppressed because it is too large Load Diff

812
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-liteon-wpx8324.dts
View File

@@ -1,812 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Liteon WPX8324";
compatible = "liteon,wpx8324", "qcom,ipq5018-mp03.5-c1", "qcom,ipq5018";
interrupt-parent = <&intc>;
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart1;
/*serial1 = &blsp1_uart2;*/
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 8MB |
* +----------+--------------+-------------------------+
* | Linux | 0x40800000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 13MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D100000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D300000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4E400000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4F300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4F400000 | 1MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x4500000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x1400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xD00000>;
};
m3_dump: m3_dump@4D100000 {
no-map;
reg = <0x0 0x4D100000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0xF00000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
no-map;
reg = <0x0 0x4E200000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
no-map;
reg = <0x0 0x4E300000 0x0 0x100000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E400000 {
no-map;
reg = <0x0 0x4E400000 0x0 0xF00000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4F300000 {
no-map;
reg = <0x0 0x4F300000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F400000 {
no-map;
reg = <0x0 0x4F400000 0x0 0x100000>;
};
#else
/* 512MB/1GB Profiles
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 16MB |
* +----------+--------------+-------------------------+
* | Linux | 0x41000000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 14MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D300000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | Caldb | 0x4D400000 | 2MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D600000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E600000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E700000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | Caldb | 0x4E800000 | 5MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4ED00000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4FD00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4FE00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | Caldb | 0x4FF00000 | 5MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x5400000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 01400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xE00000>;
};
m3_dump: m3_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0x100000>;
};
q6_caldb_region: q6_caldb_region@4D400000 {
no-map;
reg = <0x0 0x4D400000 0x0 0x200000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D600000 {
no-map;
reg = <0x0 0x4D600000 0x0 0x1000000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E600000 {
no-map;
reg = <0x0 0x4E600000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E700000 {
no-map;
reg = <0x0 0x4E700000 0x0 0x100000>;
};
q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E800000 {
no-map;
reg = <0x0 0x4E800000 0x0 0x500000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E900000 {
no-map;
reg = <0x0 0x4ED00000 0x0 0x1000000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4FD00000 {
no-map;
reg = <0x0 0x4FD00000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4FE00000 {
no-map;
reg = <0x0 0x4FE00000 0x0 0x100000>;
};
q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4FF00000 {
no-map;
reg = <0x0 0x4FF00000 0x0 0x500000>;
};
#endif
};
soc {
serial@78af000 {
status = "ok";
};
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
spi_2: spi@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&blsp2_spi0_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
tpm0: slb9670@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <1>; /* CE1 */
compatible = "infineon,slb9670";
linux,modalias = "slb9670", "slb9670a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "ok";
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 26 0>;
ethernet-phy@0 {
reg = <28>;
};
};
ess-instance {
num_devices = <0x1>;
ess-switch@0x39c00000 {
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
mdiobus = <&mdio0>;
};
port@1 {
port_id = <2>;
phy_address = <0x1c>;
mdiobus = <&mdio1>;
port_mac_sel = "QGMAC_PORT";
};
};
led_source@0 {
source = <0>;
mode = "normal";
speed = "all";
blink_en = "enable";
active = "high";
};
};
};
wifi0: wifi@c000000 {
status = "ok";
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <28>;
mdio-bus = <&mdio1>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
qcom,test@0 {
status = "ok";
};
};
thermal-zones {
status = "ok";
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_blue: led@19 {
label = "blue:uplink";
gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_orange: led@18 {
label = "orange:wifi2";
gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_green: led@39 {
label = "green:wifi5";
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
};
&tlmm {
pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>;
pinctrl-names = "default";
leds_pins: leds_pins {
led_blue {
pins = "gpio19";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_orange {
pins = "gpio18";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_green {
pins = "gpio39";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
blsp0_uart_pins: uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
blsp2_spi0_pins: blsp2_spi0_pins {
mux {
pins = "gpio31", "gpio32", "gpio33", "gpio34";
function = "blsp2_spi0";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
phy_led_pins: phy_led_pins {
gephy_led_pin {
pins = "gpio18", "gpio19", "gpio39";
/* function = "led0"; */
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
i2c_pins: i2c_pins {
i2c_scl {
pins = "gpio25";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
i2c_sda {
pins = "gpio26";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
};
button_pins: button_pins {
wps_button {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button@1 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
};
&usb3 {
status = "ok";
device-power-gpio = <&tlmm 28 0>;
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "disabled";
perst-gpio = <&tlmm 15 1>;
};
&dwc_0 {
/delete-property/ #phy-cells;
/delete-property/ phys;
/delete-property/ phy-names;
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "disabled";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "disabled";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
};
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};
&qcom_q6v5_wcss {
qcom,multipd_arch;
memory-region = <&q6_mem_regions>;
qcom,share_bootargs;
qcom,bootargs_smem = <507>;
boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
<0x2 0x4 0x2 0x12 0x0 0x0>;
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>;
#else
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>, <&q6_caldb_region>;
#endif
};
/* QCN6122 6G */
q6v5_wcss_userpd2 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 16 0>,
<&wcss_smp2p_in 17 0>,
<&wcss_smp2p_in 20 0>,
<&wcss_smp2p_in 19 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 16>,
<&wcss_smp2p_out 17>,
<&wcss_smp2p_out 18>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <2>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>;
#else
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
#endif
};
/* QCN6122 5G */
q6v5_wcss_userpd3 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 24 0>,
<&wcss_smp2p_in 25 0>,
<&wcss_smp2p_in 28 0>,
<&wcss_smp2p_in 27 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 24>,
<&wcss_smp2p_out 25>,
<&wcss_smp2p_out 26>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <3>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>;
#else
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
#endif
};
};
&qgic_msi_0 {
status = "ok";
};
&qgic_msi_1 {
status = "ok";
};
&wifi0 {
/* IPQ5018 */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x24>;
qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
#else
qcom,caldb-addr = <0x4D400000>;
m3-dump-addr = <0x4D200000>;
#endif
qcom,caldb-size = <0x200000>;
status = "ok";
};
&wifi1 {
/* QCN6122 5G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x60>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "ok";
};

891
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-muxi-ap3220l.dts
View File

@@ -1,891 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "MUXI AP3220L";
compatible = "muxi,ap3220l", "qcom,ipq5018-mp03.5-c1", "qcom,ipq5018";
interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 8MB |
* +----------+--------------+-------------------------+
* | Linux | 0x40800000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 13MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D100000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D300000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E200000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4E400000 | 15MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4F300000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4F400000 | 1MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x4500000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x1400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xD00000>;
};
m3_dump: m3_dump@4D100000 {
no-map;
reg = <0x0 0x4D100000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0xF00000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
no-map;
reg = <0x0 0x4E200000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
no-map;
reg = <0x0 0x4E300000 0x0 0x100000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E400000 {
no-map;
reg = <0x0 0x4E400000 0x0 0xF00000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4F300000 {
no-map;
reg = <0x0 0x4F300000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F400000 {
no-map;
reg = <0x0 0x4F400000 0x0 0x100000>;
};
#else
/* 512MB/1GB Profiles
* +==========+==============+=========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +----------+--------------+-------------------------+
* | NSS | 0x40000000 | 16MB |
* +----------+--------------+-------------------------+
* | Linux | 0x41000000 | Depends on total memory |
* +----------+--------------+-------------------------+
* | uboot | 0x4A600000 | 4MB |
* +----------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +----------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +----------+--------------+-------------------------+
* | TZ | 0x4AC00000 | 4MB |
* +----------+--------------+-------------------------+
* | Q6 | | |
* | code/ | 0x4B000000 | 20MB |
* | data | | |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | data | 0x4C400000 | 14MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | M3 Dump | 0x4D200000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | QDSS | 0x4D300000 | 1MB |
* +----------+--------------+-------------------------+
* | IPQ5018 | | |
* | Caldb | 0x4D400000 | 2MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | data | 0x4D600000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | M3 Dump | 0x4E600000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | QDSS | 0x4E700000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_1| | |
* | Caldb | 0x4E800000 | 5MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | data | 0x4ED00000 | 16MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | M3 Dump | 0x4FD00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | QDSS | 0x4FE00000 | 1MB |
* +----------+--------------+-------------------------+
* | QCN6122_2| | |
* | Caldb | 0x4FF00000 | 5MB |
* +----------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +===================================================+
*/
q6_mem_regions: q6_mem_regions@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 0x5400000>;
};
q6_code_data: q6_code_data@4B000000 {
no-map;
reg = <0x0 0x4B000000 0x0 01400000>;
};
q6_ipq5018_data: q6_ipq5018_data@4C400000 {
no-map;
reg = <0x0 0x4C400000 0x0 0xE00000>;
};
m3_dump: m3_dump@4D200000 {
no-map;
reg = <0x0 0x4D200000 0x0 0x100000>;
};
q6_etr_region: q6_etr_dump@4D300000 {
no-map;
reg = <0x0 0x4D300000 0x0 0x100000>;
};
q6_caldb_region: q6_caldb_region@4D400000 {
no-map;
reg = <0x0 0x4D400000 0x0 0x200000>;
};
q6_qcn6122_data1: q6_qcn6122_data1@4D600000 {
no-map;
reg = <0x0 0x4D600000 0x0 0x1000000>;
};
m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E600000 {
no-map;
reg = <0x0 0x4E600000 0x0 0x100000>;
};
q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E700000 {
no-map;
reg = <0x0 0x4E700000 0x0 0x100000>;
};
q6_qcn6122_caldb_1: q6_qcn6122_caldb_1@4E800000 {
no-map;
reg = <0x0 0x4E800000 0x0 0x500000>;
};
q6_qcn6122_data2: q6_qcn6122_data2@4E900000 {
no-map;
reg = <0x0 0x4ED00000 0x0 0x1000000>;
};
m3_dump_qcn6122_2: m3_dump_qcn6122_2@4FD00000 {
no-map;
reg = <0x0 0x4FD00000 0x0 0x100000>;
};
q6_qcn6122_etr_2: q6_qcn6122_etr_2@4FE00000 {
no-map;
reg = <0x0 0x4FE00000 0x0 0x100000>;
};
q6_qcn6122_caldb_2: q6_qcn6122_caldb_2@4FF00000 {
no-map;
reg = <0x0 0x4FF00000 0x0 0x500000>;
};
#endif
};
soc {
blsp1_uart1: serial@78af000 {
pinctrl-0 = <&blsp0_uart_pins>;
pinctrl-names = "default";
status = "okay";
};
blsp1_uart2: serial@78b0000 {
pinctrl-0 = <&blsp1_uart_pins>;
pinctrl-names = "default";
status = "disabled";
};
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "ok";
pinctrl-0 = <&mdio1_pins &phy_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 39 0>;
ethernet-phy@0 {
reg = <0>;
};
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
};
ess-instance {
num_devices = <0x2>;
ess-switch@0x39c00000 {
compatible = "qcom,ess-switch-ipq50xx";
device_id = <0>;
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
};
port@1 {
port_id = <2>;
forced-speed = <1000>;
forced-duplex = <1>;
};
};
/*
led_source@0 {
source = <0>;
mode = "normal";
speed = "all";
blink_en = "enable";
active = "high";
};
*/
};
ess-switch1@1 {
compatible = "qcom,ess-switch-qca83xx";
device_id = <1>;
switch_access_mode = "mdio";
mdio-bus = <&mdio1>;
reset_gpio = <0x27>;
switch_cpu_bmp = <0x40>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x0>; /* wan port bitmap */
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x00010 0x2613a0 /* PORT6 FORCE MODE*/
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
};
};
};
ess-uniphy@98000 {
status = "disabled";
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
mdio-bus = <&mdio1>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
qcom,test@0 {
status = "ok";
};
};
thermal-zones {
status = "ok";
};
};
&tlmm {
//pinctrl-0 = <&phy_led_pins>;
pinctrl-names = "default";
blsp0_uart_pins: uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
blsp1_uart_pins: blsp1_uart_pins {
blsp1_uart_rx_tx {
pins = "gpio23", "gpio25";
function = "blsp1_uart2";
bias-disable;
};
};
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
phy_pins: phy_pins {
phy_intr {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
bias-disable;
};
phy_reset {
pins = "gpio39";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
phy_led_pins: phy_led_pins {
gephy_led_pin {
//pins = "gpio46";
function = "led0";
drive-strength = <8>;
bias-pull-down;
};
};
button_pins: button_pins {
reset_button {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
led_pins: led_pins {
led_pwr {
pins = "gpio26";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_2g {
pins = "gpio31";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_5g {
pins = "gpio33";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&soc {
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
button@1 {
label = "reset_button";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: led_pwr {
label = "green:led_pwr";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "led_pwr";
};
led_2g {
label = "green:wifi2";
gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led_5g {
label = "green:wifi5";
gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&usb3 {
status = "ok";
device-power-gpio = <&tlmm 30 1>;
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "disabled";
perst-gpio = <&tlmm 15 1>;
};
&dwc_0 {
/delete-property/ #phy-cells;
/delete-property/ phys;
/delete-property/ phy-names;
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "disabled";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "disabled";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
};
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};
&qcom_q6v5_wcss {
qcom,multipd_arch;
memory-region = <&q6_mem_regions>;
qcom,share_bootargs;
qcom,bootargs_smem = <507>;
boot-args = <0x2 0x4 0x2 0xF 0x0 0x0>;
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>;
#else
memory-region = <&q6_ipq5018_data>, <&m3_dump>,
<&q6_etr_region>, <&q6_caldb_region>;
#endif
};
/* QCN6122 6G */
q6v5_wcss_userpd2 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 16 0>,
<&wcss_smp2p_in 17 0>,
<&wcss_smp2p_in 20 0>,
<&wcss_smp2p_in 19 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 16>,
<&wcss_smp2p_out 17>,
<&wcss_smp2p_out 18>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <2>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>;
#else
memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
#endif
};
/* QCN6122 5G */
q6v5_wcss_userpd3 {
m3_firmware = "qcn6122/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 24 0>,
<&wcss_smp2p_in 25 0>,
<&wcss_smp2p_in 28 0>,
<&wcss_smp2p_in 27 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 24>,
<&wcss_smp2p_out 25>,
<&wcss_smp2p_out 26>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <3>;
qca,auto-restart;
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>;
#else
memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
#endif
};
};
&qgic_msi_0 {
status = "ok";
};
&qgic_msi_1 {
status = "ok";
};
&wifi0 {
/* IPQ5018 */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x24>;
qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
#else
qcom,caldb-addr = <0x4D400000>;
m3-dump-addr = <0x4D200000>;
#endif
qcom,caldb-size = <0x200000>;
status = "ok";
};
&wifi1 {
/* QCN6122 6G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x60>;
qcom,bdf-addr = <0x4D600000 0x4D600000 0x4D300000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4E800000 0x4E800000 0 0 0>;
#else
qcom,caldb-addr = <0x4E800000>;
m3-dump-addr = <0x4E600000>;
#endif
qcom,caldb-size = <0x500000>;
status = "disabled";
};
&wifi2 {
/* QCN6122 5G */
qcom,multipd_arch;
qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
#ifdef __IPQ_MEM_PROFILE_256_MB__
qcom,tgt-mem-mode = <2>;
#else
qcom,tgt-mem-mode = <1>;
#endif
qcom,board_id = <0x60>;
qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
#ifdef __CNSS2__
qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
#else
qcom,caldb-addr = <0x4FF00000>;
m3-dump-addr = <0x4FD00000>;
#endif
qcom,caldb-size = <0x500000>;
status = "ok";
};

995
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-optimcloud-d50-5g.dts
View File

@@ -1,995 +0,0 @@
/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "qcom-ipq5018.dtsi"
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "OptimCloud D50-5G";
compatible = "optimcloud,d50-5g", "qcom,ipq5018-mp03.1", "qcom,ipq5018";
interrupt-parent = <&intc>;
#ifdef __IPQ_MEM_PROFILE_256_MB__
AUTO_MOUNT;
#endif
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
ethernet0 = "/soc/dp2";
ethernet1 = "/soc/dp1";
};
chosen {
bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
#ifdef __IPQ_MEM_PROFILE_256_MB__
bootargs-append = " swiotlb=1";
#else
bootargs-append = " swiotlb=1 coherent_pool=2M";
#endif
stdout-path = "serial0";
};
reserved-memory {
#ifdef __IPQ_MEM_PROFILE_256_MB__
/* 256 MB Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 8MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x40800000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* + | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 23MB |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C700000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4C900000 | 17MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4DA00000 | 16MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01700000>;
};
m3_dump@4c700000 {
no-map;
reg = <0x0 0x4C700000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
qcn9000_pcie0@4c900000 {
no-map;
reg = <0x0 0x4C900000 0x0 0x01100000>;
};
mhi_region1: dma_pool1@4da00000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4da00000 0x0 0x01000000>;
};
#elif __IPQ_MEM_PROFILE_512_MB__
/* 512 MB Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 16MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x41000000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 24MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C900000 | 1MB |
* +--------+--------------+-------------------------+
* | caldb | 0x4CA00000 | 2MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4CC00000 | 30MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4EA00000 | 16MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01800000>;
};
m3_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c900000 {
no-map;
reg = <0x0 0x4c900000 0x0 0x100000>;
};
q6_caldb_region:q6_caldb_region@4ca00000 {
no-map;
reg = <0x0 0x4ca00000 0x0 0x200000>;
};
qcn9000_pcie0@4cc00000 {
no-map;
reg = <0x0 0x4CC00000 0x0 0x01E00000>;
};
mhi_region1: dma_pool1@4ea00000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4ea00000 0x0 0x01000000>;
};
#else
/* 1G Profile
* +=========+==============+========================+
* | | | |
* | Region | Start Offset | Size |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | NSS | 0x40000000 | 16MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | | | |
* | Linux | 0x41000000 | Depends on total memory |
* | | | |
* | | | |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | uboot | 0x4A600000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | SBL | 0x4AA00000 | 1MB |
* +--------+--------------+-------------------------+
* | smem | 0x4AB00000 | 1MB |
* +--------+--------------+-------------------------+
* | | | |
* | TZ | 0x4AC00000 | 4MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | | | |
* | | | |
* | Q6 | 0x4B000000 | 24MB |
* | | | |
* | | | |
* +--------+--------------+-------------------------+
* | M3 Dump| 0x4C800000 | 1MB |
* +--------+--------------+-------------------------+
* | QDSS | 0x4C900000 | 1MB |
* +--------+--------------+-------------------------+
* | caldb | 0x4CA00000 | 2MB |
* +--------+--------------+-------------------------+
* | | | |
* |QCN9000 | 0x4CC00000 | 45MB |
* | | | |
* +--------+--------------+-------------------------+
* | | | |
* | MHI1 | 0x4F900000 | 24MB |
* | | | |
* +--------+--------------+-------------------------+
* | |
* | Rest of the memory for Linux |
* | |
* +=================================================+
*/
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x01800000>;
};
m3_dump@4c800000 {
no-map;
reg = <0x0 0x4c800000 0x0 0x100000>;
};
q6_etr_region:q6_etr_dump@4c900000 {
no-map;
reg = <0x0 0x4c900000 0x0 0x100000>;
};
q6_caldb_region:q6_caldb_region@4ca00000 {
no-map;
reg = <0x0 0x4ca00000 0x0 0x200000>;
};
qcn9000_pcie0@4cc00000 {
no-map;
reg = <0x0 0x4CC00000 0x0 0x02D00000>;
};
mhi_region1: dma_pool1@4F900000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x4F900000 0x0 0x01800000>;
};
#endif
};
soc {
serial@78af000 {
status = "ok";
};
blsp1_uart2: serial@78b0000 {
pinctrl-0 = <&blsp1_uart_pins>;
pinctrl-names = "default";
};
qpic_bam: dma@7984000{
status = "ok";
};
nand: qpic-nand@79b0000 {
pinctrl-0 = <&qspi_nand_pins>;
pinctrl-names = "default";
status = "ok";
};
spi_0: spi@78b5000 { /* BLSP1 QUP0 */
pinctrl-0 = <&blsp0_spi_pins>;
pinctrl-names = "default";
cs-select = <0>;
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "n25q128a11";
linux,modalias = "m25p80", "n25q128a11";
spi-max-frequency = <50000000>;
use-default-sizes;
};
};
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
};
mdio1: mdio@90000 {
status = "ok";
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 39 0>;
ethernet-phy@0 {
reg = <0>;
};
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
};
ess-instance {
num_devices = <0x2>;
ess-switch@0x39c00000 {
compatible = "qcom,ess-switch-ipq50xx";
device_id = <0>;
switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
cmnblk_clk = "internal_96MHz"; /* cmnblk clk*/
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <7>;
};
port@1 {
port_id = <2>;
forced-speed = <1000>;
forced-duplex = <1>;
};
};
led_source@0 {
source = <0>;
mode = "normal";
speed = "all";
blink_en = "enable";
active = "high";
};
};
ess-switch1@1 {
compatible = "qcom,ess-switch-qca83xx";
device_id = <1>;
switch_access_mode = "mdio";
mdio-bus = <&mdio1>;
reset_gpio = <0x27>;
switch_cpu_bmp = <0x40>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x0>; /* wan port bitmap */
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x00010 0x2613a0 /* PORT6 FORCE MODE*/
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
};
};
};
wifi0: wifi@c000000 {
qcom,bdf-addr = <0x4BA00000 0x4BA00000 0x4BA00000
0x0 0x0>;
qcom,caldb-addr = <0x4CA00000 0x4CA00000 0x4CA00000
0x0 0x0>;
qcom,caldb-size = <0x200000>;
status = "ok";
};
ess-uniphy@98000 {
status = "disabled";
};
qcom,sps {
status = "ok";
};
qcom,usbbam@8B04000 {
status = "ok";
};
qcom,diag@0 {
status = "ok";
};
dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <1>;
reg = <0x39C00000 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <7>;
mdio-bus = <&mdio0>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
clock-names = "nss-snoc-gmac-axi-clk";
qcom,id = <2>;
reg = <0x39D00000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
qcom,mactype = <2>;
local-mac-address = [000000000000];
phy-mode = "sgmii";
};
rpm_etm0 {
status = "disabled";
};
lpass: lpass@0xA000000{
status = "disabled";
};
pcm: pcm@0xA3C0000{
pinctrl-0 = <&audio_pins>;
pinctrl-names = "default";
status = "disabled";
};
pcm_lb: pcm_lb@0 {
status = "disabled";
};
};
thermal-zones {
status = "ok";
};
gpio_keys {
compatible = "gpio-keys-polled";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
poll-interval = <100>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
button@1 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led@35 {
label = "green:4g";
gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_5g_wifi";
default-state = "off";
};
led@30 {
label = "green:wifi";
gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_2g_wifi";
default-state = "off";
};
led@1 {
label = "green:internet";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_voice";
default-state = "off";
};
led@33 {
label = "green:lte";
gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_lte_g";
default-state = "off";
};
led@34 {
label = "red:lte";
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_lte_r";
default-state = "off";
};
led@27 {
label = "green:mesh";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_nr_g";
default-state = "off";
};
led@28 {
label = "red:mesh";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "led_nr_r";
default-state = "off";
};
};
};
&tlmm {
pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>;
pinctrl-names = "default";
blsp0_uart_pins: blsp0_uart_pins {
blsp0_uart_rx_tx {
pins = "gpio20", "gpio21";
function = "blsp0_uart0";
bias-disable;
};
};
blsp1_uart_pins: blsp1_uart_pins {
blsp1_uart_rx_tx {
pins = "gpio23", "gpio25", "gpio24", "gpio26";
function = "blsp1_uart2";
bias-disable;
};
};
blsp0_spi_pins: blsp0_spi_pins {
mux {
pins = "gpio10", "gpio11", "gpio12", "gpio13";
function = "blsp0_spi";
drive-strength = <2>;
bias-disable;
};
};
qspi_nand_pins: qspi_nand_pins {
qspi_clock {
pins = "gpio9";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
qspi_cs {
pins = "gpio8";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
qspi_data_0 {
pins = "gpio7";
function = "qspi0";
drive-strength = <8>;
bias-disable;
};
qspi_data_1 {
pins = "gpio6";
function = "qspi1";
drive-strength = <8>;
bias-disable;
};
qspi_data_2 {
pins = "gpio5";
function = "qspi2";
drive-strength = <8>;
bias-disable;
};
qspi_data_3 {
pins = "gpio4";
function = "qspi3";
drive-strength = <8>;
bias-disable;
};
};
mdio1_pins: mdio_pinmux {
mux_0 {
pins = "gpio36";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio37";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
phy_led_pins: phy_led_pins {
gephy_led_pin {
pins = "gpio46";
function = "led0";
drive-strength = <8>;
bias-pull-down;
};
};
i2c_pins: i2c_pins {
i2c_scl {
pins = "gpio25";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
i2c_sda {
pins = "gpio26";
function = "blsp2_i2c1";
drive-strength = <8>;
bias-disable;
};
};
button_pins: button_pins {
reset_button{
pins = "gpio22";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
wps_button {
pins = "gpio38";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds_pins {
led_5g_wifi {
pins = "gpio35";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_2g_wifi {
pins = "gpio30";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lte_g {
pins = "gpio33";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lte_r {
pins = "gpio34";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_nr_g {
pins = "gpio27";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_nr_r {
pins = "gpio28";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_voice {
pins = "gpio1";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
audio_pins: audio_pinmux {
mux_1 {
pins = "gpio24";
function = "audio_rxbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_2 {
pins = "gpio25";
function = "audio_rxfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_3 {
pins = "gpio26";
function = "audio_rxd";
drive-strength = <8>;
bias-pull-down;
};
mux_4 {
pins = "gpio27";
function = "audio_txmclk";
drive-strength = <8>;
bias-pull-down;
};
mux_5 {
pins = "gpio28";
function = "audio_txbclk";
drive-strength = <8>;
bias-pull-down;
};
mux_6 {
pins = "gpio29";
function = "audio_txfsync";
drive-strength = <8>;
bias-pull-down;
};
mux_7 {
pins = "gpio30";
function = "audio_txd";
drive-strength = <8>;
bias-pull-down;
};
};
};
&usb3 {
qcom,multiplexed-phy;
qcom,phy-mux-regs = <&tcsr_q6_block 0x2540>;
device-power-gpio = <&tlmm 24 1>;
status = "ok";
};
&eud {
status = "ok";
};
&pcie_x1 {
status = "disabled";
perst-gpio = <&tlmm 18 1>;
};
&pcie_x2 {
status = "ok";
perst-gpio = <&tlmm 15 1>;
};
&bt {
status = "ok";
};
&wcss {
status = "ok";
};
&q6v5_wcss {
status = "disabled";
};
&q6v5_m3 {
status = "disabled";
};
&tcsr_mutex_block {
status = "ok";
};
&tcsr_mutex {
status = "ok";
};
&smem {
status = "ok";
};
&apcs_glb {
status = "ok";
};
&tcsr_q6_block {
status = "ok";
};
&qcom_q6v5_wcss {
#ifdef __IPQ_MEM_PROFILE_256_MB__
memory-region = <&q6_region>, <&q6_etr_region>;
#else
memory-region = <&q6_region>, <&q6_etr_region>,
<&q6_caldb_region>;
#endif
/* IPQ5018 */
q6v5_wcss_userpd1 {
m3_firmware = "IPQ5018/m3_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names ="fatal",
"ready",
"spawn_ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
qca,asid = <1>;
qca,auto-restart;
qca,int_radio;
};
};
&i2c_0 {
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
status = "disabled";
};
&dbm_1p5 {
status = "ok";
};
&msm_imem {
status = "ok";
};
&blsp1_uart1 {
status = "ok";
};
&ssuniphy_0 {
status = "ok";
};
&hs_m31phy_0 {
status = "ok";
};
&pcie_x1phy {
status = "disabled";
};
&pcie_x2phy {
status = "ok";
};
&pcie_x1_rp {
status = "disabled";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
};
};
&pcie_x2_rp {
status = "ok";
mhi_1: qcom,mhi@1 {
reg = <0 0 0 0 0 >;
qrtr_instance_id = <0x20>;
#address-cells = <0x2>;
#size-cells = <0x2>;
memory-region = <&mhi_region1>;
#if !defined(__CNSS2__)
base-addr = <0x4CC00000>;
m3-dump-addr = <0x4E000000>;
etr-addr = <0x4E100000>;
qcom,caldb-addr = <0x4E200000>;
qcom,tgt-mem-mode = <0x1>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
#endif
};
};
&wifi0 {
/* IPQ5018 */
qcom,board_id = <0x24>;
status = "ok";
};
&wifi3 {
/* QCN9000 5G */
board_id = <0xa0>;
status = "ok";
};
&qfprom {
status = "ok";
};
&tsens {
status = "ok";
};

Some files were not shown because too many files have changed in this diff Show More