mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-29 17:42:41 +00:00
5f1d562f61
We previously had a beta release. Fixes: WIFI-14322 Signed-off-by: John Crispin <john@phrozen.org>
395 lines
11 KiB
C
395 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitfield.h>
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/phy.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
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#define MD32_EN BIT(0)
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#define PMEM_PRIORITY BIT(8)
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#define DMEM_PRIORITY BIT(16)
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#define BASE100T_STATUS_EXTEND (0x10)
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#define BASE1000T_STATUS_EXTEND (0x11)
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#define EXTEND_CTRL_AND_STATUS (0x16)
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#define PHY_AUX_CTRL_STATUS (0x1d)
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#define PHY_AUX_DPX_MASK GENMASK(5, 5)
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#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
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/* Registers on MDIO_MMD_VEND1 */
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#define MTK_PHY_LINK_STATUS_MISC (0xa2)
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#define MTK_PHY_FDX_ENABLE BIT(5)
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#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121)
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#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
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/* Registers on MDIO_MMD_VEND2 */
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#define MTK_PHY_LED0_ON_CTRL (0x24)
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#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
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#define MTK_PHY_LED0_ON_LINK100 BIT(1)
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#define MTK_PHY_LED0_ON_LINK10 BIT(2)
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#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
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#define MTK_PHY_LED0_POLARITY BIT(14)
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#define MTK_PHY_LED1_ON_CTRL (0x26)
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#define MTK_PHY_LED1_ON_FDX BIT(4)
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#define MTK_PHY_LED1_ON_HDX BIT(5)
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#define MTK_PHY_LED1_POLARITY BIT(14)
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#define MTK_EXT_PAGE_ACCESS 0x1f
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#define MTK_PHY_PAGE_STANDARD 0x0000
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#define MTK_PHY_PAGE_EXTENDED_1 0x1
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#define MTK_PHY_AUX_CTRL_AND_STATUS (0x14)
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#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
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/* Registers on Token Ring debug nodes */
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#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
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#define AUTO_NP_10XEN BIT(6)
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struct mtk_i2p5ge_phy_priv {
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bool fw_loaded;
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u16 tr_low;
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u16 tr_high;
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};
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enum {
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PHY_AUX_SPD_10 = 0,
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PHY_AUX_SPD_100,
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PHY_AUX_SPD_1000,
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PHY_AUX_SPD_2500,
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};
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static void tr_access(struct phy_device *phydev, bool read, u8 ch_addr, u8 node_addr, u8 data_addr)
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{
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u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
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if (read)
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tr_cmd |= BIT(13);
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tr_cmd |= (((ch_addr & 0x3) << 11) |
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((node_addr & 0xf) << 7) |
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((data_addr & 0x3f) << 1));
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dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
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__phy_write(phydev, 0x10, tr_cmd);
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}
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static void __tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, u8 data_addr)
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{
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struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
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tr_access(phydev, true, ch_addr, node_addr, data_addr);
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priv->tr_low = __phy_read(phydev, 0x11);
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priv->tr_high = __phy_read(phydev, 0x12);
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dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
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priv->tr_high, priv->tr_low);
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}
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static void tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr, u8 data_addr)
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{
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__tr_read(phydev, ch_addr, node_addr, data_addr);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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static void __tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr, u8 data_addr,
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u32 tr_data)
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{
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__phy_write(phydev, 0x11, tr_data & 0xffff);
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__phy_write(phydev, 0x12, tr_data >> 16);
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tr_access(phydev, false, ch_addr, node_addr, data_addr);
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}
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static void tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr, u8 data_addr, u32 tr_data)
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{
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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static void tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, u8 data_addr,
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u32 mask, u32 set)
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{
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u32 tr_data;
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struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__tr_read(phydev, ch_addr, node_addr, data_addr);
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tr_data = (priv->tr_high << 16) | priv->tr_low;
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tr_data = (tr_data & ~mask) | set;
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__tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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}
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static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
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}
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static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
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}
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static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
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{
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struct mtk_i2p5ge_phy_priv *priv;
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priv = devm_kzalloc(&phydev->mdio.dev,
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sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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return 0;
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}
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static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
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{
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int ret, i;
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const struct firmware *fw;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *np;
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void __iomem *pmb_addr;
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void __iomem *md32_en_cfg_base;
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struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
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u16 reg;
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struct pinctrl *pinctrl;
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if (!priv->fw_loaded) {
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np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
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if (!np)
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return -ENOENT;
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pmb_addr = of_iomap(np, 0);
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if (!pmb_addr)
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return -ENOMEM;
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md32_en_cfg_base = of_iomap(np, 1);
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if (!md32_en_cfg_base)
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return -ENOMEM;
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ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
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if (ret) {
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dev_err(dev, "failed to load firmware: %s, ret: %d\n",
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MT7988_2P5GE_PMB, ret);
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return ret;
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}
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reg = readw(md32_en_cfg_base);
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if (reg & MD32_EN) {
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phy_set_bits(phydev, 0, BIT(15));
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usleep_range(10000, 11000);
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}
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phy_set_bits(phydev, 0, BIT(11));
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/* Write magic number to safely stall MCU */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
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phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
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for (i = 0; i < fw->size - 1; i += 4)
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writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
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release_firmware(fw);
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writew(reg & ~MD32_EN, md32_en_cfg_base);
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writew(reg | MD32_EN, md32_en_cfg_base);
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phy_set_bits(phydev, 0, BIT(15));
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/* We need a delay here to stabilize initialization of MCU */
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usleep_range(7000, 8000);
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dev_info(dev, "Firmware loading/trigger ok.\n");
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priv->fw_loaded = true;
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}
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/* Setup LED */
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
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MTK_PHY_LED0_POLARITY | MTK_PHY_LED0_ON_LINK10 |
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MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000 |
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MTK_PHY_LED0_ON_LINK2500);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
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MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
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pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
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if (IS_ERR(pinctrl)) {
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dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
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return PTR_ERR(pinctrl);
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}
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
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MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
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/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
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tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
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FIELD_PREP(AUTO_NP_10XEN, 0x1));
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/* Enable downshift */
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_1);
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__phy_set_bits(phydev, MTK_PHY_AUX_CTRL_AND_STATUS, MTK_PHY_ENABLE_DOWNSHIFT);
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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return 0;
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}
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static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u32 adv;
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int ret;
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if (phydev->autoneg == AUTONEG_DISABLE) {
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/* Configure half duplex with genphy_setup_forced,
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* because genphy_c45_pma_setup_forced does not support.
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*/
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return phydev->duplex != DUPLEX_FULL
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? genphy_setup_forced(phydev)
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: genphy_c45_pma_setup_forced(phydev);
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}
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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ret = phy_modify_changed(phydev, MII_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_read_abilities(phydev);
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if (ret)
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return ret;
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/* We don't support HDX at MAC layer on mt7988.
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* So mask phy's HDX capabilities, too.
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*/
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linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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return 0;
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}
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static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
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{
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int ret;
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u16 status;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
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ret = genphy_c45_read_lpa(phydev);
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if (ret < 0)
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return ret;
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/* Read the link partner's 1G advertisement */
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ret = phy_read(phydev, MII_STAT1000);
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if (ret < 0)
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return ret;
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mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
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} else if (phydev->autoneg == AUTONEG_DISABLE) {
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linkmode_zero(phydev->lp_advertising);
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}
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status = phy_read(phydev, MII_BMSR);
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if (status & BMSR_LSTATUS) {
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ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
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if (ret < 0)
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return ret;
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switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
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case PHY_AUX_SPD_10:
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phydev->speed = SPEED_10;
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break;
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case PHY_AUX_SPD_100:
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phydev->speed = SPEED_100;
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break;
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case PHY_AUX_SPD_1000:
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phydev->speed = SPEED_1000;
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break;
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case PHY_AUX_SPD_2500:
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phydev->speed = SPEED_2500;
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break;
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}
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
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if (ret < 0)
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return ret;
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phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
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/* FIXME: The current firmware always enables rate adaptation mode. */
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phydev->rate_matching = RATE_MATCH_PAUSE;
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}
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return 0;
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}
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static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
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phy_interface_t iface)
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{
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if (iface == PHY_INTERFACE_MODE_XGMII)
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return RATE_MATCH_PAUSE;
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return RATE_MATCH_NONE;
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}
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static struct phy_driver mtk_gephy_driver[] = {
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{
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PHY_ID_MATCH_MODEL(0x00339c11),
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.name = "MediaTek MT798x 2.5GbE PHY",
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.probe = mt7988_2p5ge_phy_probe,
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.config_init = mt7988_2p5ge_phy_config_init,
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.config_aneg = mt7988_2p5ge_phy_config_aneg,
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.get_features = mt7988_2p5ge_phy_get_features,
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.read_status = mt7988_2p5ge_phy_read_status,
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.get_rate_matching = mt7988_2p5ge_phy_get_rate_matching,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = mtk_2p5ge_phy_read_page,
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.write_page = mtk_2p5ge_phy_write_page,
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},
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};
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module_phy_driver(mtk_gephy_driver);
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static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
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{ PHY_ID_MATCH_VENDOR(0x00339c00) },
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{ }
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};
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MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
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MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
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