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wlan-ap/feeds/qca-wifi-7/ipq53xx/dts/ipq5332.dtsi
mike_ding b5987cc2a7 qca-wifi-7: Support for AP72TIP and AP72TIP-v4 on APNOS v4.x 
Signed-off-by: mike_ding <mike_ding@sdc.sercomm.com>
2025-04-25 08:15:00 +02:00

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// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 device tree source
*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/clock/qcom,nsscc-ipq5332.h>
#include <dt-bindings/reset/qcom,nsscc-ipq5332.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
#clock-cells = <0>;
};
cmn_pll_nss_clk_200m: cmn-pll-nss-clk-200m {
compatible = "fixed-clock";
clock-frequency = <200000000>;
#clock-cells = <0>;
};
cmn_pll_nss_clk_300m: cmn-pll-nss-clk-300m {
compatible = "fixed-clock";
clock-frequency = <300000000>;
#clock-cells = <0>;
};
gcc_gpll0_out_aux: gcc-gpll0-out-aux {
compatible = "fixed-clock";
clock-frequency = <800000000>;
#clock-cells = <0>;
};
pcie_2lane_phy_pipe_clk: pcie-2lane-phy-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <250000000>;
#clock-cells = <0>;
};
pcie_2lane_phy_pipe_clk_x1: pcie-2lane-phy-pipe-clk-x1 {
compatible = "fixed-clock";
clock-frequency = <250000000>;
#clock-cells = <0>;
};
usb_pcie_wrapper_pipe_clk: usb-pcie-wrapper-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <250000000>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq5332", "qcom,scm";
qcom,dload-mode = <&tcsr 0x6100>;
};
};
qcn9224_legacy_irq0: qcn9224_legacy_irq0 {
compatible = "qcom,qcn9224_legacy_irq";
node_id = <0>;
status = "okay";
qcn9224_in0: legacy_interrupt {
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcn9224_legacy_irq1: qcn9224_legacy_irq1 {
compatible = "qcom,qcn9224_legacy_irq";
node_id = <1>;
status = "okay";
qcn9224_in1: legacy_interrupt {
interrupt-controller;
#interrupt-cells = <2>;
};
};
ipq-debug {
compatible = "qcom,ipq-debug";
};
memory@40000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x40000000 0x0 0x0>;
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2-ipq5332";
opp-shared;
nvmem-cells = <&cpu_speed_bin>;
nvmem-cell-names = "speed_bin";
/*
* Listed all supported CPU frequencies and opp-supported-hw
* values to select CPU frequencies based on the limits fused.
* ------------------------------------------------------------
* Frequency BIT3 BIT2 BIT1 BIT0 opp-supported-hw
* 1.0GHz 1.2GHz 1.5GHz No Limit
* ------------------------------------------------------------
* 1100000000 1 1 1 1 0xF
* 1500000000 0 0 1 1 0x3
* -----------------------------------------------------------
*/
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <850000>;
opp-supported-hw = <0xF>;
clock-latency-ns = <200000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <950000>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
};
ctx_save: ctx-save {
compatible = "qti,ctxt-save-ipq5332";
memory-region = <&minidump_mem>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pmu-v7 {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
qti,tzlog {
compatible = "qti,tzlog-ipq5332";
interrupts = <GIC_SPI 267 IRQ_TYPE_EDGE_RISING>;
qti,tz-diag-buf-size = <0x3000>;
qti,tz-ring-off = <7>;
qti,tz-log-pos-info-off = <810>;
};
qseecom: qseecom {
compatible = "ipq9574-qseecom";
memory-region = <&tzapp>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tzapp:tzapp@49600000 { /* TZAPPS */
#if !defined(__IPQ_MEM_PROFILE_512_MB__) && !defined(__IPQ_MEM_PROFILE_256_MB__)
reg = <0x0 0x49600000 0x0 0x00600000>;
#endif
no-map;
};
bootloader@4a000000 {
reg = <0x0 0x4a000000 0x0 0x500000>;
no-map;
};
sbl@4a500000 {
reg = <0x0 0x4a500000 0x0 0x100000>;
no-map;
};
tz_mem: tz@4a600000 {
reg = <0x0 0x4a600000 0x0 0x200000>;
no-map;
};
smem@4a800000 {
compatible = "qcom,smem";
reg = <0x0 0x4a800000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
minidump_mem: minidump_mem@0 {
no-map;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
qfprom {
compatible = "qcom,qfprom-ipq5332-sec";
img-addr = <0x4a100000>;
img-size = <0x500000>;
scm-cmd-id = <0x1f>;
reg = <0xA6044 0x4>;
};
qfprom: efuse@a4000 {
compatible = "qcom,qfprom";
reg = <0xa4000 0x721>;
#address-cells = <1>;
#size-cells = <1>;
cpu_speed_bin: cpu_speed_bin@1d {
reg = <0x1d 0x2>;
bits = <7 2>;
};
s11: s11@3a5 {
reg = <0x3a5 0x1>;
bits = <4 4>;
};
s12: s12@3a6 {
reg = <0x3a6 0x1>;
bits = <0 4>;
};
s13: s13@3a6 {
reg = <0x3a6 0x1>;
bits = <4 4>;
};
s14: s14@3ad {
reg = <0x3ad 0x2>;
bits = <7 4>;
};
s15: s15@3ae {
reg = <0x3ae 0x1>;
bits = <3 4>;
};
tsens_mode: mode@3e1 {
reg = <0x3e1 0x1>;
bits = <0 3>;
};
tsens_base0: base0@3e1 {
reg = <0x3e1 0x2>;
bits = <3 10>;
};
tsens_base1: base1@3e2 {
reg = <0x3e2 0x2>;
bits = <5 10>;
};
pcie0_disable: pcie0_disable@25 {
reg = <0x25 0x1>;
bits = <3 1>;
};
pcie1_disable: pcie1_disable@25 {
reg = <0x25 0x1>;
bits = <4 1>;
};
pcie2_disable: pcie2_disable@25 {
reg = <0x25 0x1>;
bits = <2 1>;
};
};
rng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
reg_update: reg-update@400000 {
compatible = "ipq,53xx-reg-update";
reg = <0x00400000 0x6200>, <0x01d80000 0x4000>;
reg-names = "memnoc_53xx", "nssnoc";
status = "okay";
};
pcie0_phy: phy@4b0000 {
compatible = "qca,uni-pcie-phy-gen3";
reg = <0x4b0000 0x800>;
phy-type = "gen3";
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>,
<&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
clock-names = "pipe_clk",
"lane_m_clk",
"lane_s_clk",
"phy_ahb_clk";
assigned-clocks = <&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>;
assigned-clock-rates = <240000000>,
<240000000>;
resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
<&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>,
<&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>;
reset-names = "phy",
"phy_phy",
"phy_ahb";
mode-fixed = <2>; /* TBD */
status = "disabled";
};
/* PHY for PCIE1 single lane mode */
pcie1_phy: phy@4b1000 {
compatible = "qca,uni-pcie-phy-gen3";
reg = <0x4b1000 0x800>;
phy-type = "gen3";
#phy-cells = <0>;
qti,multiplexed-phy;
qti,phy-mux-regs = <&tcsr 0x10544>;
phy-ahb-shared-reset;
clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
clock-names = "pipe_clk",
"lane_m_clk",
"lane_s_clk",
"phy_ahb_clk";
assigned-clocks = <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
assigned-clock-rates = <266666666>,
<240000000>;
resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
reset-names = "phy",
"phy_ahb";
mode-fixed = <2>; /* TBD */
status = "disabled";
};
/* PHY for PCIE2 single lane mode */
pcie2_phy: phy@4b1800 {
compatible = "qca,uni-pcie-phy-gen3";
reg = <0x4b1800 0x800>;
phy-type = "gen3";
#phy-cells = <0>;
phy-ahb-shared-reset;
qti,multiplexed-phy;
qti,phy-mux-regs = <&tcsr 0x10544>;
clocks = <&gcc GCC_PCIE3X1_1_PIPE_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_1_M_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_1_S_CLK>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
clock-names = "pipe_clk",
"lane_m_clk",
"lane_s_clk",
"phy_ahb_clk";
assigned-clocks = <&gcc GCC_SNOC_PCIE3_1LANE_1_M_CLK>,
<&gcc GCC_SNOC_PCIE3_1LANE_1_S_CLK>;
assigned-clock-rates = <240000000>,
<240000000>;
resets = <&gcc GCC_PCIE3X1_1_PHY_BCR>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
reset-names = "phy",
"phy_ahb";
mode-fixed = <2>; /* TBD */
status = "disabled";
};
/* PHY for PCIE1 dual lane mode */
pcie1_phy_x2: phy_x2@4b1000 {
compatible = "qca,uni-pcie-phy-gen3";
reg = <0x4b1000 0x1000>;
phy-type = "gen3";
#phy-cells = <0>;
qti,phy-mux-regs = <&tcsr 0x10544>;
clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
clock-names = "pipe_clk",
"lane_m_clk",
"lane_s_clk",
"phy_ahb_clk";
assigned-clocks = <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
<&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>;
assigned-clock-rates = <266666666>,
<240000000>;
resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
<&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
reset-names = "phy",
"phy_ahb";
mode-fixed = <2>; /* TBD */
x2 = <1>;
status = "disabled";
};
msm_imem: qcom,msm-imem@8600000 {
compatible = "qcom,msm-imem";
reg = <0x08600000 0x1000>;
ranges = <0x0 0x08600000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tz-log-buf-addr@720 {
compatible = "qcom,msm-imem-tz-log-buf-addr";
reg = <0x720 4>;
};
restart-reason-buf-addr@7a4 {
compatible = "qcom,msm-imem-restart-reason-buf-addr";
reg = <0x7a4 4>;
};
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,ipq5332-tsens";
reg = <0x4a9000 0x1000>,
<0x4a8000 0x1000>;
nvmem-cells = <&tsens_mode>, <&tsens_base0>,
<&tsens_base1>, <&s11>,
<&s12>, <&s13>,
<&s14>, <&s15>;
nvmem-cell-names = "mode", "base0",
"base1", "s11",
"s12", "s13",
"s14", "s15";
interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "combined";
#thermal-sensor-cells = <1>;
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 53>;
interrupt-controller;
#interrupt-cells = <2>;
serial_0_pins: serial0-state {
pins = "gpio18", "gpio19";
function = "blsp0_uart0";
drive-strength = <8>;
bias-pull-up;
};
mdio0_pins: mdio0-state {
mux_0 {
pins = "gpio25";
function = "mdc0";
drive-strength = <2>;
bias-pull-up;
};
mux_1 {
pins = "gpio26";
function = "mdio0";
drive-strength = <2>;
bias-pull-up;
};
};
mdio1_pins: mdio1-state {
mux_0 {
pins = "gpio27";
function = "mdc1";
drive-strength = <8>;
bias-disable;
};
mux_1 {
pins = "gpio28";
function = "mdio1";
drive-strength = <8>;
bias-pull-up;
};
};
bt_pins: bt_pins {
pta {
pins = "gpio49", "gpio50" , "gpio51";
function = "pta";
drive-strength = <8>;
bias-disable;
};
bt_reset {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq5332-gcc";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo>,
<&sleep_clk>,
<&pcie_2lane_phy_pipe_clk>,
<&pcie_2lane_phy_pipe_clk_x1>,
<&usb_pcie_wrapper_pipe_clk>;
};
nsscc: nsscc@39b00000{
compatible = "qcom,nsscc-ipq5332";
reg = <0x39b00000 0x80000>;
clocks = <&xo>,
<&cmn_pll_nss_clk_200m>,
<&cmn_pll_nss_clk_300m>,
<&gcc_gpll0_out_aux>;
clock-names = "xo",
"cmn_pll_nss_clk_200m",
"cmn_pll_nss_clk_300m",
"gcc_gpll0_out_aux";
#clock-cells = <0x1>;
#reset-cells = <0x1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1937000 {
compatible = "qcom,tcsr-ipq5332", "syscon", "simple-mfd";
reg = <0x01937000 0x21000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x01937000 0x21000>;
pwm: pwm@a010 {
compatible = "qcom,ipq9574-pwm";
reg = <0xa010 0x20>;
clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
assigned-clock-rates = <100000000>;
#pwm-cells = <2>;
status = "disabled";
};
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x1d000>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart0: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
tx-watermark = <0>;
};
blsp1_uart1: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b0000 0x200>;
interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dma-names = "tx", "rx";
status = "disabled";
};
dcc@797f000 {
compatible = "qcom,dcc-v2-ipq5332";
reg = <0x40ff000 0x1000>,
<0x4080000 0x800>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x0>;
status = "disabled";
};
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x7984000 0x1c000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
qpic_nand: nand@79b0000 {
compatible = "qcom,ipq5332-nand";
reg = <0x79b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>,
<&gcc GCC_QPIC_IO_MACRO_CLK>;
clock-names = "core", "aon", "io_macro";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>,
<&qpic_bam 3>;
dma-names = "tx", "rx", "cmd", "sts";
qcom,io_macro_max_clk = <320000000>;
qcom,io_macro_clk_rates = <24000000 100000000 200000000 \
320000000>;
status = "disabled";
};
blsp1_spi0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_spi1: spi@78b6000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_spi2: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "tx", "rx";
status = "disabled";
};
lpass: lpass@0xA000000{
compatible = "qca,lpass-ipq5332";
reg = <0xA000000 0x3BFFFF>;
clocks = <&gcc GCC_LPASS_SWAY_CLK>,
<&gcc GCC_LPASS_CORE_AXIM_CLK>,
<&gcc GCC_SNOC_LPASS_CFG_CLK>,
<&gcc GCC_PCNOC_LPASS_CLK>;
clock-names = "sway", "axim", "snoc_cfg", "pcnoc";
resets = <&gcc GCC_LPASS_BCR>;
reset-names = "lpass";
status = "disabled";
};
pcm: pcm@0xA3C0000{
compatible = "qca,ipq5332-lpass-pcm";
reg = <0xA3C0000 0x23014>;
status = "disabled";
pcm0: pcm0@0 {
interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "out0";
capture_memory = "lpm";
playback_memory = "lpm";
voice_loopback = <0>;
slave = <0>;
status = "disabled";
};
pcm1: pcm1@1 {
interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "out1";
capture_memory = "lpm";
playback_memory = "lpm";
voice_loopback = <0>;
slave = <0>;
status = "disabled";
};
};
pcm_lb: pcm_lb@0 {
compatible = "qca,ipq5332-pcm-lb";
status = "disabled";
};
wsi: wsi {
status = "disabled";
};
seccrypt: qcom,seccrypt {
compatible = "qcom,seccrypt";
status = "okay";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
<0x0b002000 0x1000>, /* GICC */
<0x0b001000 0x1000>, /* GICH */
<0x0b004000 0x1000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0b00c000 0x3000>;
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
reg = <0x00000000 0xffd>;
msi-controller;
};
v2m1: v2m@1000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00001000 0xffd>;
msi-controller;
};
v2m2: v2m@2000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00002000 0xffd>;
msi-controller;
};
};
watchdog: watchdog@b017000 {
compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
reg = <0x0b017000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
timeout-sec = <30>;
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq5332-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
clocks = <&a53pll>, <&xo>, <&gcc_gpll0_out_aux>;
clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
a53pll: clock@b116000 {
compatible = "qcom,ipq5332-a53pll";
reg = <0x0b116000 0x40>;
#clock-cells = <0>;
clocks = <&xo>;
clock-names = "xo";
};
mdio: mdio@90000 {
compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio";
reg = <0x90000 0x64>, <0x7A00610 0x4>, <0x7A10610 0x4>, <0x9B000 0x800>;
reg-names = "ppe", "eth_ldo1", "eth_ldo2", "cmn_blk";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc GCC_MDIO_AHB_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
<&gcc GCC_UNIPHY0_SYS_CLK>,
<&gcc GCC_UNIPHY1_AHB_CLK>,
<&gcc GCC_UNIPHY1_SYS_CLK>;
clock-names = "gcc_mdio_ahb_clk",
"uniphy0_ahb_clk",
"uniphy0_sys_clk",
"uniphy1_ahb_clk",
"uniphy1_sys_clk";
status = "disabled";
};
wifi0: wifi@c0000000 {
compatible = "qcom,cnss-qca5332", "qcom,ipq5332-wifi";
reg = <0xc000000 0x1000000>;
qcom,tgt-mem-mode = <0>;
qcom,rproc = <&q6v5_wcss>;
qcom,bdf-addr = <0x4B500000 0x4B500000 0x4B500000
0x0 0x0 0x0>;
qcom,caldb-addr = <0x4CE00000 0x4CE00000 0x0
0x0 0x0 0x0>;
qcom,caldb-size = <0x500000>;
interrupts = <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>, /* misc-pulse1 */
<GIC_SPI 560 IRQ_TYPE_EDGE_RISING>, /* misc-latch */
<GIC_SPI 561 IRQ_TYPE_EDGE_RISING>, /* sw-exception */
<GIC_SPI 422 IRQ_TYPE_EDGE_RISING>, /* ce0 */
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>, /* ce1 */
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>, /* ce2 */
<GIC_SPI 425 IRQ_TYPE_EDGE_RISING>, /* ce3 */
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>, /* ce4 */
<GIC_SPI 427 IRQ_TYPE_EDGE_RISING>, /* ce5 */
<GIC_SPI 428 IRQ_TYPE_EDGE_RISING>, /* ce6 */
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>, /* ce7 */
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>, /* ce8 */
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, /* ce9 */
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, /* ce10 */
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, /* ce11 */
<GIC_SPI 491 IRQ_TYPE_EDGE_RISING>, /* host2wbm-desc-feed */
<GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, /* host2reo-re-injection */
<GIC_SPI 493 IRQ_TYPE_EDGE_RISING>, /* host2reo-command */
<GIC_SPI 544 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-monitor-ring1 */
<GIC_SPI 457 IRQ_TYPE_EDGE_RISING>, /* reo2ost-exception */
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, /* wbm2host-rx-release */
<GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, /* reo2host-status */
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>, /* reo2host-destination-ring4 */
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>, /* reo2host-destination-ring3 */
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>, /* reo2host-destination-ring2 */
<GIC_SPI 451 IRQ_TYPE_EDGE_RISING>, /* reo2host-destination-ring1 */
<GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-destination-mac3 */
<GIC_SPI 488 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-destination-mac2 */
<GIC_SPI 484 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-destination-mac1 */
<GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-host-buf-ring-mac3 */
<GIC_SPI 554 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-host-buf-ring-mac2 */
<GIC_SPI 549 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-host-buf-ring-mac1 */
<GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, /* host2tcl-input-ring4 */
<GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, /* host2tcl-input-ring3 */
<GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, /* host2tcl-input-ring2 */
<GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, /* host2tcl-input-ring1 */
<GIC_SPI 458 IRQ_TYPE_EDGE_RISING>, /* wbm2host-tx-completions-ath-ring4 */
<GIC_SPI 450 IRQ_TYPE_EDGE_RISING>, /* wbm2host-tx-completions-ring4 */
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>, /* wbm2host-tx-completions-ring3 */
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, /* wbm2host-tx-completions-ring2 */
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>, /* wbm2host-tx-completions-ring1 */
<GIC_SPI 543 IRQ_TYPE_EDGE_RISING>, /* host2tx-monitor-ring1 */
<GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, /* txmon2host-monitor-destination-mac3 */
<GIC_SPI 486 IRQ_TYPE_EDGE_RISING>, /* txmon2host-monitor-destination-mac2 */
<GIC_SPI 482 IRQ_TYPE_EDGE_RISING>, /* txmon2host-monitor-destination-mac1 */
<GIC_SPI 419 IRQ_TYPE_EDGE_RISING>, /* umac_reset */
/* Unused Interrupts */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-monitor-ring3 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* host2rxdma-monitor-ring2 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* ppdu-end-interrupts-mac3 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* ppdu-end-interrupts-mac2 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* ppdu-end-interrupts-mac1 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-status-ring-mac3 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-status-ring-mac2 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-monitor-status-ring-mac1 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-destination-ring-mac3 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>, /* rxdma2host-destination-ring-mac2 */
<GIC_SPI 558 IRQ_TYPE_EDGE_RISING>; /* rxdma2host-destination-ring-mac1 */
interrupt-names = "misc-pulse1",
"misc-latch",
"sw-exception",
"ce0",
"ce1",
"ce2",
"ce3",
"ce4",
"ce5",
"ce6",
"ce7",
"ce8",
"ce9",
"ce10",
"ce11",
"host2wbm-desc-feed",
"host2reo-re-injection",
"host2reo-command",
"host2rxdma-monitor-ring1",
"reo2ost-exception",
"wbm2host-rx-release",
"reo2host-status",
"reo2host-destination-ring4",
"reo2host-destination-ring3",
"reo2host-destination-ring2",
"reo2host-destination-ring1",
"rxdma2host-monitor-destination-mac3",
"rxdma2host-monitor-destination-mac2",
"rxdma2host-monitor-destination-mac1",
"host2rxdma-host-buf-ring-mac3",
"host2rxdma-host-buf-ring-mac2",
"host2rxdma-host-buf-ring-mac1",
"host2tcl-input-ring4",
"host2tcl-input-ring3",
"host2tcl-input-ring2",
"host2tcl-input-ring1",
"wbm2host-tx-completions-ath-ring4",
"wbm2host-tx-completions-ring4",
"wbm2host-tx-completions-ring3",
"wbm2host-tx-completions-ring2",
"wbm2host-tx-completions-ring1",
"host2tx-monitor-ring1",
"txmon2host-monitor-destination-mac3",
"txmon2host-monitor-destination-mac2",
"txmon2host-monitor-destination-mac1",
"umac_reset",
/* Unused Interrupts */
"host2rxdma-monitor-ring3",
"host2rxdma-monitor-ring2",
"ppdu-end-interrupts-mac3",
"ppdu-end-interrupts-mac2",
"ppdu-end-interrupts-mac1",
"rxdma2host-monitor-status-ring-mac3",
"rxdma2host-monitor-status-ring-mac2",
"rxdma2host-monitor-status-ring-mac1",
"rxdma2host-destination-ring-mac3",
"rxdma2host-destination-ring-mac2",
"rxdma2host-destination-ring-mac1";
qcom,pta-num = <0>;
qcom,coex-mode = <0x2>;
qcom,bt-active-time = <0x18>;
qcom,bt-priority-time = <0x12>;
qcom,coex-algo = <0x2>;
qcom,pta-priority = <0x80800505>;
status = "disabled";
};
wifi1: wifi1@c0000000 {
compatible = "qcom,cnss-qcn6432" , "qcom,qcn6432-wifi";
msi-parent = <&v2m0>;
status = "disabled";
};
wifi2: wifi2@c0000000 {
compatible = "qcom,cnss-qcn6432" , "qcom,qcn6432-wifi";
msi-parent = <&v2m0>;
status = "disabled";
};
wifi3: wifi3@f00000 {
compatible = "qcom,cnss-qcn9224";
qcom,wlan-ramdump-dynamic = <0x600000>;
qca,auto-restart;
interrupt-bmap = <0x100512>;
#ifdef __IPQ_MEM_PROFILE_512_MB__
/* qcn9224 tgt-mem-mode=1 layout - 37MB
* +=========+==============+=========+
* | Region | Start Offset | Size |
* +---------+--------------+---------+
* | HREMOTE | 0x4ED00000 | 20MB |
* +---------+--------------+---------+
* | M3 Dump | 0x50100000 | 1MB |
* +---------+--------------+---------+
* | ETR | 0x50200000 | 1MB |
* +---------+--------------+---------+
* | Caldb | 0x50300000 | 8MB |
* +---------+--------------+---------+
* |Pageable | 0x50B00000 | 7MB |
* +==================================+
*/
base-addr = <0x4ED00000>;
m3-dump-addr = <0x50100000>;
etr-addr = <0x50200000>;
caldb-addr = <0x50300000>;
pageable-addr = <0x50B00000>;
hremote-size = <0x1400000>;
pageable-size = <0x700000>;
tgt-mem-mode = <0x1>;
#else
/* qcn9224 tgt-mem-mode=0 layout - 50MB
* +=========+==============+=========+
* | Region | Start Offset | Size |
* +---------+--------------+---------+
* | HREMOTE | 0x4ED00000 | 28MB |
* +---------+--------------+---------+
* | M3 Dump | 0x50900000 | 1MB |
* +---------+--------------+---------+
* | ETR | 0x50A00000 | 1MB |
* +---------+--------------+---------+
* | Caldb | 0x50B00000 | 8MB |
* +---------+--------------+---------+
* |Pageable | 0x51300000 | 12MB |
* +==================================+
*/
base-addr = <0x4ED00000>;
m3-dump-addr = <0x50900000>;
etr-addr = <0x50A00000>;
caldb-addr = <0x50B00000>;
pageable-addr = <0x51300000>;
hremote-size = <0x1C00000>;
pageable-size = <0xC00000>;
tgt-mem-mode = <0x0>;
#endif
caldb-size = <0x800000>;
qca,extended-intc;
interrupts-extended =
<&qcn9224_in0 5 0>,
<&qcn9224_in0 6 0>,
<&qcn9224_in0 7 0>,
<&qcn9224_in0 8 0>,
<&qcn9224_in0 9 0>,
<&qcn9224_in0 10 0>,
<&qcn9224_in0 11 0>,
<&qcn9224_in0 12 0>,
<&qcn9224_in0 13 0>,
<&qcn9224_in0 14 0>,
<&qcn9224_in0 15 0>,
<&qcn9224_in0 16 0>,
<&qcn9224_in0 17 0>,
<&qcn9224_in0 18 0>,
<&qcn9224_in0 19 0>,
<&qcn9224_in0 20 0>,
<&qcn9224_in0 49 0>,
<&qcn9224_in0 48 0>,
<&qcn9224_in0 47 0>,
<&qcn9224_in0 46 0>,
<&qcn9224_in0 45 0>,
<&qcn9224_in0 44 0>,
<&qcn9224_in0 43 0>,
<&qcn9224_in0 42 0>,
<&qcn9224_in0 50 0>,
<&qcn9224_in0 52 0>,
<&qcn9224_in0 51 0>,
<&qcn9224_in0 30 0>,
<&qcn9224_in0 29 0>,
<&qcn9224_in0 28 0>,
<&qcn9224_in0 27 0>,
<&qcn9224_in0 26 0>,
<&qcn9224_in0 25 0>,
<&qcn9224_in0 31 0>,
<&qcn9224_in0 80 0>,
<&qcn9224_in0 71 0>,
<&qcn9224_in0 96 0>,
<&qcn9224_in0 97 0>,
<&qcn9224_in0 67 0>,
<&qcn9224_in0 100 0>,
<&qcn9224_in0 99 0>,
<&qcn9224_in0 68 0>,
<&qcn9224_in0 69 0>,
<&qcn9224_in0 121 0>,
<&qcn9224_in0 119 0>,
<&qcn9224_in0 122 0>,
<&qcn9224_in0 120 0>,
<&qcn9224_in0 116 0>,
<&qcn9224_in0 113 0>,
<&qcn9224_in0 115 0>,
<&qcn9224_in0 112 0>,
<&qcn9224_in0 114 0>,
<&qcn9224_in0 111 0>,
<&qcn9224_in0 110 0>,
<&qcn9224_in0 109 0>,
<&qcn9224_in0 108 0>,
<&qcn9224_in0 39 0>,
<&qcn9224_in0 38 0>,
<&qcn9224_in0 37 0>,
<&qcn9224_in0 36 0>,
<&qcn9224_in0 35 0>,
<&qcn9224_in0 34 0>,
<&qcn9224_in0 33 0>,
<&qcn9224_in0 41 0>,
<&qcn9224_in0 40 0>,
<&qcn9224_in0 32 0>,
<&qcn9224_in0 24 0>,
<&qcn9224_in0 23 0>,
<&qcn9224_in0 22 0>,
<&qcn9224_in0 21 0>,
<&qcn9224_in0 66 0>,
<&qcn9224_in0 78 0>,
<&qcn9224_in0 117 0>,
<&qcn9224_in0 118 0>,
<&qcn9224_in0 61 0>,
<&qcn9224_in0 60 0>,
<&qcn9224_in0 57 0>,
<&qcn9224_in0 56 0>,
<&qcn9224_in0 63 0>,
<&qcn9224_in0 62 0>,
<&qcn9224_in0 59 0>,
<&qcn9224_in0 58 0>,
<&qcn9224_in0 65 0>,
<&qcn9224_in0 83 0>,
<&qcn9224_in0 75 0>,
<&qcn9224_in0 82 0>,
<&qcn9224_in0 81 0>,
<&qcn9224_in0 74 0>,
<&qcn9224_in0 73 0>,
<&qcn9224_in0 72 0>,
<&qcn9224_in0 98 0>,
<&qcn9224_in0 107 0>,
<&qcn9224_in0 106 0>,
<&qcn9224_in0 105 0>,
<&qcn9224_in0 104 0>,
<&qcn9224_in0 103 0>,
<&qcn9224_in0 102 0>,
<&qcn9224_in0 101 0>,
<&qcn9224_in0 76 0>,
<&qcn9224_in0 77 0>,
<&qcn9224_in0 143 0>,
<&qcn9224_in0 142 0>,
<&qcn9224_in0 141 0>,
<&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ce0",
"ce1",
"ce2",
"ce3",
"ce4",
"ce5",
"ce6",
"ce7",
"ce8",
"ce9",
"ce10",
"ce11",
"ce12",
"ce13",
"ce14",
"ce15",
"reo2sw8_intr2",
"reo2sw7_intr2",
"reo2sw6_intr2",
"reo2sw5_intr2",
"reo2sw4_intr2",
"reo2sw3_intr2",
"reo2sw2_intr2",
"reo2sw1_intr2",
"reo2sw0_intr2",
"reo2sw8_intr",
"reo2sw7_intr",
"reo2sw6_inrr",
"reo2sw5_intr",
"reo2sw4_intr",
"reo2sw3_intr",
"reo2sw2_intr",
"reo2sw1_intr",
"reo2sw0_intr",
"reo2status_intr2",
"reo_status",
"reo2rxdma_out_2",
"reo2rxdma_out_1",
"reo_cmd",
"sw2reo6",
"sw2reo5",
"sw2reo1",
"sw2reo",
"rxdma2reo_mlo_0_dst_ring1",
"rxdma2reo_mlo_0_dst_ring0",
"rxdma2reo_mlo_1_dst_ring1",
"rxdma2reo_mlo_1_dst_ring0",
"rxdma2reo_dst_ring1",
"rxdma2reo_dst_ring0",
"rxdma2sw_dst_ring1",
"rxdma2sw_dst_ring0",
"rxdma2release_dst_ring1",
"rxdma2release_dst_ring0",
"sw2rxdma_2_src_ring",
"sw2rxdma_1_src_ring",
"sw2rxdma_0",
"wbm2sw6_release2",
"wbm2sw5_release2",
"wbm2sw4_release2",
"wbm2sw3_release2",
"wbm2sw2_release2",
"wbm2sw1_release2",
"wbm2sw0_release2",
"wbm2sw6_release",
"wbm2sw5_release",
"wbm2sw4_release",
"wbm2sw3_release",
"wbm2sw2_release",
"wbm2sw1_release",
"wbm2sw0_release",
"wbm2sw_link",
"wbm_error_release",
"sw2txmon_src_ring",
"sw2rxmon_src_ring",
"txmon2sw_p1_intr1",
"txmon2sw_p1_intr0",
"txmon2sw_p0_dest1",
"txmon2sw_p0_dest0",
"rxmon2sw_p1_intr1",
"rxmon2sw_p1_intr0",
"rxmon2sw_p0_dest1",
"rxmon2sw_p0_dest0",
"sw_release",
"sw2tcl_credit2",
"sw2tcl_credit",
"sw2tcl4",
"sw2tcl5",
"sw2tcl3",
"sw2tcl2",
"sw2tcl1",
"sw2wbm1",
"misc_8",
"misc_7",
"misc_6",
"misc_5",
"misc_4",
"misc_3",
"misc_2",
"misc_1",
"misc_0",
"mhi2",
"mhi1",
"mhi0",
"inta";
status = "disabled";
};
wifi4: wifi4@f00000 {
compatible = "qcom,cnss-qcn9224";
qcom,wlan-ramdump-dynamic = <0x600000>;
qca,auto-restart;
interrupt-bmap = <0x100512>;
#ifdef __IPQ_MEM_PROFILE_512_MB__
/* qcn9224 tgt-mem-mode=1 layout - 37MB
* +=========+==============+=========+
* | Region | Start Offset | Size |
* +---------+--------------+---------+
* | HREMOTE | 0x51200000 | 20MB |
* +---------+--------------+---------+
* | M3 Dump | 0x52600000 | 1MB |
* +---------+--------------+---------+
* | ETR | 0x52700000 | 1MB |
* +---------+--------------+---------+
* | Caldb | 0x52800000 | 8MB |
* +---------+--------------+---------+
* |Pageable | 0x53000000 | 7MB |
* +==================================+
*/
base-addr = <0x51200000>;
m3-dump-addr = <0x52600000>;
etr-addr = <0x52700000>;
caldb-addr = <0x52800000>;
pageable-addr = <0x53000000>;
hremote-size = <0x1400000>;
pageable-size = <0x700000>;
tgt-mem-mode = <0x1>;
#else
/* qcn9224 tgt-mem-mode=0 layout - 50MB
* +=========+==============+=========+
* | Region | Start Offset | Size |
* +---------+--------------+---------+
* | HREMOTE | 0x51F00000 | 28MB |
* +---------+--------------+---------+
* | M3 Dump | 0x53B00000 | 1MB |
* +---------+--------------+---------+
* | ETR | 0x53C00000 | 1MB |
* +---------+--------------+---------+
* | Caldb | 0x53D00000 | 8MB |
* +---------+--------------+---------+
* |Pageable | 0x54500000 | 12MB |
* +==================================+
*/
base-addr = <0x51F00000>;
m3-dump-addr = <0x53B00000>;
etr-addr = <0x53C00000>;
caldb-addr = <0x53D00000>;
pageable-addr = <0x54500000>;
hremote-size = <0x1C00000>;
pageable-size = <0xC00000>;
tgt-mem-mode = <0x0>;
#endif
caldb-size = <0x800000>;
qca,extended-intc;
interrupts-extended =
<&qcn9224_in1 5 0>,
<&qcn9224_in1 6 0>,
<&qcn9224_in1 7 0>,
<&qcn9224_in1 8 0>,
<&qcn9224_in1 9 0>,
<&qcn9224_in1 10 0>,
<&qcn9224_in1 11 0>,
<&qcn9224_in1 12 0>,
<&qcn9224_in1 13 0>,
<&qcn9224_in1 14 0>,
<&qcn9224_in1 15 0>,
<&qcn9224_in1 16 0>,
<&qcn9224_in1 17 0>,
<&qcn9224_in1 18 0>,
<&qcn9224_in1 19 0>,
<&qcn9224_in1 20 0>,
<&qcn9224_in1 49 0>,
<&qcn9224_in1 48 0>,
<&qcn9224_in1 47 0>,
<&qcn9224_in1 46 0>,
<&qcn9224_in1 45 0>,
<&qcn9224_in1 44 0>,
<&qcn9224_in1 43 0>,
<&qcn9224_in1 42 0>,
<&qcn9224_in1 50 0>,
<&qcn9224_in1 52 0>,
<&qcn9224_in1 51 0>,
<&qcn9224_in1 30 0>,
<&qcn9224_in1 29 0>,
<&qcn9224_in1 28 0>,
<&qcn9224_in1 27 0>,
<&qcn9224_in1 26 0>,
<&qcn9224_in1 25 0>,
<&qcn9224_in1 31 0>,
<&qcn9224_in1 80 0>,
<&qcn9224_in1 71 0>,
<&qcn9224_in1 96 0>,
<&qcn9224_in1 97 0>,
<&qcn9224_in1 67 0>,
<&qcn9224_in1 100 0>,
<&qcn9224_in1 99 0>,
<&qcn9224_in1 68 0>,
<&qcn9224_in1 69 0>,
<&qcn9224_in1 121 0>,
<&qcn9224_in1 119 0>,
<&qcn9224_in1 122 0>,
<&qcn9224_in1 120 0>,
<&qcn9224_in1 116 0>,
<&qcn9224_in1 113 0>,
<&qcn9224_in1 115 0>,
<&qcn9224_in1 112 0>,
<&qcn9224_in1 114 0>,
<&qcn9224_in1 111 0>,
<&qcn9224_in1 110 0>,
<&qcn9224_in1 109 0>,
<&qcn9224_in1 108 0>,
<&qcn9224_in1 39 0>,
<&qcn9224_in1 38 0>,
<&qcn9224_in1 37 0>,
<&qcn9224_in1 36 0>,
<&qcn9224_in1 35 0>,
<&qcn9224_in1 34 0>,
<&qcn9224_in1 33 0>,
<&qcn9224_in1 41 0>,
<&qcn9224_in1 40 0>,
<&qcn9224_in1 32 0>,
<&qcn9224_in1 24 0>,
<&qcn9224_in1 23 0>,
<&qcn9224_in1 22 0>,
<&qcn9224_in1 21 0>,
<&qcn9224_in1 66 0>,
<&qcn9224_in1 78 0>,
<&qcn9224_in1 117 0>,
<&qcn9224_in1 118 0>,
<&qcn9224_in1 61 0>,
<&qcn9224_in1 60 0>,
<&qcn9224_in1 57 0>,
<&qcn9224_in1 56 0>,
<&qcn9224_in1 63 0>,
<&qcn9224_in1 62 0>,
<&qcn9224_in1 59 0>,
<&qcn9224_in1 58 0>,
<&qcn9224_in1 65 0>,
<&qcn9224_in1 83 0>,
<&qcn9224_in1 75 0>,
<&qcn9224_in1 82 0>,
<&qcn9224_in1 81 0>,
<&qcn9224_in1 74 0>,
<&qcn9224_in1 73 0>,
<&qcn9224_in1 72 0>,
<&qcn9224_in1 98 0>,
<&qcn9224_in1 107 0>,
<&qcn9224_in1 106 0>,
<&qcn9224_in1 105 0>,
<&qcn9224_in1 104 0>,
<&qcn9224_in1 103 0>,
<&qcn9224_in1 102 0>,
<&qcn9224_in1 101 0>,
<&qcn9224_in1 76 0>,
<&qcn9224_in1 77 0>,
<&qcn9224_in1 143 0>,
<&qcn9224_in1 142 0>,
<&qcn9224_in1 141 0>,
<&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ce0",
"ce1",
"ce2",
"ce3",
"ce4",
"ce5",
"ce6",
"ce7",
"ce8",
"ce9",
"ce10",
"ce11",
"ce12",
"ce13",
"ce14",
"ce15",
"reo2sw8_intr2",
"reo2sw7_intr2",
"reo2sw6_intr2",
"reo2sw5_intr2",
"reo2sw4_intr2",
"reo2sw3_intr2",
"reo2sw2_intr2",
"reo2sw1_intr2",
"reo2sw0_intr2",
"reo2sw8_intr",
"reo2sw7_intr",
"reo2sw6_inrr",
"reo2sw5_intr",
"reo2sw4_intr",
"reo2sw3_intr",
"reo2sw2_intr",
"reo2sw1_intr",
"reo2sw0_intr",
"reo2status_intr2",
"reo_status",
"reo2rxdma_out_2",
"reo2rxdma_out_1",
"reo_cmd",
"sw2reo6",
"sw2reo5",
"sw2reo1",
"sw2reo",
"rxdma2reo_mlo_0_dst_ring1",
"rxdma2reo_mlo_0_dst_ring0",
"rxdma2reo_mlo_1_dst_ring1",
"rxdma2reo_mlo_1_dst_ring0",
"rxdma2reo_dst_ring1",
"rxdma2reo_dst_ring0",
"rxdma2sw_dst_ring1",
"rxdma2sw_dst_ring0",
"rxdma2release_dst_ring1",
"rxdma2release_dst_ring0",
"sw2rxdma_2_src_ring",
"sw2rxdma_1_src_ring",
"sw2rxdma_0",
"wbm2sw6_release2",
"wbm2sw5_release2",
"wbm2sw4_release2",
"wbm2sw3_release2",
"wbm2sw2_release2",
"wbm2sw1_release2",
"wbm2sw0_release2",
"wbm2sw6_release",
"wbm2sw5_release",
"wbm2sw4_release",
"wbm2sw3_release",
"wbm2sw2_release",
"wbm2sw1_release",
"wbm2sw0_release",
"wbm2sw_link",
"wbm_error_release",
"sw2txmon_src_ring",
"sw2rxmon_src_ring",
"txmon2sw_p1_intr1",
"txmon2sw_p1_intr0",
"txmon2sw_p0_dest1",
"txmon2sw_p0_dest0",
"rxmon2sw_p1_intr1",
"rxmon2sw_p1_intr0",
"rxmon2sw_p0_dest1",
"rxmon2sw_p0_dest0",
"sw_release",
"sw2tcl_credit2",
"sw2tcl_credit",
"sw2tcl4",
"sw2tcl5",
"sw2tcl3",
"sw2tcl2",
"sw2tcl1",
"sw2wbm1",
"misc_8",
"misc_7",
"misc_6",
"misc_5",
"misc_4",
"misc_3",
"misc_2",
"misc_1",
"misc_0",
"mhi2",
"mhi1",
"mhi0",
"inta";
status = "disabled";
};
ess_instance: ess-instance {
compatible = "qcom,ess-instance";
ess-switch@3a000000 {
compatible = "qcom,ess-switch-ipq53xx";
reg = <0x3a000000 0x1000000>;
switch_access_mode = "local bus";
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
<&gcc GCC_UNIPHY0_SYS_CLK>,
<&gcc GCC_UNIPHY1_AHB_CLK>,
<&gcc GCC_UNIPHY1_SYS_CLK>,
<&gcc GCC_NSSNOC_NSSCC_CLK>,
<&gcc GCC_NSSCC_CLK>,
<&gcc GCC_NSSNOC_SNOC_1_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_IM_SLEEP_CLK>,
<&nsscc NSS_CC_PORT1_MAC_CLK>,
<&nsscc NSS_CC_PORT2_MAC_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
<&nsscc NSS_CC_NSSNOC_PPE_CLK>,
<&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>,
<&nsscc NSS_CC_PPE_EDMA_CLK>,
<&nsscc NSS_CC_PPE_EDMA_CFG_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>,
<&nsscc NSS_CC_PORT1_RX_CLK>,
<&nsscc NSS_CC_PORT1_TX_CLK>,
<&nsscc NSS_CC_PORT2_RX_CLK>,
<&nsscc NSS_CC_PORT2_TX_CLK>,
<&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>,
<&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>,
<&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>,
<&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>;
clock-names = "cmn_ahb_clk",
"cmn_sys_clk",
"uniphy0_ahb_clk",
"uniphy0_sys_clk",
"uniphy1_ahb_clk",
"uniphy1_sys_clk",
"gcc_nssnoc_nsscc_clk",
"gcc_nsscc_clk",
"gcc_nssnoc_snoc_1_clk",
"gcc_nssnoc_snoc_clk",
"gcc_im_sleep_clk",
"port1_mac_clk",
"port2_mac_clk",
"nss_ppe_clk",
"nss_ppe_cfg_clk",
"nssnoc_ppe_clk",
"nssnoc_ppe_cfg_clk",
"nss_edma_clk",
"nss_edma_cfg_clk",
"nss_ppe_ipe_clk",
"nss_ppe_btq_clk",
"nss_port1_rx_clk",
"nss_port1_tx_clk",
"nss_port2_rx_clk",
"nss_port2_tx_clk",
"uniphy0_port1_rx_clk",
"uniphy0_port1_tx_clk",
"uniphy1_port5_rx_clk",
"uniphy1_port5_tx_clk";
resets = <&nsscc NSS_CC_PPE_BCR>,
<&gcc GCC_UNIPHY0_BCR>,
<&gcc GCC_UNIPHY1_BCR>,
<&gcc GCC_UNIPHY0_AHB_CLK_ARES>,
<&gcc GCC_UNIPHY1_AHB_CLK_ARES>,
<&gcc GCC_UNIPHY0_SYS_CLK_ARES>,
<&gcc GCC_UNIPHY1_SYS_CLK_ARES>,
<&gcc GCC_UNIPHY0_XPCS_ARES>,
<&gcc GCC_UNIPHY1_XPCS_ARES>,
<&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK_ARES>,
<&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK_ARES>,
<&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK_ARES>,
<&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK_ARES>,
<&nsscc NSS_CC_PORT1_RX_CLK_ARES>,
<&nsscc NSS_CC_PORT1_TX_CLK_ARES>,
<&nsscc NSS_CC_PORT2_RX_CLK_ARES>,
<&nsscc NSS_CC_PORT2_TX_CLK_ARES>,
<&nsscc NSS_CC_PORT1_MAC_CLK_ARES>,
<&nsscc NSS_CC_PORT2_MAC_CLK_ARES>;
reset-names = "ppe_rst",
"uniphy0_soft_rst",
"uniphy1_soft_rst",
"uniphy0_ahb_rst",
"uniphy1_ahb_rst",
"uniphy0_sys_rst",
"uniphy1_sys_rst",
"uniphy0_xpcs_rst",
"uniphy1_xpcs_rst",
"uniphy_port1_rx_rst",
"uniphy_port1_tx_rst",
"uniphy_port2_rx_rst",
"uniphy_port2_tx_rst",
"nss_port1_rx_rst",
"nss_port1_tx_rst",
"nss_port2_rx_rst",
"nss_port2_tx_rst",
"nss_port1_mac_rst",
"nss_port2_mac_rst";
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 63>;
mcast_queue = <256 263>;
l0sp = <0 0>;
l0cdrr = <0 7>;
l0edrr = <0 7>;
l1cdrr = <0 0>;
l1edrr = <0 0>;
};
port@1 {
port_id = <1>;
ucast_queue = <204 211>;
mcast_queue = <272 275>;
l0sp = <51 52>;
l0cdrr = <108 115>;
l0edrr = <108 115>;
l1cdrr = <23 24>;
l1edrr = <23 24>;
};
port@2 {
port_id = <2>;
ucast_queue = <212 219>;
mcast_queue = <276 279>;
l0sp = <53 54>;
l0cdrr = <116 123>;
l0edrr = <116 123>;
l1cdrr = <25 26>;
l1edrr = <25 26>;
};
reserved {
ucast_queue = <64 203>;
mcast_queue = <264 271>;
l0sp = <1 50>;
l0cdrr = <8 107>;
l0edrr = <8 107>;
l1cdrr = <1 22>;
l1edrr = <1 22>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
/* L0 SP */
sp = <0>;
/* cpri cdrr epri edrr */
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/* unicast queue */
ucast_queue = <0>;
ucast_loop_pri = <8>;
/* multicast queue */
mcast_queue = <256>;
/* sp cpri cdrr epri edrr */
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <8>;
ucast_loop_pri = <8>;
mcast_queue = <257>;
cfg = <0 0 0 0 0>;
};
group@2 {
ucast_queue = <16>;
ucast_loop_pri = <8>;
mcast_queue = <258>;
cfg = <0 0 0 0 0>;
};
group@3 {
ucast_queue = <24>;
ucast_loop_pri = <8>;
mcast_queue = <259>;
cfg = <0 0 0 0 0>;
};
group@4 {
ucast_queue = <32>;
ucast_loop_pri = <8>;
mcast_queue = <260>;
cfg = <0 0 0 0 0>;
};
group@5 {
ucast_queue = <40>;
ucast_loop_pri = <8>;
mcast_queue = <261>;
cfg = <0 0 0 0 0>;
};
group@6 {
ucast_queue = <48>;
ucast_loop_pri = <8>;
mcast_queue = <262>;
cfg = <0 0 0 0 0>;
};
group@7 {
ucast_queue = <56>;
ucast_loop_pri = <8>;
mcast_queue = <263>;
cfg = <0 0 0 0 0>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <51>;
cfg = <0 23 0 23>;
};
group@1 {
sp = <52>;
cfg = <1 24 1 24>;
};
};
l0scheduler {
group@0 {
ucast_queue = <204>;
ucast_loop_pri = <8>;
/* max priority per SP */
ucast_max_pri = <4>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <51 0 108 0 108>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <53>;
cfg = <0 25 0 25>;
};
group@1 {
sp = <54>;
cfg = <1 26 1 26>;
};
};
l0scheduler {
group@0 {
ucast_queue = <212>;
ucast_loop_pri = <8>;
ucast_max_pri = <4>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <53 0 116 0 116>;
};
};
};
};
};
};
ess-uniphy@7a00000 {
compatible = "qcom,ess-uniphy";
reg = <0x7a00000 0x20000>;
uniphy_access_mode = "local bus";
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@b120000 {
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@b123000 {
reg = <0x0b123000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@b124000 {
reg = <0x0b124000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@b125000 {
reg = <0x0b125000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@b126000 {
reg = <0x0b126000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@b127000 {
reg = <0x0b127000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@b128000 {
reg = <0x0b128000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
/* 1L controller with 2L/2x1L Flexible PHY 2nd lane */
pcie2: pcie@10000000 {
compatible = "qti,pcie-ipq5332";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x10001000 0x1000>,
<0xf0000 0x3000>,
<0x10100000 0x1000>,
<0x59C188 0x4>;
reg-names = "dbi", "elbi", "atu", "parf", "config", "system_noc";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
axi-halt-val = <0x1e>; /* increase halt window size to 1GB */
ranges = <0x81000000 0 0x10200000 0x10200000 0 0x00100000>, /* downstream I/O */
<0x82000000 0 0x10300000 0x10300000 0 0x07d00000>; /* non-prefetchable memory */
phys = <&pcie2_phy>;
phy-names = "pciephy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 399 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 400 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 401 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 402 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global_irq";
clocks = <&gcc GCC_PCIE3X1_1_AXI_M_CLK>,
<&gcc GCC_PCIE3X1_1_AXI_S_CLK>,
<&gcc GCC_PCIE3X1_1_AHB_CLK>,
<&gcc GCC_PCIE3X2_AUX_CLK>,
<&gcc GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X1_1_RCHG_CLK>;
clock-names = "axi_m",
"axi_s",
"ahb",
"aux",
"axi_bridge",
"rchng";
assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
<&gcc GCC_PCIE3X1_1_AXI_M_CLK>,
<&gcc GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X1_1_AXI_S_CLK>,
<&gcc GCC_PCIE3X1_1_RCHG_CLK>;
assigned-clock-rates = <2000000>,
<240000000>,
<240000000>,
<240000000>,
<100000000>;
resets = <&gcc GCC_PCIE3X1_1_PIPE_ARES>,
<&gcc GCC_PCIE3X1_1_CORE_STICKY_ARES>,
<&gcc GCC_PCIE3X1_1_AXI_M_CLK_ARES>,
<&gcc GCC_PCIE3X1_1_AXI_S_CLK_ARES>,
<&gcc GCC_PCIE3X1_1_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE3X1_1_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE3X1_1_AHB_CLK_ARES>,
<&gcc GCC_PCIE3X1_1_AUX_CLK_ARES>;
reset-names = "pipe",
"sticky",
"axi_m",
"axi_s",
"axi_m_sticky",
"axi_s_sticky",
"ahb",
"aux";
msi-parent = <&v2m0>;
nvmem-cells = <&pcie2_disable>;
status = "disabled";
};
/* 1L controller with USB/PCIe combo PHY */
pcie0: pcie@20000000 {
compatible = "qti,pcie-ipq5332";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x20001000 0x1000>,
<0x80000 0x3000>,
<0x20100000 0x1000>,
<0x59C108 0x4>;
reg-names = "dbi", "elbi", "atu", "parf", "config", "system_noc";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
axi-halt-val = <0x1e>; /* increase halt window size to 1GB */
phys = <&pcie0_phy>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0x20200000 0 0x00100000>, /* downstream I/O */
<0x82000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global_irq";
clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
<&gcc GCC_PCIE3X1_0_AHB_CLK>,
<&gcc GCC_PCIE3X1_0_AUX_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X1_0_RCHG_CLK>;
clock-names = "axi_m",
"axi_s",
"ahb",
"aux",
"axi_bridge",
"rchng";
assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
<&gcc GCC_PCIE3X1_0_RCHG_CLK>;
assigned-clock-rates = <2000000>,
<240000000>,
<240000000>,
<240000000>,
<100000000>;
resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
<&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
<&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
<&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>,
<&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>;
reset-names = "pipe",
"sticky",
"axi_m",
"axi_s",
"axi_m_sticky",
"axi_s_sticky",
"ahb",
"aux";
msi-parent = <&v2m0>;
nvmem-cells = <&pcie0_disable>;
status = "disabled";
};
/* 2L controller with 2L/2x1L Flexible PHY.
* Connected to the 1st lane of the Flexible PHY in 1L mode
*/
pcie1: pcie@18000000 {
compatible = "qti,pcie-ipq5332";
reg = <0x18000000 0xf1d>,
<0x18000f20 0xa8>,
<0x18001000 0x1000>,
<0x88000 0x3000>,
<0x18100000 0x1000>,
<0x59C210 0x4>;
reg-names = "dbi", "elbi", "atu", "parf", "config", "system_noc";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
slv-addr-space-sz = <0x8000000>;
axi-halt-val = <0x1e>; /* increase halt window size to 1GB */
phys = <&pcie1_phy_x2>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x18200000 0x18200000 0 0x00100000>, /* downstream I/O */
<0x82000000 0 0x18300000 0x18300000 0 0x07d00000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 412 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 413 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 414 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global_irq";
clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
<&gcc GCC_PCIE3X2_AXI_S_CLK>,
<&gcc GCC_PCIE3X2_AHB_CLK>,
<&gcc GCC_PCIE3X2_AUX_CLK>,
<&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X2_RCHG_CLK>;
clock-names = "axi_m",
"axi_s",
"ahb",
"aux",
"axi_bridge",
"rchng";
assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
<&gcc GCC_PCIE3X2_AXI_M_CLK>,
<&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
<&gcc GCC_PCIE3X2_AXI_S_CLK>,
<&gcc GCC_PCIE3X2_RCHG_CLK>;
assigned-clock-rates = <2000000>,
<266666666>,
<240000000>,
<240000000>,
<100000000>;
resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
<&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
<&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
<&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
<&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
<&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
<&gcc GCC_PCIE3X2_AHB_CLK_ARES>,
<&gcc GCC_PCIE3X2_AUX_CLK_ARES>;
reset-names = "pipe",
"sticky",
"axi_m",
"axi_s",
"axi_m_sticky",
"axi_s_sticky",
"ahb",
"aux";
msi-parent = <&v2m0>;
nvmem-cells = <&pcie1_disable>;
status = "disabled";
};
ssuniphy_0: ssuniphy@4b0000 {
compatible = "qca,ipq5332-uni-ssphy";
reg = <0x4b0000 0x800>;
clocks = <&gcc GCC_USB0_PIPE_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
clock-names = "pipe_clk", "phy_cfg_ahb_clk",
"phy_ahb_clk";
resets = <&gcc GCC_USB0_PHY_BCR>;
reset-names = "por_rst";
#phy-cells = <0>;
status = "disabled";
};
hs_m31phy_0: hs_m31phy@7b000 {
compatible = "qcom,ipq5332-m31-usb-hsphy";
reg = <0x0007b000 0x12C>,
<0x08af8800 0x400>;
reg-names = "m31usb_phy_base",
"qscratch_base";
phy_type= "utmi";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
reset-names = "usb2_phy_reset";
status = "disabled";
};
usb3: usb3@8a00000 {
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_SNOC_USB_CLK>,
<&gcc GCC_USB0_SLEEP_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>,
<&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_LFPS_CLK>,
<&gcc GCC_USB0_PIPE_CLK>;
clock-names = "core",
"iface",
"sleep",
"mock_utmi",
"cfg_ahb_clk",
"aux_clk",
"lfps_clk",
"pipe_clk";
assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
<&gcc GCC_USB0_MOCK_UTMI_CLK>,
<&gcc GCC_USB0_AUX_CLK>,
<&gcc GCC_USB0_LFPS_CLK>;
assigned-clock-rates = <200000000>,
<60000000>,
<2000000>,
<25000000>;
resets = <&gcc GCC_USB_BCR>;
qcom,phy-mux-regs = <&tcsr 0x10540>;
dwc_0: dwc3@8a00000 {
compatible = "snps,dwc3";
reg = <0x08a00000 0xe000>;
clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clock-names = "ref";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&hs_m31phy_0>;
#phy-cells = <0>;
phys = <&ssuniphy_0>;
phy-names = "usb3-phy";
tx-fifo-resize;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,ref-clock-period-ns = <21>;
dr_mode = "host";
};
};
edma@3ab00000 {
compatible = "qcom,edma";
reg = <0x3ab00000 0xed000>;
reg-names = "edma-reg-base";
reset-names = "edma_rst";
clocks = <&nsscc NSS_CC_NSS_CSR_CLK>,
<&nsscc NSS_CC_NSSNOC_NSS_CSR_CLK>,
<&nsscc NSS_CC_CE_APB_CLK>,
<&nsscc NSS_CC_CE_AXI_CLK>,
<&nsscc NSS_CC_NSSNOC_CE_APB_CLK>,
<&nsscc NSS_CC_NSSNOC_CE_AXI_CLK>,
<&nsscc NSS_CC_PPE_EDMA_CLK>,
<&gcc GCC_NSS_TS_CLK>,
<&gcc GCC_NSSCC_CLK>,
<&gcc GCC_NSSCFG_CLK>,
<&gcc GCC_NSSNOC_ATB_CLK>,
<&gcc GCC_NSSNOC_NSSCC_CLK>,
<&gcc GCC_NSSNOC_PCNOC_1_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_NSSNOC_SNOC_1_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSSNOC_XO_DCD_CLK>,
<&gcc GCC_SNOC_NSSNOC_CLK>,
<&gcc GCC_SNOC_NSSNOC_1_CLK>;
clock-names = "nss-csr-clk", "nss-nssnoc-csr-clk", "nss-ce-ahb-clk",
"nss-ce-axi-clk", "nss-nssnoc-ce-ahb-clk", "nss-nssnoc-ce-axi-clk", "nss-edma-clk",
"nss-ts-clk", "nss-nsscc-clk", "nss-nsscfg-clk", "nss-nssnoc-atb-clk",
"nss-nssnoc-nsscc-clk", "nss-nssnoc-pcnoc-1-clk", "nss-nssnoc-qosgen-ref-clk",
"nss-nssnoc-snoc-1-clk", "nss-nssnoc-snoc-clk", "nss-nssnoc-timeout-ref-clk",
"nss-nssnoc-xo-dcd-clk", "nss-snoc-nssnoc-clk", "nss-snoc-nssnoc-1-clk";
};
nss-ppe {
compatible = "qcom,nss-ppe";
};
eip: eip196@39800000 {
compatible = "qcom,eip";
reg-names = "eip_pbase";
reg = <0x39800000 0x7ffff>;
reg_offset = <0x80000>;
ranges;
clocks = <&nsscc NSS_CC_EIP_CLK>,
<&nsscc NSS_CC_NSSNOC_EIP_CLK>;
clock-names = "eip_clk", "eip_nocclk";
clock-frequency = /bits/ 64 <300000000 300000000>;
status = "okay";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
dma0 {
tx_cpu = /bits/ 8 <0>;
rx_cpu = /bits/ 8 <0>;
ring-name = "lookaside";
ring-id = /bits/ 8 <0>;
};
dma1 {
tx_cpu = /bits/ 8 <1>;
rx_cpu = /bits/ 8 <1>;
ring-name = "lookaside";
ring-id = /bits/ 8 <1>;
};
dma2 {
tx_cpu = /bits/ 8 <2>;
rx_cpu = /bits/ 8 <2>;
ring-name = "lookaside";
ring-id = /bits/ 8 <2>;
};
dma3 {
tx_cpu = /bits/ 8 <3>;
rx_cpu = /bits/ 8 <3>;
ring-name = "lookaside";
ring-id = /bits/ 8 <3>;
};
};
eip_crypto: eip_crypto {
compatible = "qcom,eip_crypto";
status = "okay";
};
q6v5_wcss: remoteproc@d100000 {
compatible = "qcom,ipq5332-q6-mpd";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0xd100000 0x4040>;
interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
<&wcss_smp2p_in 0 0>,
<&wcss_smp2p_in 1 0>,
<&wcss_smp2p_in 2 0>,
<&wcss_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 0>,
<&wcss_smp2p_out 1>;
qcom,smem-state-names = "shutdown",
"stop";
memory-region = <&q6_region>;
qcom,bootargs_smem = <507>;
qcom,bootargs_version = <2>;
qcom,userpd-bootargs;
glink-edge {
interrupts = <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
label = "rtr";
qcom,remote-pid = <1>;
mboxes = <&apcs_glb 8>;
};
q6_wcss_pd1: remoteproc_pd1 {
compatible = "qcom,ipq5332-wcss-ahb-mpd";
m3_firmware = "IPQ5332/iu_fw.mdt";
interrupts-extended = <&wcss_smp2p_in 8 0>,
<&wcss_smp2p_in 9 0>,
<&wcss_smp2p_in 12 0>,
<&wcss_smp2p_in 11 0>;
interrupt-names = "fatal",
"ready",
"spawn-ack",
"stop-ack";
qcom,smem-states = <&wcss_smp2p_out 8>,
<&wcss_smp2p_out 9>,
<&wcss_smp2p_out 10>;
qcom,smem-state-names = "shutdown",
"stop",
"spawn";
};
};
};
license_manager: license_manager {
compatible = "qti,license-manager-service";
license-file = "";
status = "disabled";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
qcom,test@0 {
compatible = "qcom,testmhi";
qcom,wlan-ramdump-dynamic = <0x600000>;
};
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 9>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
thermal_zones: thermal-zones {
misc-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 13>;
trips {
misc-critical {
temperature = <125000>;
hysteresis = <9000>;
type = "critical";
};
};
};
cpu-top-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 14>;
trips {
cpu-top-critical {
temperature = <115000>;
hysteresis = <9000>;
type = "critical";
};
cpu-passive {
temperature = <105000>;
hysteresis = <9000>;
type = "passive";
};
};
};
top-glue-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 15>;
trips {
top-glue-critical {
temperature = <125000>;
hysteresis = <9000>;
type = "critical";
};
};
};
};
};
#ifndef __CPU_THERMAL__
#include "ipq5332-thermald.dtsi"
#endif
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