mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-29 09:32:34 +00:00
379 lines
6.9 KiB
Plaintext
Executable File
379 lines
6.9 KiB
Plaintext
Executable File
/dts-v1/;
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#include "mt7981.dtsi"
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/ {
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model = "EdgeCore EAP112";
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compatible = "edgecore,eap112";
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chosen {
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bootargs = "console=ttyS0,115200n1 loglevel=8 \
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earlycon=uart8250,mmio32,0x11002000";
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};
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aliases {
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led-boot = &led_green;
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led-failsafe = &led_green;
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led-running = &led_green;
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led-upgrade = &led_green;
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serial0 = &uart0;
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};
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memory {
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// fpga ddr2: 128MB*2
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reg = <0 0x40000000 0 0x20000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_green: led@0 {
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label = "green:power";
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gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
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};
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led_orange: led@1 {
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label = "orange:wan";
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gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
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};
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led_blue: led@2 {
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label = "blue:wlan5g";
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gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
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};
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};
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nmbm_spim_nand {
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compatible = "generic,nmbm";
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#address-cells = <1>;
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#size-cells = <1>;
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lower-mtd-device = <&spi_nand>;
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forced-create;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x00000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x180000 0x0200000>;
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};
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partition@380000 {
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label = "FIP";
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reg = <0x380000 0x0200000>;
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};
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partition@580000 {
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label = "rootfs1";
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reg = <0x580000 0x4000000>;
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compatible = "linux,ubi";
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};
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partition@4580000 {
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label = "rootfs2";
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reg = <0x4580000 0x4000000>;
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compatible = "linux,ubi";
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};
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};
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};
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sound_wm8960 {
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compatible = "mediatek,mt7986-wm8960-sound";
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audio-routing = "Headphone", "HP_L",
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"Headphone", "HP_R",
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"LINPUT1", "AMIC",
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"RINPUT1", "AMIC";
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status = "disabled";
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platform {
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sound-dai = <&afe>;
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};
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codec {
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sound-dai = <&wm8960>;
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};
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};
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sound_si3218x {
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compatible = "mediatek,mt7986-si3218x-sound";
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status = "disabled";
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platform {
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sound-dai = <&afe>;
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};
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codec {
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sound-dai = <&proslic_spi>;
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};
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};
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};
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&afe {
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pinctrl-names = "default";
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pinctrl-0 = <&pcm_pins>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "disabled";
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wm8960: wm8960@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "sgmii";
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phy-handle = <&phy1>; // add phy handler
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mtd-mac-address = <&factory 0x24>;
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "gmii";
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phy-handle = <&phy0>;
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mtd-mac-address = <&factory 0x2a>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id03a2.9461";
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reg = <0>;
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phy-mode = "gmii";
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nvmem-cells = <&phy_calibration>;
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nvmem-cell-names = "phy-cal-data";
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};
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id03a2.9471";
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reg = <24>; // set phy address to 0x18
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reset-gpios = <&pio 39 1>;
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reset-assert-us = <600>;
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reset-deassert-us = <20000>;
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phy-mode = "sgmii";
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};
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};
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};
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&hnat {
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mtketh-wan = "eth1";
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mtketh-lan = "lan";
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mtketh-max-gmac = <2>;
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status = "okay";
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand: spi_nand@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic_pins>;
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status = "okay";
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proslic_spi: proslic_spi@0 {
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compatible = "silabs,proslic_spi";
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reg = <0>;
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spi-max-frequency = <10000000>;
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spi-cpha = <1>;
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spi-cpol = <1>;
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channel_count = <1>;
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debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
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reset_gpio = <&pio 15 0>;
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ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
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};
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};
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&wbsys {
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mediatek,mtd-eeprom = <&factory 0x0000>;
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status = "okay";
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pinctrl-names = "dbdc";
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pinctrl-0 = <&wf_dbdc_pins>;
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};
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&spi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_pins>;
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status = "okay";
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slb9670: slb9670@0 {
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compatible = "infineon,slb9670";
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reg = <0>; /* CE0 */
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#address-cells = <1>;
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#size-cells = <0>;
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spi-cal-enable;
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spi-cal-mode = "read-data";
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spi-cal-datalen = <2>;
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spi-cal-data = /bits/ 8 <0x00 0x1b>;
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spi-max-frequency = <40000000>;
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};
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};
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&pio {
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i2c_pins: i2c-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c0_0";
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};
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};
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pcm_pins: pcm-pins-g0 {
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mux {
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function = "pcm";
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groups = "pcm";
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};
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};
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pwm0_pin: pwm0-pin-g0 {
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mux {
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function = "pwm";
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groups = "pwm0_0";
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};
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};
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pwm1_pin: pwm1-pin-g0 {
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mux {
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function = "pwm";
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groups = "pwm1_0";
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};
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};
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pwm2_pin: pwm2-pin {
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mux {
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function = "pwm";
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groups = "pwm2";
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};
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};
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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spic_pins: spi1-pins {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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};
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spi2_pins: spi2-pins {
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mux {
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function = "spi";
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groups = "spi2";
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};
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};
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uart1_pins: uart1-pins-g1 {
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mux {
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function = "uart";
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groups = "uart1_1";
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};
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};
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uart2_pins: uart2-pins-g1 {
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mux {
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function = "uart";
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groups = "uart2_1";
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};
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};
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wf_dbdc_pins: wf_dbdc-pins {
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mux {
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function = "eth";
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groups = "wf0_mode1";
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};
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conf {
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pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
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"WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
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"WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
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"WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
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"WF_CBA_RESETB", "WF_DIG_RESETB";
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drive-strength = <MTK_DRIVE_4mA>;
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};
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};
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};
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&xhci {
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mediatek,u3p-dis-msk = <0x0>;
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>;
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status = "okay";
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};
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