mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-29 09:32:34 +00:00
581 lines
15 KiB
Plaintext
581 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ5332 RDP468 board device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "ipq5332.dtsi"
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#include "ipq5332-default-memory.dtsi"
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/ {
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model = "CIG WF672";
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compatible = "cig,wf672", "qcom,ipq5332-rdp468", "qcom,ipq5332";
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ramoops@49c00000 {
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compatible = "ramoops";
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no-map;
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reg = <0x0 0x49c00000 0x0 0x50000>;
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record-size = <0x20000>;
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console-size = <0x8000>;
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pmsg-size = <0x8000>;
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};
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};
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aliases {
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serial0 = &blsp1_uart0;
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serial1 = &blsp1_uart1;
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ethernet0 = "/soc/dp1";
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ethernet1 = "/soc/dp2";
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led-boot = &led_power_green;
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led-failsafe = &led_power_red;
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led-running = &led_power_green;
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led-upgrade = &led_power_green;
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};
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chosen {
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stdout-path = "serial0";
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};
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soc@0 {
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mdio:mdio@90000 {
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pinctrl-0 = <&mdio1_pins>;
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pinctrl-names = "default";
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/*gpio51 for manhattan reset*/
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phy-reset-gpio = <&tlmm 21 GPIO_ACTIVE_LOW>;
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phyaddr_fixup = <0xC90F018>;
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uniphyaddr_fixup = <0xC90F014>;
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mdio_clk_fixup; /* MDIO clock sequence fix up flag */
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <1>;
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compatible ="ethernet-phy-ieee802.3-c45";
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fixup;
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};
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phy1: ethernet-phy@1 {
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reg = <30>;
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fixup;
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};
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};
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ess-instance {
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num_devices = <0x1>;
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ess-switch@3a000000 {
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pinctrl-0 = <&sfp_pins>;
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pinctrl-names = "default";
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switch_cpu_bmp = <0x1>; /* cpu port bitmap */
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switch_lan_bmp = <0x2>; /* lan port bitmap */
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switch_wan_bmp = <0x4>; /* wan port bitmap */
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switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/
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switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
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switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
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qcom,port_phyinfo {
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port@0 {
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port_id = <1>;
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phy_address = <1>;
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ethernet-phy-ieee802.3-c45;
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forced-speed = <2500>;
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forced-duplex = <1>;
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mdiobus = <&mdio>;
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};
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port@1 {
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port_id = <2>;
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phy_address = <30>;
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phy_i2c_address =<30>;
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phy-i2c-mode;
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sfp_rx_los_pin = <&tlmm 43 0>;
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sfp_mod_present_pin = <&tlmm 45 0>;
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sfp_tx_dis_pin = <&extgpio 11 0>;
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media-type = "sfp"; /* fiber mode */
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};
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};
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};
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};
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dp2 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <1>;
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reg = <0x3a500000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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mdio-bus = <&mdio>;
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qcom,phy-mdio-addr = <1>;
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qcom,link-poll = <1>;
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phy-mode = "sgmii";
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};
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gmac2:dp1 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <2>;
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reg = <0x3a504000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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qcom,phy-mdio-addr = <30>;
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qcom,link-poll = <1>;
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phy-mode = "sgmii";
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};
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x5-cpe {
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compatible = "x55-poweron";
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pwykey = <&extgpio2 13 0>;
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status = "ok";
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};
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/* EDMA host driver configuration for the board */
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edma@3ab00000 {
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qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */
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qcom,txdesc-rings = <12>; /* Total number of Tx desc rings to be provisioned */
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qcom,mht-txdesc-rings = <8>; /* Extra Tx desc rings to be provisioned for MHT SW ports */
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qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */
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qcom,txcmpl-rings = <12>; /* Total number of Tx complete rings to be provisioned */
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qcom,mht-txcmpl-rings = <8>; /* Extra Tx complete rings to be provisioned for mht sw ports. */
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qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */
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qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */
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qcom,rxdesc-ring-start = <12>; /* Rx desc ring start ID */
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qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */
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qcom,rx-page-mode = <0>; /* Rx fill ring page mode */
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qcom,tx-map-priority-level = <1>; /* Tx priority level per port */
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qcom,rx-map-priority-level = <1>; /* Rx priority level per core */
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qcom,ppeds-num = <2>; /* Number of PPEDS nodes */
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/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
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qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node#0 ring and queue map */
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<2 2 2 2 40 8>; /* PPEDS Node#1 ring and queue map */
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qcom,txdesc-map = <8 9 10 11>, /* Port0 per-core Tx ring map */
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<12 13 14 15>, /* MHT-Port1 per-core Tx ring map */
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<4 5 6 7>, /* MHT-Port2 per-core Tx ring map/packets from vp*/
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<16 17 18 19>, /* MHT-Port3 per-core Tx ring map */
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<20 21 22 23>; /* MHT-Port4 per-core Tx ring map */
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qcom,txdesc-fc-grp-map = <1 2 3 4 5>; /* Per GMAC flow control group map */
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qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */
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qcom,rxdesc-map = <12 13 14 15>; /* Per-core Rx desc ring map */
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qcom,rx-queue-start = <0>; /* Rx queue start */
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qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */
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<1 9 17 25>, /* Priority 1 queues per-core Rx ring map */
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<2 10 18 26>, /* Priority 2 queues per-core Rx ring map */
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<3 11 19 27>, /* Priority 3 queues per-core Rx ring map */
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<4 12 20 28>, /* Priority 4 queues per-core Rx ring map */
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<5 13 21 29>, /* Priority 5 queues per-core Rx ring map */
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<6 14 22 30>, /* Priority 6 queues per-core Rx ring map */
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<7 15 23 31>; /* Priority 7 queues per-core Rx ring map */
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interrupts = <0 163 4>, /* Tx complete ring id #4 IRQ info */
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<0 164 4>, /* Tx complete ring id #5 IRQ info */
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<0 165 4>, /* Tx complete ring id #6 IRQ info */
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<0 166 4>, /* Tx complete ring id #7 IRQ info */
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<0 167 4>, /* Tx complete ring id #8 IRQ info */
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<0 168 4>, /* Tx complete ring id #9 IRQ info */
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<0 169 4>, /* Tx complete ring id #10 IRQ info */
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<0 170 4>, /* Tx complete ring id #11 IRQ info */
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<0 171 4>, /* Tx complete ring id #12 IRQ info */
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<0 172 4>, /* Tx complete ring id #13 IRQ info */
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<0 173 4>, /* Tx complete ring id #14 IRQ info */
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<0 174 4>, /* Tx complete ring id #15 IRQ info */
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<0 139 4>, /* Rx desc ring id #12 IRQ info */
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<0 140 4>, /* Rx desc ring id #13 IRQ info */
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<0 141 4>, /* Rx desc ring id #14 IRQ info */
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<0 142 4>, /* Rx desc ring id #15 IRQ info */
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<0 191 4>, /* Misc error IRQ info */
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<0 160 4>, /* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
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<0 128 4>, /* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
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<0 152 4>, /* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
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<0 161 4>, /* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
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<0 129 4>, /* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
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<0 153 4>, /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
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<0 175 4>, /* MHT port Tx complete ring id #16 IRQ info */
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<0 176 4>, /* MHT port Tx complete ring id #17 IRQ info */
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<0 177 4>, /* MHT port Tx complete ring id #18 IRQ info */
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<0 178 4>, /* MHT port Tx complete ring id #19 IRQ info */
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<0 179 4>, /* MHT port Tx complete ring id #20 IRQ info */
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<0 180 4>, /* MHT port Tx complete ring id #21 IRQ info */
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<0 181 4>, /* MHT port Tx complete ring id #22 IRQ info */
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<0 182 4>; /* MHT port Tx complete ring id #23 IRQ info */
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};
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pwmleds {
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compatible = "pwm-leds";
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led_power_red:red {
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label = "pwm:red";
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pwms = <&pwm 3 1250000>;
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max-brightness = <160>;
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linux,default-trigger = "none";
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default-state = "off";
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};
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led_power_green:green {
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label = "pwm:green";
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pwms = <&pwm 2 1250000>;
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max-brightness = <160>;
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linux,default-trigger = "none";
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default-state = "off";
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};
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led_power_blue: blue {
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label = "pwm:blue";
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pwms = <&pwm 1 1250000>;
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max-brightness = <160>;
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linux,default-trigger = "none";
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default-state = "off";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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status = "okay";
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button@1 {
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label = "rst";
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linux,code = <KEY_RESTART>;
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gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
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linux,input-type = <1>;
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debounce-interval = <60>;
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};
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};
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poe {
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compatible = "poe-judge";
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detect-mode = <0x4>;
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detect-gpio1 = <&extgpio 0 0>;
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detect-gpio2 = <&extgpio 1 0>;
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detect-gpio3 = <&extgpio 2 0>;
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status = "ok";
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};
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wsi: wsi {
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id = <0>;
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num_chip = <2>;
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status = "okay";
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chip_info = <0 1 1>,
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<1 1 0>;
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};
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};
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};
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&wifi0 {
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led-gpio = <&tlmm 36 GPIO_ACTIVE_HIGH>;
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qcom,rproc = <&q6_wcss_pd1>;
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qcom,rproc_rpd = <&q6v5_wcss>;
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qcom,multipd_arch;
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qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
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memory-region = <&q6_region>;
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qcom,wsi = <&wsi>;
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qcom,wsi_index = <0>;
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qcom,board_id = <0x12>;
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status = "okay";
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};
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&qcn9224_pcie1 {
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status = "okay";
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};
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&blsp1_uart0 {
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pinctrl-0 = <&serial_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&blsp1_uart1 {
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pinctrl-0 = <&serial_1_pins &pta_slic>;
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pinctrl-names = "default";
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status = "okay";
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};
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&blsp1_i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c_1_pins>;
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pinctrl-names = "default";
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extgpio:pca9555@20{
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compatible = "nxp,pca9555";
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reg = <0x20>;
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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extgpio2:pca9555@21{
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compatible = "nxp,pca9555";
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reg = <0x21>;
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pinctrl-names = "default";
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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lsm303_acc@19{
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compatible = "st,lsm303agr_acc";
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reg = <0x19>;
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};
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lsm303_mag@1e{
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compatible = "st,lsm303agr_mag";
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reg = <0x1e>;
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};
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ilps22qs@5c{
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compatible = "st,ilps22qs";
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reg = <0x5c>;
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};
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temp-sense@70 {
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compatible = "ti,tmp103";
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reg = <0x70>;
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};
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};
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&blsp1_spi0 {
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pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "n25q128a11", "micron,n25q128a11", "jedec,spi-nor";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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};
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};
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&blsp1_spi2 {
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pinctrl-0 = <&spi_2_pins>;
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pinctrl-names = "default";
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cs-select = <0>;
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status = "disabled";
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};
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&sdhc {
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bus-width = <4>;
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max-frequency = <192000000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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pinctrl-0 = <&sdc_default_state>;
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reset = <&tlmm 20 0>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&xo {
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clock-frequency = <24000000>;
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};
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&qpic_bam {
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status = "okay";
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};
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&pcie1_phy_x2 {
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status = "okay";
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};
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&pcie0_phy {
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status = "okay";
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};
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&pcie0 {
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pinctrl-0 = <&pcie0_default_state>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie1 {
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pinctrl-0 = <&pcie1_default_state>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
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status = "okay";
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pcie1_rp {
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reg = <0 0 0 0 0>;
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qcom,mhi@1 {
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reg = <0 0 0 0 0>;
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boot-args = <0x2 0x4 0x34 0x3 0x0 0x0 /* MX Rail, GPIO52, Drive strength 0x3 */
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0x4 0x4 0x18 0x3 0x0 0x0 /* RFA1p2 Rail, GPIO24, Drive strength 0x3 */
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0x0 0x4 0x0 0x0 0x0 0x0>; /* End of arguments */
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memory-region = <&qcn9224_pcie1>;
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qcom,wsi = <&wsi>;
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qcom,wsi_index = <1>;
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qcom,board_id = <0x1015>;
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};
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};
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};
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/* PINCTRL */
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&tlmm {
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i2c_1_pins: i2c-1-state {
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pins = "gpio29", "gpio30";
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function = "blsp1_i2c0";
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drive-strength = <8>;
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bias-pull-up;
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};
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spi_2_pins: spi-2-pins {
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pins = "gpio33", "gpio34", "gpio35", "gpio36";
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function = "blsp2_spi0";
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drive-strength = <8>;
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bias-pull-down;
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};
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pta_slic: pta_slic {
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pta1_0 {
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pins = "gpio49";
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function = "pta1_0";
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drive-strength = <8>;
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bias-disable;
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};
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pta1_1 {
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pins = "gpio50";
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function = "pta1_1";
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drive-strength = <8>;
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bias-disable;
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};
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pta1_2 {
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pins = "gpio51";
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function = "pta1_2";
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drive-strength = <8>;
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bias-disable;
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};
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};
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sfp_pins: sfp-state {
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pins = "gpio43";
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function = "gpio";
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bias-pull-up;
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input-enable;
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};
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spi_0_data_clk_pins: spi-0-data-clk-state {
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pins = "gpio14", "gpio15", "gpio16";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-down;
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};
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spi_0_cs_pins: spi-0-cs-state {
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pins = "gpio17";
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function = "blsp0_spi";
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drive-strength = <2>;
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bias-pull-up;
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};
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serial_1_pins: serial1-pinmux {
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|
pins = "gpio33", "gpio34", "gpio35", "gpio36";
|
|
function = "blsp1_uart2";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
button_pins: button-state {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
pwm_pins: pwm-state {
|
|
|
|
mux_1 {
|
|
pins = "gpio25";
|
|
function = "pwm2";
|
|
drive-strength = <8>;
|
|
};
|
|
mux_2 {
|
|
pins = "gpio26";
|
|
function = "pwm2";
|
|
drive-strength = <8>;
|
|
};
|
|
mux_3 {
|
|
pins = "gpio31";
|
|
function = "pwm1";
|
|
drive-strength = <8>;
|
|
};
|
|
};
|
|
|
|
sdc_default_state: sdc-default-state {
|
|
clk-pins {
|
|
pins = "gpio13";
|
|
function = "sdc_clk";
|
|
drive-strength = <8>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio12";
|
|
function = "sdc_cmd";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
function = "sdc_data";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_default_state: pcie0-default-state {
|
|
pins = "gpio38";
|
|
function = "gpio";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
output-low;
|
|
};
|
|
|
|
pcie1_default_state: pcie1-default-state {
|
|
pins = "gpio47";
|
|
function = "gpio";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
&license_manager {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3 {
|
|
qcom,select-utmi-as-pipe-clk;
|
|
status = "okay";
|
|
dwc3@8a00000 {
|
|
/delete-property/ #phy-cells;
|
|
/delete-property/ phys;
|
|
/delete-property/ phy-names;
|
|
};
|
|
};
|
|
|
|
&pwm {
|
|
pinctrl-0 = <&pwm_pins>;
|
|
pinctrl-names = "default";
|
|
dft-pwm-status = <0>, <0>, <1>, <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&hs_m31phy_0 {
|
|
status = "okay";
|
|
};
|
|
|