mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-10-29 09:32:34 +00:00
281 lines
9.1 KiB
C
Executable File
281 lines
9.1 KiB
C
Executable File
/*
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* Copyright (c) 2014, 2017-2019, The Linux Foundation. All rights reserved.
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*qca808x_start*/
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#ifndef _SSDK_INIT_H_
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#define _SSDK_INIT_H_
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "sw.h"
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/*qca808x_end*/
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#include "fal_led.h"
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/*qca808x_start*/
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typedef enum {
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HSL_MDIO = 1,
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HSL_HEADER,
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}
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hsl_access_mode;
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typedef enum
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{
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HSL_NO_CPU = 0,
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HSL_CPU_1,
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HSL_CPU_2,
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HSL_CPU_1_PLUS,
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} hsl_init_mode;
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typedef sw_error_t
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(*mdio_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
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a_uint16_t data);
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typedef sw_error_t
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(*mdio_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
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a_uint16_t * data);
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typedef sw_error_t
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(*i2c_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
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a_uint16_t data);
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typedef sw_error_t
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(*i2c_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
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a_uint16_t * data);
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/*qca808x_end*/
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typedef sw_error_t
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(*hdr_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef sw_error_t
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(*hdr_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef sw_error_t
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(*psgmii_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef sw_error_t
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(*psgmii_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef sw_error_t
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(*uniphy_reg_set) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef sw_error_t
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(*uniphy_reg_get) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
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typedef void (*mii_reg_set)(a_uint32_t reg, a_uint32_t val);
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typedef a_uint32_t (*mii_reg_get)(a_uint32_t reg);
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/*qca808x_start*/
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typedef struct
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{
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mdio_reg_set mdio_set;
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mdio_reg_get mdio_get;
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/*qca808x_end*/
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hdr_reg_set header_reg_set;
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hdr_reg_get header_reg_get;
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psgmii_reg_set psgmii_reg_set;
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psgmii_reg_get psgmii_reg_get;
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uniphy_reg_set uniphy_reg_set;
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uniphy_reg_get uniphy_reg_get;
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mii_reg_set mii_reg_set;
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mii_reg_get mii_reg_get;
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/*qca808x_start*/
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i2c_reg_set i2c_set;
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i2c_reg_get i2c_get;
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} hsl_reg_func;
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/*qca808x_end*/
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typedef struct
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{
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a_bool_t mac0_rgmii;
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a_bool_t mac5_rgmii;
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a_bool_t rx_delay_s0;
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a_bool_t rx_delay_s1;
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a_bool_t tx_delay_s0;
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a_bool_t tx_delay_s1;
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a_bool_t rgmii_rxclk_delay;
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a_bool_t rgmii_txclk_delay;
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a_bool_t phy4_rx_delay;
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a_bool_t phy4_tx_delay;
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} garuda_init_spec_cfg;
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/*qca808x_start*/
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typedef enum
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{
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CHIP_UNSPECIFIED = 0,
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CHIP_ATHENA,
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CHIP_GARUDA,
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CHIP_SHIVA,
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CHIP_HORUS,
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CHIP_ISIS,
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CHIP_ISISC,
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CHIP_DESS,
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CHIP_HPPE,
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} ssdk_chip_type;
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/*qca808x_end*/
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typedef struct
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{
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a_uint32_t cpu_bmp;
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a_uint32_t lan_bmp;
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a_uint32_t wan_bmp;
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a_uint32_t inner_bmp;
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} ssdk_port_cfg;
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typedef struct
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{
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a_uint32_t led_num;
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a_uint32_t led_source_id;
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led_ctrl_pattern_t led_pattern;
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} led_source_cfg_t;
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/*qca808x_start*/
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typedef struct
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{
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hsl_init_mode cpu_mode;
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hsl_access_mode reg_mode;
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hsl_reg_func reg_func;
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ssdk_chip_type chip_type;
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a_uint32_t chip_revision;
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/* os specific parameter */
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/* when uk_if based on netlink, it's netlink protocol type*/
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/* when uk_if based on ioctl, it's minor device number, major number
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is always 10(misc device) */
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a_uint32_t nl_prot;
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/* chip specific parameter */
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void * chip_spec_cfg;
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/*qca808x_end*/
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/* port cfg */
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ssdk_port_cfg port_cfg;
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a_uint32_t mac_mode;
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a_uint32_t led_source_num;
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led_source_cfg_t led_source_cfg[15];
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/*qca808x_start*/
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a_uint32_t phy_id;
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a_uint32_t mac_mode1;
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a_uint32_t mac_mode2;
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} ssdk_init_cfg;
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/*qca808x_end*/
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#if defined ATHENA
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#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
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#elif defined GARUDA
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#define def_init_cfg_cpu2 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2,};
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#define def_init_spec_cfg_cpu2 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_TRUE, \
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.rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
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.tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
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.rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE,\
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.phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
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#define def_init_cfg_cpu1 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
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#define def_init_spec_cfg_cpu1 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
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.rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
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.tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
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.rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
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.phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
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#define def_init_cfg_cpu1plus {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1_PLUS,};
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#define def_init_spec_cfg_cpu1plus {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
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.rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
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.tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\
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.rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
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.phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
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#define def_init_cfg_nocpu {.reg_mode = HSL_MDIO, .cpu_mode = HSL_NO_CPU,};
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#define def_init_spec_cfg_nocpu { .mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
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.rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
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.tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\
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.rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
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.phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
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#define def_init_cfg_cpu1_gmii {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
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#define def_init_spec_cfg_cpu1_gmii {.mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
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.rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
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.tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
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.rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
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.phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
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#define def_init_cfg def_init_cfg_cpu2
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#define def_init_spec_cfg def_init_spec_cfg_cpu2
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#elif defined SHIVA
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#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
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#elif defined HORUS
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#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
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#elif defined ISIS
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#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
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#elif defined ISISC
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/*qca808x_start*/
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#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
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/*qca808x_end*/
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#endif
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typedef struct
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{
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a_bool_t in_acl;
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a_bool_t in_fdb;
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a_bool_t in_igmp;
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a_bool_t in_leaky;
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a_bool_t in_led;
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a_bool_t in_mib;
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a_bool_t in_mirror;
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a_bool_t in_misc;
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a_bool_t in_portcontrol;
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a_bool_t in_portvlan;
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a_bool_t in_qos;
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a_bool_t in_rate;
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a_bool_t in_stp;
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a_bool_t in_vlan;
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a_bool_t in_reduced_acl;
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a_bool_t in_ip;
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a_bool_t in_nat;
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a_bool_t in_cosmap;
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a_bool_t in_sec;
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a_bool_t in_trunk;
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a_bool_t in_nathelper;
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a_bool_t in_interfacectrl;
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} ssdk_features;
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/*qca808x_start*/
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#define CFG_STR_SIZE 20
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typedef struct
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{
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a_uint8_t build_ver[CFG_STR_SIZE];
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a_uint8_t build_date[CFG_STR_SIZE];
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a_uint8_t chip_type[CFG_STR_SIZE]; //GARUDA
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a_uint8_t cpu_type[CFG_STR_SIZE]; //mips
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a_uint8_t os_info[CFG_STR_SIZE]; //OS=linux OS_VER=2_6
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a_bool_t fal_mod;
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a_bool_t kernel_mode;
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a_bool_t uk_if;
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/*qca808x_end*/
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ssdk_features features;
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/*qca808x_start*/
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ssdk_init_cfg init_cfg;
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} ssdk_cfg_t;
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sw_error_t
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ssdk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
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/*qca808x_end*/
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sw_error_t
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ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
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/*qca808x_start*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* _SSDK_INIT_H */
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/*qca808x_end*/
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