mirror of
https://github.com/Telecominfraproject/wlan-ap.git
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64 lines
2.0 KiB
Diff
64 lines
2.0 KiB
Diff
From 6d57a301283407567b00c4a289ffedbace33a7b3 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Mon, 18 May 2020 12:28:37 +0200
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Subject: [PATCH 11/40] ipq806x: add GSBI1 node to DTSI
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IPQ806x series also has a GSBI1 with UART and I2C peripherals, so lets add the node for it.
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Its needed for Edgecore ECW5410 which uses the UART from GSBI1 as second UART for Bluetooth.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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.../arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++
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1 file changed, 35 insertions(+)
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diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064.dtsi
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index d850553000..1af6353ee4 100644
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--- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -721,6 +721,41 @@
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reg = <0x12100000 0x10000>;
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};
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+ gsbi1: gsbi@12440000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <1>;
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+ reg = <0x12440000 0x100>;
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+ clocks = <&gcc GSBI1_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ syscon-tcsr = <&tcsr>;
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+
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+ gsbi1_serial: serial@12450000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x12450000 0x100>,
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+ <0x12400000 0x03>;
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ gsbi1_i2c: i2c@12460000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x12460000 0x1000>;
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+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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--
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2.25.1
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