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cec87c02e22a940422fd198d98e368eb5c3f52dd
wlan-ap/patches/0054-ipq807x-add-edgecore-eap106-support.patch
peter-edgecore 69f60362ca add edgecore EAP106 support
2021-06-25 09:41:42 +08:00

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From 6c4680359a5e164570e5d8e0b75c4dafbb1abccd Mon Sep 17 00:00:00 2001
From: "peter.chiu" <peter.chiu@4ipnet.com>
Date: Thu, 24 Jun 2021 17:16:48 +0800
Subject: [PATCH] ipq807x: add edgecore eap106 support
---
.../linux/ipq807x/base-files/etc/board.d/01_leds | 4 +
.../ipq807x/base-files/etc/board.d/02_network | 1 +
.../etc/hotplug.d/firmware/10-ath11k-caldata | 2 +
target/linux/ipq807x/base-files/etc/init.d/aq_phy | 1 +
target/linux/ipq807x/image/ipq807x.mk | 10 +
target/linux/ipq807x/patches/111-eap106.patch | 765 +++++++++++++++++++++
6 files changed, 783 insertions(+)
mode change 100644 => 100755 target/linux/ipq807x/image/ipq807x.mk
create mode 100644 target/linux/ipq807x/patches/111-eap106.patch
diff --git a/target/linux/ipq807x/base-files/etc/board.d/01_leds b/target/linux/ipq807x/base-files/etc/board.d/01_leds
index 1402a74..7225667 100755
--- a/target/linux/ipq807x/base-files/etc/board.d/01_leds
+++ b/target/linux/ipq807x/base-files/etc/board.d/01_leds
@@ -20,6 +20,10 @@ edgecore,eap102)
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tx"
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tx"
;;
+edgecore,eap106)
+ ucidef_set_led_netdev "wan" "WAN" "led1_yellow" "br-wan" "tx rx link"
+ ucidef_set_led_netdev "lan" "LAN" "led2_amber" "br-lan" "tx rx link"
+ ;;
esac
board_config_flush
diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network
index e90a73f..72ba9e0 100755
--- a/target/linux/ipq807x/base-files/etc/board.d/02_network
+++ b/target/linux/ipq807x/base-files/etc/board.d/02_network
@@ -29,6 +29,7 @@ qcom_setup_interfaces()
;;
cig,wf194c|\
edgecore,eap102|\
+ edgecore,eap106|\
sercomm,wallaby)
ucidef_set_interface_lan "eth0"
ucidef_set_interface_wan "eth1"
diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
index 25b2288..2c35c06 100755
--- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
+++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
@@ -49,6 +49,7 @@ case "$FIRMWARE" in
case "$board" in
cig,wf194c|\
edgecore,eap102 |\
+ edgecore,eap106 |\
qcom,ipq807x-hk01|\
qcom,ipq807x-hk14|\
tplink,ex227|\
@@ -85,6 +86,7 @@ ath11k/qcn9000/hw1.0/caldata_2.bin)
ath11k-macs)
case "$board" in
edgecore,eap102|\
+ edgecore,eap106|\
cig,wf188n)
ath11k_generate_macs
;;
diff --git a/target/linux/ipq807x/base-files/etc/init.d/aq_phy b/target/linux/ipq807x/base-files/etc/init.d/aq_phy
index 41a52cc..5ff174d 100755
--- a/target/linux/ipq807x/base-files/etc/init.d/aq_phy
+++ b/target/linux/ipq807x/base-files/etc/init.d/aq_phy
@@ -6,6 +6,7 @@ boot() {
. /lib/functions.sh
case "$(board_name)" in
+ edgecore,eap106|\
cig,wf194c)
aq-fw-download /lib/firmware/AQR-G4_v5.4.B-AQR_CIG_WIFI_ID44715_VER1673.cld miireg 0 > /dev/null
sleep 1
diff --git a/target/linux/ipq807x/image/ipq807x.mk b/target/linux/ipq807x/image/ipq807x.mk
old mode 100644
new mode 100755
index 000d279..55c344b
--- a/target/linux/ipq807x/image/ipq807x.mk
+++ b/target/linux/ipq807x/image/ipq807x.mk
@@ -44,6 +44,16 @@ define Device/edgecore_eap102
DEVICE_PACKAGES := ath11k-wifi-edgecore-eap102 kmod-usb2 uboot-envtools
endef
TARGET_DEVICES += edgecore_eap102
+
+define Device/edgecore_eap106
+ DEVICE_TITLE := Edgecore EAP106
+ DEVICE_DTS := qcom-ipq807x-eap106
+ DEVICE_DTS_CONFIG=config@hk02
+ SUPPORTED_DEVICES := edgecore,eap106
+ DEVICE_PACKAGES := ath11k-wifi-edgecore-eap106 aq-fw-download uboot-envtools kmod-usb3 kmod-usb2
+endef
+TARGET_DEVICES += edgecore_eap106
+
define Device/tplink_ex227
DEVICE_TITLE := TP-Link EX227
DEVICE_DTS := qcom-ipq807x-ex227
diff --git a/target/linux/ipq807x/patches/111-eap106.patch b/target/linux/ipq807x/patches/111-eap106.patch
new file mode 100644
index 0000000..632a688
--- /dev/null
+++ b/target/linux/ipq807x/patches/111-eap106.patch
@@ -0,0 +1,765 @@
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap106.dts
+===================================================================
+--- /dev/null
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap106.dts
+@@ -0,0 +1,716 @@
++/dts-v1/;
++/*
++ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include "qcom-ipq807x-soc.dtsi"
++#include "qcom-ipq807x-hk-cpu.dtsi"
++
++/ {
++ #address-cells = <0x2>;
++ #size-cells = <0x2>;
++ model = "Qualcomm Technologies, Inc. IPQ807x/AP-HK02";
++ compatible = "qcom,ipq807x-hk02", "qcom,ipq807x";
++ qcom,msm-id = <0x143 0x0>;
++ interrupt-parent = <&intc>;
++ qcom,board-id = <0x8 0x0>;
++ qcom,pmic-id = <0x0 0x0 0x0 0x0>;
++
++ aliases {
++ /*
++ * Aliases as required by u-boot
++ * to patch MAC addresses
++ */
++ ethernet0 = "/soc/dp1";
++ ethernet1 = "/soc/dp2";
++ };
++ chosen {
++ bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
++ #ifdef __IPQ_MEM_PROFILE_256_MB__
++ bootargs-append = " swiotlb=1";
++ #else
++ bootargs-append = " swiotlb=1 coherent_pool=2M";
++ #endif
++ };
++};
++
++&tlmm {
++ leds_pins: leds_pinmux {
++
++ led1_yellow {
++ pins = "gpio25";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-pull-down;
++ };
++ led1_green {
++ pins = "gpio28";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-pull-down;
++ };
++ led2_amber {
++ pins = "gpio29";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-pull-down;
++ };
++ led2_blue {
++ pins = "gpio32";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-pull-down;
++ };
++ };
++
++ mdio_pins: mdio_pinmux {
++ mux_0 {
++ pins = "gpio68";
++ function = "mdc";
++ drive-strength = <8>;
++ bias-pull-up;
++ };
++ mux_1 {
++ pins = "gpio69";
++ function = "mdio";
++ drive-strength = <8>;
++ bias-pull-up;
++ };
++ };
++
++ uart_pins: uart_pins {
++ mux {
++ pins = "gpio23", "gpio24";
++ function = "blsp4_uart1";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ i2c_0_pins: i2c_0_pinmux {
++ mux {
++ pins = "gpio42", "gpio43";
++ function = "blsp1_i2c";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ spi_0_pins: spi_0_pins {
++ mux {
++ pins = "gpio38", "gpio39", "gpio40", "gpio41";
++ function = "blsp0_spi";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ qpic_pins: qpic_pins {
++ data_0 {
++ pins = "gpio15";
++ function = "qpic_pad0";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_1 {
++ pins = "gpio12";
++ function = "qpic_pad1";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_2 {
++ pins = "gpio13";
++ function = "qpic_pad2";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_3 {
++ pins = "gpio14";
++ function = "qpic_pad3";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_4 {
++ pins = "gpio5";
++ function = "qpic_pad4";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_5 {
++ pins = "gpio6";
++ function = "qpic_pad5";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_6 {
++ pins = "gpio7";
++ function = "qpic_pad6";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_7 {
++ pins = "gpio8";
++ function = "qpic_pad7";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ data_8 {
++ pins = "gpio16";
++ function = "qpic_pad8";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ qpic_pad {
++ pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4",
++ "gpio9", "gpio10", "gpio11", "gpio17";
++ function = "qpic_pad";
++ drive-strength = <8>;
++ bias-disable;
++ };
++ };
++
++ hsuart_pins: hsuart_pins {
++ mux {
++ pins = "gpio46", "gpio47", "gpio48", "gpio49";
++ function = "blsp2_uart";
++ drive-strength = <8>;
++ bias-disable;
++ output-low;
++ };
++ mux_1 {
++ pins = "gpio51";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-disable;
++ output-high;
++ };
++ };
++
++ button_pins: button_pins {
++ wps_button {
++ pins = "gpio57";
++ function = "gpio";
++ drive-strength = <8>;
++ bias-pull-up;
++ };
++ };
++
++ uniphy_pins: uniphy_pinmux {
++ mux {
++ pins = "gpio60";
++ function = "rx2";
++ bias-disable;
++ };
++ };
++ cnss_wlan_en_active: cnss_wlan_en_active {
++ mux {
++ pins = "gpio57";
++ function = "gpio";
++ drive-strength = <16>;
++ output-high;
++ bias-pull-up;
++ };
++ };
++
++ cnss_wlan_en_sleep: cnss_wlan_en_sleep {
++ mux {
++ pins = "gpio57";
++ function = "gpio";
++ drive-strength = <2>;
++ output-low;
++ bias-pull-down;
++ };
++ };
++};
++
++&soc {
++ gpio_keys {
++ compatible = "gpio-keys";
++ pinctrl-0 = <&button_pins>;
++ pinctrl-names = "default";
++
++ button@1 {
++ label = "wps";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
++ linux,input-type = <1>;
++ debounce-interval = <60>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-0 = <&leds_pins>;
++ pinctrl-names = "default";
++
++ led@25 {
++ label = "led1_yellow";
++ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "led1_yellow";
++ default-state = "off";
++ };
++
++ led@28 {
++ label = "led1_green";
++ gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "led1_green";
++ default-state = "off";
++ };
++
++ led@29 {
++ label = "led2_amber";
++ gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "led2_amber";
++ default-state = "off";
++ };
++
++ led@32 {
++ label = "led2_blue";
++ gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "led2_blue";
++ default-state = "off";
++ };
++ };
++
++ mdio@90000 {
++ pinctrl-0 = <&mdio_pins>;
++ pinctrl-names = "default";
++ phy-reset-gpio = <&tlmm 37 0>;
++ phy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ phy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++ phy4: ethernet-phy@4 {
++ reg = <4>;
++ };
++ phy5: ethernet-phy@5 {
++ compatible ="ethernet-phy-ieee802.3-c45";
++ reg = <8>;
++ };
++ };
++
++ ess-switch@3a000000 {
++ pinctrl-0 = <&uniphy_pins>;
++ pinctrl-names = "default";
++ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
++ switch_lan_bmp = <0x30>; /* lan port bitmap */
++ switch_wan_bmp = <0x40>; /* wan port bitmap */
++ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
++ switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
++ switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
++ bm_tick_mode = <0>; /* bm tick mode */
++ tm_tick_mode = <0>; /* tm tick mode */
++ port_scheduler_resource {
++ port@0 {
++ port_id = <0>;
++ ucast_queue = <0 143>;
++ mcast_queue = <256 271>;
++ l0sp = <0 35>;
++ l0cdrr = <0 47>;
++ l0edrr = <0 47>;
++ l1cdrr = <0 7>;
++ l1edrr = <0 7>;
++ };
++ port@1 {
++ port_id = <1>;
++ ucast_queue = <144 159>;
++ mcast_queue = <272 275>;
++ l0sp = <36 39>;
++ l0cdrr = <48 63>;
++ l0edrr = <48 63>;
++ l1cdrr = <8 11>;
++ l1edrr = <8 11>;
++ };
++ port@2 {
++ port_id = <2>;
++ ucast_queue = <160 175>;
++ mcast_queue = <276 279>;
++ l0sp = <40 43>;
++ l0cdrr = <64 79>;
++ l0edrr = <64 79>;
++ l1cdrr = <12 15>;
++ l1edrr = <12 15>;
++ };
++ port@3 {
++ port_id = <3>;
++ ucast_queue = <176 191>;
++ mcast_queue = <280 283>;
++ l0sp = <44 47>;
++ l0cdrr = <80 95>;
++ l0edrr = <80 95>;
++ l1cdrr = <16 19>;
++ l1edrr = <16 19>;
++ };
++ port@4 {
++ port_id = <4>;
++ ucast_queue = <192 207>;
++ mcast_queue = <284 287>;
++ l0sp = <48 51>;
++ l0cdrr = <96 111>;
++ l0edrr = <96 111>;
++ l1cdrr = <20 23>;
++ l1edrr = <20 23>;
++ };
++ port@5 {
++ port_id = <5>;
++ ucast_queue = <208 223>;
++ mcast_queue = <288 291>;
++ l0sp = <52 55>;
++ l0cdrr = <112 127>;
++ l0edrr = <112 127>;
++ l1cdrr = <24 27>;
++ l1edrr = <24 27>;
++ };
++ port@6 {
++ port_id = <6>;
++ ucast_queue = <224 239>;
++ mcast_queue = <292 295>;
++ l0sp = <56 59>;
++ l0cdrr = <128 143>;
++ l0edrr = <128 143>;
++ l1cdrr = <28 31>;
++ l1edrr = <28 31>;
++ };
++ port@7 {
++ port_id = <7>;
++ ucast_queue = <240 255>;
++ mcast_queue = <296 299>;
++ l0sp = <60 63>;
++ l0cdrr = <144 159>;
++ l0edrr = <144 159>;
++ l1cdrr = <32 35>;
++ l1edrr = <32 35>;
++ };
++ };
++ port_scheduler_config {
++ port@0 {
++ port_id = <0>;
++ l1scheduler {
++ group@0 {
++ sp = <0 1>; /*L0 SPs*/
++ /*cpri cdrr epri edrr*/
++ cfg = <0 0 0 0>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ /*unicast queues*/
++ ucast_queue = <0 4 8>;
++ /*multicast queues*/
++ mcast_queue = <256 260>;
++ /*sp cpri cdrr epri edrr*/
++ cfg = <0 0 0 0 0>;
++ };
++ group@1 {
++ ucast_queue = <1 5 9>;
++ mcast_queue = <257 261>;
++ cfg = <0 1 1 1 1>;
++ };
++ group@2 {
++ ucast_queue = <2 6 10>;
++ mcast_queue = <258 262>;
++ cfg = <0 2 2 2 2>;
++ };
++ group@3 {
++ ucast_queue = <3 7 11>;
++ mcast_queue = <259 263>;
++ cfg = <0 3 3 3 3>;
++ };
++ };
++ };
++ port@1 {
++ port_id = <1>;
++ l1scheduler {
++ group@0 {
++ sp = <36>;
++ cfg = <0 8 0 8>;
++ };
++ group@1 {
++ sp = <37>;
++ cfg = <1 9 1 9>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <144>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <272>;
++ mcast_loop_pri = <4>;
++ cfg = <36 0 48 0 48>;
++ };
++ };
++ };
++ port@2 {
++ port_id = <2>;
++ l1scheduler {
++ group@0 {
++ sp = <40>;
++ cfg = <0 12 0 12>;
++ };
++ group@1 {
++ sp = <41>;
++ cfg = <1 13 1 13>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <160>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <276>;
++ mcast_loop_pri = <4>;
++ cfg = <40 0 64 0 64>;
++ };
++ };
++ };
++ port@3 {
++ port_id = <3>;
++ l1scheduler {
++ group@0 {
++ sp = <44>;
++ cfg = <0 16 0 16>;
++ };
++ group@1 {
++ sp = <45>;
++ cfg = <1 17 1 17>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <176>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <280>;
++ mcast_loop_pri = <4>;
++ cfg = <44 0 80 0 80>;
++ };
++ };
++ };
++ port@4 {
++ port_id = <4>;
++ l1scheduler {
++ group@0 {
++ sp = <48>;
++ cfg = <0 20 0 20>;
++ };
++ group@1 {
++ sp = <49>;
++ cfg = <1 21 1 21>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <192>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <284>;
++ mcast_loop_pri = <4>;
++ cfg = <48 0 96 0 96>;
++ };
++ };
++ };
++ port@5 {
++ port_id = <5>;
++ l1scheduler {
++ group@0 {
++ sp = <52>;
++ cfg = <0 24 0 24>;
++ };
++ group@1 {
++ sp = <53>;
++ cfg = <1 25 1 25>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <208>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <288>;
++ mcast_loop_pri = <4>;
++ cfg = <52 0 112 0 112>;
++ };
++ };
++ };
++ port@6 {
++ port_id = <6>;
++ l1scheduler {
++ group@0 {
++ sp = <56>;
++ cfg = <0 28 0 28>;
++ };
++ group@1 {
++ sp = <57>;
++ cfg = <1 29 1 29>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <224>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <292>;
++ mcast_loop_pri = <4>;
++ cfg = <56 0 128 0 128>;
++ };
++ };
++ };
++ port@7 {
++ port_id = <7>;
++ l1scheduler {
++ group@0 {
++ sp = <60>;
++ cfg = <0 32 0 32>;
++ };
++ group@1 {
++ sp = <61>;
++ cfg = <1 33 1 33>;
++ };
++ };
++ l0scheduler {
++ group@0 {
++ ucast_queue = <240>;
++ ucast_loop_pri = <16>;
++ mcast_queue = <296>;
++ cfg = <60 0 144 0 144>;
++ };
++ };
++ };
++ };
++ };
++
++ dp1 {
++ device_type = "network";
++ compatible = "qcom,nss-dp";
++ qcom,id = <4>;
++ reg = <0x3a001600 0x200>;
++ qcom,mactype = <0>;
++ local-mac-address = [000000000000];
++ qcom,link-poll = <1>;
++ qcom,phy-mdio-addr = <3>;
++ phy-mode = "sgmii";
++ };
++
++ dp2 {
++ device_type = "network";
++ compatible = "qcom,nss-dp";
++ qcom,id = <6>;
++ reg = <0x3a007000 0x3fff>;
++ qcom,mactype = <1>;
++ local-mac-address = [000000000000];
++ qcom,link-poll = <1>;
++ qcom,phy-mdio-addr = <8>;
++ phy-mode = "sgmii";
++ };
++ wifi3: wifi3@f00000 {
++ compatible = "qcom,cnss-qcn9000";
++ wlan-en-gpio = <&tlmm 57 0>;
++ pinctrl-names = "wlan_en_active", "wlan_en_sleep";
++ pinctrl-0 = <&cnss_wlan_en_active>;
++ pinctrl-1 = <&cnss_wlan_en_sleep>;
++ status = "disabled";
++ };
++};
++
++&serial_blsp4 {
++ pinctrl-0 = <&uart_pins>;
++ pinctrl-names = "default";
++ status = "ok";
++};
++
++&spi_0 { /* BLSP1 QUP1 */
++ pinctrl-0 = <&spi_0_pins>;
++ pinctrl-names = "default";
++ cs-select = <0>;
++ status = "ok";
++
++ m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0>;
++ compatible = "n25q128a11";
++ linux,modalias = "m25p80", "n25q128a11";
++ spi-max-frequency = <50000000>;
++ use-default-sizes;
++ };
++};
++
++&serial_blsp2 {
++ pinctrl-0 = <&hsuart_pins>;
++ pinctrl-names = "default";
++ status = "ok";
++};
++
++&msm_imem {
++ status = "disabled";
++};
++
++&ssphy_0 {
++ status = "ok";
++};
++
++&qusb_phy_0 {
++ status = "ok";
++};
++
++&ssphy_1 {
++ status = "ok";
++};
++
++&qusb_phy_1 {
++ status = "ok";
++};
++
++&usb3_0 {
++ status = "ok";
++};
++
++&usb3_1 {
++ status = "ok";
++};
++
++&cryptobam {
++ status = "ok";
++};
++
++&crypto {
++ status = "ok";
++};
++
++&i2c_0 {
++ pinctrl-0 = <&i2c_0_pins>;
++ pinctrl-names = "default";
++ status = "ok";
++};
++
++&i2c_1 {
++ status = "disabled";
++};
++
++&qpic_bam {
++ status = "ok";
++};
++
++&nand {
++ pinctrl-0 = <&qpic_pins>;
++ pinctrl-names = "default";
++ status = "ok";
++};
++
++&pcie0 {
++ status = "disabled";
++};
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/net/phy/aquantia.c
+===================================================================
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/drivers/net/phy/aquantia.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/net/phy/aquantia.c
+@@ -29,6 +29,7 @@
+ #define PHY_ID_AQR109 0x03a1b502
+ #define PHY_ID_AQR111 0x03a1b610
+ #define PHY_ID_AQR111B0 0x03a1b612
++#define PHY_ID_AQR111C 0x03a1b7e2
+ #define PHY_ID_AQR112 0x03a1b660
+ #define PHY_ID_AQR113C 0x31c31C10
+ #define PHY_ID_AQR112C 0x03a1b792
+@@ -701,6 +702,23 @@ static struct phy_driver aquantia_driver
+ .driver = { .owner = THIS_MODULE,},
+ },
+ {
++ .phy_id = PHY_ID_AQR111C,
++ .phy_id_mask = 0xfffffff0,
++ .name = "Aquantia AQR111C",
++ .features = PHY_AQUANTIA_FEATURES,
++ .flags = PHY_HAS_INTERRUPT,
++ .probe = aquantia_phy_probe,
++ .soft_reset = aquantia_soft_reset,
++ .config_init = aquantia_config_init,
++ .aneg_done = aquantia_aneg_done,
++ .config_aneg = aquantia_config_aneg,
++ .config_intr = aquantia_config_intr,
++ .ack_interrupt = aquantia_ack_interrupt,
++ .read_status = aquantia_read_status,
++ .update_link = aquantia_update_link,
++ .driver = { .owner = THIS_MODULE,},
++},
++{
+ .phy_id = PHY_ID_AQR112,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Aquantia AQR112",
+@@ -790,6 +808,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_AQR109, 0xfffffff0 },
+ { PHY_ID_AQR111, 0xfffffff0 },
+ { PHY_ID_AQR111B0, 0xfffffff0 },
++ { PHY_ID_AQR111C, 0xfffffff0 },
+ { PHY_ID_AQR112, 0xfffffff0 },
+ { PHY_ID_AQR113C, 0xfffffff0 },
+ { PHY_ID_AQR112C, 0xfffffff0 },
--
2.7.4
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