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Rebasing and rerunning linter

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This commit is contained in:
mdlewisfb
2018-10-23 12:50:56 -07:00
parent 04a7d72656
commit 4e4581357d
39 changed files with 294 additions and 290 deletions
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2
firmware/ec/.clang-format
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@@ -15,7 +15,7 @@ AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlinesLeft: true
AlignOperands: true
AlignTrailingComments: false
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false

2
firmware/ec/common/inc/global/Framework.h
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@@ -121,7 +121,7 @@ typedef struct Driver {
} Driver;
typedef struct SSHookSet {
ssHook_Cb preInitFxn; /* Function will run before post is executed */
ssHook_Cb preInitFxn; /* Function will run before post is executed */
ssHook_Cb postInitFxn; /* Function will run after post is executed */
} SSHookSet;

14
firmware/ec/common/inc/global/ocmp_frame.h
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@@ -52,8 +52,8 @@ typedef enum {
typedef enum {
OCMP_COMM_IFACE_UART = 1, // Uart - 1
OCMP_COMM_IFACE_ETHERNET, // Ethernet - 2
OCMP_COMM_IFACE_SBD, // SBD(Satellite) - 3
OCMP_COMM_IFACE_USB // Usb - 4
OCMP_COMM_IFACE_SBD, // SBD(Satellite) - 3
OCMP_COMM_IFACE_USB // Usb - 4
} OCMPInterface;
/*
@@ -145,21 +145,21 @@ typedef enum { OCMP_DEBUG_READ = 1, OCMP_DEBUG_WRITE } eOCMPDebugOperation;
* Source Interface, Sequence number, and timestamp.
*/
typedef struct __attribute__((packed, aligned(1))) {
uint8_t ocmpSof; // SOF - It must be 0x55
uint8_t ocmpSof; // SOF - It must be 0x55
uint8_t ocmpFrameLen; // Framelen - tells about the configuration size ONLY.
OCMPInterface ocmpInterface; // Interface - UART/Ethernet/SBD
uint32_t ocmpSeqNumber; // SeqNo - Don't know!!!
uint32_t ocmpTimestamp; // Timestamp - When AP sent the command?
uint32_t ocmpSeqNumber; // SeqNo - Don't know!!!
uint32_t ocmpTimestamp; // Timestamp - When AP sent the command?
} OCMPHeader;
/*
* This is the Message structure for Subsystem level information
*/
typedef struct __attribute__((packed, aligned(1))) {
OC_SS subsystem; // RF/GPP/BMS/Watchdog etc..
OC_SS subsystem; // RF/GPP/BMS/Watchdog etc..
uint8_t componentID; // Compononent ID. Different for different subsystem.
OCMPMsgType
msgtype; // Msg type is Config/Status/Alert/Command/Watchdog/Debug
msgtype; // Msg type is Config/Status/Alert/Command/Watchdog/Debug
uint8_t action; // Action is - Get/Set/Reply.
uint16_t parameters; // List of Parameters to be set or get.
#ifndef OCWARE_HOST

6
firmware/ec/common/inc/global/post_frame.h
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@@ -41,9 +41,9 @@ typedef struct __attribute__((packed, aligned(1))) {
} POSTData;
/*****************************************************************************
* FUNCTION PROTOTYPES
* FUNCTION PROTOTYPES
*****************************************************************************/
void post_update_POSTData(POSTData *pData, uint8_t I2CBus, uint8_t devAddress,
uint16_t manId, uint16_t devId);
void post_update_POSTData(POSTData *pData, uint8_t I2CBus, uint8_t devAddress,
uint16_t manId, uint16_t devId);
#endif /* POST_FRAME_H_ */

4
firmware/ec/inc/common/global_header.h
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@@ -62,9 +62,9 @@
#else
# define DEBUG(...) //
# define LOGGER(...) //
# define LOGGER(...) //
# define LOGGER_WARNING(...) //
# define LOGGER_ERROR(...) //
# define LOGGER_ERROR(...) //
# ifdef DEBUG_LOGS
# define LOGGER_DEBUG(...) //
# endif

4
firmware/ec/inc/devices/eeprom.h
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@@ -47,8 +47,8 @@ typedef struct Eeprom_Cfg {
I2C_Dev i2c_dev;
OcGpio_Pin *pin_wp;
EepromDev_Cfg type; /*!< Device specific config (page size, etc) */
OCMPSubsystem ss; /* TODO: The HW config need not know about the subsytem
to be fixed later */
OCMPSubsystem ss; /* TODO: The HW config need not know about the subsytem
to be fixed later */
} Eeprom_Cfg, *Eeprom_Handle;
typedef enum {

18
firmware/ec/inc/devices/ext_battery.h
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@@ -21,19 +21,19 @@
* External Battery Temperature sensors Low, High and Critical Temeprature Alert
* Limits
*/
#define PWR_EXT_BATT_TEMP_LOW_LIMIT -20 //(in Celcius)
#define PWR_EXT_BATT_TEMP_HIGH_LIMIT 75 //(in Celcius)
#define PWR_EXT_BATT_TEMP_LOW_LIMIT -20 //(in Celcius)
#define PWR_EXT_BATT_TEMP_HIGH_LIMIT 75 //(in Celcius)
#define PWR_EXT_BATT_TEMP_CRITICAL_LIMIT 80 //(in Celcius)
#define PWR_EXT_BATT_DIE_TEMP_LIMIT 60
/* Config parameters for External battery charger */
#define PWR_EXTBATT_ICHARGE_VAL 10660 // milliAmps
#define PWR_EXTBATT_VCHARGE_VAL 12000 // milliVolts
#define PWR_EXTBATT_UNDERVOLTAGE_VAL 9500 // milliVolts
#define PWR_EXTBATT_OVERVOLTAGE_VAL 13800 // milliVolts
#define PWR_EXTBATT_ICHARGE_VAL 10660 // milliAmps
#define PWR_EXTBATT_VCHARGE_VAL 12000 // milliVolts
#define PWR_EXTBATT_UNDERVOLTAGE_VAL 9500 // milliVolts
#define PWR_EXTBATT_OVERVOLTAGE_VAL 13800 // milliVolts
#define PWR_EXTBATT_INPUTBATTUNDERVOLATGE_VAL 16200 // milliVolts
#define PWR_EXTBATT_INPUTHICURRENT_VAL 17000 // milliAmps
#define PWR_EXTBATT_LOWBATTCURRENT_VAL 100 // milliAmps
#define PWR_EXTBATT_INPUTCURRENTLIMIT_VAL 16500 // milliAmps
#define PWR_EXTBATT_INPUTHICURRENT_VAL 17000 // milliAmps
#define PWR_EXTBATT_LOWBATTCURRENT_VAL 100 // milliAmps
#define PWR_EXTBATT_INPUTCURRENTLIMIT_VAL 16500 // milliAmps
#endif /* EXT_BATTERY_H_ */

18
firmware/ec/inc/devices/ina226.h
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@@ -21,11 +21,11 @@
*****************************************************************************/
/* Mask/Enable Register Bits */
#define INA_ALERT_EN_MASK 0xF800 /* Upper 5 bits are the enable bits */
#define INA_MSK_SOL (1 << 15) /* Shunt over-voltage */
#define INA_MSK_SUL (1 << 14) /* Shunt under-voltage */
#define INA_MSK_BOL (1 << 13) /* Bus over-voltage */
#define INA_MSK_BUL (1 << 12) /* Bus under-voltage */
#define INA_MSK_POL (1 << 11) /* Power over limit */
#define INA_MSK_SOL (1 << 15) /* Shunt over-voltage */
#define INA_MSK_SUL (1 << 14) /* Shunt under-voltage */
#define INA_MSK_BOL (1 << 13) /* Bus over-voltage */
#define INA_MSK_BUL (1 << 12) /* Bus under-voltage */
#define INA_MSK_POL (1 << 11) /* Power over limit */
#define INA_MSK_CNVR \
(1 << 10) /* Conversion ready - enable alert when \
* CVRF is set (ready for next conversion) */
@@ -33,10 +33,10 @@
#define INA_MSK_AFF \
(1 << 4) /* Alert Function Flag (caused by alert) \
* In latch mode, cleared on mask read */
#define INA_MSK_CVRF \
(1 << 3) /* Conversion Ready Flag, cleared when \
* writing to cfg reg or mask read */
#define INA_MSK_OVF (1 << 2) /* Math Overflow Flag (data may be invalid) */
#define INA_MSK_CVRF \
(1 << 3) /* Conversion Ready Flag, cleared when \
* writing to cfg reg or mask read */
#define INA_MSK_OVF (1 << 2) /* Math Overflow Flag (data may be invalid) */
#define INA_MSK_APOL (1 << 1) /* Alert Polarity (1 = invert, active high) */
#define INA_MSK_LEN \
(1 << 0) /* Alert Latch Enable \

12
firmware/ec/inc/devices/int_battery.h
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@@ -13,14 +13,14 @@
* MACRO DEFINITIONS
*****************************************************************************/
#define PWR_INT_BATT_RSNSB 30 // milli ohms
#define PWR_INT_BATT_RSNSI 7 // milli ohms
#define PWR_INT_BATT_RSNSI 7 // milli ohms
/* Config parameters for Internal battery charger */
#define PWR_INTBATT_UNDERVOLTAGE_VAL 9000 // milliVolts
#define PWR_INTBATT_OVERVOLTAGE_VAL 12600 // milliVolts
#define PWR_INTBATT_UNDERVOLTAGE_VAL 9000 // milliVolts
#define PWR_INTBATT_OVERVOLTAGE_VAL 12600 // milliVolts
#define PWR_INTBATT_INPUTUNDERVOLATGE_VAL 16200 // milliVolts
#define PWR_INTBATT_INPUTOVERCURRENT_VAL 5000 // milliAmps
#define PWR_INTBATT_LOWBATTERYCURRENT_VAL 100 // milliAmps
#define PWR_INTBATT_INPUTCURRENTLIMIT_VAL 5570 // milliAmps
#define PWR_INTBATT_INPUTOVERCURRENT_VAL 5000 // milliAmps
#define PWR_INTBATT_LOWBATTERYCURRENT_VAL 100 // milliAmps
#define PWR_INTBATT_INPUTCURRENTLIMIT_VAL 5570 // milliAmps
#endif /* INT_BATTERY_H_ */

50
firmware/ec/inc/devices/ltc4015.h
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@@ -25,20 +25,20 @@
#define LTC4015_ALERT_EN_MASK \
0xFFFF /* Bits 15-0 are the enable bits(except bit 14) */
#define LTC4015_MSK_MSRV (1 << 15) /* Measurement system results valid */
#define LTC4015_MSK_QCL (1 << 13) /* QCOUNT Low alert */
#define LTC4015_MSK_QCH (1 << 12) /* QCOUNT High alert */
#define LTC4015_MSK_BVL (1 << 11) /* Battery voltage Low alert */
#define LTC4015_MSK_BVH (1 << 10) /* Battery voltage High alert */
#define LTC4015_MSK_IVL (1 << 9) /* Input voltage Low alert */
#define LTC4015_MSK_IVH (1 << 8) /* Input voltage High alert */
#define LTC4015_MSK_SVL (1 << 7) /* System voltage Low alert */
#define LTC4015_MSK_SVH (1 << 6) /* System voltage High alert */
#define LTC4015_MSK_ICH (1 << 5) /* Input current High alert */
#define LTC4015_MSK_BCL (1 << 4) /* Battery current Low alert */
#define LTC4015_MSK_DTH (1 << 3) /* Die temperature High alert */
#define LTC4015_MSK_BSRH (1 << 2) /* BSR High alert */
#define LTC4015_MSK_NTCH (1 << 1) /* NTC ratio High alert */
#define LTC4015_MSK_NTCL (1 << 0) /* NTC ratio Low alert */
#define LTC4015_MSK_QCL (1 << 13) /* QCOUNT Low alert */
#define LTC4015_MSK_QCH (1 << 12) /* QCOUNT High alert */
#define LTC4015_MSK_BVL (1 << 11) /* Battery voltage Low alert */
#define LTC4015_MSK_BVH (1 << 10) /* Battery voltage High alert */
#define LTC4015_MSK_IVL (1 << 9) /* Input voltage Low alert */
#define LTC4015_MSK_IVH (1 << 8) /* Input voltage High alert */
#define LTC4015_MSK_SVL (1 << 7) /* System voltage Low alert */
#define LTC4015_MSK_SVH (1 << 6) /* System voltage High alert */
#define LTC4015_MSK_ICH (1 << 5) /* Input current High alert */
#define LTC4015_MSK_BCL (1 << 4) /* Battery current Low alert */
#define LTC4015_MSK_DTH (1 << 3) /* Die temperature High alert */
#define LTC4015_MSK_BSRH (1 << 2) /* BSR High alert */
#define LTC4015_MSK_NTCH (1 << 1) /* NTC ratio High alert */
#define LTC4015_MSK_NTCL (1 << 0) /* NTC ratio Low alert */
#define LTC4015_MSK_BMFA (1 << 1) /* Battery Missing Fault alert */
@@ -59,17 +59,17 @@ typedef enum LTC4015_Chem {
typedef enum LTC4015_Event {
LTC4015_EVT_MSRV = LTC4015_MSK_MSRV, /* Measurement system results valid */
LTC4015_EVT_QCL = LTC4015_MSK_QCL, /* QCOUNT Low alert */
LTC4015_EVT_QCH = LTC4015_MSK_QCH, /* QCOUNT High alert */
LTC4015_EVT_BVL = LTC4015_MSK_BVL, /* Battery voltage Low alert */
LTC4015_EVT_BVH = LTC4015_MSK_BVH, /* Battery voltage High alert */
LTC4015_EVT_IVL = LTC4015_MSK_IVL, /* Input voltage Low alert */
LTC4015_EVT_IVH = LTC4015_MSK_IVH, /* Input voltage High alert */
LTC4015_EVT_SVL = LTC4015_MSK_SVL, /* System voltage Low alert */
LTC4015_EVT_SVH = LTC4015_MSK_SVH, /* System voltage High alert */
LTC4015_EVT_ICH = LTC4015_MSK_ICH, /* Input current High alert */
LTC4015_EVT_BCL = LTC4015_MSK_BCL, /* Battery current Low alert */
LTC4015_EVT_DTH = LTC4015_MSK_DTH, /* Die temperature High alert */
LTC4015_EVT_QCL = LTC4015_MSK_QCL, /* QCOUNT Low alert */
LTC4015_EVT_QCH = LTC4015_MSK_QCH, /* QCOUNT High alert */
LTC4015_EVT_BVL = LTC4015_MSK_BVL, /* Battery voltage Low alert */
LTC4015_EVT_BVH = LTC4015_MSK_BVH, /* Battery voltage High alert */
LTC4015_EVT_IVL = LTC4015_MSK_IVL, /* Input voltage Low alert */
LTC4015_EVT_IVH = LTC4015_MSK_IVH, /* Input voltage High alert */
LTC4015_EVT_SVL = LTC4015_MSK_SVL, /* System voltage Low alert */
LTC4015_EVT_SVH = LTC4015_MSK_SVH, /* System voltage High alert */
LTC4015_EVT_ICH = LTC4015_MSK_ICH, /* Input current High alert */
LTC4015_EVT_BCL = LTC4015_MSK_BCL, /* Battery current Low alert */
LTC4015_EVT_DTH = LTC4015_MSK_DTH, /* Die temperature High alert */
LTC4015_EVT_BSRH = LTC4015_MSK_BSRH, /* BSR High alert */
LTC4015_EVT_NTCL = LTC4015_MSK_NTCL, /* NTC ratio High alert */
LTC4015_EVT_NTCH = LTC4015_MSK_NTCH, /* NTC ratio Low alert */

4
firmware/ec/inc/devices/ltc4275.h
View File

@@ -42,8 +42,8 @@ typedef enum {
} ePDAlert;
typedef enum {
LTC4275_CONNECT_EVT = 1 << 2, /* PD device Connected. */
LTC4275_DISCONNECT_EVT = 1 << 1, /* PD device removed. */
LTC4275_CONNECT_EVT = 1 << 2, /* PD device Connected. */
LTC4275_DISCONNECT_EVT = 1 << 1, /* PD device removed. */
LTC4275_INCOMPATIBLE_EVT = 1 << 0, /* Incomaptible device */
} LTC4275_Event;

4
firmware/ec/inc/devices/powerSource.h
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@@ -27,8 +27,8 @@ typedef enum {
} ePowerSource;
typedef enum {
PWR_SRC_ACTIVE = 0, /* If source is primary source */
PWR_SRC_AVAILABLE, /* If source is available */
PWR_SRC_ACTIVE = 0, /* If source is primary source */
PWR_SRC_AVAILABLE, /* If source is available */
PWR_SRC_NON_AVAILABLE /* If source is not connected */
} ePowerSourceState;

2
firmware/ec/inc/utils/util.h
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@@ -68,7 +68,7 @@ extern "C" {
typedef struct {
uint16_t event; // Event type.
uint8_t state; // Event state;
uint8_t state; // Event state;
} appEvtHdr_t;
/*********************************************************************

12
firmware/ec/src/bigbrother.c
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@@ -189,8 +189,8 @@ extern OcGpio_Port gbc_io_0;
// OcGpio_Pin pin_r_irq_intrpt = { &gbc_io_0, 0, OCGPIO_CFG_IN_PU };
// OcGpio_Pin pin_inven_eeprom_wp = { &gbc_io_0, 1,
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_s_id_eeprom_wp = { &gbc_io_0,
// 2, OCGPIO_CFG_OUT_OD_NOPULL };
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_s_id_eeprom_wp = {
// &gbc_io_0, 2, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_uart_sel = { &gbc_io_0, 3, OCGPIO_CFG_OUT_OD_NOPULL };
// OcGpio_Pin pin_tempsen_evt1 = { &gbc_io_0, 4 };
// OcGpio_Pin pin_tempsen_evt2 = { &gbc_io_0, 5 };
@@ -198,8 +198,8 @@ OcGpio_Pin pin_uart_sel = { &gbc_io_0, 3, OCGPIO_CFG_OUT_OD_NOPULL };
// OcGpio_Pin pin_tempsen_evt4 = { &gbc_io_0, 7 };
// OcGpio_Pin pin_tempsen_evt5 = { &gbc_io_0, 8 };
// OcGpio_Pin pin_buzzer_on = { &gbc_io_0, 10,
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_int_bat_prsnt = { &gbc_io_0,
// 11 }; OcGpio_Pin pin_ext_bat_prsnt = { &gbc_io_0, 12 };
// OCGPIO_CFG_OUT_OD_NOPULL }; OcGpio_Pin pin_int_bat_prsnt = {
// &gbc_io_0, 11 }; OcGpio_Pin pin_ext_bat_prsnt = { &gbc_io_0, 12 };
OcGpio_Pin pin_ec_syncconn_gpio1 = { &gbc_io_0, 13, OCGPIO_CFG_OUT_OD_NOPULL };
OcGpio_Pin pin_eth_sw_ec_intn = { &gbc_io_0, 14 };
@@ -308,8 +308,8 @@ static void bigborther_spwan_task(void)
/* Check the list for possible devices connected. */
/* Launches other tasks */
usb_rx_createtask(); // P - 05
usb_tx_createtask(); // P - 04
usb_rx_createtask(); // P - 05
usb_tx_createtask(); // P - 04
gossiper_createtask(); // P - 06
ebmp_create_task();
watchdog_create_task();

32
firmware/ec/src/devices/adt7481.c
View File

@@ -20,26 +20,26 @@
*****************************************************************************/
#define ADT7481_REG_R_LOCAL_TEMP 0x00 /* Local Temperature Value */
#define ADT7481_REG_R_REMOTE1_TEMP_H \
0x01 /* Remote 1 Temperature Value High Byte */
0x01 /* Remote 1 Temperature Value High Byte */
#define ADT7481_REG_R_STATUS1 0x02 /* Status Register 1 */
#define ADT7481_REG_R_CONFIG1 0x03 /* Configuration Register 1 */
#define ADT7481_REG_R_CONVERSION_RATE \
0x04 /* Conversion Rate/Channel Selector */
#define ADT7481_REG_R_LOCAL_HIGHLIMIT 0x05 /* Local Temperature High Limit */
#define ADT7481_REG_R_LOCAL_LOWLIMIT 0x06 /* Local Temperature Low Limit */
#define ADT7481_REG_R_LOCAL_LOWLIMIT 0x06 /* Local Temperature Low Limit */
#define ADT7481_REG_R_REMOTE1_HIGHLIMIT_H \
0x07 /* Remote 1 Temp High Limit High Byte */
#define ADT7481_REG_R_REMOTE1_LOWLIMIT_H \
0x08 /* Remote 1 Temp Low Limit High Byte */
0x08 /* Remote 1 Temp Low Limit High Byte */
#define ADT7481_REG_W_CONFIG1 0x09 /* Configuration Register */
#define ADT7481_REG_W_CONVERSION_RATE \
0x0A /* Conversion Rate/Channel Selector */
#define ADT7481_REG_W_LOCAL_HIGHLIMIT 0x0B /* Local Temperature High Limit */
#define ADT7481_REG_W_LOCAL_LOWLIMIT 0x0C /* Local Temperature Low Limit */
#define ADT7481_REG_W_LOCAL_LOWLIMIT 0x0C /* Local Temperature Low Limit */
#define ADT7481_REG_W_REMOTE1_HIGHLIMIT_H \
0x0D /* Remote 1 Temp High Limit High Byte */
#define ADT7481_REG_W_REMOTE1_LOWLIMIT_H \
0x0E /* Remote 1 Temp Low Limit High Byte */
0x0E /* Remote 1 Temp Low Limit High Byte */
#define ADT7481_REG_W_ONE_SHOT 0x0F /* One-Shot */
#define ADT7481_REG_R_REMOTE1_TEMP_L \
0x10 /* Remote 1 Temperature Value Low Byte */
@@ -61,15 +61,15 @@
0x14 /* Remote 1 Temp Low Limit Low Byte */
#define ADT7481_REG_R_REMOTE1_THERMLIMIT 0x19 /* Remote 1 THERM Limit */
#define ADT7481_REG_W_REMOTE1_THERMLIMIT 0x19 /* Remote 1 THERM Limit */
#define ADT7481_REG_R_LOCAL_THERMLIMIT 0x20 /* Local THERM Limit */
#define ADT7481_REG_W_LOCAL_THERMLIMIT 0x20 /* Local THERM Limit */
#define ADT7481_REG_R_THERM_HYST 0x21 /* THERM Hysteresis */
#define ADT7481_REG_W_THERM_HYST 0x21 /* THERM Hysteresis */
#define ADT7481_REG_R_CONECUTIVE_ALERT 0x22 /* Consecutive ALERT */
#define ADT7481_REG_W_CONECUTIVE_ALERT 0x22 /* Consecutive ALERT */
#define ADT7481_REG_R_STATUS2 0x23 /* Status Register 2 */
#define ADT7481_REG_R_CONFIG2 0x24 /* Configuration 2 Register */
#define ADT7481_REG_W_CONFIG2 0x24 /* Configuration 2 Register */
#define ADT7481_REG_R_LOCAL_THERMLIMIT 0x20 /* Local THERM Limit */
#define ADT7481_REG_W_LOCAL_THERMLIMIT 0x20 /* Local THERM Limit */
#define ADT7481_REG_R_THERM_HYST 0x21 /* THERM Hysteresis */
#define ADT7481_REG_W_THERM_HYST 0x21 /* THERM Hysteresis */
#define ADT7481_REG_R_CONECUTIVE_ALERT 0x22 /* Consecutive ALERT */
#define ADT7481_REG_W_CONECUTIVE_ALERT 0x22 /* Consecutive ALERT */
#define ADT7481_REG_R_STATUS2 0x23 /* Status Register 2 */
#define ADT7481_REG_R_CONFIG2 0x24 /* Configuration 2 Register */
#define ADT7481_REG_W_CONFIG2 0x24 /* Configuration 2 Register */
#define ADT7481_REG_R_REMOTE2_TEMP_H \
0x30 /* Remote 2 Temperature Value High Byte */
#define ADT7481_REG_R_REMOTE2_HIGHLIMIT_H \
@@ -100,8 +100,8 @@
0x37 /* Remote 2 Temp Low Limit Low Byte */
#define ADT7481_REG_R_REMOTE2_THERMLIMIT 0x39 /* Remote 2 THERM Limit */
#define ADT7481_REG_W_REMOTE2_THERMLIMIT 0x39 /* Remote 2 THERM Limit */
#define ADT7481_REG_R_CHIP_ID 0x3D /* Device ID */
#define ADT7481_REG_R_MAN_ID 0x3E /* Manufacturer ID */
#define ADT7481_REG_R_CHIP_ID 0x3D /* Device ID */
#define ADT7481_REG_R_MAN_ID 0x3E /* Manufacturer ID */
/*
* Macros to convert temperature values to register values and vice versa.

6
firmware/ec/src/devices/g510.c
View File

@@ -253,10 +253,10 @@ static void testModule_task(UArg a0, UArg a1)
GSM_clccSet(s_hGsm, true); /* Enable clcc (call state) msg */
/* Finish device configuration */
if (!GSM_cnmi(s_hGsm, 2, 1, 0, 0, 0) || /* enable sms arrival notif */
if (!GSM_cnmi(s_hGsm, 2, 1, 0, 0, 0) || /* enable sms arrival notif */
!GSM_cmgf(s_hGsm, GSM_MSG_FMT_TEXT) || /* set to text mode */
!GSM_csmp(s_hGsm, 17, 167, 0, 0) || /* text mode parameters */
!GSM_csdh(s_hGsm, true)) { /* display extra info for cgmr */
!GSM_csmp(s_hGsm, 17, 167, 0, 0) || /* text mode parameters */
!GSM_csdh(s_hGsm, true)) { /* display extra info for cgmr */
s_hGsm = NULL; /* TODO: proper teardown of handle */
}

2
firmware/ec/src/devices/i2c/XR20M1170.c
View File

@@ -357,7 +357,7 @@ static bool register_config(UART_Handle handle, UART_Params *params)
/* Set halt/resume levels - these can be relatively low since data should
* normally be cleared quite quickly */
XrRegTcr tcr = {
.rxHaltLvl = 40 / 4, /* 0-60, multiple of 4 */
.rxHaltLvl = 40 / 4, /* 0-60, multiple of 4 */
.rxResumeLvl = 12 / 4, /* 0-60, multiple of 4 */
};
writeData(handle, XR_REG_TCR, &tcr, sizeof(tcr));

14
firmware/ec/src/devices/i2c/XR20M1170.h
View File

@@ -59,13 +59,13 @@ typedef struct XR20M1170_HWAttrs {
typedef struct XR20M1170_Object {
/* UART state variable */
struct {
bool opened : 1; /* Has the obj been opened */
UART_Mode readMode : 1; /* Mode for all read calls */
UART_Mode writeMode : 1; /* Mode for all write calls */
UART_DataMode readDataMode : 1; /* Type of data being read */
UART_DataMode writeDataMode : 1; /* Type of data being written */
bool opened : 1; /* Has the obj been opened */
UART_Mode readMode : 1; /* Mode for all read calls */
UART_Mode writeMode : 1; /* Mode for all write calls */
UART_DataMode readDataMode : 1; /* Type of data being read */
UART_DataMode writeDataMode : 1; /* Type of data being written */
UART_ReturnMode readReturnMode : 1; /* Receive return mode */
UART_Echo readEcho : 1; /* Echo received data back */
UART_Echo readEcho : 1; /* Echo received data back */
/*
* Flag to determine if a timeout has occurred when the user called
* UART_read(). This flag is set by the timeoutClk clock object.
@@ -95,7 +95,7 @@ typedef struct XR20M1170_Object {
// UART_PAR parityType; /* Parity bit type for UART */
//
// /* UART read variables */
RingBuf_Object ringBuffer; /* local circular buffer object */
RingBuf_Object ringBuffer; /* local circular buffer object */
GateMutex_Handle ringBufMutex; // Mutex for accessing ring buffer
// /* A complement pair of read functions for both the ISR and
// UART_read() */ UARTTiva_FxnSet readFxns; unsigned char *readBuf;

38
firmware/ec/src/devices/i2c/XR20M1170_Registers.h
View File

@@ -45,17 +45,17 @@ typedef enum XrRegister {
XR_REG_TCR = 0x06, /* EFR[4] == 1 && MCR[2] == 1 */
XR_REG_TLR = 0x07, /* EFR[4] == 1 && MCR[2] == 1 */
XR_REG_TXLVL = 0x08, // LCR[7] = 0
XR_REG_RXLVL = 0x09, // LCR[7] = 0
XR_REG_IODIR = 0x0A, // LCR[7] = 0
XR_REG_IOSTATE = 0x0B, // LCR[7] = 0
XR_REG_TXLVL = 0x08, // LCR[7] = 0
XR_REG_RXLVL = 0x09, // LCR[7] = 0
XR_REG_IODIR = 0x0A, // LCR[7] = 0
XR_REG_IOSTATE = 0x0B, // LCR[7] = 0
XR_REG_IOINTENA = 0x0C, // LCR[7] = 0
XR_REG_IOCTRL = 0x0E, // LCR[7] = 0
XR_REG_EFCR = 0x0F, // LCR[7] = 0
XR_REG_IOCTRL = 0x0E, // LCR[7] = 0
XR_REG_EFCR = 0x0F, // LCR[7] = 0
XR_REG_EFR = 0x02, // LCR = 0xBF
XR_REG_XON1 = 0x04, // LCR = 0xBF
XR_REG_XON2 = 0x05, // LCR = 0xBF
XR_REG_EFR = 0x02, // LCR = 0xBF
XR_REG_XON1 = 0x04, // LCR = 0xBF
XR_REG_XON2 = 0x05, // LCR = 0xBF
XR_REG_XOFF1 = 0x06, // LCR = 0xBF
XR_REG_XOFF2 = 0x07, // LCR = 0xBF
} XrRegister;
@@ -104,19 +104,19 @@ typedef enum XrStopBit {
typedef enum XrParity {
XR_PARITY_NONE = 0x0, //!< No parity
XR_PARITY_ODD = 0x1, //!< Parity bit is odd
XR_PARITY_ODD = 0x1, //!< Parity bit is odd
XR_PARITY_EVEN = 0x3, //!< Parity bit is even
XR_PARITY_ONE = 0x5, //!< Parity bit is always one
XR_PARITY_ONE = 0x5, //!< Parity bit is always one
XR_PARITY_ZERO = 0x7, //!< Parity bit is always zero
} XrParity;
// TODO: a lot of these should be enums
typedef struct PACKED XrRegLcr {
XrWordLen wordLen : 2; // Word length to be transmitted or received
XrWordLen wordLen : 2; // Word length to be transmitted or received
XrStopBit stopBits : 1; // Length of stop bit
XrParity parity : 3; // Parity format
bool txBreak : 1; // Causes a break condition to be transmitted
bool divisorEn : 1; // Baud rate generator divisor (DLL, DLM and DLD)
XrParity parity : 3; // Parity format
bool txBreak : 1; // Causes a break condition to be transmitted
bool divisorEn : 1; // Baud rate generator divisor (DLL, DLM and DLD)
} XrRegLcr;
typedef struct PACKED XrRegDld {
@@ -178,7 +178,7 @@ typedef struct PACKED XrRegFcr {
/* Transmission Control Register (TCR) */
typedef struct PACKED XrRegTcr {
uint8_t rxHaltLvl : 4; /*!< x4, 0-60 - RTS goes high after this level */
uint8_t rxHaltLvl : 4; /*!< x4, 0-60 - RTS goes high after this level */
uint8_t rxResumeLvl : 4; /*!< x4, 0-60 - RTS returns low below this level */
} XrRegTcr;
@@ -203,9 +203,9 @@ typedef struct PACKED XrRegIer {
bool lsrIntEn : 1;
bool msrIntEn : 1;
bool sleepModeEn : 1; //!< EFR[4] = 1 to modify
bool xoffIntEn : 1; //!< EFR[4] = 1 to modify
bool rtsIntEn : 1; //!< EFR[4] = 1 to modify
bool ctsIntEn : 1; //!< EFR[4] = 1 to modify
bool xoffIntEn : 1; //!< EFR[4] = 1 to modify
bool rtsIntEn : 1; //!< EFR[4] = 1 to modify
bool ctsIntEn : 1; //!< EFR[4] = 1 to modify
} XrRegIer;
// Note: in order of priority

4
firmware/ec/src/devices/i2c/threaded_int.c
View File

@@ -25,9 +25,9 @@
// Config simply to map context to our GPIO interrupts
typedef struct InterruptConfig {
Semaphore_Handle sem; //!< Semaphore to wake up INT thread
Semaphore_Handle sem; //!< Semaphore to wake up INT thread
ThreadedInt_Callback cb; //!< Callback to run when interrupt occurs
void *context; //!< Pointer to pass to cb function
void *context; //!< Pointer to pass to cb function
} InterruptConfig;
static InterruptConfig s_intConfigs[MAX_DEVICES] = {};
static int s_numDevices = 0;

6
firmware/ec/src/devices/ina226.c
View File

@@ -56,10 +56,10 @@
* CONSTANTS DEFINITIONS
*****************************************************************************/
/* INA226 LSB Values */
#define INA226_VSHUNT_LSB 2.5 /* 2.5uV or 2500nV (uV default) */
#define INA226_VBUS_LSB 1.25 /* 1.25mV or 1250uV (mV default) */
#define INA226_VSHUNT_LSB 2.5 /* 2.5uV or 2500nV (uV default) */
#define INA226_VBUS_LSB 1.25 /* 1.25mV or 1250uV (mV default) */
#define INA226_CURRENT_LSB 0.1 /* 0.100mA 0r 100uA (mA default) */
#define INA226_POWER_LSB 2.5 /* 2.5mW or 2500uW (mW default) */
#define INA226_POWER_LSB 2.5 /* 2.5mW or 2500uW (mW default) */
/* Configure the Configuration register with Number of Samples and Conversion
* Time for Shunt and Bus Voltage.

28
firmware/ec/src/devices/led.c
View File

@@ -70,7 +70,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_2] =
@@ -78,7 +78,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_3] =
@@ -86,7 +86,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
},
[HCI_LED_4] =
@@ -94,7 +94,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_5] =
@@ -102,7 +102,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_6] =
@@ -110,7 +110,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_7] =
@@ -118,7 +118,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_LEFT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // I010
.ledRed = ~SX1509_IO_PIN_10, // I010
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_8] =
@@ -126,7 +126,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_5, // IO5
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledRed = ~SX1509_IO_PIN_4, // IO4
.ledOff = SX1509_IO_PIN_5 | SX1509_IO_PIN_4,
},
[HCI_LED_9] =
@@ -134,7 +134,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_3, // IO3
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledRed = ~SX1509_IO_PIN_2, // IO2
.ledOff = SX1509_IO_PIN_3 | SX1509_IO_PIN_2,
},
[HCI_LED_10] =
@@ -142,7 +142,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_1, // IO1
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledRed = ~SX1509_IO_PIN_0, // IO0
.ledOff = SX1509_IO_PIN_1 | SX1509_IO_PIN_0,
},
[HCI_LED_11] =
@@ -150,7 +150,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_A,
.ledGreen = ~SX1509_IO_PIN_7, // IO7
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledRed = ~SX1509_IO_PIN_6, // IO6
.ledOff = SX1509_IO_PIN_7 | SX1509_IO_PIN_6,
},
[HCI_LED_12] =
@@ -158,7 +158,7 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_9, // IO9
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledRed = ~SX1509_IO_PIN_8, // IO8
.ledOff = SX1509_IO_PIN_9 | SX1509_IO_PIN_8,
},
[HCI_LED_13] =
@@ -166,14 +166,14 @@ static const hciLedData ledData[HCI_LED_TOTAL_NOS] =
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_11, // IO11
.ledRed = ~SX1509_IO_PIN_10, // IO10
.ledRed = ~SX1509_IO_PIN_10, // IO10
.ledOff = SX1509_IO_PIN_11 | SX1509_IO_PIN_10,
},
[HCI_LED_14] = {
.ioexpDev = HCI_LED_DRIVER_RIGHT,
.ledReg = SX1509_REG_B,
.ledGreen = ~SX1509_IO_PIN_13, // IO13
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledRed = ~SX1509_IO_PIN_12, // IO12
.ledOff = SX1509_IO_PIN_13 | SX1509_IO_PIN_12,
} };

6
firmware/ec/src/devices/sbdn9603.c
View File

@@ -55,7 +55,7 @@ static UART_Handle open_comm(const Iridium_Cfg *iridium)
/* reset - for proper reset, Iridium should be disabled for ~2s */
OcGpio_write(&iridium->pin_enable, false); /* Just to be sure it's low */
Task_sleep(2100); // TODO: should be ~2s
Task_sleep(2100); // TODO: should be ~2s
OcGpio_write(&iridium->pin_enable, true);
Task_sleep(200); // TODO: idk...probably doesn't need to be long
@@ -92,8 +92,8 @@ ReturnStatus sbd_init(const Iridium_Cfg *iridium)
}
/* TODO: module verification? */
if (!SBD_k(s_hSbd, SBD_FLOW_CONTROL_HW) /* Enable HW flow control */
|| !SBD_sbdmta(s_hSbd, true) /* Ring indication enable */
if (!SBD_k(s_hSbd, SBD_FLOW_CONTROL_HW) /* Enable HW flow control */
|| !SBD_sbdmta(s_hSbd, true) /* Ring indication enable */
|| !SBD_sbdareg(s_hSbd, SBD_AREG_MODE_AUTO) /* Auto registration */
|| !SBD_cier(s_hSbd, true, false, true, false,
false)) { /* Service change indications */

16
firmware/ec/src/devices/se98a.c
View File

@@ -35,18 +35,18 @@
/* Configuration Bits */
#define SE98A_CFG_HEN_H (1 << 10) /* Hysteresis Enable High Bit */
#define SE98A_CFG_HEN_L (1 << 9) /* Hysteresis Enable Low Bit */
#define SE98A_CFG_SHMD (1 << 8) /* Shutdown Mode */
#define SE98A_CFG_HEN_L (1 << 9) /* Hysteresis Enable Low Bit */
#define SE98A_CFG_SHMD (1 << 8) /* Shutdown Mode */
#define SE98A_CFG_CTLB (1 << 7) /* Critical Trip Lock Bit */
#define SE98A_CFG_AWLB (1 << 6) /* Alarm Window Lock Bit */
#define SE98A_CFG_CTLB (1 << 7) /* Critical Trip Lock Bit */
#define SE98A_CFG_AWLB (1 << 6) /* Alarm Window Lock Bit */
#define SE98A_CFG_CEVENT (1 << 5) /* (WO) Clear EVENT */
#define SE98A_CFG_ESTAT (1 << 4) /* (RO) EVENT Status */
#define SE98A_CFG_ESTAT (1 << 4) /* (RO) EVENT Status */
#define SE98A_CFG_EOCTL (1 << 3) /* EVENT Output Control */
#define SE98A_CFG_CVO (1 << 2) /* Critical Event Only */
#define SE98A_CFG_EP (1 << 1) /* EVENT Polarity */
#define SE98A_CFG_EMD (1 << 0) /* EVENT Mode */
#define SE98A_CFG_CVO (1 << 2) /* Critical Event Only */
#define SE98A_CFG_EP (1 << 1) /* EVENT Polarity */
#define SE98A_CFG_EMD (1 << 0) /* EVENT Mode */
#define SE98A_CFG_HYS_0 (0x0 << 9)
#define SE98A_CFG_HYS_1P5 (0x1 << 9)

126
firmware/ec/src/devices/sx1509.c
View File

@@ -32,30 +32,34 @@
0x05 /* Output buffer low drive register I/O[7..0] (Bank A) */
#define SX1509_REG_PULL_UP_B 0x06 /* Pull_up register I/O[15..8] (Bank B) */
#define SX1509_REG_PULL_UP_A 0x07 /* Pull_up register I/O[7..0] (Bank A) */
#define SX1509_REG_PULL_DOWN_B 0x08 /* Pull_down register I/O[15..8] (Bank B) \
*/
#define SX1509_REG_PULL_DOWN_A 0x09 /* Pull_down register I/O[7..0] (Bank A) \
*/
#define SX1509_REG_PULL_DOWN_B \
0x08 /* Pull_down register I/O[15..8] (Bank B) \
*/
#define SX1509_REG_PULL_DOWN_A \
0x09 /* Pull_down register I/O[7..0] (Bank A) \
*/
#define SX1509_REG_OPEN_DRAIN_B \
0x0A /* Open drain register I/O[15..8] (Bank B) */
#define SX1509_REG_OPEN_DRAIN_A \
0x0B /* Open drain register I/O[7..0] (Bank A) */
0x0B /* Open drain register I/O[7..0] (Bank A) */
#define SX1509_REG_POLARITY_B 0x0C /* Polarity register I/O[15..8] (Bank B) */
#define SX1509_REG_POLARITY_A 0x0D /* Polarity register I/O[7..0] (Bank A) */
#define SX1509_REG_DIR_B 0x0E /* Direction register I/O[15..8] (Bank B) */
#define SX1509_REG_DIR_A 0x0F /* Direction register I/O[7..0] (Bank A) */
#define SX1509_REG_DATA_B 0x10 /* Data register I/O[15..8] (Bank B) */
#define SX1509_REG_DATA_A 0x11 /* Data register I/O[7..0] (Bank A) */
#define SX1509_REG_DIR_B 0x0E /* Direction register I/O[15..8] (Bank B) */
#define SX1509_REG_DIR_A 0x0F /* Direction register I/O[7..0] (Bank A) */
#define SX1509_REG_DATA_B 0x10 /* Data register I/O[15..8] (Bank B) */
#define SX1509_REG_DATA_A 0x11 /* Data register I/O[7..0] (Bank A) */
#define SX1509_REG_INTERRUPT_MASK_B \
0x12 /* Interrupt mask register I/O[15..8] (Bank B) */
#define SX1509_REG_INTERRUPT_MASK_A \
0x13 /* Interrupt mask register I/O[7..0] (Bank A) */
#define SX1509_REG_SENSE_HIGH_B \
0x14 /* Sense register for I/O[15:12] (Bank B) */
#define SX1509_REG_SENSE_LOW_B 0x15 /* Sense register for I/O[11:8] (Bank B) \
#define SX1509_REG_SENSE_LOW_B \
0x15 /* Sense register for I/O[11:8] (Bank B) \
*/
#define SX1509_REG_SENSE_HIGH_A \
0x16 /* Sense register for I/O[7:4] (Bank A) \
*/
#define SX1509_REG_SENSE_HIGH_A 0x16 /* Sense register for I/O[7:4] (Bank A) \
*/
#define SX1509_REG_SENSE_LOW_A 0x17 /* Sense register for I/O[3:0] (Bank A) */
#define SX1509_REG_INTERRUPT_SOURCE_B \
0x18 /* Interrupt source register I/O[15..8] (Bank B) */
@@ -67,7 +71,7 @@
0x1B /* Event status register I/O[7..0] (Bank A) */
#define SX1509_REG_LEVEL_SHIFTER_1 0x1C /* Level shifter register 1 */
#define SX1509_REG_LEVEL_SHIFTER_2 0x1D /* Level shifter register 2 */
#define SX1509_REG_CLOCK 0x1E /* Clock management register */
#define SX1509_REG_CLOCK 0x1E /* Clock management register */
#define SX1509_REG_MISC 0x1F /* Miscellaneous device settings register */
#define SX1509_REG_LED_DRIVER_ENABLE_B \
0x20 /* LED driver enable register I/O[15..8] (Bank B) */
@@ -77,76 +81,76 @@
#define SX1509_REG_DEBOUNCE_ENABLE_B \
0x23 /* Debounce enable register I/O[15..8] (Bank B) */
#define SX1509_REG_DEBOUNCE_ENABLE_A \
0x24 /* Debounce enable register I/O[7..0] (Bank A) */
0x24 /* Debounce enable register I/O[7..0] (Bank A) */
#define SX1509_REG_T_ON_0 0x29 /* ON time register for I/O[0] */
#define SX1509_REG_I_ON_0 0x2A /* ON intensity register for I/O[0] */
#define SX1509_REG_OFF_0 0x2B /* OFF time/intensity register for I/O[0] */
#define SX1509_REG_OFF_0 0x2B /* OFF time/intensity register for I/O[0] */
#define SX1509_REG_T_ON_1 0x2C /* ON time register for I/O[1] */
#define SX1509_REG_I_ON_1 0x2D /* ON intensity register for I/O[1] */
#define SX1509_REG_OFF_1 0x2E /* OFF time/intensity register for I/O[1] */
#define SX1509_REG_OFF_1 0x2E /* OFF time/intensity register for I/O[1] */
#define SX1509_REG_T_ON_2 0x2F /* ON time register for I/O[2] */
#define SX1509_REG_I_ON_2 0x30 /* ON intensity register for I/O[2] */
#define SX1509_REG_OFF_2 0x31 /* OFF time/intensity register for I/O[2] */
#define SX1509_REG_OFF_2 0x31 /* OFF time/intensity register for I/O[2] */
#define SX1509_REG_T_ON_3 0x32 /* ON time register for I/O[3] */
#define SX1509_REG_I_ON_3 0x33 /* ON intensity register for I/O[3] */
#define SX1509_REG_OFF_3 0x34 /* OFF time/intensity register for I/O[3] */
#define SX1509_REG_OFF_3 0x34 /* OFF time/intensity register for I/O[3] */
#define SX1509_REG_T_ON_4 0x35 /* ON time register for I/O[4] */
#define SX1509_REG_I_ON_4 0x36 /* ON intensity register for I/O[4] */
#define SX1509_REG_OFF_4 0x37 /* OFF time/intensity register for I/O[4] */
#define SX1509_REG_T_RISE_4 0x38 /* Fade in register for I/O[4] */
#define SX1509_REG_T_FALL_4 0x39 /* Fade out register for I/O[4] */
#define SX1509_REG_T_ON_5 0x3A /* ON time register for I/O[5] */
#define SX1509_REG_I_ON_5 0x3B /* ON intensity register for I/O[5] */
#define SX1509_REG_OFF_5 0x3C /* OFF time/intensity register for I/O[5] */
#define SX1509_REG_T_RISE_5 0x3D /* Fade in register for I/O[5] */
#define SX1509_REG_T_FALL_5 0x3E /* Fade out register for I/O[5] */
#define SX1509_REG_T_ON_6 0x3F /* ON time register for I/O[6] */
#define SX1509_REG_I_ON_6 0x40 /* ON intensity register for I/O[6] */
#define SX1509_REG_OFF_6 0x41 /* OFF time/intensity register for I/O[6] */
#define SX1509_REG_T_RISE_6 0x42 /* Fade in register for I/O[6] */
#define SX1509_REG_T_FALL_6 0x43 /* Fade out register for I/O[6] */
#define SX1509_REG_T_ON_7 0x44 /* ON time register for I/O[7] */
#define SX1509_REG_I_ON_7 0x45 /* ON intensity register for I/O[7] */
#define SX1509_REG_OFF_7 0x46 /* OFF time/intensity register for I/O[7] */
#define SX1509_REG_T_RISE_7 0x47 /* Fade in register for I/O[7] */
#define SX1509_REG_T_FALL_7 0x48 /* Fade out register for I/O[7] */
#define SX1509_REG_T_ON_8 0x49 /* ON time register for I/O[8] */
#define SX1509_REG_I_ON_8 0x4A /* ON intensity register for I/O[8] */
#define SX1509_REG_OFF_8 0x4B /* OFF time/intensity register for I/O[8] */
#define SX1509_REG_T_ON_9 0x4C /* ON time register for I/O[9] */
#define SX1509_REG_I_ON_9 0x4D /* ON intensity register for I/O[9] */
#define SX1509_REG_OFF_9 0x4E /* OFF time/intensity register for I/O[9] */
#define SX1509_REG_T_ON_10 0x4F /* ON time register for I/O[10] */
#define SX1509_REG_I_ON_10 0x50 /* ON intensity register for I/O[10] */
#define SX1509_REG_OFF_10 0x51 /* OFF time/intensity register for I/O[10] */
#define SX1509_REG_T_ON_11 0x52 /* ON time register for I/O[11] */
#define SX1509_REG_I_ON_11 0x53 /* ON intensity register for I/O[11] */
#define SX1509_REG_OFF_11 0x54 /* OFF time/intensity register for I/O[11] */
#define SX1509_REG_T_ON_12 0x55 /* ON time register for I/O[12] */
#define SX1509_REG_I_ON_12 0x56 /* ON intensity register for I/O[12] */
#define SX1509_REG_OFF_12 0x57 /* OFF time/intensity register for I/O[12] */
#define SX1509_REG_OFF_4 0x37 /* OFF time/intensity register for I/O[4] */
#define SX1509_REG_T_RISE_4 0x38 /* Fade in register for I/O[4] */
#define SX1509_REG_T_FALL_4 0x39 /* Fade out register for I/O[4] */
#define SX1509_REG_T_ON_5 0x3A /* ON time register for I/O[5] */
#define SX1509_REG_I_ON_5 0x3B /* ON intensity register for I/O[5] */
#define SX1509_REG_OFF_5 0x3C /* OFF time/intensity register for I/O[5] */
#define SX1509_REG_T_RISE_5 0x3D /* Fade in register for I/O[5] */
#define SX1509_REG_T_FALL_5 0x3E /* Fade out register for I/O[5] */
#define SX1509_REG_T_ON_6 0x3F /* ON time register for I/O[6] */
#define SX1509_REG_I_ON_6 0x40 /* ON intensity register for I/O[6] */
#define SX1509_REG_OFF_6 0x41 /* OFF time/intensity register for I/O[6] */
#define SX1509_REG_T_RISE_6 0x42 /* Fade in register for I/O[6] */
#define SX1509_REG_T_FALL_6 0x43 /* Fade out register for I/O[6] */
#define SX1509_REG_T_ON_7 0x44 /* ON time register for I/O[7] */
#define SX1509_REG_I_ON_7 0x45 /* ON intensity register for I/O[7] */
#define SX1509_REG_OFF_7 0x46 /* OFF time/intensity register for I/O[7] */
#define SX1509_REG_T_RISE_7 0x47 /* Fade in register for I/O[7] */
#define SX1509_REG_T_FALL_7 0x48 /* Fade out register for I/O[7] */
#define SX1509_REG_T_ON_8 0x49 /* ON time register for I/O[8] */
#define SX1509_REG_I_ON_8 0x4A /* ON intensity register for I/O[8] */
#define SX1509_REG_OFF_8 0x4B /* OFF time/intensity register for I/O[8] */
#define SX1509_REG_T_ON_9 0x4C /* ON time register for I/O[9] */
#define SX1509_REG_I_ON_9 0x4D /* ON intensity register for I/O[9] */
#define SX1509_REG_OFF_9 0x4E /* OFF time/intensity register for I/O[9] */
#define SX1509_REG_T_ON_10 0x4F /* ON time register for I/O[10] */
#define SX1509_REG_I_ON_10 0x50 /* ON intensity register for I/O[10] */
#define SX1509_REG_OFF_10 0x51 /* OFF time/intensity register for I/O[10] */
#define SX1509_REG_T_ON_11 0x52 /* ON time register for I/O[11] */
#define SX1509_REG_I_ON_11 0x53 /* ON intensity register for I/O[11] */
#define SX1509_REG_OFF_11 0x54 /* OFF time/intensity register for I/O[11] */
#define SX1509_REG_T_ON_12 0x55 /* ON time register for I/O[12] */
#define SX1509_REG_I_ON_12 0x56 /* ON intensity register for I/O[12] */
#define SX1509_REG_OFF_12 0x57 /* OFF time/intensity register for I/O[12] */
#define SX1509_REG_T_RISE_12 0x58 /* Fade in register for I/O[12] */
#define SX1509_REG_T_FALL_12 0x59 /* Fade out register for I/O[12] */
#define SX1509_REG_T_ON_13 0x5A /* ON time register for I/O[13] */
#define SX1509_REG_I_ON_13 0x5B /* ON intensity register for I/O[13] */
#define SX1509_REG_OFF_13 0x5C /* OFF time/intensity register for I/O[13] */
#define SX1509_REG_T_ON_13 0x5A /* ON time register for I/O[13] */
#define SX1509_REG_I_ON_13 0x5B /* ON intensity register for I/O[13] */
#define SX1509_REG_OFF_13 0x5C /* OFF time/intensity register for I/O[13] */
#define SX1509_REG_T_RISE_13 0x5D /* Fade in register for I/O[13] */
#define SX1509_REG_T_FALL_13 0x5E /* Fade out register for I/O[13] */
#define SX1509_REG_T_ON_14 0x5F /* ON time register for I/O[14] */
#define SX1509_REG_I_ON_14 0x60 /* ON intensity register for I/O[14] */
#define SX1509_REG_OFF_14 0x61 /* OFF time/intensity register for I/O[14] */
#define SX1509_REG_T_ON_14 0x5F /* ON time register for I/O[14] */
#define SX1509_REG_I_ON_14 0x60 /* ON intensity register for I/O[14] */
#define SX1509_REG_OFF_14 0x61 /* OFF time/intensity register for I/O[14] */
#define SX1509_REG_T_RISE_14 0x62 /* Fade in register for I/O[14] */
#define SX1509_REG_T_FALL_14 0x63 /* Fade out register for I/O[14] */
#define SX1509_REG_T_ON_15 0x64 /* ON time register for I/O[15] */
#define SX1509_REG_I_ON_15 0x65 /* ON intensity register for I/O[15] */
#define SX1509_REG_OFF_15 0x66 /* OFF time/intensity register for I/O[15] */
#define SX1509_REG_T_ON_15 0x64 /* ON time register for I/O[15] */
#define SX1509_REG_I_ON_15 0x65 /* ON intensity register for I/O[15] */
#define SX1509_REG_OFF_15 0x66 /* OFF time/intensity register for I/O[15] */
#define SX1509_REG_T_RISE_15 0x67 /* Fade in register for I/O[15] */
#define SX1509_REG_T_FALL_15 0x68 /* Fade out register for I/O[15] */
#define SX1509_REG_HIGH_INPUT_B \
0x69 /* High input enable register I/O[15..8] (Bank B) */
#define SX1509_REG_HIGH_INPUT_A \
0x6A /* High input enable register I/O[7..0] (Bank A) */
#define SX1509_REG_RESET 0x7D /* Software reset register */
#define SX1509_REG_RESET 0x7D /* Software reset register */
#define SX1509_REG_TEST_1 0x7E /* Test register 1 */
#define SX1509_REG_TEST_2 0x7F /* Test register 2 */

4
firmware/ec/src/devices/uart/UartMon.h
View File

@@ -53,7 +53,7 @@
extern const UART_FxnTable UartMon_fxnTable;
typedef struct UartMon_Cfg {
unsigned int uart_in_idx; /*!< The UART we're going to monitor */
unsigned int uart_in_idx; /*!< The UART we're going to monitor */
unsigned int uart_debug_idx; /*!< The UART we're going to forward to */
} UartMon_Cfg;
@@ -63,7 +63,7 @@ typedef struct UartMon_Object {
bool opened : 1; /*!< Is there an open handle to the driver */
} state;
UART_Handle hUart_in; /*!< Handle to the monitored UART */
UART_Handle hUart_in; /*!< Handle to the monitored UART */
UART_Handle hUart_debug; /*!< Handle to the forwarding UART */
} UartMon_Object;

2
firmware/ec/src/devices/uart/at_cmd.c
View File

@@ -287,7 +287,7 @@ static bool AT_cmd_read_line(AT_Handle handle, At_RawResponse *res)
if (handle->binaryReadHandler) {
handle->s_bufLen =
lineLen + 1; // TODO: this is dumb, get_line_type should
// just know about the temp buf
// just know about the temp buf
res->size = handle->binaryReadHandler(handle, res->data);
handle->binaryReadHandler = NULL;
return (res->size >= 0);

10
firmware/ec/src/devices/uart/gsm.h
View File

@@ -37,11 +37,11 @@ typedef enum GsmCallState {
GSM_CALL_STATE_ACTIVE = 0,
GSM_CALL_STATE_HELD = 1,
GSM_CALL_STATE_DIALING = 2, /* MO */
GSM_CALL_STATE_DIALING = 2, /* MO */
GSM_CALL_STATE_ALERTING = 3, /* MO */
GSM_CALL_STATE_INCOMING = 4, /* MT */
GSM_CALL_STATE_WAITING = 5, /* MT */
GSM_CALL_STATE_WAITING = 5, /* MT */
GSM_CALL_STATE_RELEASED = 6,
} GsmCallState;
@@ -194,10 +194,10 @@ typedef enum GsmCmgdFlag {
bool GSM_cmgd(GSM_Handle handle, int index, GsmCmgdFlag flag);
typedef enum GsmCFun {
GSM_CFUN_OFF = 0, /*!< Power off module */
GSM_CFUN_FULL = 1, /*!< Enable full radio functionality */
GSM_CFUN_OFF = 0, /*!< Power off module */
GSM_CFUN_FULL = 1, /*!< Enable full radio functionality */
GSM_CFUN_AIRPLANE = 4, /*!< Turn off radio functionality */
GSM_CFUN_RESET = 15 /*!< Hardware reset */
GSM_CFUN_RESET = 15 /*!< Hardware reset */
} GsmCFun;
bool GSM_cfun(GSM_Handle handle, GsmCFun fun);

10
firmware/ec/src/devices/uart/sbd.h
View File

@@ -65,17 +65,17 @@ typedef struct SbdixInfo {
typedef struct SbdsInfo {
int moFlag; //!< Message in mobile originated buffer
int moMsn; //!< MO message sequence number
int moMsn; //!< MO message sequence number
int mtFlag; //!< Message in mobile terminated buffer
int mtMsn; //!< MT Message sequence number
int mtMsn; //!< MT Message sequence number
} SbdsInfo;
typedef struct SbdsxInfo {
SbdsInfo sbdsInfo; //!< Regular SBD status info
int raFlag; //!< Ring alert still needs to be answered
int msgWaiting; //!< Number of MT messages at gateway
//!< (updated every SBD session)
int raFlag; //!< Ring alert still needs to be answered
int msgWaiting; //!< Number of MT messages at gateway
//!< (updated every SBD session)
} SbdsxInfo;
typedef enum SbdCiev {

6
firmware/ec/src/drivers/GpioSX1509.c
View File

@@ -150,9 +150,9 @@ static int GpioSX1509_read(const OcGpio_Pin *pin)
/* TODO: this mapping is pretty gross with the shifts */
static const uint8_t EDGE_SENSE_MAP[] = {
[OCGPIO_CFG_INT_NONE >> OCGPIO_CFG_INT_LSB] = 0x00, /* 00 */
[OCGPIO_CFG_INT_RISING >> OCGPIO_CFG_INT_LSB] = 0x01, /* 01 */
[OCGPIO_CFG_INT_FALLING >> OCGPIO_CFG_INT_LSB] = 0x02, /* 10 */
[OCGPIO_CFG_INT_NONE >> OCGPIO_CFG_INT_LSB] = 0x00, /* 00 */
[OCGPIO_CFG_INT_RISING >> OCGPIO_CFG_INT_LSB] = 0x01, /* 01 */
[OCGPIO_CFG_INT_FALLING >> OCGPIO_CFG_INT_LSB] = 0x02, /* 10 */
[OCGPIO_CFG_INT_BOTH_EDGES >> OCGPIO_CFG_INT_LSB] = 0x03, /* 11 */
};

6
firmware/ec/src/drivers/OcGpio.h
View File

@@ -45,8 +45,8 @@ typedef struct OcGpio_FnTable {
/*! A port defines a specific driver instance to route through */
struct OcGpio_Port {
const OcGpio_FnTable *fn_table; /*!< virtual table for driver */
const void *cfg; /*!< driver-specific config settings */
void *object_data; /*!< driver-specific data (in RAM) */
const void *cfg; /*!< driver-specific config settings */
void *object_data; /*!< driver-specific data (in RAM) */
};
/*! A pin provides us with everything we need to route data to the appropriate
@@ -55,7 +55,7 @@ struct OcGpio_Port {
*/
struct OcGpio_Pin {
const OcGpio_Port *port; /*!< Pointer to IO driver instance */
uint16_t idx; /*!< Driver-specific index */
uint16_t idx; /*!< Driver-specific index */
uint16_t hw_cfg; /*!< Any special attributes for the pin (eg. invert) */
};

70
firmware/ec/src/interfaces/USB/usbcdcd.c
View File

@@ -235,27 +235,27 @@ tUSBBuffer rxBuffer;
static tUSBDCDCDevice serialDevice;
tUSBBuffer rxBuffer = {
false, /* This is a receive buffer. */
cbRxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketRead, /* pfnTransfer */
false, /* This is a receive buffer. */
cbRxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketRead, /* pfnTransfer */
USBDCDCRxPacketAvailable, /* pfnAvailable */
(void *)&serialDevice, /* pvHandle */
receiveBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
{ { 0, 0, 0, 0 }, 0, 0 } /* private data workspace */
(void *)&serialDevice, /* pvHandle */
receiveBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
{ { 0, 0, 0, 0 }, 0, 0 } /* private data workspace */
};
tUSBBuffer txBuffer = {
true, /* This is a transmit buffer. */
cbTxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketWrite, /* pfnTransfer */
true, /* This is a transmit buffer. */
cbTxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketWrite, /* pfnTransfer */
USBDCDCTxPacketAvailable, /* pfnAvailable */
(void *)&serialDevice, /* pvHandle */
transmitBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
{ { 0, 0, 0, 0 }, 0, 0 } /* private data workspace */
(void *)&serialDevice, /* pvHandle */
transmitBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
{ { 0, 0, 0, 0 }, 0, 0 } /* private data workspace */
};
static tUSBDCDCDevice serialDevice = { USB_VID_TI_1CBE,
@@ -284,27 +284,27 @@ static tCDCSerInstance serialInstance;
const tUSBDCDCDevice serialDevice;
const tUSBBuffer rxBuffer = {
false, /* This is a receive buffer. */
cbRxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketRead, /* pfnTransfer */
false, /* This is a receive buffer. */
cbRxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketRead, /* pfnTransfer */
USBDCDCRxPacketAvailable, /* pfnAvailable */
(void *)&serialDevice, /* pvHandle */
receiveBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
receiveBufferWorkspace /* pvWorkspace */
(void *)&serialDevice, /* pvHandle */
receiveBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
receiveBufferWorkspace /* pvWorkspace */
};
const tUSBBuffer txBuffer = {
true, /* This is a transmit buffer. */
cbTxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketWrite, /* pfnTransfer */
true, /* This is a transmit buffer. */
cbTxHandler, /* pfnCallback */
(void *)&serialDevice, /* Callback data is our device pointer. */
USBDCDCPacketWrite, /* pfnTransfer */
USBDCDCTxPacketAvailable, /* pfnAvailable */
(void *)&serialDevice, /* pvHandle */
transmitBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
transmitBufferWorkspace /* pvWorkspace */
(void *)&serialDevice, /* pvHandle */
transmitBuffer, /* pcBuffer */
USBBUFFERSIZE, /* ulBufferSize */
transmitBufferWorkspace /* pvWorkspace */
};
const tUSBDCDCDevice serialDevice = {
@@ -331,9 +331,9 @@ const tUSBDCDCDevice serialDevice = {
static tLineCoding g_sLineCoding = {
115200, /* 115200 baud rate. */
1, /* 1 Stop Bit. */
0, /* No Parity. */
8 /* 8 Bits of data. */
1, /* 1 Stop Bit. */
0, /* No Parity. */
8 /* 8 Bits of data. */
};
/*

4
firmware/ec/src/registry/SSRegistry.c
View File

@@ -428,9 +428,9 @@ static void subsystem_init(OCMPSubsystem ss_id)
/* Spin up the task */
Task_Params taskParams;
Task_Params_init(&taskParams);
taskParams.stack = OC_task_stack[ss_id]; // ss->taskStack;
taskParams.stack = OC_task_stack[ss_id]; // ss->taskStack;
taskParams.stackSize = OC_TASK_STACK_SIZE; // ss->taskStackSize;
taskParams.priority = OC_TASK_PRIORITY; // ss->taskPriority;
taskParams.priority = OC_TASK_PRIORITY; // ss->taskPriority;
taskParams.arg0 = (UArg)ss;
taskParams.arg1 = ss_id;

2
firmware/ec/src/subsystem/obc/obc.c
View File

@@ -35,7 +35,7 @@ ReturnStatus iridium_sw_reset(const Iridium_Cfg *iridium)
/* reset - for proper reset, Iridium should be disabled for ~2s */
OcGpio_write(&iridium->pin_enable, false); /* Just to be sure it's low */
Task_sleep(2100); // TODO: should be ~2s
Task_sleep(2100); // TODO: should be ~2s
OcGpio_write(&iridium->pin_enable, true);
Task_sleep(200); // TODO: idk...probably doesn't need to be lon
return RETURN_OK;

2
firmware/ec/src/utils/util.c
View File

@@ -55,7 +55,7 @@
// RTOS queue for profile/app messages.
typedef struct _queueRec_ {
Queue_Elem _elem; // queue element
uint8_t *pData; // pointer to app data
uint8_t *pData; // pointer to app data
} queueRec_t;
/*********************************************************************

2
firmware/ec/test/suites/Test_eeprom.c
View File

@@ -53,7 +53,7 @@ static Eeprom_Cfg s_dev = {
};
static uint16_t EEPROM_regs[] = {
[0x00] = 0x00, /* Init */
[0x00] = 0x00, /* Init */
[0xC601] = 0x00, /* SERIAL INFO */
[0xAC01] = 0x00, /* BOARD INFO */
[0x0A01] = 0x00, /* DEVICE INFO */

4
firmware/ec/test/suites/Test_ina226.c
View File

@@ -163,7 +163,7 @@ static void _test_alert(INA226_Dev *dev, INA226_Event evt, uint16_t alert_mask,
FakeGpio_triggerInterrupt(dev->cfg.pin_alert);
TEST_ASSERT_EQUAL(0, s_alert_data.triggered);
INA226_regs[0x06] |= (1 << 4); /* Fault caused alert */
INA226_regs[0x06] |= (1 << 4); /* Fault caused alert */
alert_mask = INA226_regs[0x06]; /* Store reg value for later comparison */
FakeGpio_triggerInterrupt(dev->cfg.pin_alert);
@@ -239,7 +239,7 @@ void test_current_limit(void)
TEST_ASSERT_EQUAL(1000, current_val); // 1000mA
TEST_ASSERT_EQUAL(RETURN_OK, ina226_setCurrentLim(&s_dev, 3000)); // 3000mA
TEST_ASSERT_EQUAL_HEX16(0x0960, INA226_regs[0x07]); // 2400
TEST_ASSERT_EQUAL_HEX16(0x0960, INA226_regs[0x07]); // 2400
TEST_ASSERT_EQUAL(RETURN_OK, ina226_readCurrentLim(&s_dev, &current_val));
TEST_ASSERT_EQUAL(3000, current_val); // 3000mA

16
firmware/ec/test/suites/Test_powerSource.c
View File

@@ -211,7 +211,7 @@ static PWRSRC_Dev p_dev = {
void test_pwr_process_get_status_parameters_data_poeavailable(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x00; // PoE Availability
uint8_t index = 0x00; // PoE Availability
PWR_GpioPins[0x55] = 0x0; // PoE Enable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x18; // Int/Ext Battery Disable
@@ -227,7 +227,7 @@ void test_pwr_process_get_status_parameters_data_poeavailable(void)
void test_pwr_process_get_status_parameters_data_poeaccessible(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x01; // PoE Accessibility
uint8_t index = 0x01; // PoE Accessibility
PWR_GpioPins[0x55] = 0x0; // PoE Enable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x18; // Int/Ext Battery Disable
@@ -243,7 +243,7 @@ void test_pwr_process_get_status_parameters_data_poeaccessible(void)
void test_pwr_process_get_status_parameters_data_solaravailable(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x02; // SOLAR Availability
uint8_t index = 0x02; // SOLAR Availability
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x0; // Aux/solar Enable
SX1509_regs[0x10] = 0x18; // Int/Ext Battery Disable
@@ -259,7 +259,7 @@ void test_pwr_process_get_status_parameters_data_solaravailable(void)
void test_pwr_process_get_status_parameters_data_solaraccessible(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x03; // SOLAR Accessibility
uint8_t index = 0x03; // SOLAR Accessibility
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x0; // Aux/solar Enable
SX1509_regs[0x10] = 0x18; // Int/Ext Battery Disable
@@ -275,7 +275,7 @@ void test_pwr_process_get_status_parameters_data_solaraccessible(void)
void test_pwr_process_get_status_parameters_data_extavailable(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x04; // Ext Batt availability
uint8_t index = 0x04; // Ext Batt availability
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x08; // Int Batt OFF, Ext batt ON
@@ -291,7 +291,7 @@ void test_pwr_process_get_status_parameters_data_extavailable(void)
void test_pwr_process_get_status_parameters_data_extaccessible(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x05; // Ext Batt accessibility
uint8_t index = 0x05; // Ext Batt accessibility
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x08; // Int Batt OFF, Ext batt ON
@@ -307,7 +307,7 @@ void test_pwr_process_get_status_parameters_data_extaccessible(void)
void test_pwr_process_get_status_parameters_data_intavailable(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x06; // Int Batt Availability
uint8_t index = 0x06; // Int Batt Availability
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x10; // Ext Batt OFF, Int batt ON
@@ -323,7 +323,7 @@ void test_pwr_process_get_status_parameters_data_intavailable(void)
void test_pwr_process_get_status_parameters_data_intaccessible(void)
{
uint8_t powerStatus = 0;
uint8_t index = 0x07; // Int Batt Accessibility
uint8_t index = 0x07; // Int Batt Accessibility
PWR_GpioPins[0x55] = 0x1; // PoE Disable
PWR_GpioPins[0x1E] = 0x1; // Aux/solar Disable
SX1509_regs[0x10] = 0x10; // Ext Batt OFF, Int batt ON

16
firmware/ec/test/suites/Test_sx1509.c
View File

@@ -229,7 +229,7 @@ void test_ioexp_led_inputbuffer(void)
/* Test setting input buffer values */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_inputbuffer(
&s_sx1509_dev, SX1509_REG_AB, 0x55,
0xAA)); // LSB(Reg A), LSB(Reg B)
0xAA)); // LSB(Reg A), LSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0x55, SX1509_regs[0x01]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0xAA, SX1509_regs[0x00]); // Reg B
@@ -244,7 +244,7 @@ void test_ioexp_led_pullup(void)
/* Test setting pull up values */
TEST_ASSERT_EQUAL(
RETURN_OK, ioexp_led_config_pullup(&s_sx1509_dev, SX1509_REG_AB, 0x27,
0x82)); // LSB(Reg A), MSB(Reg B)
0x82)); // LSB(Reg A), MSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0x27, SX1509_regs[0x07]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0x82, SX1509_regs[0x06]); // Reg B
@@ -274,7 +274,7 @@ void test_ioexp_led_opendrain(void)
/* Test setting open drain values */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_opendrain(
&s_sx1509_dev, SX1509_REG_AB, 0x45,
0x54)); // LSB(Reg A), MSB(Reg B)
0x54)); // LSB(Reg A), MSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0x45, SX1509_regs[0x0B]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0x54, SX1509_regs[0x0A]); // Reg B
@@ -289,7 +289,7 @@ void test_ioexp_led_data_direction(void)
/* Test setting data direction values */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_data_direction(
&s_sx1509_dev, SX1509_REG_AB, 0xAB,
0xD9)); // LSB(Reg A), MSB(Reg B)
0xD9)); // LSB(Reg A), MSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0xAB, SX1509_regs[0x0F]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0xD9, SX1509_regs[0x0E]); // Reg B
@@ -364,7 +364,7 @@ void test_ioexp_led_enable_leddriver(void)
/* Test setting led driver values */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_enable_leddriver(
&s_sx1509_dev, SX1509_REG_AB, 0x52,
0xF8)); // LSB(Reg A), MSB(Reg B)
0xF8)); // LSB(Reg A), MSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0x52, SX1509_regs[0x21]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0xF8, SX1509_regs[0x20]); // Reg B
@@ -395,7 +395,7 @@ void test_ioexp_led_interrupt(void)
/* Test setting interrupt values */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_interrupt(
&s_sx1509_dev, SX1509_REG_AB, 0x27,
0x28)); // LSB(Reg A), MSB(Reg B)
0x28)); // LSB(Reg A), MSB(Reg B)
TEST_ASSERT_EQUAL_HEX8(0x27, SX1509_regs[0x13]); // Reg A
TEST_ASSERT_EQUAL_HEX8(0x28, SX1509_regs[0x12]); // Reg B
@@ -411,7 +411,7 @@ void test_ioexp_led_edge_sense_A(void)
/* Rising edge */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_edge_sense_A(
&s_sx1509_dev, SX1509_REG_AB, 0x55,
0x55)); // Low(Reg A), High(Reg A)
0x55)); // Low(Reg A), High(Reg A)
TEST_ASSERT_EQUAL_HEX8(0x55, SX1509_regs[0x17]); // Low Reg A
TEST_ASSERT_EQUAL_HEX8(0x55, SX1509_regs[0x16]); // High Reg A
@@ -434,7 +434,7 @@ void test_ioexp_led_edge_sense_B(void)
/* Falling edge */
TEST_ASSERT_EQUAL(RETURN_OK, ioexp_led_config_edge_sense_B(
&s_sx1509_dev, SX1509_REG_AB, 0xAA,
0xAA)); // Low(Reg B), High(Reg B)
0xAA)); // Low(Reg B), High(Reg B)
TEST_ASSERT_EQUAL_HEX8(0xAA, SX1509_regs[0x15]); // Low Reg B
TEST_ASSERT_EQUAL_HEX8(0xAA, SX1509_regs[0x14]); // High Reg B