mirror of
https://github.com/outbackdingo/OpCore-Simplify.git
synced 2026-01-27 10:19:49 +00:00
Rewrite ACPI patch to create a new RTC device for Intel HEDT systems
This commit is contained in:
Hoang Hong Quan
@@ -2451,124 +2451,81 @@ DefinitionBlock("", "SSDT", 2, "ZPSS", "RMNE", 0x00001000)
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return not self.utils.contains_any(cpu_data.IntelCPUGenerations, cpu_codename, start=21) is None and cpu_codename.endswith(("-X", "-P", "-W", "-E", "-EP", "-EX"))
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def fix_system_clock_hedt(self):
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if not self.lpc_bus_device:
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return
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awac_device = self.acpi.get_device_paths_with_hid("ACPI000E", self.dsdt)
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rtc_device_name = self.acpi.get_device_paths_with_hid("PNP0B00", self.dsdt)[0][0].split(".")[-1]
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try:
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rtc_device = self.acpi.get_device_paths_with_hid("PNP0B00", self.dsdt)[0][0]
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if rtc_device.endswith("RTC"):
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rtc_device += "_"
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except:
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if not self.lpc_bus_device:
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return
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rtc_device = self.lpc_bus_device + ".RTC0"
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new_rtc_device = ".".join(rtc_device.split(".")[:-1] + [self.get_unique_device(rtc_device, rtc_device.split(".")[-1])[0]])
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patches = []
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comment = "Creates a new RTC device to resolve PCI Configuration issues in macOS Big Sur 11+"
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ssdt_name = "SSDT-RTC0-RANGE"
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ssdt_content = """
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// Resource: https://github.com/acidanthera/OpenCorePkg/blob/master/Docs/AcpiSamples/Source/SSDT-RTC0-RANGE.dsl
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/*
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* On certain motherboards(mainly Asus X299 boards), not all ports are
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* mapped in the RTC device. For the majority of the time, users will not notice
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* this issue though in extreme circumstances macOS may halt in early booting.
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* Most prominently seen around the PCI Configuration stage with macOS 11 Big Sur.
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*
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* To resolve this, we'll want to create a new RTC device(PNP0B00) with the correct
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* range.
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*
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* Note that due to AWAC systems having an _STA method already defined, attempting
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* to set another _STA method in your RTC device will conflict. To resolve this,
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* SSDT-AWAC should be removed and instead opt for this SSDT instead.
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*/
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DefinitionBlock ("", "SSDT", 2, "ZPSS", "RtcRange", 0x00000000)
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{
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External ([[LPCPath]], DeviceObj)"""
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{"""
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if not awac_device:
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ssdt_content += """
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External ([[LPCPath]].[[RTCName]], DeviceObj)"""
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ssdt_content += """
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Scope ([[LPCPath]])
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{"""
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if not awac_device:
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ssdt_content += """
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Scope ([[RTCName]])
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{
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (_OSI ("Darwin"))
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{
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Return (Zero)
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}
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Else
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{
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Return (0x0F)
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}
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}
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}"""
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sta = self.get_sta_var(var=None, device=rtc_device, dev_hid=None, dev_name=rtc_device.split(".")[-1], table=self.dsdt)
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patches.extend(sta.get("patches", []))
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ssdt_content += """
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Device (RTC0)
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ssdt_content += """
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External ([[device_path]], DeviceObj)
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Scope ([[device_path]])
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{
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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/*
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* Change the below _CSR range to match your hardware.
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*
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* For this example, we'll use the Asus Strix X299-E Gaming's ACPI, and show how to correct it.
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* Within the original RTC device, we see that sections 0x70 through 0x77 are mapped:
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*
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* Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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* {
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* IO (Decode16,
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* 0x0070, // Range Minimum 1
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* 0x0070, // Range Maximum 1
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* 0x01, // Alignment 1
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* 0x02, // Length 1
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* )
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* IO (Decode16,
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* 0x0074, // Range Minimum 2
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* 0x0074, // Range Maximum 2
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* 0x01, // Alignment 2
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* 0x04, // Length 2
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* )
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* IRQNoFlags ()
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* {8}
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* })
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*
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* Though Asus seems to have forgotten to map sections 0x72 and 0x73 in the first bank, so
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* we'll want to expand the range to include them under Length 1.
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* Note that not all boards will be the same, verify with your ACPI tables for both the range and
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* missing regions.
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*/
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Name (_HID, EisaId ("PNP0B00")) // _HID: Hardware ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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If (_OSI ("Darwin"))
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{
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IO (Decode16,
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0x0070, // Range Minimum 1
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0x0070, // Range Maximum 1
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0x01, // Alignment 1
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0x04, // Length 1 (Expanded to include 0x72 and 0x73)
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)
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IO (Decode16,
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0x0074, // Range Minimum 2
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0x0074, // Range Maximum 2
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0x01, // Alignment 2
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0x04, // Length 2
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)
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IRQNoFlags ()
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{8}
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})
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Method (_STA, 0, NotSerialized) // _STA: Status
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Return (Zero)
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}
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Else
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{
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If (_OSI ("Darwin"))
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{
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Return (0x0F)
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}
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Else
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{
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Return (Zero)
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}
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Return (0x0F)
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}
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}
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}""".replace("[[device_path]]", rtc_device)
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ssdt_content += """
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External ([[parent_path]], DeviceObj)
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Device ([[device_path]])
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{
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Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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IO (Decode16,
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0x0070, // Range Minimum
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0x0070, // Range Maximum
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0x01, // Alignment
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0x04, // Length
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)
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IO (Decode16,
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0x0074, // Range Minimum
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0x0074, // Range Maximum
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0x01, // Alignment
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0x04, // Length
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)
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IRQNoFlags ()
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{8}
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})
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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If (_OSI ("Darwin"))
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{
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Return (0x0F)
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}
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Else
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{
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Return (Zero)
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}
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}
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}
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}"""
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ssdt_content = ssdt_content.replace("[[LPCPath]]", self.lpc_bus_device).replace("[[RTCName]]", rtc_device_name)
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}""".replace("[[parent_path]]", ".".join(rtc_device.split(".")[:-1])).replace("[[device_path]]", new_rtc_device)
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return {
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"Add": [
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{
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@@ -2576,7 +2533,8 @@ DefinitionBlock ("", "SSDT", 2, "ZPSS", "RtcRange", 0x00000000)
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"Enabled": self.write_ssdt(ssdt_name, ssdt_content),
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"Path": ssdt_name + ".aml"
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}
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]
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],
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"Patch": patches
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}
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def instant_wake_fix(self):
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