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Revert "CIG WF-186w : Support LAN/WAN"

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This reverts commit f51773945c0650c5a87f0afc3db1857ab61e7f5b.

Signed-off-by: Ken <xshi@actiontec.com>
This commit is contained in:
Ken
2023-05-25 16:55:43 +08:00
parent 1dc511cf15
commit 8e450f79c5
2 changed files with 3 additions and 96 deletions
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3
feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-cig-wf186w.dts
View File

@@ -474,6 +474,7 @@
mdio0: mdio@88000 {
status = "ok";
ethernet-phy@0 {
reg = <7>;
};
@@ -484,7 +485,7 @@
pinctrl-0 = <&mdio1_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 35 0>;
cig_clk_div = <0xff>;
ethernet-phy@0 {
reg = <0x1d>;
};

96
feeds/ipq807x/ipq807x/patches/700-RTL8367C_S.patch
View File

@@ -1556,98 +1556,4 @@
+
};
struct rtl8367_extif_config {
--- a/drivers/net/phy/mdio-qca.c 2023-05-25 15:43:34.247357289 +0800
+++ b/drivers/net/phy/mdio-qca.c 2023-05-25 15:50:20.030811654 +0800
@@ -37,8 +37,9 @@
#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR 0
#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE 1
#define MDIO_CTRL_4_ACCESS_CODE_C45_READ 2
-#define CTRL_0_REG_DEFAULT_VALUE 0x1500F
-#define CTRL_0_REG_C45_DEFAULT_VALUE 0x1510F
+#define CTRL_0_REG_DEFAULT_VALUE(div) (0x15000 | (div & 0xff))
+#define CTRL_0_REG_C45_DEFAULT_VALUE(div) (0x15100 | (div & 0xff))
+
#define QCA_MDIO_RETRY 1000
#define QCA_MDIO_DELAY 10
@@ -56,6 +57,7 @@ struct qca_mdio_data {
struct clk *mdio_clk;
void __iomem *membase;
int phy_irq[PHY_MAX_ADDR];
+ int clk_div;
};
static int qca_mdio_wait_busy(struct qca_mdio_data *am)
@@ -91,7 +93,7 @@ static int qca_mdio_read(struct mii_bus
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
- writel(CTRL_0_REG_C45_DEFAULT_VALUE,
+ writel(CTRL_0_REG_C45_DEFAULT_VALUE(am->clk_div),
am->membase + MDIO_CTRL_0_REG);
/* issue the phy address and mmd */
writel((mii_id << 8) | mmd, am->membase + MDIO_CTRL_1_REG);
@@ -100,7 +102,7 @@ static int qca_mdio_read(struct mii_bus
cmd = MDIO_CTRL_4_ACCESS_START |
MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
} else {
- writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
+ writel(CTRL_0_REG_DEFAULT_VALUE(am->clk_div), am->membase + MDIO_CTRL_0_REG);
/* issue the phy address and reg */
writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ;
@@ -140,7 +142,7 @@ static int qca_mdio_write(struct mii_bus
unsigned int mmd = (regnum >> 16) & 0x1F;
unsigned int reg = regnum & 0xFFFF;
- writel(CTRL_0_REG_C45_DEFAULT_VALUE,
+ writel(CTRL_0_REG_C45_DEFAULT_VALUE(am->clk_div),
am->membase + MDIO_CTRL_0_REG);
/* issue the phy address and mmd */
writel((mii_id << 8) | mmd, am->membase + MDIO_CTRL_1_REG);
@@ -152,7 +154,7 @@ static int qca_mdio_write(struct mii_bus
if (qca_mdio_wait_busy(am))
return -ETIMEDOUT;
} else {
- writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
+ writel(CTRL_0_REG_DEFAULT_VALUE(am->clk_div), am->membase + MDIO_CTRL_0_REG);
/* issue the phy address and reg */
writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
}
@@ -252,7 +254,7 @@ static int qca_mdio_probe(struct platfor
struct resource *res;
int ret, i;
struct reset_control *rst = ERR_PTR(-EINVAL);
-
+ int clk_div = 0xf;
if (of_machine_is_compatible("qcom,ipq5018")) {
qca_tcsr_ldo_rdy_set(true);
rst = of_reset_control_get(pdev->dev.of_node, "gephy_mdc_rst");
@@ -260,9 +262,13 @@ static int qca_mdio_probe(struct platfor
reset_control_deassert(rst);
usleep_range(100000, 110000);
}
+ if (0 == of_property_read_u32(pdev->dev.of_node, "cig_clk_div", &ret))
+ clk_div = ret;
+ dev_err(&pdev->dev,"CIG clk_div =%x\n",clk_div);
}
- ret = qca_phy_reset(pdev);
+
+ ret = qca_phy_reset(pdev);
if (ret)
dev_err(&pdev->dev, "Could not find reset gpio\n");
@@ -299,8 +305,8 @@ static int qca_mdio_probe(struct platfor
ret = -ENOMEM;
goto err_disable_clk;
}
-
- writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
+ am->clk_div = clk_div ;
+ writel(CTRL_0_REG_DEFAULT_VALUE(am->clk_div), am->membase + MDIO_CTRL_0_REG);
am->mii_bus->name = "qca_mdio";
am->mii_bus->read = &qca_mdio_read;
struct rtl8367_extif_config {