Add new build target ryu_p2 for Ryu P2 boards

The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a new EC chip with bigger flash, so make the corresponding changes: - Pinout changes - HW Timer: TIM5 - USB PD Tx Timer: TIM3_CH4 - USB PD Rx Timer: TIM2_CH4 - Use UART2 for EC console - Disable UART Tx DMA as it conflicts with USB PD Tx DMA - Use 24MHz HSE x2 = 48MHz for SYSCLK BRANCH=None BUG=chrome-os-partner:32660 TEST=Sanity check on a new board: - i2cscan - PD negotiation - UART console - gettime Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221404 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2026-01-04 22:11:41 +00:00 · 2014-10-05 16:29:04 +08:00
parent fbefbbca1e
commit 00551f7331
12 changed files with 804 additions and 8 deletions
--- a/board/ryu_p2/Makefile
+++ b/board/ryu_p2/Makefile
@@ -0,0 +1 @@
+../../Makefile
--- a/board/ryu_p2/board.c
+++ b/board/ryu_p2/board.c
@@ -0,0 +1,180 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* ryu board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "battery.h"
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "inductive_charging.h"
+#include "power.h"
+#include "power_button.h"
+#include "registers.h"
+#include "task.h"
+#include "usb_pd.h"
+#include "usb_pd_config.h"
+#include "util.h"
+
+void vbus_evt(enum gpio_signal signal)
+{
+	ccprintf("VBUS %d, %d!\n", signal, gpio_get_level(signal));
+	task_wake(TASK_ID_PD);
+}
+
+void unhandled_evt(enum gpio_signal signal)
+{
+	ccprintf("Unhandled INT %d,%d!\n", signal, gpio_get_level(signal));
+}
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/*
+	 * Determine recovery mode is requested by the power, volup, and
+	 * voldown buttons being pressed.
+	 */
+	if (power_button_signal_asserted() &&
+	    !gpio_get_level(GPIO_BTN_VOLD_L) &&
+	    !gpio_get_level(GPIO_BTN_VOLU_L))
+		host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+	/*
+	 * Enable CC lines after all GPIO have been initialized. Note, it is
+	 * important that this is enabled after the CC_DEVICE_ODL lines are
+	 * set low to specify device mode.
+	 */
+	gpio_set_level(GPIO_USBC_CC_EN, 1);
+
+	/* Enable interrupts on VBUS transitions. */
+	gpio_enable_interrupt(GPIO_CHGR_ACOK);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/* power signal list.  Must match order of enum power_signal. */
+const struct power_signal_info power_signal_list[] = {
+	{GPIO_AP_HOLD, 1, "AP_HOLD"},
+	{GPIO_AP_IN_SUSPEND,  1, "SUSPEND_ASSERTED"},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Vbus sensing. Converted to mV, /10 voltage divider. */
+	[ADC_VBUS] = {"VBUS",  30000, 4096, 0, STM32_AIN(0)},
+	/* USB PD CC lines sensing. Converted to mV (3000mV/4096). */
+	[ADC_CC1_PD] = {"CC1_PD", 3000, 4096, 0, STM32_AIN(1)},
+	[ADC_CC2_PD] = {"CC2_PD", 3000, 4096, 0, STM32_AIN(3)},
+	/* Charger current sensing. Converted to mA. */
+	[ADC_IADP] = {"IADP",  7500, 4096, 0, STM32_AIN(8)},
+	[ADC_IBAT] = {"IBAT", 37500, 4096, 0, STM32_AIN(13)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"master", I2C_PORT_MASTER, 100,
+		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+	{"slave",  I2C_PORT_SLAVE, 100,
+		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+void board_set_usb_mux(int port, enum typec_mux mux, int polarity)
+{
+	/* reset everything */
+	gpio_set_level(GPIO_USBC_SS_EN_L, 1);
+	gpio_set_level(GPIO_USBC_DP_MODE_L, 1);
+	gpio_set_level(GPIO_USBC_DP_POLARITY, 1);
+	gpio_set_level(GPIO_USBC_SS1_USB_MODE_L, 1);
+	gpio_set_level(GPIO_USBC_SS2_USB_MODE_L, 1);
+
+	if (mux == TYPEC_MUX_NONE)
+		/* everything is already disabled, we can return */
+		return;
+
+	if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK) {
+		/* USB 3.0 uses 2 superspeed lanes */
+		gpio_set_level(polarity ? GPIO_USBC_SS2_USB_MODE_L :
+					  GPIO_USBC_SS1_USB_MODE_L, 0);
+	}
+
+	if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK) {
+		/* DP uses available superspeed lanes (x2 or x4) */
+		gpio_set_level(GPIO_USBC_DP_POLARITY, polarity);
+		gpio_set_level(GPIO_USBC_DP_MODE_L, 0);
+	}
+	/* switch on superspeed lanes */
+	gpio_set_level(GPIO_USBC_SS_EN_L, 0);
+}
+
+int board_get_usb_mux(int port, const char **dp_str, const char **usb_str)
+{
+	int has_ss = !gpio_get_level(GPIO_USBC_SS_EN_L);
+	int has_usb = !gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ||
+		      !gpio_get_level(GPIO_USBC_SS2_USB_MODE_L);
+	int has_dp = !gpio_get_level(GPIO_USBC_DP_MODE_L);
+
+	if (has_dp)
+		*dp_str = gpio_get_level(GPIO_USBC_DP_POLARITY) ? "DP2" : "DP1";
+	else
+		*dp_str = NULL;
+
+	if (has_usb)
+		*usb_str = gpio_get_level(GPIO_USBC_SS1_USB_MODE_L) ?
+				"USB2" : "USB1";
+	else
+		*usb_str = NULL;
+
+	return has_ss;
+}
+
+/**
+ * Discharge battery when on AC power for factory test.
+ */
+int board_discharge_on_ac(int enable)
+{
+	return charger_discharge_on_ac(enable);
+}
+
+int extpower_is_present(void)
+{
+	return gpio_get_level(GPIO_CHGR_ACOK);
+}
+
+/* Battery temperature ranges in degrees C */
+static const struct battery_info info = {
+	/* Design voltage */
+	.voltage_max    = 4350,
+	.voltage_normal = 3800,
+	.voltage_min    = 2800,
+	/* Pre-charge current: I <= 0.01C */
+	.precharge_current  = 64,  /* mA */
+	/* Operational temperature range */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 45,
+	.charging_min_c       = 0,
+	.charging_max_c       = 50,
+	.discharging_min_c    = -20,
+	.discharging_max_c    = 60,
+};
+
+const struct battery_info *battery_get_info(void)
+{
+	return &info;
+}
+
+/* Fake lid switch */
+int lid_is_open(void)
+{
+	return 1;
+}
--- a/board/ryu_p2/board.h
+++ b/board/ryu_p2/board.h
@@ -0,0 +1,111 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ryu board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART2 (PD4/PD5) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 2
+
+/* By default, enable all console messages excepted USB */
+#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_USBPD))
+
+/* Optional features */
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_FLASH_ERASE_CHECK
+#define CONFIG_USB_PD_INTERNAL_COMP
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_VCONN
+#define CONFIG_ADC
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#undef  CONFIG_LID_SWITCH
+#define CONFIG_VBOOT_HASH
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_TASK_PROFILING
+#define CONFIG_INDUCTIVE_CHARGING
+#undef CONFIG_HIBERNATE
+#undef CONFIG_UART_TX_DMA /* DMAC_CH7 is used by USB PD */
+#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART2_RX
+
+/*
+ * Pericom I2C workaround
+ * TODO(crosbug.com/p/31529): Remove this.
+ */
+#define CONFIG_I2C_SCL_GATE_PORT I2C_PORT_MASTER
+#define CONFIG_I2C_SCL_GATE_ADDR 0x4a
+#define CONFIG_I2C_SCL_GATE_GPIO GPIO_PERICOM_CLK_EN
+
+/* Charging/Power configuration */
+#undef CONFIG_BATTERY_RYU /* TODO implement */
+#define CONFIG_BATTERY_BQ27541
+#define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_V2
+#define CONFIG_CHARGER_BQ24773
+#define CONFIG_CHARGER_ILIM_PIN_DISABLED
+#define CONFIG_CHARGER_SENSE_RESISTOR 5
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHIPSET_TEGRA
+#define CONFIG_PMIC_FW_LONG_PRESS_TIMER
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
+
+/* I2C ports configuration */
+#define I2C_PORT_MASTER 0
+#define I2C_PORT_SLAVE  1
+#define I2C_PORT_EC I2C_PORT_SLAVE
+#define I2C_PORT_CHARGER I2C_PORT_MASTER
+#define I2C_PORT_BATTERY I2C_PORT_MASTER
+
+/* slave address for host commands */
+#ifdef HAS_TASK_HOSTCMD
+#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3c
+#endif
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 5
+
+#include "gpio_signal.h"
+
+enum power_signal {
+	TEGRA_XPSHOLD = 0,
+	TEGRA_SUSPEND_ASSERTED,
+
+	/* Number of power signals */
+	POWER_SIGNAL_COUNT
+};
+
+/* ADC signal */
+enum adc_channel {
+	ADC_VBUS = 0,
+	ADC_CC1_PD,
+	ADC_CC2_PD,
+	ADC_IADP,
+	ADC_IBAT,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+/* Discharge battery when on AC power for factory test. */
+int board_discharge_on_ac(int enable);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
--- a/board/ryu_p2/build.mk
+++ b/board/ryu_p2/build.mk
@@ -0,0 +1,13 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F373VB
+CHIP:=stm32
+CHIP_FAMILY:=stm32f3
+CHIP_VARIANT:=stm32f373
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
--- a/board/ryu_p2/ec.tasklist
+++ b/board/ryu_p2/ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE)
--- a/board/ryu_p2/gpio.inc
+++ b/board/ryu_p2/gpio.inc
@@ -0,0 +1,124 @@
+/* -*- mode:c -*-
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO(CHGR_ACOK,            D, 4,  GPIO_INT_BOTH | GPIO_PULL_UP,    vbus_evt)
+GPIO(BC_TEMP_ALERT_L,      C, 5,  GPIO_INT_FALLING,                unhandled_evt)
+GPIO(POWER_BUTTON_L,       C, 13, GPIO_INT_BOTH,                   power_button_interrupt) /* active high, the name is for compatibility with existing code */
+GPIO(USBC_BC12_INT_L,      D, 11, GPIO_INT_FALLING | GPIO_PULL_UP, unhandled_evt)
+GPIO(LID_OPEN,             E, 1,  GPIO_INT_BOTH | GPIO_PULL_UP,    unhandled_evt)
+GPIO(CHARGE_DONE,          E, 6,  GPIO_INT_BOTH,                   inductive_charging_interrupt)
+GPIO(LB_INT_L,             E, 7,  GPIO_INT_FALLING | GPIO_PULL_UP, unhandled_evt)
+GPIO(LIGHTBAR_EN_L,        E, 8,  GPIO_INT_FALLING | GPIO_PULL_UP, unhandled_evt)
+GPIO(AP_IN_SUSPEND,        F, 9,  GPIO_INT_BOTH,                   power_signal_interrupt)
+GPIO(BASE_PRES_L,          E, 10, GPIO_INT_BOTH | GPIO_PULL_UP,    unhandled_evt)
+GPIO(AP_HOLD,              E, 3,  GPIO_INT_BOTH, power_signal_interrupt)
+
+/* Buttons */
+GPIO(BTN_VOLD_L,           C, 0,  GPIO_INPUT | GPIO_PULL_UP,       NULL)
+GPIO(BTN_VOLU_L,           A, 2,  GPIO_INPUT | GPIO_PULL_UP,       NULL)
+
+/* PD RX/TX */
+GPIO(USBC_CC1_PD,          A, 1,  GPIO_ANALOG,   NULL)
+GPIO(USBC_CC2_PD,          A, 3,  GPIO_ANALOG,   NULL)
+GPIO(USBC_CC_EN,           A, 4,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_CC_TX_DATA,      A, 6,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_CC_TX_EN,        D, 7,  GPIO_OUT_LOW,  NULL)
+
+#if 0
+/* Alternate functions */
+GPIO(USBC_TX_CLKOUT,       B, 1,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_TX_CLKIN,        B, 3,  GPIO_OUT_LOW,  NULL)
+#endif
+
+/* System power */
+GPIO(PMIC_PWRON_L,         D, 14, GPIO_ODR_HIGH, NULL)
+GPIO(PMIC_WARM_RESET_L,    E, 4,  GPIO_ODR_HIGH, NULL)
+GPIO(EN_PP3300_RSVD,       E, 13, GPIO_INPUT,    NULL)
+/* sensor temp output and PMIC reset input */
+GPIO(PMIC_THERM_L,         D, 12, GPIO_ODR_HIGH, NULL)
+
+GPIO(VBUS_SENSE,           A, 0,  GPIO_ANALOG,   NULL)
+GPIO(CHGR_IADP,            B, 0,  GPIO_ANALOG,   NULL)
+GPIO(CHGR_IBAT,            C, 3,  GPIO_ANALOG,   NULL)
+
+/* Inductive charging */
+GPIO(CHARGE_EN,            D, 13, GPIO_OUT_LOW,  NULL)
+GPIO(BASE_CHG_VDD_EN,      E, 5,  GPIO_OUT_LOW,  NULL)
+
+/* USB-C Power and muxes control */
+GPIO(USBC_CHARGE_EN_L,     A, 7,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_5V_EN,           D, 8,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_VCONN1_EN_L,     F, 10, GPIO_OUT_HIGH, NULL)
+GPIO(USBC_VCONN2_EN_L,     D, 10, GPIO_OUT_HIGH, NULL)
+
+GPIO(USBC_CC1_DEVICE_ODL,  A, 5,  GPIO_ODR_LOW,  NULL)
+GPIO(USBC_CC2_DEVICE_ODL,  E, 14, GPIO_ODR_LOW,  NULL)
+
+GPIO(USBC_DP_MODE_L,       D, 1,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_DP_POLARITY,     D, 2,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_SS1_USB_MODE_L,  D, 3,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_SS2_USB_MODE_L,  D, 9,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_SS_EN_L,         E, 0,  GPIO_OUT_HIGH, NULL)
+
+/* Inputs */
+GPIO(BOARD_ID0,            E, 11,  GPIO_INPUT,    NULL)
+GPIO(BOARD_ID1,            E, 12,  GPIO_INPUT,    NULL)
+GPIO(SH_SIGNAL,            E, 2,   GPIO_INPUT,    NULL)
+
+/* Lightbar reset */
+GPIO(LB_RST_L,             D, 15, GPIO_ODR_HIGH | GPIO_PULL_UP, NULL)
+
+#if 0
+/* Alternate functions */
+GPIO(USB_DM,               A, 11, GPIO_ANALOG,   NULL)
+GPIO(USB_DP,               A, 12, GPIO_ANALOG,   NULL)
+GPIO(UART_TX,              D, 5,  GPIO_OUT_LOW,  NULL)
+GPIO(UART_RX,              D, 6,  GPIO_OUT_LOW,  NULL)
+#endif
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(MASTER_I2C_SCL,       A, 15, GPIO_INPUT,    NULL)
+GPIO(MASTER_I2C_SDA,       A, 14, GPIO_INPUT,    NULL)
+GPIO(SLAVE_I2C_SCL,        A, 9,  GPIO_INPUT,    NULL)
+GPIO(SLAVE_I2C_SDA,        A, 10, GPIO_INPUT,    NULL)
+
+/* SCL gating for PI3USB9281 */
+GPIO(PERICOM_CLK_EN,       C, 15, GPIO_OUT_LOW,  NULL)
+
+/* Case closed debugging. */
+GPIO(PD_DISABLE_DEBUG,     C, 6,  GPIO_OUT_HIGH, NULL)
+GPIO(SPI_FLASH_NSS,        B, 9,  GPIO_INPUT,    NULL)
+GPIO(SPI_FLASH_SCK,        B, 10, GPIO_INPUT,    NULL)
+GPIO(SPI_FLASH_MOSI,       B, 15, GPIO_INPUT,    NULL)
+GPIO(SPI_FLASH_MISO,       B, 14, GPIO_INPUT,    NULL)
+GPIO(VDDSPI_EN,            C, 12, GPIO_OUT_LOW,  NULL)
+GPIO(SH_RESET_L,           C, 4,  GPIO_ODR_HIGH, NULL)
+GPIO(SH_BOOT,              C, 9,  GPIO_ODR_HIGH, NULL)
+GPIO(EC_INT_L,             F, 2,  GPIO_ODR_HIGH, NULL)
+GPIO(ENTERING_RW,          E, 15, GPIO_OUT_LOW,  NULL)
+GPIO(WP_L,                 F, 6,  GPIO_INPUT,    NULL)
+
+#if 0
+/* Alternate functions */
+GPIO(SH_UART_TX,           C, 11, GPIO_OUT_LOW,  NULL)
+GPIO(SH_UART_RX,           C, 10, GPIO_INPUT,    NULL)
+GPIO(AP_UART_TX,           B, 6,  GPIO_OUT_LOW,  NULL)
+GPIO(AP_UART_RX,           B, 7,  GPIO_INPUT,    NULL)
+#endif
+
+UNIMPLEMENTED(AP_RESET_L)
+
+ALTERNATE(B, 0x0008, 5, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
+ALTERNATE(B, 0x0002, 2, MODULE_USB_PD, 0) /* TIM3_CH4: PB1 */
+ALTERNATE(B, 0x00C0, 7, MODULE_UART,   0) /* USART1: PB6/PB7 */
+ALTERNATE(D, 0x0060, 7, MODULE_UART,   0) /* USART2: PD4/PD5 */
+ALTERNATE(C, 0x0C00, 7, MODULE_UART,   0) /* USART3: PC10/PC11 */
+ALTERNATE(A, 0xC600, 4, MODULE_I2C,    0) /* I2C SLAVE:PA9/10 MASTER:PA14/15 */
--- a/board/ryu_p2/usb_pd_config.h
+++ b/board/ryu_p2/usb_pd_config.h
@@ -0,0 +1,176 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery board configuration */
+
+#ifndef __USB_PD_CONFIG_H
+#define __USB_PD_CONFIG_H
+
+/* Port and task configuration */
+#define PD_PORT_COUNT 1
+#define PORT_TO_TASK_ID(port) TASK_ID_PD
+#define TASK_ID_TO_PORT(id)   0
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX_C0 3
+#define TIM_CLOCK_PD_RX_C0 2
+
+#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
+#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
+
+/* Timer channel */
+#define TIM_RX_CCR_C0 4
+#define TIM_TX_CCR_C0 4
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_RX_CCR_REG(p) TIM_CCR_C0
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX(p) TIM_REG_TX_C0
+#define TIM_REG_RX(p) TIM_REG_RX_C0
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX is using SPI1 on PA6, PB3, and PB5 */
+#define SPI_REGS(p) STM32_SPI1_REGS
+
+static inline void spi_enable_clock(int port)
+{
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+}
+
+#define DMAC_SPI_TX(p) STM32_DMAC_CH3
+
+/* RX is using COMP1 triggering TIM2 CH4 */
+#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM2_IC4
+#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM2_IC4
+
+#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
+#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_CCR_CS  1
+#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+#define DMAC_TIM_RX(p) STM32_DMAC_CH7
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(int port)
+{
+	/* 40 MHz pin speed on SPI MISO PA6 */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003000;
+	/* 40 MHz pin speed on TIM3_CH4 (PB1) */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x0000000C;
+}
+
+/* Reset SPI peripheral used for TX */
+static inline void pd_tx_spi_reset(int port)
+{
+	/* Reset SPI1 */
+	STM32_RCC_APB2RSTR |= (1 << 12);
+	STM32_RCC_APB2RSTR &= ~(1 << 12);
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int port, int polarity)
+{
+	/* put SPI function on TX pin : PA6 is SPI MISO */
+	gpio_set_alternate_function(GPIO_A, 0x0040, 5);
+
+	/* set the low level reference */
+	gpio_set_level(GPIO_USBC_CC_TX_EN, 1);
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int port, int polarity)
+{
+	/* output low on SPI TX (PA6 is SPI1 MISO) to disable the FET */
+	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+					& ~(3 << (2*6)))
+					|  (1 << (2*6));
+
+	/* put the low level reference in Hi-Z */
+	gpio_set_level(GPIO_USBC_CC_TX_EN, 0);
+}
+
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int port, int polarity)
+{
+	/*
+	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
+	 *                            CC2 -> PA3 (COMP2 INP)
+	 * use VrefInt / 2 as INM (about 600mV)
+	 */
+	STM32_COMP_CSR = (STM32_COMP_CSR
+		 & ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
+		   | STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
+		| STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP2INSEL_VREF12
+		| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+	gpio_config_module(MODULE_USB_PD, 1);
+}
+
+static inline void pd_set_host_mode(int port, int enable)
+{
+	if (enable) {
+		/* We never charging in power source mode */
+		gpio_set_level(GPIO_USBC_CHARGE_EN_L, 1);
+		/* High-Z is used for host mode. */
+		gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 1);
+		gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 1);
+	} else {
+		/* Kill VBUS power supply */
+		gpio_set_level(GPIO_USBC_5V_EN, 0);
+		/* Pull low for device mode. */
+		gpio_set_level(GPIO_USBC_CC1_DEVICE_ODL, 0);
+		gpio_set_level(GPIO_USBC_CC2_DEVICE_ODL, 0);
+		/* Enable the charging path*/
+		gpio_set_level(GPIO_USBC_CHARGE_EN_L, 0);
+	}
+
+}
+
+static inline int pd_adc_read(int port, int cc)
+{
+	if (cc == 0)
+		return adc_read_channel(ADC_CC1_PD);
+	else
+		return adc_read_channel(ADC_CC2_PD);
+}
+
+static inline void pd_set_vconn(int port, int polarity, int enable)
+{
+	/* Set VCONN on the opposite CC line from the polarity */
+	gpio_set_level(polarity ? GPIO_USBC_VCONN1_EN_L :
+				  GPIO_USBC_VCONN2_EN_L, !enable);
+}
+
+static inline int pd_snk_is_vbus_provided(int port)
+{
+	return gpio_get_level(GPIO_CHGR_ACOK);
+}
+
+/* Standard-current DFP : no-connect voltage is 1.55V */
+#define PD_SRC_VNC 1550 /* mV */
+
+/* UFP-side : threshold for DFP connection detection */
+#define PD_SNK_VA   200 /* mV */
+
+/* start as a sink in case we have no other power supply/battery */
+#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
+
+/* delay necessary for the voltage transition on the power supply */
+#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */
+
+#endif /* __USB_PD_CONFIG_H */
--- a/board/ryu_p2/usb_pd_policy.c
+++ b/board/ryu_p2/usb_pd_policy.c
@@ -0,0 +1,138 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+/* TODO(crosbug.com/p/28869): update source and sink tables to spec. */
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000,   500, PDO_FIXED_EXTERNAL),
+		PDO_FIXED(5000,   900, 0),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* TODO(crosbug.com/p/28869): update source and sink tables to spec. */
+const uint32_t pd_snk_pdo[] = {
+		PDO_BATT(4500,   5500, 15000),
+		PDO_BATT(11500, 12500, 36000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/* Cap on the max voltage requested as a sink (in millivolts) */
+static unsigned max_mv = -1; /* no cap */
+
+int pd_choose_voltage(int cnt, uint32_t *src_caps, uint32_t *rdo)
+{
+	int i;
+	int sel_mv;
+	int max_uw = 0;
+	int max_ma;
+	int max_i = -1;
+
+	/* Get max power */
+	for (i = 0; i < cnt; i++) {
+		int uw;
+		int mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
+		if ((src_caps[i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+			uw = 250000 * (src_caps[i] & 0x3FF);
+		} else {
+			int ma = (src_caps[i] & 0x3FF) * 10;
+			uw = ma * mv;
+		}
+		if ((uw > max_uw) && (mv <= max_mv)) {
+			max_i = i;
+			max_uw = uw;
+			sel_mv = mv;
+		}
+	}
+	if (max_i < 0)
+		return -EC_ERROR_UNKNOWN;
+
+	/* request all the power ... */
+	if ((src_caps[max_i] & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
+		int uw = 250000 * (src_caps[max_i] & 0x3FF);
+		max_ma = uw / sel_mv;
+		*rdo = RDO_BATT(max_i + 1, uw/2, uw, 0);
+		ccprintf("Request [%d] %dV %dmW\n",
+			 max_i, sel_mv/1000, uw/1000);
+	} else {
+		int ma = 10 * (src_caps[max_i] & 0x3FF);
+		max_ma = ma;
+		*rdo = RDO_FIXED(max_i + 1, ma / 2, ma, 0);
+		ccprintf("Request [%d] %dV %dmA\n",
+			 max_i, sel_mv/1000, ma);
+	}
+	return max_ma;
+}
+
+void pd_set_input_current_limit(int port, uint32_t max_ma)
+{
+	int rv = charge_set_input_current_limit(MAX(max_ma,
+					CONFIG_CHARGER_INPUT_CURRENT));
+	if (rv < 0)
+		CPRINTS("Failed to set input current limit for PD");
+}
+
+void pd_set_max_voltage(unsigned mv)
+{
+	max_mv = mv;
+}
+
+int pd_request_voltage(uint32_t rdo)
+{
+	int op_ma = rdo & 0x3FF;
+	int max_ma = (rdo >> 10) & 0x3FF;
+	int idx = rdo >> 28;
+	uint32_t pdo;
+	uint32_t pdo_ma;
+
+	if (!idx || idx > pd_src_pdo_cnt)
+		return EC_ERROR_INVAL; /* Invalid index */
+
+	/* check current ... */
+	pdo = pd_src_pdo[idx - 1];
+	pdo_ma = (pdo & 0x3ff);
+	if (op_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much op current */
+	if (max_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much max current */
+
+	ccprintf("Switch to %d V %d mA (for %d/%d mA)\n",
+		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
+		 ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
+
+	return EC_SUCCESS;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* provide VBUS */
+	gpio_set_level(GPIO_USBC_5V_EN, 1);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Kill VBUS */
+	gpio_set_level(GPIO_USBC_5V_EN, 0);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
--- a/chip/stm32/adc-stm32f.c
+++ b/chip/stm32/adc-stm32f.c
@@ -247,6 +247,8 @@ int adc_read_all_channels(int *data)
 	}

 exit_all_channels:
+	dma_disable(STM32_DMAC_ADC);
+
 	if (restore_watchdog)
 		adc_enable_watchdog_no_lock();

--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -198,16 +198,39 @@ DECLARE_IRQ(STM32_IRQ_RTC_WAKEUP, __rtc_alarm_irq, 1);

 static void config_hispeed_clock(void)
 {
-	/* Ensure that HSI48 is ON */
-	if (!(STM32_RCC_CR2 & (1 << 17))) {
-		/* Enable HSI */
-		STM32_RCC_CR2 |= 1 << 16;
-		/* Wait for HSI to be ready */
-		while (!(STM32_RCC_CR2 & (1 << 17)))
+#ifdef CHIP_FAMILY_STM32F3
+	/* Ensure that HSE is ON */
+	if (!(STM32_RCC_CR & (1 << 17))) {
+		/* Enable HSE */
+		STM32_RCC_CR |= 1 << 16;
+		/* Wait for HSE to be ready */
+		while (!(STM32_RCC_CR & (1 << 17)))
 			;
 	}

-#if (CPU_CLOCK == HSI48_CLOCK)
+	/*
+	 * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
+	 * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz
+	 * ADCCLK = PCLK / 6 = 4MHz
+	 * USB uses SYSCLK = 48MHz
+	 */
+	/*STM32_RCC_CFGR = 0x0041a400;*/
+	STM32_RCC_CFGR = 0x0041a400;
+
+	/* Enable the PLL */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until the PLL is ready */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* Wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+#elif (CPU_CLOCK == HSI48_CLOCK)
 	/*
 	 * HSI48 = 48MHz, no prescaler, no MCO, no PLL
 	 * therefore PCLK = FCLK = SYSCLK = 48MHz
@@ -254,7 +277,7 @@ static void config_hispeed_clock(void)
 		;

 #else
-#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
+#error "CPU_CLOCK must be either 48MHz or 38.4MHz for STM32F0"
 #endif
 }

--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -544,6 +544,8 @@ void pd_hw_init(int port)
 	/* Timer ICx input configuration */
 	if (TIM_RX_CCR_IDX(port) == 1)
 		phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0;
+	else if (TIM_RX_CCR_IDX(port) == 4)
+		phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8;
 	else
 		/*  Unsupported RX timer capture input */
 		ASSERT(0);
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -69,6 +69,7 @@ BOARDS_STM32=(
 	plankton
 	ryu
 	ryu_sh
+	ryu_p2
 	samus_pd
 	snow
 	spring